1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017 Etnaviv Project
4 * Copyright (C) 2017 Zodiac Inflight Innovations
7 #include "common.xml.h"
8 #include "etnaviv_gpu.h"
9 #include "etnaviv_perfmon.h"
10 #include "state_hi.xml.h"
12 struct etnaviv_pm_domain;
14 struct etnaviv_pm_signal {
18 u32 (*sample)(struct etnaviv_gpu *gpu,
19 const struct etnaviv_pm_domain *domain,
20 const struct etnaviv_pm_signal *signal);
23 struct etnaviv_pm_domain {
26 /* profile register */
31 const struct etnaviv_pm_signal *signal;
34 struct etnaviv_pm_domain_meta {
36 const struct etnaviv_pm_domain *domains;
40 static u32 perf_reg_read(struct etnaviv_gpu *gpu,
41 const struct etnaviv_pm_domain *domain,
42 const struct etnaviv_pm_signal *signal)
44 gpu_write(gpu, domain->profile_config, signal->data);
46 return gpu_read(gpu, domain->profile_read);
49 static inline void pipe_select(struct etnaviv_gpu *gpu, u32 clock, unsigned pipe)
51 clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK);
52 clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(pipe);
54 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
57 static u32 pipe_perf_reg_read(struct etnaviv_gpu *gpu,
58 const struct etnaviv_pm_domain *domain,
59 const struct etnaviv_pm_signal *signal)
61 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
65 for (i = 0; i < gpu->identity.pixel_pipes; i++) {
66 pipe_select(gpu, clock, i);
67 value += perf_reg_read(gpu, domain, signal);
70 /* switch back to pixel pipe 0 to prevent GPU hang */
71 pipe_select(gpu, clock, 0);
76 static u32 pipe_reg_read(struct etnaviv_gpu *gpu,
77 const struct etnaviv_pm_domain *domain,
78 const struct etnaviv_pm_signal *signal)
80 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
84 for (i = 0; i < gpu->identity.pixel_pipes; i++) {
85 pipe_select(gpu, clock, i);
86 value += gpu_read(gpu, signal->data);
89 /* switch back to pixel pipe 0 to prevent GPU hang */
90 pipe_select(gpu, clock, 0);
95 static u32 hi_total_cycle_read(struct etnaviv_gpu *gpu,
96 const struct etnaviv_pm_domain *domain,
97 const struct etnaviv_pm_signal *signal)
99 u32 reg = VIVS_HI_PROFILE_TOTAL_CYCLES;
101 if (gpu->identity.model == chipModel_GC880 ||
102 gpu->identity.model == chipModel_GC2000 ||
103 gpu->identity.model == chipModel_GC2100)
104 reg = VIVS_MC_PROFILE_CYCLE_COUNTER;
106 return gpu_read(gpu, reg);
109 static u32 hi_total_idle_cycle_read(struct etnaviv_gpu *gpu,
110 const struct etnaviv_pm_domain *domain,
111 const struct etnaviv_pm_signal *signal)
113 u32 reg = VIVS_HI_PROFILE_IDLE_CYCLES;
115 if (gpu->identity.model == chipModel_GC880 ||
116 gpu->identity.model == chipModel_GC2000 ||
117 gpu->identity.model == chipModel_GC2100)
118 reg = VIVS_HI_PROFILE_TOTAL_CYCLES;
120 return gpu_read(gpu, reg);
123 static const struct etnaviv_pm_domain doms_3d[] = {
126 .profile_read = VIVS_MC_PROFILE_HI_READ,
127 .profile_config = VIVS_MC_PROFILE_CONFIG2,
129 .signal = (const struct etnaviv_pm_signal[]) {
132 VIVS_HI_PROFILE_READ_BYTES8,
136 "TOTAL_WRITE_BYTES8",
137 VIVS_HI_PROFILE_WRITE_BYTES8,
148 &hi_total_idle_cycle_read
151 "AXI_CYCLES_READ_REQUEST_STALLED",
152 VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED,
156 "AXI_CYCLES_WRITE_REQUEST_STALLED",
157 VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED,
161 "AXI_CYCLES_WRITE_DATA_STALLED",
162 VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED,
169 .profile_read = VIVS_MC_PROFILE_PE_READ,
170 .profile_config = VIVS_MC_PROFILE_CONFIG0,
172 .signal = (const struct etnaviv_pm_signal[]) {
174 "PIXEL_COUNT_KILLED_BY_COLOR_PIPE",
175 VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE,
179 "PIXEL_COUNT_KILLED_BY_DEPTH_PIPE",
180 VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE,
184 "PIXEL_COUNT_DRAWN_BY_COLOR_PIPE",
185 VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE,
189 "PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE",
190 VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE,
197 .profile_read = VIVS_MC_PROFILE_SH_READ,
198 .profile_config = VIVS_MC_PROFILE_CONFIG0,
200 .signal = (const struct etnaviv_pm_signal[]) {
203 VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES,
208 VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER,
212 "RENDERED_PIXEL_COUNTER",
213 VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_PIXEL_COUNTER,
218 VIVS_MC_PROFILE_CONFIG0_SH_VS_INST_COUNTER,
222 "RENDERED_VERTICE_COUNTER",
223 VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_VERTICE_COUNTER,
227 "VTX_BRANCH_INST_COUNTER",
228 VIVS_MC_PROFILE_CONFIG0_SH_VTX_BRANCH_INST_COUNTER,
232 "VTX_TEXLD_INST_COUNTER",
233 VIVS_MC_PROFILE_CONFIG0_SH_VTX_TEXLD_INST_COUNTER,
237 "PXL_BRANCH_INST_COUNTER",
238 VIVS_MC_PROFILE_CONFIG0_SH_PXL_BRANCH_INST_COUNTER,
242 "PXL_TEXLD_INST_COUNTER",
243 VIVS_MC_PROFILE_CONFIG0_SH_PXL_TEXLD_INST_COUNTER,
250 .profile_read = VIVS_MC_PROFILE_PA_READ,
251 .profile_config = VIVS_MC_PROFILE_CONFIG1,
253 .signal = (const struct etnaviv_pm_signal[]) {
256 VIVS_MC_PROFILE_CONFIG1_PA_INPUT_VTX_COUNTER,
260 "INPUT_PRIM_COUNTER",
261 VIVS_MC_PROFILE_CONFIG1_PA_INPUT_PRIM_COUNTER,
265 "OUTPUT_PRIM_COUNTER",
266 VIVS_MC_PROFILE_CONFIG1_PA_OUTPUT_PRIM_COUNTER,
270 "DEPTH_CLIPPED_COUNTER",
271 VIVS_MC_PROFILE_CONFIG1_PA_DEPTH_CLIPPED_COUNTER,
275 "TRIVIAL_REJECTED_COUNTER",
276 VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER,
281 VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER,
288 .profile_read = VIVS_MC_PROFILE_SE_READ,
289 .profile_config = VIVS_MC_PROFILE_CONFIG1,
291 .signal = (const struct etnaviv_pm_signal[]) {
293 "CULLED_TRIANGLE_COUNT",
294 VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT,
298 "CULLED_LINES_COUNT",
299 VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT,
306 .profile_read = VIVS_MC_PROFILE_RA_READ,
307 .profile_config = VIVS_MC_PROFILE_CONFIG1,
309 .signal = (const struct etnaviv_pm_signal[]) {
312 VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT,
317 VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT,
321 "VALID_QUAD_COUNT_AFTER_EARLY_Z",
322 VIVS_MC_PROFILE_CONFIG1_RA_VALID_QUAD_COUNT_AFTER_EARLY_Z,
326 "TOTAL_PRIMITIVE_COUNT",
327 VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_PRIMITIVE_COUNT,
331 "PIPE_CACHE_MISS_COUNTER",
332 VIVS_MC_PROFILE_CONFIG1_RA_PIPE_CACHE_MISS_COUNTER,
336 "PREFETCH_CACHE_MISS_COUNTER",
337 VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER,
342 VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT,
349 .profile_read = VIVS_MC_PROFILE_TX_READ,
350 .profile_config = VIVS_MC_PROFILE_CONFIG1,
352 .signal = (const struct etnaviv_pm_signal[]) {
354 "TOTAL_BILINEAR_REQUESTS",
355 VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS,
359 "TOTAL_TRILINEAR_REQUESTS",
360 VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS,
364 "TOTAL_DISCARDED_TEXTURE_REQUESTS",
365 VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_DISCARDED_TEXTURE_REQUESTS,
369 "TOTAL_TEXTURE_REQUESTS",
370 VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TEXTURE_REQUESTS,
375 VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_COUNT,
379 "MEM_READ_IN_8B_COUNT",
380 VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_IN_8B_COUNT,
385 VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_COUNT,
389 "CACHE_HIT_TEXEL_COUNT",
390 VIVS_MC_PROFILE_CONFIG1_TX_CACHE_HIT_TEXEL_COUNT,
394 "CACHE_MISS_TEXEL_COUNT",
395 VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_TEXEL_COUNT,
402 .profile_read = VIVS_MC_PROFILE_MC_READ,
403 .profile_config = VIVS_MC_PROFILE_CONFIG2,
405 .signal = (const struct etnaviv_pm_signal[]) {
407 "TOTAL_READ_REQ_8B_FROM_PIPELINE",
408 VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE,
412 "TOTAL_READ_REQ_8B_FROM_IP",
413 VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP,
417 "TOTAL_WRITE_REQ_8B_FROM_PIPELINE",
418 VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE,
425 static const struct etnaviv_pm_domain doms_2d[] = {
428 .profile_read = VIVS_MC_PROFILE_PE_READ,
429 .profile_config = VIVS_MC_PROFILE_CONFIG0,
431 .signal = (const struct etnaviv_pm_signal[]) {
433 "PIXELS_RENDERED_2D",
434 VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D,
441 static const struct etnaviv_pm_domain doms_vg[] = {
444 static const struct etnaviv_pm_domain_meta doms_meta[] = {
446 .feature = chipFeatures_PIPE_3D,
447 .nr_domains = ARRAY_SIZE(doms_3d),
448 .domains = &doms_3d[0]
451 .feature = chipFeatures_PIPE_2D,
452 .nr_domains = ARRAY_SIZE(doms_2d),
453 .domains = &doms_2d[0]
456 .feature = chipFeatures_PIPE_VG,
457 .nr_domains = ARRAY_SIZE(doms_vg),
458 .domains = &doms_vg[0]
462 static unsigned int num_pm_domains(const struct etnaviv_gpu *gpu)
464 unsigned int num = 0, i;
466 for (i = 0; i < ARRAY_SIZE(doms_meta); i++) {
467 const struct etnaviv_pm_domain_meta *meta = &doms_meta[i];
469 if (gpu->identity.features & meta->feature)
470 num += meta->nr_domains;
476 static const struct etnaviv_pm_domain *pm_domain(const struct etnaviv_gpu *gpu,
479 const struct etnaviv_pm_domain *domain = NULL;
480 unsigned int offset = 0, i;
482 for (i = 0; i < ARRAY_SIZE(doms_meta); i++) {
483 const struct etnaviv_pm_domain_meta *meta = &doms_meta[i];
485 if (!(gpu->identity.features & meta->feature))
488 if (index - offset >= meta->nr_domains) {
489 offset += meta->nr_domains;
493 domain = meta->domains + (index - offset);
499 int etnaviv_pm_query_dom(struct etnaviv_gpu *gpu,
500 struct drm_etnaviv_pm_domain *domain)
502 const unsigned int nr_domains = num_pm_domains(gpu);
503 const struct etnaviv_pm_domain *dom;
505 if (domain->iter >= nr_domains)
508 dom = pm_domain(gpu, domain->iter);
512 domain->id = domain->iter;
513 domain->nr_signals = dom->nr_signals;
514 strncpy(domain->name, dom->name, sizeof(domain->name));
517 if (domain->iter == nr_domains)
523 int etnaviv_pm_query_sig(struct etnaviv_gpu *gpu,
524 struct drm_etnaviv_pm_signal *signal)
526 const unsigned int nr_domains = num_pm_domains(gpu);
527 const struct etnaviv_pm_domain *dom;
528 const struct etnaviv_pm_signal *sig;
530 if (signal->domain >= nr_domains)
533 dom = pm_domain(gpu, signal->domain);
537 if (signal->iter >= dom->nr_signals)
540 sig = &dom->signal[signal->iter];
542 signal->id = signal->iter;
543 strncpy(signal->name, sig->name, sizeof(signal->name));
546 if (signal->iter == dom->nr_signals)
547 signal->iter = 0xffff;
552 int etnaviv_pm_req_validate(const struct drm_etnaviv_gem_submit_pmr *r,
555 const struct etnaviv_pm_domain_meta *meta = &doms_meta[exec_state];
556 const struct etnaviv_pm_domain *dom;
558 if (r->domain >= meta->nr_domains)
561 dom = meta->domains + r->domain;
563 if (r->signal >= dom->nr_signals)
569 void etnaviv_perfmon_process(struct etnaviv_gpu *gpu,
570 const struct etnaviv_perfmon_request *pmr, u32 exec_state)
572 const struct etnaviv_pm_domain_meta *meta = &doms_meta[exec_state];
573 const struct etnaviv_pm_domain *dom;
574 const struct etnaviv_pm_signal *sig;
575 u32 *bo = pmr->bo_vma;
578 dom = meta->domains + pmr->domain;
579 sig = &dom->signal[pmr->signal];
580 val = sig->sample(gpu, dom, sig);
582 *(bo + pmr->offset) = val;