1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017 Etnaviv Project
4 * Copyright (C) 2017 Zodiac Inflight Innovations
7 #include "etnaviv_gpu.h"
8 #include "etnaviv_perfmon.h"
9 #include "state_hi.xml.h"
11 struct etnaviv_pm_domain;
13 struct etnaviv_pm_signal {
17 u32 (*sample)(struct etnaviv_gpu *gpu,
18 const struct etnaviv_pm_domain *domain,
19 const struct etnaviv_pm_signal *signal);
22 struct etnaviv_pm_domain {
25 /* profile register */
30 const struct etnaviv_pm_signal *signal;
33 struct etnaviv_pm_domain_meta {
34 const struct etnaviv_pm_domain *domains;
38 static u32 simple_reg_read(struct etnaviv_gpu *gpu,
39 const struct etnaviv_pm_domain *domain,
40 const struct etnaviv_pm_signal *signal)
42 return gpu_read(gpu, signal->data);
45 static u32 perf_reg_read(struct etnaviv_gpu *gpu,
46 const struct etnaviv_pm_domain *domain,
47 const struct etnaviv_pm_signal *signal)
49 gpu_write(gpu, domain->profile_config, signal->data);
51 return gpu_read(gpu, domain->profile_read);
54 static u32 pipe_reg_read(struct etnaviv_gpu *gpu,
55 const struct etnaviv_pm_domain *domain,
56 const struct etnaviv_pm_signal *signal)
58 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
62 for (i = 0; i < gpu->identity.pixel_pipes; i++) {
63 clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK);
64 clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(i);
65 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
66 gpu_write(gpu, domain->profile_config, signal->data);
67 value += gpu_read(gpu, domain->profile_read);
70 /* switch back to pixel pipe 0 to prevent GPU hang */
71 clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK);
72 clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(0);
73 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
78 static const struct etnaviv_pm_domain doms_3d[] = {
81 .profile_read = VIVS_MC_PROFILE_HI_READ,
82 .profile_config = VIVS_MC_PROFILE_CONFIG2,
84 .signal = (const struct etnaviv_pm_signal[]) {
87 VIVS_HI_PROFILE_TOTAL_CYCLES,
92 VIVS_HI_PROFILE_IDLE_CYCLES,
96 "AXI_CYCLES_READ_REQUEST_STALLED",
97 VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED,
101 "AXI_CYCLES_WRITE_REQUEST_STALLED",
102 VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED,
106 "AXI_CYCLES_WRITE_DATA_STALLED",
107 VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED,
114 .profile_read = VIVS_MC_PROFILE_PE_READ,
115 .profile_config = VIVS_MC_PROFILE_CONFIG0,
117 .signal = (const struct etnaviv_pm_signal[]) {
119 "PIXEL_COUNT_KILLED_BY_COLOR_PIPE",
120 VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE,
124 "PIXEL_COUNT_KILLED_BY_DEPTH_PIPE",
125 VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE,
129 "PIXEL_COUNT_DRAWN_BY_COLOR_PIPE",
130 VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE,
134 "PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE",
135 VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE,
142 .profile_read = VIVS_MC_PROFILE_SH_READ,
143 .profile_config = VIVS_MC_PROFILE_CONFIG0,
145 .signal = (const struct etnaviv_pm_signal[]) {
148 VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES,
153 VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER,
157 "RENDERED_PIXEL_COUNTER",
158 VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_PIXEL_COUNTER,
163 VIVS_MC_PROFILE_CONFIG0_SH_VS_INST_COUNTER,
167 "RENDERED_VERTICE_COUNTER",
168 VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_VERTICE_COUNTER,
172 "VTX_BRANCH_INST_COUNTER",
173 VIVS_MC_PROFILE_CONFIG0_SH_VTX_BRANCH_INST_COUNTER,
177 "VTX_TEXLD_INST_COUNTER",
178 VIVS_MC_PROFILE_CONFIG0_SH_VTX_TEXLD_INST_COUNTER,
182 "PXL_BRANCH_INST_COUNTER",
183 VIVS_MC_PROFILE_CONFIG0_SH_PXL_BRANCH_INST_COUNTER,
187 "PXL_TEXLD_INST_COUNTER",
188 VIVS_MC_PROFILE_CONFIG0_SH_PXL_TEXLD_INST_COUNTER,
195 .profile_read = VIVS_MC_PROFILE_PA_READ,
196 .profile_config = VIVS_MC_PROFILE_CONFIG1,
198 .signal = (const struct etnaviv_pm_signal[]) {
201 VIVS_MC_PROFILE_CONFIG1_PA_INPUT_VTX_COUNTER,
205 "INPUT_PRIM_COUNTER",
206 VIVS_MC_PROFILE_CONFIG1_PA_INPUT_PRIM_COUNTER,
210 "OUTPUT_PRIM_COUNTER",
211 VIVS_MC_PROFILE_CONFIG1_PA_OUTPUT_PRIM_COUNTER,
215 "DEPTH_CLIPPED_COUNTER",
216 VIVS_MC_PROFILE_CONFIG1_PA_DEPTH_CLIPPED_COUNTER,
220 "TRIVIAL_REJECTED_COUNTER",
221 VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER,
226 VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER,
233 .profile_read = VIVS_MC_PROFILE_SE_READ,
234 .profile_config = VIVS_MC_PROFILE_CONFIG1,
236 .signal = (const struct etnaviv_pm_signal[]) {
238 "CULLED_TRIANGLE_COUNT",
239 VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT,
243 "CULLED_LINES_COUNT",
244 VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT,
251 .profile_read = VIVS_MC_PROFILE_RA_READ,
252 .profile_config = VIVS_MC_PROFILE_CONFIG1,
254 .signal = (const struct etnaviv_pm_signal[]) {
257 VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT,
262 VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT,
266 "VALID_QUAD_COUNT_AFTER_EARLY_Z",
267 VIVS_MC_PROFILE_CONFIG1_RA_VALID_QUAD_COUNT_AFTER_EARLY_Z,
271 "TOTAL_PRIMITIVE_COUNT",
272 VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_PRIMITIVE_COUNT,
276 "PIPE_CACHE_MISS_COUNTER",
277 VIVS_MC_PROFILE_CONFIG1_RA_PIPE_CACHE_MISS_COUNTER,
281 "PREFETCH_CACHE_MISS_COUNTER",
282 VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER,
287 VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT,
294 .profile_read = VIVS_MC_PROFILE_TX_READ,
295 .profile_config = VIVS_MC_PROFILE_CONFIG1,
297 .signal = (const struct etnaviv_pm_signal[]) {
299 "TOTAL_BILINEAR_REQUESTS",
300 VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS,
304 "TOTAL_TRILINEAR_REQUESTS",
305 VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS,
309 "TOTAL_DISCARDED_TEXTURE_REQUESTS",
310 VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_DISCARDED_TEXTURE_REQUESTS,
314 "TOTAL_TEXTURE_REQUESTS",
315 VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TEXTURE_REQUESTS,
320 VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_COUNT,
324 "MEM_READ_IN_8B_COUNT",
325 VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_IN_8B_COUNT,
330 VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_COUNT,
334 "CACHE_HIT_TEXEL_COUNT",
335 VIVS_MC_PROFILE_CONFIG1_TX_CACHE_HIT_TEXEL_COUNT,
339 "CACHE_MISS_TEXEL_COUNT",
340 VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_TEXEL_COUNT,
347 .profile_read = VIVS_MC_PROFILE_MC_READ,
348 .profile_config = VIVS_MC_PROFILE_CONFIG2,
350 .signal = (const struct etnaviv_pm_signal[]) {
352 "TOTAL_READ_REQ_8B_FROM_PIPELINE",
353 VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE,
357 "TOTAL_READ_REQ_8B_FROM_IP",
358 VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP,
362 "TOTAL_WRITE_REQ_8B_FROM_PIPELINE",
363 VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE,
370 static const struct etnaviv_pm_domain doms_2d[] = {
373 .profile_read = VIVS_MC_PROFILE_PE_READ,
374 .profile_config = VIVS_MC_PROFILE_CONFIG0,
376 .signal = (const struct etnaviv_pm_signal[]) {
378 "PIXELS_RENDERED_2D",
379 VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D,
386 static const struct etnaviv_pm_domain doms_vg[] = {
389 static const struct etnaviv_pm_domain_meta doms_meta[] = {
391 .nr_domains = ARRAY_SIZE(doms_3d),
392 .domains = &doms_3d[0]
395 .nr_domains = ARRAY_SIZE(doms_2d),
396 .domains = &doms_2d[0]
399 .nr_domains = ARRAY_SIZE(doms_vg),
400 .domains = &doms_vg[0]
404 int etnaviv_pm_query_dom(struct etnaviv_gpu *gpu,
405 struct drm_etnaviv_pm_domain *domain)
407 const struct etnaviv_pm_domain_meta *meta = &doms_meta[domain->pipe];
408 const struct etnaviv_pm_domain *dom;
410 if (domain->iter >= meta->nr_domains)
413 dom = meta->domains + domain->iter;
415 domain->id = domain->iter;
416 domain->nr_signals = dom->nr_signals;
417 strncpy(domain->name, dom->name, sizeof(domain->name));
420 if (domain->iter == meta->nr_domains)
426 int etnaviv_pm_query_sig(struct etnaviv_gpu *gpu,
427 struct drm_etnaviv_pm_signal *signal)
429 const struct etnaviv_pm_domain_meta *meta = &doms_meta[signal->pipe];
430 const struct etnaviv_pm_domain *dom;
431 const struct etnaviv_pm_signal *sig;
433 if (signal->domain >= meta->nr_domains)
436 dom = meta->domains + signal->domain;
438 if (signal->iter > dom->nr_signals)
441 sig = &dom->signal[signal->iter];
443 signal->id = signal->iter;
444 strncpy(signal->name, sig->name, sizeof(signal->name));
447 if (signal->iter == dom->nr_signals)
448 signal->iter = 0xffff;
453 int etnaviv_pm_req_validate(const struct drm_etnaviv_gem_submit_pmr *r,
456 const struct etnaviv_pm_domain_meta *meta = &doms_meta[exec_state];
457 const struct etnaviv_pm_domain *dom;
459 if (r->domain >= meta->nr_domains)
462 dom = meta->domains + r->domain;
464 if (r->signal > dom->nr_signals)
470 void etnaviv_perfmon_process(struct etnaviv_gpu *gpu,
471 const struct etnaviv_perfmon_request *pmr, u32 exec_state)
473 const struct etnaviv_pm_domain_meta *meta = &doms_meta[exec_state];
474 const struct etnaviv_pm_domain *dom;
475 const struct etnaviv_pm_signal *sig;
476 u32 *bo = pmr->bo_vma;
479 dom = meta->domains + pmr->domain;
480 sig = &dom->signal[pmr->signal];
481 val = sig->sample(gpu, dom, sig);
483 *(bo + pmr->offset) = val;