Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[linux-2.6-microblaze.git] / drivers / gpu / drm / etnaviv / etnaviv_gpu.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2015-2018 Etnaviv Project
4  */
5
6 #include <linux/clk.h>
7 #include <linux/component.h>
8 #include <linux/delay.h>
9 #include <linux/dma-fence.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/thermal.h>
17
18 #include "etnaviv_cmdbuf.h"
19 #include "etnaviv_dump.h"
20 #include "etnaviv_gpu.h"
21 #include "etnaviv_gem.h"
22 #include "etnaviv_mmu.h"
23 #include "etnaviv_perfmon.h"
24 #include "etnaviv_sched.h"
25 #include "common.xml.h"
26 #include "state.xml.h"
27 #include "state_hi.xml.h"
28 #include "cmdstream.xml.h"
29
30 #ifndef PHYS_OFFSET
31 #define PHYS_OFFSET 0
32 #endif
33
34 static const struct platform_device_id gpu_ids[] = {
35         { .name = "etnaviv-gpu,2d" },
36         { },
37 };
38
39 /*
40  * Driver functions:
41  */
42
43 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
44 {
45         struct etnaviv_drm_private *priv = gpu->drm->dev_private;
46
47         switch (param) {
48         case ETNAVIV_PARAM_GPU_MODEL:
49                 *value = gpu->identity.model;
50                 break;
51
52         case ETNAVIV_PARAM_GPU_REVISION:
53                 *value = gpu->identity.revision;
54                 break;
55
56         case ETNAVIV_PARAM_GPU_FEATURES_0:
57                 *value = gpu->identity.features;
58                 break;
59
60         case ETNAVIV_PARAM_GPU_FEATURES_1:
61                 *value = gpu->identity.minor_features0;
62                 break;
63
64         case ETNAVIV_PARAM_GPU_FEATURES_2:
65                 *value = gpu->identity.minor_features1;
66                 break;
67
68         case ETNAVIV_PARAM_GPU_FEATURES_3:
69                 *value = gpu->identity.minor_features2;
70                 break;
71
72         case ETNAVIV_PARAM_GPU_FEATURES_4:
73                 *value = gpu->identity.minor_features3;
74                 break;
75
76         case ETNAVIV_PARAM_GPU_FEATURES_5:
77                 *value = gpu->identity.minor_features4;
78                 break;
79
80         case ETNAVIV_PARAM_GPU_FEATURES_6:
81                 *value = gpu->identity.minor_features5;
82                 break;
83
84         case ETNAVIV_PARAM_GPU_FEATURES_7:
85                 *value = gpu->identity.minor_features6;
86                 break;
87
88         case ETNAVIV_PARAM_GPU_FEATURES_8:
89                 *value = gpu->identity.minor_features7;
90                 break;
91
92         case ETNAVIV_PARAM_GPU_FEATURES_9:
93                 *value = gpu->identity.minor_features8;
94                 break;
95
96         case ETNAVIV_PARAM_GPU_FEATURES_10:
97                 *value = gpu->identity.minor_features9;
98                 break;
99
100         case ETNAVIV_PARAM_GPU_FEATURES_11:
101                 *value = gpu->identity.minor_features10;
102                 break;
103
104         case ETNAVIV_PARAM_GPU_FEATURES_12:
105                 *value = gpu->identity.minor_features11;
106                 break;
107
108         case ETNAVIV_PARAM_GPU_STREAM_COUNT:
109                 *value = gpu->identity.stream_count;
110                 break;
111
112         case ETNAVIV_PARAM_GPU_REGISTER_MAX:
113                 *value = gpu->identity.register_max;
114                 break;
115
116         case ETNAVIV_PARAM_GPU_THREAD_COUNT:
117                 *value = gpu->identity.thread_count;
118                 break;
119
120         case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
121                 *value = gpu->identity.vertex_cache_size;
122                 break;
123
124         case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
125                 *value = gpu->identity.shader_core_count;
126                 break;
127
128         case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
129                 *value = gpu->identity.pixel_pipes;
130                 break;
131
132         case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
133                 *value = gpu->identity.vertex_output_buffer_size;
134                 break;
135
136         case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
137                 *value = gpu->identity.buffer_size;
138                 break;
139
140         case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
141                 *value = gpu->identity.instruction_count;
142                 break;
143
144         case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
145                 *value = gpu->identity.num_constants;
146                 break;
147
148         case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
149                 *value = gpu->identity.varyings_count;
150                 break;
151
152         case ETNAVIV_PARAM_SOFTPIN_START_ADDR:
153                 if (priv->mmu_global->version == ETNAVIV_IOMMU_V2)
154                         *value = ETNAVIV_SOFTPIN_START_ADDRESS;
155                 else
156                         *value = ~0ULL;
157                 break;
158
159         default:
160                 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
161                 return -EINVAL;
162         }
163
164         return 0;
165 }
166
167
168 #define etnaviv_is_model_rev(gpu, mod, rev) \
169         ((gpu)->identity.model == chipModel_##mod && \
170          (gpu)->identity.revision == rev)
171 #define etnaviv_field(val, field) \
172         (((val) & field##__MASK) >> field##__SHIFT)
173
174 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
175 {
176         if (gpu->identity.minor_features0 &
177             chipMinorFeatures0_MORE_MINOR_FEATURES) {
178                 u32 specs[4];
179                 unsigned int streams;
180
181                 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
182                 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
183                 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
184                 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
185
186                 gpu->identity.stream_count = etnaviv_field(specs[0],
187                                         VIVS_HI_CHIP_SPECS_STREAM_COUNT);
188                 gpu->identity.register_max = etnaviv_field(specs[0],
189                                         VIVS_HI_CHIP_SPECS_REGISTER_MAX);
190                 gpu->identity.thread_count = etnaviv_field(specs[0],
191                                         VIVS_HI_CHIP_SPECS_THREAD_COUNT);
192                 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
193                                         VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
194                 gpu->identity.shader_core_count = etnaviv_field(specs[0],
195                                         VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
196                 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
197                                         VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
198                 gpu->identity.vertex_output_buffer_size =
199                         etnaviv_field(specs[0],
200                                 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
201
202                 gpu->identity.buffer_size = etnaviv_field(specs[1],
203                                         VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
204                 gpu->identity.instruction_count = etnaviv_field(specs[1],
205                                         VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
206                 gpu->identity.num_constants = etnaviv_field(specs[1],
207                                         VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
208
209                 gpu->identity.varyings_count = etnaviv_field(specs[2],
210                                         VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
211
212                 /* This overrides the value from older register if non-zero */
213                 streams = etnaviv_field(specs[3],
214                                         VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
215                 if (streams)
216                         gpu->identity.stream_count = streams;
217         }
218
219         /* Fill in the stream count if not specified */
220         if (gpu->identity.stream_count == 0) {
221                 if (gpu->identity.model >= 0x1000)
222                         gpu->identity.stream_count = 4;
223                 else
224                         gpu->identity.stream_count = 1;
225         }
226
227         /* Convert the register max value */
228         if (gpu->identity.register_max)
229                 gpu->identity.register_max = 1 << gpu->identity.register_max;
230         else if (gpu->identity.model == chipModel_GC400)
231                 gpu->identity.register_max = 32;
232         else
233                 gpu->identity.register_max = 64;
234
235         /* Convert thread count */
236         if (gpu->identity.thread_count)
237                 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
238         else if (gpu->identity.model == chipModel_GC400)
239                 gpu->identity.thread_count = 64;
240         else if (gpu->identity.model == chipModel_GC500 ||
241                  gpu->identity.model == chipModel_GC530)
242                 gpu->identity.thread_count = 128;
243         else
244                 gpu->identity.thread_count = 256;
245
246         if (gpu->identity.vertex_cache_size == 0)
247                 gpu->identity.vertex_cache_size = 8;
248
249         if (gpu->identity.shader_core_count == 0) {
250                 if (gpu->identity.model >= 0x1000)
251                         gpu->identity.shader_core_count = 2;
252                 else
253                         gpu->identity.shader_core_count = 1;
254         }
255
256         if (gpu->identity.pixel_pipes == 0)
257                 gpu->identity.pixel_pipes = 1;
258
259         /* Convert virtex buffer size */
260         if (gpu->identity.vertex_output_buffer_size) {
261                 gpu->identity.vertex_output_buffer_size =
262                         1 << gpu->identity.vertex_output_buffer_size;
263         } else if (gpu->identity.model == chipModel_GC400) {
264                 if (gpu->identity.revision < 0x4000)
265                         gpu->identity.vertex_output_buffer_size = 512;
266                 else if (gpu->identity.revision < 0x4200)
267                         gpu->identity.vertex_output_buffer_size = 256;
268                 else
269                         gpu->identity.vertex_output_buffer_size = 128;
270         } else {
271                 gpu->identity.vertex_output_buffer_size = 512;
272         }
273
274         switch (gpu->identity.instruction_count) {
275         case 0:
276                 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
277                     gpu->identity.model == chipModel_GC880)
278                         gpu->identity.instruction_count = 512;
279                 else
280                         gpu->identity.instruction_count = 256;
281                 break;
282
283         case 1:
284                 gpu->identity.instruction_count = 1024;
285                 break;
286
287         case 2:
288                 gpu->identity.instruction_count = 2048;
289                 break;
290
291         default:
292                 gpu->identity.instruction_count = 256;
293                 break;
294         }
295
296         if (gpu->identity.num_constants == 0)
297                 gpu->identity.num_constants = 168;
298
299         if (gpu->identity.varyings_count == 0) {
300                 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
301                         gpu->identity.varyings_count = 12;
302                 else
303                         gpu->identity.varyings_count = 8;
304         }
305
306         /*
307          * For some cores, two varyings are consumed for position, so the
308          * maximum varying count needs to be reduced by one.
309          */
310         if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
311             etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
312             etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
313             etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
314             etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
315             etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
316             etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
317             etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
318             etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
319             etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
320             etnaviv_is_model_rev(gpu, GC880, 0x5106))
321                 gpu->identity.varyings_count -= 1;
322 }
323
324 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
325 {
326         u32 chipIdentity;
327
328         chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
329
330         /* Special case for older graphic cores. */
331         if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
332                 gpu->identity.model    = chipModel_GC500;
333                 gpu->identity.revision = etnaviv_field(chipIdentity,
334                                          VIVS_HI_CHIP_IDENTITY_REVISION);
335         } else {
336                 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
337
338                 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
339                 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
340                 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID);
341
342                 /*
343                  * Reading these two registers on GC600 rev 0x19 result in a
344                  * unhandled fault: external abort on non-linefetch
345                  */
346                 if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) {
347                         gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);
348                         gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);
349                 }
350
351                 /*
352                  * !!!! HACK ALERT !!!!
353                  * Because people change device IDs without letting software
354                  * know about it - here is the hack to make it all look the
355                  * same.  Only for GC400 family.
356                  */
357                 if ((gpu->identity.model & 0xff00) == 0x0400 &&
358                     gpu->identity.model != chipModel_GC420) {
359                         gpu->identity.model = gpu->identity.model & 0x0400;
360                 }
361
362                 /* Another special case */
363                 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
364                         u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
365
366                         if (chipDate == 0x20080814 && chipTime == 0x12051100) {
367                                 /*
368                                  * This IP has an ECO; put the correct
369                                  * revision in it.
370                                  */
371                                 gpu->identity.revision = 0x1051;
372                         }
373                 }
374
375                 /*
376                  * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
377                  * reality it's just a re-branded GC3000. We can identify this
378                  * core by the upper half of the revision register being all 1.
379                  * Fix model/rev here, so all other places can refer to this
380                  * core by its real identity.
381                  */
382                 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
383                         gpu->identity.model = chipModel_GC3000;
384                         gpu->identity.revision &= 0xffff;
385                 }
386
387                 if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617))
388                         gpu->identity.eco_id = 1;
389
390                 if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511))
391                         gpu->identity.eco_id = 1;
392         }
393
394         dev_info(gpu->dev, "model: GC%x, revision: %x\n",
395                  gpu->identity.model, gpu->identity.revision);
396
397         gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
398         /*
399          * If there is a match in the HWDB, we aren't interested in the
400          * remaining register values, as they might be wrong.
401          */
402         if (etnaviv_fill_identity_from_hwdb(gpu))
403                 return;
404
405         gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
406
407         /* Disable fast clear on GC700. */
408         if (gpu->identity.model == chipModel_GC700)
409                 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
410
411         if ((gpu->identity.model == chipModel_GC500 &&
412              gpu->identity.revision < 2) ||
413             (gpu->identity.model == chipModel_GC300 &&
414              gpu->identity.revision < 0x2000)) {
415
416                 /*
417                  * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
418                  * registers.
419                  */
420                 gpu->identity.minor_features0 = 0;
421                 gpu->identity.minor_features1 = 0;
422                 gpu->identity.minor_features2 = 0;
423                 gpu->identity.minor_features3 = 0;
424                 gpu->identity.minor_features4 = 0;
425                 gpu->identity.minor_features5 = 0;
426         } else
427                 gpu->identity.minor_features0 =
428                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
429
430         if (gpu->identity.minor_features0 &
431             chipMinorFeatures0_MORE_MINOR_FEATURES) {
432                 gpu->identity.minor_features1 =
433                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
434                 gpu->identity.minor_features2 =
435                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
436                 gpu->identity.minor_features3 =
437                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
438                 gpu->identity.minor_features4 =
439                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
440                 gpu->identity.minor_features5 =
441                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
442         }
443
444         /* GC600 idle register reports zero bits where modules aren't present */
445         if (gpu->identity.model == chipModel_GC600)
446                 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
447                                  VIVS_HI_IDLE_STATE_RA |
448                                  VIVS_HI_IDLE_STATE_SE |
449                                  VIVS_HI_IDLE_STATE_PA |
450                                  VIVS_HI_IDLE_STATE_SH |
451                                  VIVS_HI_IDLE_STATE_PE |
452                                  VIVS_HI_IDLE_STATE_DE |
453                                  VIVS_HI_IDLE_STATE_FE;
454
455         etnaviv_hw_specs(gpu);
456 }
457
458 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
459 {
460         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
461                   VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
462         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
463 }
464
465 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
466 {
467         if (gpu->identity.minor_features2 &
468             chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
469                 clk_set_rate(gpu->clk_core,
470                              gpu->base_rate_core >> gpu->freq_scale);
471                 clk_set_rate(gpu->clk_shader,
472                              gpu->base_rate_shader >> gpu->freq_scale);
473         } else {
474                 unsigned int fscale = 1 << (6 - gpu->freq_scale);
475                 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
476
477                 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
478                 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
479                 etnaviv_gpu_load_clock(gpu, clock);
480         }
481 }
482
483 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
484 {
485         u32 control, idle;
486         unsigned long timeout;
487         bool failed = true;
488
489         /* We hope that the GPU resets in under one second */
490         timeout = jiffies + msecs_to_jiffies(1000);
491
492         while (time_is_after_jiffies(timeout)) {
493                 /* enable clock */
494                 unsigned int fscale = 1 << (6 - gpu->freq_scale);
495                 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
496                 etnaviv_gpu_load_clock(gpu, control);
497
498                 /* isolate the GPU. */
499                 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
500                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
501
502                 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
503                         gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
504                                   VIVS_MMUv2_AHB_CONTROL_RESET);
505                 } else {
506                         /* set soft reset. */
507                         control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
508                         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
509                 }
510
511                 /* wait for reset. */
512                 usleep_range(10, 20);
513
514                 /* reset soft reset bit. */
515                 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
516                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
517
518                 /* reset GPU isolation. */
519                 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
520                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
521
522                 /* read idle register. */
523                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
524
525                 /* try resetting again if FE is not idle */
526                 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
527                         dev_dbg(gpu->dev, "FE is not idle\n");
528                         continue;
529                 }
530
531                 /* read reset register. */
532                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
533
534                 /* is the GPU idle? */
535                 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
536                     ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
537                         dev_dbg(gpu->dev, "GPU is not idle\n");
538                         continue;
539                 }
540
541                 /* disable debug registers, as they are not normally needed */
542                 control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
543                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
544
545                 failed = false;
546                 break;
547         }
548
549         if (failed) {
550                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
551                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
552
553                 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
554                         idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
555                         control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
556                         control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
557
558                 return -EBUSY;
559         }
560
561         /* We rely on the GPU running, so program the clock */
562         etnaviv_gpu_update_clock(gpu);
563
564         return 0;
565 }
566
567 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
568 {
569         u32 pmc, ppc;
570
571         /* enable clock gating */
572         ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
573         ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
574
575         /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
576         if (gpu->identity.revision == 0x4301 ||
577             gpu->identity.revision == 0x4302)
578                 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
579
580         gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
581
582         pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
583
584         /* Disable PA clock gating for GC400+ without bugfix except for GC420 */
585         if (gpu->identity.model >= chipModel_GC400 &&
586             gpu->identity.model != chipModel_GC420 &&
587             !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
588                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
589
590         /*
591          * Disable PE clock gating on revs < 5.0.0.0 when HZ is
592          * present without a bug fix.
593          */
594         if (gpu->identity.revision < 0x5000 &&
595             gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
596             !(gpu->identity.minor_features1 &
597               chipMinorFeatures1_DISABLE_PE_GATING))
598                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
599
600         if (gpu->identity.revision < 0x5422)
601                 pmc |= BIT(15); /* Unknown bit */
602
603         /* Disable TX clock gating on affected core revisions. */
604         if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
605             etnaviv_is_model_rev(gpu, GC2000, 0x5108))
606                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
607
608         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
609         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
610
611         gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
612 }
613
614 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
615 {
616         gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
617         gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
618                   VIVS_FE_COMMAND_CONTROL_ENABLE |
619                   VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
620
621         if (gpu->sec_mode == ETNA_SEC_KERNEL) {
622                 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
623                           VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
624                           VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
625         }
626 }
627
628 static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu)
629 {
630         u32 address = etnaviv_cmdbuf_get_va(&gpu->buffer,
631                                 &gpu->mmu_context->cmdbuf_mapping);
632         u16 prefetch;
633
634         /* setup the MMU */
635         etnaviv_iommu_restore(gpu, gpu->mmu_context);
636
637         /* Start command processor */
638         prefetch = etnaviv_buffer_init(gpu);
639
640         etnaviv_gpu_start_fe(gpu, address, prefetch);
641 }
642
643 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
644 {
645         /*
646          * Base value for VIVS_PM_PULSE_EATER register on models where it
647          * cannot be read, extracted from vivante kernel driver.
648          */
649         u32 pulse_eater = 0x01590880;
650
651         if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
652             etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
653                 pulse_eater |= BIT(23);
654
655         }
656
657         if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
658             etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
659                 pulse_eater &= ~BIT(16);
660                 pulse_eater |= BIT(17);
661         }
662
663         if ((gpu->identity.revision > 0x5420) &&
664             (gpu->identity.features & chipFeatures_PIPE_3D))
665         {
666                 /* Performance fix: disable internal DFS */
667                 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);
668                 pulse_eater |= BIT(18);
669         }
670
671         gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
672 }
673
674 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
675 {
676         if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
677              etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
678             gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
679                 u32 mc_memory_debug;
680
681                 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
682
683                 if (gpu->identity.revision == 0x5007)
684                         mc_memory_debug |= 0x0c;
685                 else
686                         mc_memory_debug |= 0x08;
687
688                 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
689         }
690
691         /* enable module-level clock gating */
692         etnaviv_gpu_enable_mlcg(gpu);
693
694         /*
695          * Update GPU AXI cache atttribute to "cacheable, no allocate".
696          * This is necessary to prevent the iMX6 SoC locking up.
697          */
698         gpu_write(gpu, VIVS_HI_AXI_CONFIG,
699                   VIVS_HI_AXI_CONFIG_AWCACHE(2) |
700                   VIVS_HI_AXI_CONFIG_ARCACHE(2));
701
702         /* GC2000 rev 5108 needs a special bus config */
703         if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
704                 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
705                 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
706                                 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
707                 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
708                               VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
709                 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
710         }
711
712         if (gpu->sec_mode == ETNA_SEC_KERNEL) {
713                 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
714                 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
715                 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
716         }
717
718         /* setup the pulse eater */
719         etnaviv_gpu_setup_pulse_eater(gpu);
720
721         gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
722 }
723
724 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
725 {
726         struct etnaviv_drm_private *priv = gpu->drm->dev_private;
727         int ret, i;
728
729         ret = pm_runtime_get_sync(gpu->dev);
730         if (ret < 0) {
731                 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
732                 goto pm_put;
733         }
734
735         etnaviv_hw_identify(gpu);
736
737         if (gpu->identity.model == 0) {
738                 dev_err(gpu->dev, "Unknown GPU model\n");
739                 ret = -ENXIO;
740                 goto fail;
741         }
742
743         /* Exclude VG cores with FE2.0 */
744         if (gpu->identity.features & chipFeatures_PIPE_VG &&
745             gpu->identity.features & chipFeatures_FE20) {
746                 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
747                 ret = -ENXIO;
748                 goto fail;
749         }
750
751         /*
752          * On cores with security features supported, we claim control over the
753          * security states.
754          */
755         if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
756             (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
757                 gpu->sec_mode = ETNA_SEC_KERNEL;
758
759         ret = etnaviv_hw_reset(gpu);
760         if (ret) {
761                 dev_err(gpu->dev, "GPU reset failed\n");
762                 goto fail;
763         }
764
765         ret = etnaviv_iommu_global_init(gpu);
766         if (ret)
767                 goto fail;
768
769         /*
770          * Set the GPU linear window to be at the end of the DMA window, where
771          * the CMA area is likely to reside. This ensures that we are able to
772          * map the command buffers while having the linear window overlap as
773          * much RAM as possible, so we can optimize mappings for other buffers.
774          *
775          * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads
776          * to different views of the memory on the individual engines.
777          */
778         if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
779             (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
780                 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev);
781                 if (dma_mask < PHYS_OFFSET + SZ_2G)
782                         priv->mmu_global->memory_base = PHYS_OFFSET;
783                 else
784                         priv->mmu_global->memory_base = dma_mask - SZ_2G + 1;
785         } else if (PHYS_OFFSET >= SZ_2G) {
786                 dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n");
787                 priv->mmu_global->memory_base = PHYS_OFFSET;
788                 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
789         }
790
791         /*
792          * If the GPU is part of a system with DMA addressing limitations,
793          * request pages for our SHM backend buffers from the DMA32 zone to
794          * hopefully avoid performance killing SWIOTLB bounce buffering.
795          */
796         if (dma_addressing_limited(gpu->dev))
797                 priv->shm_gfp_mask |= GFP_DMA32;
798
799         /* Create buffer: */
800         ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer,
801                                   PAGE_SIZE);
802         if (ret) {
803                 dev_err(gpu->dev, "could not create command buffer\n");
804                 goto fail;
805         }
806
807         /* Setup event management */
808         spin_lock_init(&gpu->event_spinlock);
809         init_completion(&gpu->event_free);
810         bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
811         for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
812                 complete(&gpu->event_free);
813
814         /* Now program the hardware */
815         mutex_lock(&gpu->lock);
816         etnaviv_gpu_hw_init(gpu);
817         gpu->exec_state = -1;
818         mutex_unlock(&gpu->lock);
819
820         pm_runtime_mark_last_busy(gpu->dev);
821         pm_runtime_put_autosuspend(gpu->dev);
822
823         gpu->initialized = true;
824
825         return 0;
826
827 fail:
828         pm_runtime_mark_last_busy(gpu->dev);
829 pm_put:
830         pm_runtime_put_autosuspend(gpu->dev);
831
832         return ret;
833 }
834
835 #ifdef CONFIG_DEBUG_FS
836 struct dma_debug {
837         u32 address[2];
838         u32 state[2];
839 };
840
841 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
842 {
843         u32 i;
844
845         debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
846         debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
847
848         for (i = 0; i < 500; i++) {
849                 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
850                 debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
851
852                 if (debug->address[0] != debug->address[1])
853                         break;
854
855                 if (debug->state[0] != debug->state[1])
856                         break;
857         }
858 }
859
860 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
861 {
862         struct dma_debug debug;
863         u32 dma_lo, dma_hi, axi, idle;
864         int ret;
865
866         seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
867
868         ret = pm_runtime_get_sync(gpu->dev);
869         if (ret < 0)
870                 goto pm_put;
871
872         dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
873         dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
874         axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
875         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
876
877         verify_dma(gpu, &debug);
878
879         seq_puts(m, "\tidentity\n");
880         seq_printf(m, "\t model: 0x%x\n", gpu->identity.model);
881         seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision);
882         seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id);
883         seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id);
884         seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id);
885
886         seq_puts(m, "\tfeatures\n");
887         seq_printf(m, "\t major_features: 0x%08x\n",
888                    gpu->identity.features);
889         seq_printf(m, "\t minor_features0: 0x%08x\n",
890                    gpu->identity.minor_features0);
891         seq_printf(m, "\t minor_features1: 0x%08x\n",
892                    gpu->identity.minor_features1);
893         seq_printf(m, "\t minor_features2: 0x%08x\n",
894                    gpu->identity.minor_features2);
895         seq_printf(m, "\t minor_features3: 0x%08x\n",
896                    gpu->identity.minor_features3);
897         seq_printf(m, "\t minor_features4: 0x%08x\n",
898                    gpu->identity.minor_features4);
899         seq_printf(m, "\t minor_features5: 0x%08x\n",
900                    gpu->identity.minor_features5);
901         seq_printf(m, "\t minor_features6: 0x%08x\n",
902                    gpu->identity.minor_features6);
903         seq_printf(m, "\t minor_features7: 0x%08x\n",
904                    gpu->identity.minor_features7);
905         seq_printf(m, "\t minor_features8: 0x%08x\n",
906                    gpu->identity.minor_features8);
907         seq_printf(m, "\t minor_features9: 0x%08x\n",
908                    gpu->identity.minor_features9);
909         seq_printf(m, "\t minor_features10: 0x%08x\n",
910                    gpu->identity.minor_features10);
911         seq_printf(m, "\t minor_features11: 0x%08x\n",
912                    gpu->identity.minor_features11);
913
914         seq_puts(m, "\tspecs\n");
915         seq_printf(m, "\t stream_count:  %d\n",
916                         gpu->identity.stream_count);
917         seq_printf(m, "\t register_max: %d\n",
918                         gpu->identity.register_max);
919         seq_printf(m, "\t thread_count: %d\n",
920                         gpu->identity.thread_count);
921         seq_printf(m, "\t vertex_cache_size: %d\n",
922                         gpu->identity.vertex_cache_size);
923         seq_printf(m, "\t shader_core_count: %d\n",
924                         gpu->identity.shader_core_count);
925         seq_printf(m, "\t pixel_pipes: %d\n",
926                         gpu->identity.pixel_pipes);
927         seq_printf(m, "\t vertex_output_buffer_size: %d\n",
928                         gpu->identity.vertex_output_buffer_size);
929         seq_printf(m, "\t buffer_size: %d\n",
930                         gpu->identity.buffer_size);
931         seq_printf(m, "\t instruction_count: %d\n",
932                         gpu->identity.instruction_count);
933         seq_printf(m, "\t num_constants: %d\n",
934                         gpu->identity.num_constants);
935         seq_printf(m, "\t varyings_count: %d\n",
936                         gpu->identity.varyings_count);
937
938         seq_printf(m, "\taxi: 0x%08x\n", axi);
939         seq_printf(m, "\tidle: 0x%08x\n", idle);
940         idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
941         if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
942                 seq_puts(m, "\t FE is not idle\n");
943         if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
944                 seq_puts(m, "\t DE is not idle\n");
945         if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
946                 seq_puts(m, "\t PE is not idle\n");
947         if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
948                 seq_puts(m, "\t SH is not idle\n");
949         if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
950                 seq_puts(m, "\t PA is not idle\n");
951         if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
952                 seq_puts(m, "\t SE is not idle\n");
953         if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
954                 seq_puts(m, "\t RA is not idle\n");
955         if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
956                 seq_puts(m, "\t TX is not idle\n");
957         if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
958                 seq_puts(m, "\t VG is not idle\n");
959         if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
960                 seq_puts(m, "\t IM is not idle\n");
961         if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
962                 seq_puts(m, "\t FP is not idle\n");
963         if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
964                 seq_puts(m, "\t TS is not idle\n");
965         if ((idle & VIVS_HI_IDLE_STATE_BL) == 0)
966                 seq_puts(m, "\t BL is not idle\n");
967         if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0)
968                 seq_puts(m, "\t ASYNCFE is not idle\n");
969         if ((idle & VIVS_HI_IDLE_STATE_MC) == 0)
970                 seq_puts(m, "\t MC is not idle\n");
971         if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0)
972                 seq_puts(m, "\t PPA is not idle\n");
973         if ((idle & VIVS_HI_IDLE_STATE_WD) == 0)
974                 seq_puts(m, "\t WD is not idle\n");
975         if ((idle & VIVS_HI_IDLE_STATE_NN) == 0)
976                 seq_puts(m, "\t NN is not idle\n");
977         if ((idle & VIVS_HI_IDLE_STATE_TP) == 0)
978                 seq_puts(m, "\t TP is not idle\n");
979         if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
980                 seq_puts(m, "\t AXI low power mode\n");
981
982         if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
983                 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
984                 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
985                 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
986
987                 seq_puts(m, "\tMC\n");
988                 seq_printf(m, "\t read0: 0x%08x\n", read0);
989                 seq_printf(m, "\t read1: 0x%08x\n", read1);
990                 seq_printf(m, "\t write: 0x%08x\n", write);
991         }
992
993         seq_puts(m, "\tDMA ");
994
995         if (debug.address[0] == debug.address[1] &&
996             debug.state[0] == debug.state[1]) {
997                 seq_puts(m, "seems to be stuck\n");
998         } else if (debug.address[0] == debug.address[1]) {
999                 seq_puts(m, "address is constant\n");
1000         } else {
1001                 seq_puts(m, "is running\n");
1002         }
1003
1004         seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
1005         seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
1006         seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
1007         seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
1008         seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
1009                    dma_lo, dma_hi);
1010
1011         ret = 0;
1012
1013         pm_runtime_mark_last_busy(gpu->dev);
1014 pm_put:
1015         pm_runtime_put_autosuspend(gpu->dev);
1016
1017         return ret;
1018 }
1019 #endif
1020
1021 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu)
1022 {
1023         unsigned int i = 0;
1024
1025         dev_err(gpu->dev, "recover hung GPU!\n");
1026
1027         if (pm_runtime_get_sync(gpu->dev) < 0)
1028                 goto pm_put;
1029
1030         mutex_lock(&gpu->lock);
1031
1032         etnaviv_hw_reset(gpu);
1033
1034         /* complete all events, the GPU won't do it after the reset */
1035         spin_lock(&gpu->event_spinlock);
1036         for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS)
1037                 complete(&gpu->event_free);
1038         bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
1039         spin_unlock(&gpu->event_spinlock);
1040
1041         etnaviv_gpu_hw_init(gpu);
1042         gpu->exec_state = -1;
1043         gpu->mmu_context = NULL;
1044
1045         mutex_unlock(&gpu->lock);
1046         pm_runtime_mark_last_busy(gpu->dev);
1047 pm_put:
1048         pm_runtime_put_autosuspend(gpu->dev);
1049 }
1050
1051 /* fence object management */
1052 struct etnaviv_fence {
1053         struct etnaviv_gpu *gpu;
1054         struct dma_fence base;
1055 };
1056
1057 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
1058 {
1059         return container_of(fence, struct etnaviv_fence, base);
1060 }
1061
1062 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
1063 {
1064         return "etnaviv";
1065 }
1066
1067 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
1068 {
1069         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1070
1071         return dev_name(f->gpu->dev);
1072 }
1073
1074 static bool etnaviv_fence_signaled(struct dma_fence *fence)
1075 {
1076         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1077
1078         return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0;
1079 }
1080
1081 static void etnaviv_fence_release(struct dma_fence *fence)
1082 {
1083         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1084
1085         kfree_rcu(f, base.rcu);
1086 }
1087
1088 static const struct dma_fence_ops etnaviv_fence_ops = {
1089         .get_driver_name = etnaviv_fence_get_driver_name,
1090         .get_timeline_name = etnaviv_fence_get_timeline_name,
1091         .signaled = etnaviv_fence_signaled,
1092         .release = etnaviv_fence_release,
1093 };
1094
1095 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1096 {
1097         struct etnaviv_fence *f;
1098
1099         /*
1100          * GPU lock must already be held, otherwise fence completion order might
1101          * not match the seqno order assigned here.
1102          */
1103         lockdep_assert_held(&gpu->lock);
1104
1105         f = kzalloc(sizeof(*f), GFP_KERNEL);
1106         if (!f)
1107                 return NULL;
1108
1109         f->gpu = gpu;
1110
1111         dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1112                        gpu->fence_context, ++gpu->next_fence);
1113
1114         return &f->base;
1115 }
1116
1117 /* returns true if fence a comes after fence b */
1118 static inline bool fence_after(u32 a, u32 b)
1119 {
1120         return (s32)(a - b) > 0;
1121 }
1122
1123 /*
1124  * event management:
1125  */
1126
1127 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1128         unsigned int *events)
1129 {
1130         unsigned long timeout = msecs_to_jiffies(10 * 10000);
1131         unsigned i, acquired = 0;
1132
1133         for (i = 0; i < nr_events; i++) {
1134                 unsigned long ret;
1135
1136                 ret = wait_for_completion_timeout(&gpu->event_free, timeout);
1137
1138                 if (!ret) {
1139                         dev_err(gpu->dev, "wait_for_completion_timeout failed");
1140                         goto out;
1141                 }
1142
1143                 acquired++;
1144                 timeout = ret;
1145         }
1146
1147         spin_lock(&gpu->event_spinlock);
1148
1149         for (i = 0; i < nr_events; i++) {
1150                 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1151
1152                 events[i] = event;
1153                 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
1154                 set_bit(event, gpu->event_bitmap);
1155         }
1156
1157         spin_unlock(&gpu->event_spinlock);
1158
1159         return 0;
1160
1161 out:
1162         for (i = 0; i < acquired; i++)
1163                 complete(&gpu->event_free);
1164
1165         return -EBUSY;
1166 }
1167
1168 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1169 {
1170         if (!test_bit(event, gpu->event_bitmap)) {
1171                 dev_warn(gpu->dev, "event %u is already marked as free",
1172                          event);
1173         } else {
1174                 clear_bit(event, gpu->event_bitmap);
1175                 complete(&gpu->event_free);
1176         }
1177 }
1178
1179 /*
1180  * Cmdstream submission/retirement:
1181  */
1182 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1183         u32 id, struct drm_etnaviv_timespec *timeout)
1184 {
1185         struct dma_fence *fence;
1186         int ret;
1187
1188         /*
1189          * Look up the fence and take a reference. We might still find a fence
1190          * whose refcount has already dropped to zero. dma_fence_get_rcu
1191          * pretends we didn't find a fence in that case.
1192          */
1193         rcu_read_lock();
1194         fence = idr_find(&gpu->fence_idr, id);
1195         if (fence)
1196                 fence = dma_fence_get_rcu(fence);
1197         rcu_read_unlock();
1198
1199         if (!fence)
1200                 return 0;
1201
1202         if (!timeout) {
1203                 /* No timeout was requested: just test for completion */
1204                 ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
1205         } else {
1206                 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1207
1208                 ret = dma_fence_wait_timeout(fence, true, remaining);
1209                 if (ret == 0)
1210                         ret = -ETIMEDOUT;
1211                 else if (ret != -ERESTARTSYS)
1212                         ret = 0;
1213
1214         }
1215
1216         dma_fence_put(fence);
1217         return ret;
1218 }
1219
1220 /*
1221  * Wait for an object to become inactive.  This, on it's own, is not race
1222  * free: the object is moved by the scheduler off the active list, and
1223  * then the iova is put.  Moreover, the object could be re-submitted just
1224  * after we notice that it's become inactive.
1225  *
1226  * Although the retirement happens under the gpu lock, we don't want to hold
1227  * that lock in this function while waiting.
1228  */
1229 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1230         struct etnaviv_gem_object *etnaviv_obj,
1231         struct drm_etnaviv_timespec *timeout)
1232 {
1233         unsigned long remaining;
1234         long ret;
1235
1236         if (!timeout)
1237                 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1238
1239         remaining = etnaviv_timeout_to_jiffies(timeout);
1240
1241         ret = wait_event_interruptible_timeout(gpu->fence_event,
1242                                                !is_active(etnaviv_obj),
1243                                                remaining);
1244         if (ret > 0)
1245                 return 0;
1246         else if (ret == -ERESTARTSYS)
1247                 return -ERESTARTSYS;
1248         else
1249                 return -ETIMEDOUT;
1250 }
1251
1252 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1253         struct etnaviv_event *event, unsigned int flags)
1254 {
1255         const struct etnaviv_gem_submit *submit = event->submit;
1256         unsigned int i;
1257
1258         for (i = 0; i < submit->nr_pmrs; i++) {
1259                 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1260
1261                 if (pmr->flags == flags)
1262                         etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
1263         }
1264 }
1265
1266 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1267         struct etnaviv_event *event)
1268 {
1269         u32 val;
1270
1271         /* disable clock gating */
1272         val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1273         val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1274         gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1275
1276         /* enable debug register */
1277         val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1278         val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1279         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1280
1281         sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
1282 }
1283
1284 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1285         struct etnaviv_event *event)
1286 {
1287         const struct etnaviv_gem_submit *submit = event->submit;
1288         unsigned int i;
1289         u32 val;
1290
1291         sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1292
1293         for (i = 0; i < submit->nr_pmrs; i++) {
1294                 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1295
1296                 *pmr->bo_vma = pmr->sequence;
1297         }
1298
1299         /* disable debug register */
1300         val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1301         val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1302         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1303
1304         /* enable clock gating */
1305         val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1306         val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1307         gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1308 }
1309
1310
1311 /* add bo's to gpu's ring, and kick gpu: */
1312 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
1313 {
1314         struct etnaviv_gpu *gpu = submit->gpu;
1315         struct dma_fence *gpu_fence;
1316         unsigned int i, nr_events = 1, event[3];
1317         int ret;
1318
1319         if (!submit->runtime_resumed) {
1320                 ret = pm_runtime_get_sync(gpu->dev);
1321                 if (ret < 0) {
1322                         pm_runtime_put_noidle(gpu->dev);
1323                         return NULL;
1324                 }
1325                 submit->runtime_resumed = true;
1326         }
1327
1328         /*
1329          * if there are performance monitor requests we need to have
1330          * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
1331          *   requests.
1332          * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
1333          *   and update the sequence number for userspace.
1334          */
1335         if (submit->nr_pmrs)
1336                 nr_events = 3;
1337
1338         ret = event_alloc(gpu, nr_events, event);
1339         if (ret) {
1340                 DRM_ERROR("no free events\n");
1341                 pm_runtime_put_noidle(gpu->dev);
1342                 return NULL;
1343         }
1344
1345         mutex_lock(&gpu->lock);
1346
1347         gpu_fence = etnaviv_gpu_fence_alloc(gpu);
1348         if (!gpu_fence) {
1349                 for (i = 0; i < nr_events; i++)
1350                         event_free(gpu, event[i]);
1351
1352                 goto out_unlock;
1353         }
1354
1355         if (!gpu->mmu_context) {
1356                 etnaviv_iommu_context_get(submit->mmu_context);
1357                 gpu->mmu_context = submit->mmu_context;
1358                 etnaviv_gpu_start_fe_idleloop(gpu);
1359         } else {
1360                 etnaviv_iommu_context_get(gpu->mmu_context);
1361                 submit->prev_mmu_context = gpu->mmu_context;
1362         }
1363
1364         if (submit->nr_pmrs) {
1365                 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
1366                 kref_get(&submit->refcount);
1367                 gpu->event[event[1]].submit = submit;
1368                 etnaviv_sync_point_queue(gpu, event[1]);
1369         }
1370
1371         gpu->event[event[0]].fence = gpu_fence;
1372         submit->cmdbuf.user_size = submit->cmdbuf.size - 8;
1373         etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context,
1374                              event[0], &submit->cmdbuf);
1375
1376         if (submit->nr_pmrs) {
1377                 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
1378                 kref_get(&submit->refcount);
1379                 gpu->event[event[2]].submit = submit;
1380                 etnaviv_sync_point_queue(gpu, event[2]);
1381         }
1382
1383 out_unlock:
1384         mutex_unlock(&gpu->lock);
1385
1386         return gpu_fence;
1387 }
1388
1389 static void sync_point_worker(struct work_struct *work)
1390 {
1391         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1392                                                sync_point_work);
1393         struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1394         u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
1395
1396         event->sync_point(gpu, event);
1397         etnaviv_submit_put(event->submit);
1398         event_free(gpu, gpu->sync_point_event);
1399
1400         /* restart FE last to avoid GPU and IRQ racing against this worker */
1401         etnaviv_gpu_start_fe(gpu, addr + 2, 2);
1402 }
1403
1404 static void dump_mmu_fault(struct etnaviv_gpu *gpu)
1405 {
1406         u32 status_reg, status;
1407         int i;
1408
1409         if (gpu->sec_mode == ETNA_SEC_NONE)
1410                 status_reg = VIVS_MMUv2_STATUS;
1411         else
1412                 status_reg = VIVS_MMUv2_SEC_STATUS;
1413
1414         status = gpu_read(gpu, status_reg);
1415         dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
1416
1417         for (i = 0; i < 4; i++) {
1418                 u32 address_reg;
1419
1420                 if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4))))
1421                         continue;
1422
1423                 if (gpu->sec_mode == ETNA_SEC_NONE)
1424                         address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
1425                 else
1426                         address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
1427
1428                 dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i,
1429                                     gpu_read(gpu, address_reg));
1430         }
1431 }
1432
1433 static irqreturn_t irq_handler(int irq, void *data)
1434 {
1435         struct etnaviv_gpu *gpu = data;
1436         irqreturn_t ret = IRQ_NONE;
1437
1438         u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1439
1440         if (intr != 0) {
1441                 int event;
1442
1443                 pm_runtime_mark_last_busy(gpu->dev);
1444
1445                 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1446
1447                 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1448                         dev_err(gpu->dev, "AXI bus error\n");
1449                         intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1450                 }
1451
1452                 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1453                         dump_mmu_fault(gpu);
1454                         intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1455                 }
1456
1457                 while ((event = ffs(intr)) != 0) {
1458                         struct dma_fence *fence;
1459
1460                         event -= 1;
1461
1462                         intr &= ~(1 << event);
1463
1464                         dev_dbg(gpu->dev, "event %u\n", event);
1465
1466                         if (gpu->event[event].sync_point) {
1467                                 gpu->sync_point_event = event;
1468                                 queue_work(gpu->wq, &gpu->sync_point_work);
1469                         }
1470
1471                         fence = gpu->event[event].fence;
1472                         if (!fence)
1473                                 continue;
1474
1475                         gpu->event[event].fence = NULL;
1476
1477                         /*
1478                          * Events can be processed out of order.  Eg,
1479                          * - allocate and queue event 0
1480                          * - allocate event 1
1481                          * - event 0 completes, we process it
1482                          * - allocate and queue event 0
1483                          * - event 1 and event 0 complete
1484                          * we can end up processing event 0 first, then 1.
1485                          */
1486                         if (fence_after(fence->seqno, gpu->completed_fence))
1487                                 gpu->completed_fence = fence->seqno;
1488                         dma_fence_signal(fence);
1489
1490                         event_free(gpu, event);
1491                 }
1492
1493                 ret = IRQ_HANDLED;
1494         }
1495
1496         return ret;
1497 }
1498
1499 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1500 {
1501         int ret;
1502
1503         ret = clk_prepare_enable(gpu->clk_reg);
1504         if (ret)
1505                 return ret;
1506
1507         ret = clk_prepare_enable(gpu->clk_bus);
1508         if (ret)
1509                 goto disable_clk_reg;
1510
1511         ret = clk_prepare_enable(gpu->clk_core);
1512         if (ret)
1513                 goto disable_clk_bus;
1514
1515         ret = clk_prepare_enable(gpu->clk_shader);
1516         if (ret)
1517                 goto disable_clk_core;
1518
1519         return 0;
1520
1521 disable_clk_core:
1522         clk_disable_unprepare(gpu->clk_core);
1523 disable_clk_bus:
1524         clk_disable_unprepare(gpu->clk_bus);
1525 disable_clk_reg:
1526         clk_disable_unprepare(gpu->clk_reg);
1527
1528         return ret;
1529 }
1530
1531 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1532 {
1533         clk_disable_unprepare(gpu->clk_shader);
1534         clk_disable_unprepare(gpu->clk_core);
1535         clk_disable_unprepare(gpu->clk_bus);
1536         clk_disable_unprepare(gpu->clk_reg);
1537
1538         return 0;
1539 }
1540
1541 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1542 {
1543         unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1544
1545         do {
1546                 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1547
1548                 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1549                         return 0;
1550
1551                 if (time_is_before_jiffies(timeout)) {
1552                         dev_warn(gpu->dev,
1553                                  "timed out waiting for idle: idle=0x%x\n",
1554                                  idle);
1555                         return -ETIMEDOUT;
1556                 }
1557
1558                 udelay(5);
1559         } while (1);
1560 }
1561
1562 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1563 {
1564         if (gpu->initialized && gpu->mmu_context) {
1565                 /* Replace the last WAIT with END */
1566                 mutex_lock(&gpu->lock);
1567                 etnaviv_buffer_end(gpu);
1568                 mutex_unlock(&gpu->lock);
1569
1570                 /*
1571                  * We know that only the FE is busy here, this should
1572                  * happen quickly (as the WAIT is only 200 cycles).  If
1573                  * we fail, just warn and continue.
1574                  */
1575                 etnaviv_gpu_wait_idle(gpu, 100);
1576
1577                 etnaviv_iommu_context_put(gpu->mmu_context);
1578                 gpu->mmu_context = NULL;
1579         }
1580
1581         gpu->exec_state = -1;
1582
1583         return etnaviv_gpu_clk_disable(gpu);
1584 }
1585
1586 #ifdef CONFIG_PM
1587 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1588 {
1589         int ret;
1590
1591         ret = mutex_lock_killable(&gpu->lock);
1592         if (ret)
1593                 return ret;
1594
1595         etnaviv_gpu_update_clock(gpu);
1596         etnaviv_gpu_hw_init(gpu);
1597
1598         mutex_unlock(&gpu->lock);
1599
1600         return 0;
1601 }
1602 #endif
1603
1604 static int
1605 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1606                                   unsigned long *state)
1607 {
1608         *state = 6;
1609
1610         return 0;
1611 }
1612
1613 static int
1614 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1615                                   unsigned long *state)
1616 {
1617         struct etnaviv_gpu *gpu = cdev->devdata;
1618
1619         *state = gpu->freq_scale;
1620
1621         return 0;
1622 }
1623
1624 static int
1625 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1626                                   unsigned long state)
1627 {
1628         struct etnaviv_gpu *gpu = cdev->devdata;
1629
1630         mutex_lock(&gpu->lock);
1631         gpu->freq_scale = state;
1632         if (!pm_runtime_suspended(gpu->dev))
1633                 etnaviv_gpu_update_clock(gpu);
1634         mutex_unlock(&gpu->lock);
1635
1636         return 0;
1637 }
1638
1639 static struct thermal_cooling_device_ops cooling_ops = {
1640         .get_max_state = etnaviv_gpu_cooling_get_max_state,
1641         .get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1642         .set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1643 };
1644
1645 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1646         void *data)
1647 {
1648         struct drm_device *drm = data;
1649         struct etnaviv_drm_private *priv = drm->dev_private;
1650         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1651         int ret;
1652
1653         if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
1654                 gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
1655                                 (char *)dev_name(dev), gpu, &cooling_ops);
1656                 if (IS_ERR(gpu->cooling))
1657                         return PTR_ERR(gpu->cooling);
1658         }
1659
1660         gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1661         if (!gpu->wq) {
1662                 ret = -ENOMEM;
1663                 goto out_thermal;
1664         }
1665
1666         ret = etnaviv_sched_init(gpu);
1667         if (ret)
1668                 goto out_workqueue;
1669
1670 #ifdef CONFIG_PM
1671         ret = pm_runtime_get_sync(gpu->dev);
1672 #else
1673         ret = etnaviv_gpu_clk_enable(gpu);
1674 #endif
1675         if (ret < 0)
1676                 goto out_sched;
1677
1678
1679         gpu->drm = drm;
1680         gpu->fence_context = dma_fence_context_alloc(1);
1681         idr_init(&gpu->fence_idr);
1682         spin_lock_init(&gpu->fence_spinlock);
1683
1684         INIT_WORK(&gpu->sync_point_work, sync_point_worker);
1685         init_waitqueue_head(&gpu->fence_event);
1686
1687         priv->gpu[priv->num_gpus++] = gpu;
1688
1689         pm_runtime_mark_last_busy(gpu->dev);
1690         pm_runtime_put_autosuspend(gpu->dev);
1691
1692         return 0;
1693
1694 out_sched:
1695         etnaviv_sched_fini(gpu);
1696
1697 out_workqueue:
1698         destroy_workqueue(gpu->wq);
1699
1700 out_thermal:
1701         if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1702                 thermal_cooling_device_unregister(gpu->cooling);
1703
1704         return ret;
1705 }
1706
1707 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1708         void *data)
1709 {
1710         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1711
1712         DBG("%s", dev_name(gpu->dev));
1713
1714         flush_workqueue(gpu->wq);
1715         destroy_workqueue(gpu->wq);
1716
1717         etnaviv_sched_fini(gpu);
1718
1719 #ifdef CONFIG_PM
1720         pm_runtime_get_sync(gpu->dev);
1721         pm_runtime_put_sync_suspend(gpu->dev);
1722 #else
1723         etnaviv_gpu_hw_suspend(gpu);
1724 #endif
1725
1726         if (gpu->initialized) {
1727                 etnaviv_cmdbuf_free(&gpu->buffer);
1728                 etnaviv_iommu_global_fini(gpu);
1729                 gpu->initialized = false;
1730         }
1731
1732         gpu->drm = NULL;
1733         idr_destroy(&gpu->fence_idr);
1734
1735         if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1736                 thermal_cooling_device_unregister(gpu->cooling);
1737         gpu->cooling = NULL;
1738 }
1739
1740 static const struct component_ops gpu_ops = {
1741         .bind = etnaviv_gpu_bind,
1742         .unbind = etnaviv_gpu_unbind,
1743 };
1744
1745 static const struct of_device_id etnaviv_gpu_match[] = {
1746         {
1747                 .compatible = "vivante,gc"
1748         },
1749         { /* sentinel */ }
1750 };
1751 MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
1752
1753 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1754 {
1755         struct device *dev = &pdev->dev;
1756         struct etnaviv_gpu *gpu;
1757         int err;
1758
1759         gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1760         if (!gpu)
1761                 return -ENOMEM;
1762
1763         gpu->dev = &pdev->dev;
1764         mutex_init(&gpu->lock);
1765         mutex_init(&gpu->fence_lock);
1766
1767         /* Map registers: */
1768         gpu->mmio = devm_platform_ioremap_resource(pdev, 0);
1769         if (IS_ERR(gpu->mmio))
1770                 return PTR_ERR(gpu->mmio);
1771
1772         /* Get Interrupt: */
1773         gpu->irq = platform_get_irq(pdev, 0);
1774         if (gpu->irq < 0) {
1775                 dev_err(dev, "failed to get irq: %d\n", gpu->irq);
1776                 return gpu->irq;
1777         }
1778
1779         err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1780                                dev_name(gpu->dev), gpu);
1781         if (err) {
1782                 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1783                 return err;
1784         }
1785
1786         /* Get Clocks: */
1787         gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg");
1788         DBG("clk_reg: %p", gpu->clk_reg);
1789         if (IS_ERR(gpu->clk_reg))
1790                 return PTR_ERR(gpu->clk_reg);
1791
1792         gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus");
1793         DBG("clk_bus: %p", gpu->clk_bus);
1794         if (IS_ERR(gpu->clk_bus))
1795                 return PTR_ERR(gpu->clk_bus);
1796
1797         gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1798         DBG("clk_core: %p", gpu->clk_core);
1799         if (IS_ERR(gpu->clk_core))
1800                 return PTR_ERR(gpu->clk_core);
1801         gpu->base_rate_core = clk_get_rate(gpu->clk_core);
1802
1803         gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader");
1804         DBG("clk_shader: %p", gpu->clk_shader);
1805         if (IS_ERR(gpu->clk_shader))
1806                 return PTR_ERR(gpu->clk_shader);
1807         gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
1808
1809         /* TODO: figure out max mapped size */
1810         dev_set_drvdata(dev, gpu);
1811
1812         /*
1813          * We treat the device as initially suspended.  The runtime PM
1814          * autosuspend delay is rather arbitary: no measurements have
1815          * yet been performed to determine an appropriate value.
1816          */
1817         pm_runtime_use_autosuspend(gpu->dev);
1818         pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1819         pm_runtime_enable(gpu->dev);
1820
1821         err = component_add(&pdev->dev, &gpu_ops);
1822         if (err < 0) {
1823                 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1824                 return err;
1825         }
1826
1827         return 0;
1828 }
1829
1830 static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1831 {
1832         component_del(&pdev->dev, &gpu_ops);
1833         pm_runtime_disable(&pdev->dev);
1834         return 0;
1835 }
1836
1837 #ifdef CONFIG_PM
1838 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1839 {
1840         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1841         u32 idle, mask;
1842
1843         /* If there are any jobs in the HW queue, we're not idle */
1844         if (atomic_read(&gpu->sched.hw_rq_count))
1845                 return -EBUSY;
1846
1847         /* Check whether the hardware (except FE and MC) is idle */
1848         mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE |
1849                                   VIVS_HI_IDLE_STATE_MC);
1850         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1851         if (idle != mask) {
1852                 dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n",
1853                                      idle);
1854                 return -EBUSY;
1855         }
1856
1857         return etnaviv_gpu_hw_suspend(gpu);
1858 }
1859
1860 static int etnaviv_gpu_rpm_resume(struct device *dev)
1861 {
1862         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1863         int ret;
1864
1865         ret = etnaviv_gpu_clk_enable(gpu);
1866         if (ret)
1867                 return ret;
1868
1869         /* Re-initialise the basic hardware state */
1870         if (gpu->drm && gpu->initialized) {
1871                 ret = etnaviv_gpu_hw_resume(gpu);
1872                 if (ret) {
1873                         etnaviv_gpu_clk_disable(gpu);
1874                         return ret;
1875                 }
1876         }
1877
1878         return 0;
1879 }
1880 #endif
1881
1882 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1883         SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1884                            NULL)
1885 };
1886
1887 struct platform_driver etnaviv_gpu_driver = {
1888         .driver = {
1889                 .name = "etnaviv-gpu",
1890                 .owner = THIS_MODULE,
1891                 .pm = &etnaviv_gpu_pm_ops,
1892                 .of_match_table = etnaviv_gpu_match,
1893         },
1894         .probe = etnaviv_gpu_platform_probe,
1895         .remove = etnaviv_gpu_platform_remove,
1896         .id_table = gpu_ids,
1897 };