1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MIPI Display Bus Interface (DBI) LCD controller support
5 * Copyright 2016 Noralf Trønnes
8 #include <linux/debugfs.h>
9 #include <linux/delay.h>
10 #include <linux/dma-buf.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/module.h>
13 #include <linux/regulator/consumer.h>
14 #include <linux/spi/spi.h>
16 #include <drm/drm_connector.h>
17 #include <drm/drm_damage_helper.h>
18 #include <drm/drm_drv.h>
19 #include <drm/drm_gem_cma_helper.h>
20 #include <drm/drm_format_helper.h>
21 #include <drm/drm_fourcc.h>
22 #include <drm/drm_gem_framebuffer_helper.h>
23 #include <drm/drm_mipi_dbi.h>
24 #include <drm/drm_modes.h>
25 #include <drm/drm_probe_helper.h>
26 #include <drm/drm_rect.h>
27 #include <drm/drm_vblank.h>
28 #include <video/mipi_display.h>
30 #define MIPI_DBI_MAX_SPI_READ_SPEED 2000000 /* 2MHz */
32 #define DCS_POWER_MODE_DISPLAY BIT(2)
33 #define DCS_POWER_MODE_DISPLAY_NORMAL_MODE BIT(3)
34 #define DCS_POWER_MODE_SLEEP_MODE BIT(4)
35 #define DCS_POWER_MODE_PARTIAL_MODE BIT(5)
36 #define DCS_POWER_MODE_IDLE_MODE BIT(6)
37 #define DCS_POWER_MODE_RESERVED_MASK (BIT(0) | BIT(1) | BIT(7))
42 * This library provides helpers for MIPI Display Bus Interface (DBI)
43 * compatible display controllers.
45 * Many controllers for tiny lcd displays are MIPI compliant and can use this
46 * library. If a controller uses registers 0x2A and 0x2B to set the area to
47 * update and uses register 0x2C to write to frame memory, it is most likely
50 * Only MIPI Type 1 displays are supported since a full frame memory is needed.
52 * There are 3 MIPI DBI implementation types:
54 * A. Motorola 6800 type parallel bus
56 * B. Intel 8080 type parallel bus
58 * C. SPI type with 3 options:
60 * 1. 9-bit with the Data/Command signal as the ninth bit
61 * 2. Same as above except it's sent as 16 bits
62 * 3. 8-bit with the Data/Command signal as a separate D/CX pin
64 * Currently mipi_dbi only supports Type C options 1 and 3 with
65 * mipi_dbi_spi_init().
68 #define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \
71 DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \
73 DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, (int)len, data);\
75 DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \
78 static const u8 mipi_dbi_dcs_read_commands[] = {
79 MIPI_DCS_GET_DISPLAY_ID,
80 MIPI_DCS_GET_RED_CHANNEL,
81 MIPI_DCS_GET_GREEN_CHANNEL,
82 MIPI_DCS_GET_BLUE_CHANNEL,
83 MIPI_DCS_GET_DISPLAY_STATUS,
84 MIPI_DCS_GET_POWER_MODE,
85 MIPI_DCS_GET_ADDRESS_MODE,
86 MIPI_DCS_GET_PIXEL_FORMAT,
87 MIPI_DCS_GET_DISPLAY_MODE,
88 MIPI_DCS_GET_SIGNAL_MODE,
89 MIPI_DCS_GET_DIAGNOSTIC_RESULT,
90 MIPI_DCS_READ_MEMORY_START,
91 MIPI_DCS_READ_MEMORY_CONTINUE,
92 MIPI_DCS_GET_SCANLINE,
93 MIPI_DCS_GET_DISPLAY_BRIGHTNESS,
94 MIPI_DCS_GET_CONTROL_DISPLAY,
95 MIPI_DCS_GET_POWER_SAVE,
96 MIPI_DCS_GET_CABC_MIN_BRIGHTNESS,
97 MIPI_DCS_READ_DDB_START,
98 MIPI_DCS_READ_DDB_CONTINUE,
102 static bool mipi_dbi_command_is_read(struct mipi_dbi *dbi, u8 cmd)
106 if (!dbi->read_commands)
109 for (i = 0; i < 0xff; i++) {
110 if (!dbi->read_commands[i])
112 if (cmd == dbi->read_commands[i])
120 * mipi_dbi_command_read - MIPI DCS read command
121 * @dbi: MIPI DBI structure
125 * Send MIPI DCS read command to the controller.
128 * Zero on success, negative error code on failure.
130 int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val)
132 if (!dbi->read_commands)
135 if (!mipi_dbi_command_is_read(dbi, cmd))
138 return mipi_dbi_command_buf(dbi, cmd, val, 1);
140 EXPORT_SYMBOL(mipi_dbi_command_read);
143 * mipi_dbi_command_buf - MIPI DCS command with parameter(s) in an array
144 * @dbi: MIPI DBI structure
146 * @data: Parameter buffer
147 * @len: Buffer length
150 * Zero on success, negative error code on failure.
152 int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len)
157 /* SPI requires dma-safe buffers */
158 cmdbuf = kmemdup(&cmd, 1, GFP_KERNEL);
162 mutex_lock(&dbi->cmdlock);
163 ret = dbi->command(dbi, cmdbuf, data, len);
164 mutex_unlock(&dbi->cmdlock);
170 EXPORT_SYMBOL(mipi_dbi_command_buf);
172 /* This should only be used by mipi_dbi_command() */
173 int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len)
178 buf = kmemdup(data, len, GFP_KERNEL);
182 ret = mipi_dbi_command_buf(dbi, cmd, buf, len);
188 EXPORT_SYMBOL(mipi_dbi_command_stackbuf);
191 * mipi_dbi_buf_copy - Copy a framebuffer, transforming it if necessary
192 * @dst: The destination buffer
193 * @fb: The source framebuffer
194 * @clip: Clipping rectangle of the area to be copied
195 * @swap: When true, swap MSB/LSB of 16-bit values
198 * Zero on success, negative error code on failure.
200 int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb,
201 struct drm_rect *clip, bool swap)
203 struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0);
204 struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(gem);
205 struct dma_buf_attachment *import_attach = gem->import_attach;
206 struct drm_format_name_buf format_name;
207 void *src = cma_obj->vaddr;
211 ret = dma_buf_begin_cpu_access(import_attach->dmabuf,
217 switch (fb->format->format) {
218 case DRM_FORMAT_RGB565:
220 drm_fb_swab16(dst, src, fb, clip);
222 drm_fb_memcpy(dst, src, fb, clip);
224 case DRM_FORMAT_XRGB8888:
225 drm_fb_xrgb8888_to_rgb565(dst, src, fb, clip, swap);
228 dev_err_once(fb->dev->dev, "Format is not supported: %s\n",
229 drm_get_format_name(fb->format->format,
235 ret = dma_buf_end_cpu_access(import_attach->dmabuf,
239 EXPORT_SYMBOL(mipi_dbi_buf_copy);
241 static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect)
243 struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0);
244 struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(gem);
245 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);
246 unsigned int height = rect->y2 - rect->y1;
247 unsigned int width = rect->x2 - rect->x1;
248 struct mipi_dbi *dbi = &dbidev->dbi;
249 bool swap = dbi->swap_bytes;
254 if (!dbidev->enabled)
257 if (!drm_dev_enter(fb->dev, &idx))
260 full = width == fb->width && height == fb->height;
262 DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect));
264 if (!dbi->dc || !full || swap ||
265 fb->format->format == DRM_FORMAT_XRGB8888) {
267 ret = mipi_dbi_buf_copy(dbidev->tx_buf, fb, rect, swap);
274 mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS,
275 (rect->x1 >> 8) & 0xff, rect->x1 & 0xff,
276 ((rect->x2 - 1) >> 8) & 0xff, (rect->x2 - 1) & 0xff);
277 mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS,
278 (rect->y1 >> 8) & 0xff, rect->y1 & 0xff,
279 ((rect->y2 - 1) >> 8) & 0xff, (rect->y2 - 1) & 0xff);
281 ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr,
285 dev_err_once(fb->dev->dev, "Failed to update display %d\n", ret);
291 * mipi_dbi_pipe_update - Display pipe update helper
292 * @pipe: Simple display pipe
293 * @old_state: Old plane state
295 * This function handles framebuffer flushing and vblank events. Drivers can use
296 * this as their &drm_simple_display_pipe_funcs->update callback.
298 void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe,
299 struct drm_plane_state *old_state)
301 struct drm_plane_state *state = pipe->plane.state;
302 struct drm_crtc *crtc = &pipe->crtc;
303 struct drm_rect rect;
305 if (drm_atomic_helper_damage_merged(old_state, state, &rect))
306 mipi_dbi_fb_dirty(state->fb, &rect);
308 if (crtc->state->event) {
309 spin_lock_irq(&crtc->dev->event_lock);
310 drm_crtc_send_vblank_event(crtc, crtc->state->event);
311 spin_unlock_irq(&crtc->dev->event_lock);
312 crtc->state->event = NULL;
315 EXPORT_SYMBOL(mipi_dbi_pipe_update);
318 * mipi_dbi_enable_flush - MIPI DBI enable helper
319 * @dbidev: MIPI DBI device structure
320 * @crtc_state: CRTC state
321 * @plane_state: Plane state
323 * This function sets &mipi_dbi->enabled, flushes the whole framebuffer and
324 * enables the backlight. Drivers can use this in their
325 * &drm_simple_display_pipe_funcs->enable callback.
327 * Note: Drivers which don't use mipi_dbi_pipe_update() because they have custom
328 * framebuffer flushing, can't use this function since they both use the same
331 void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev,
332 struct drm_crtc_state *crtc_state,
333 struct drm_plane_state *plane_state)
335 struct drm_framebuffer *fb = plane_state->fb;
336 struct drm_rect rect = {
344 if (!drm_dev_enter(&dbidev->drm, &idx))
347 dbidev->enabled = true;
348 mipi_dbi_fb_dirty(fb, &rect);
349 backlight_enable(dbidev->backlight);
353 EXPORT_SYMBOL(mipi_dbi_enable_flush);
355 static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev)
357 struct drm_device *drm = &dbidev->drm;
358 u16 height = drm->mode_config.min_height;
359 u16 width = drm->mode_config.min_width;
360 struct mipi_dbi *dbi = &dbidev->dbi;
361 size_t len = width * height * 2;
364 if (!drm_dev_enter(drm, &idx))
367 memset(dbidev->tx_buf, 0, len);
369 mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, 0, 0,
370 (width >> 8) & 0xFF, (width - 1) & 0xFF);
371 mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, 0, 0,
372 (height >> 8) & 0xFF, (height - 1) & 0xFF);
373 mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START,
374 (u8 *)dbidev->tx_buf, len);
380 * mipi_dbi_pipe_disable - MIPI DBI pipe disable helper
381 * @pipe: Display pipe
383 * This function disables backlight if present, if not the display memory is
384 * blanked. The regulator is disabled if in use. Drivers can use this as their
385 * &drm_simple_display_pipe_funcs->disable callback.
387 void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe)
389 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
391 if (!dbidev->enabled)
396 dbidev->enabled = false;
398 if (dbidev->backlight)
399 backlight_disable(dbidev->backlight);
401 mipi_dbi_blank(dbidev);
403 if (dbidev->regulator)
404 regulator_disable(dbidev->regulator);
406 EXPORT_SYMBOL(mipi_dbi_pipe_disable);
408 static int mipi_dbi_connector_get_modes(struct drm_connector *connector)
410 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(connector->dev);
411 struct drm_display_mode *mode;
413 mode = drm_mode_duplicate(connector->dev, &dbidev->mode);
415 DRM_ERROR("Failed to duplicate mode\n");
419 if (mode->name[0] == '\0')
420 drm_mode_set_name(mode);
422 mode->type |= DRM_MODE_TYPE_PREFERRED;
423 drm_mode_probed_add(connector, mode);
425 if (mode->width_mm) {
426 connector->display_info.width_mm = mode->width_mm;
427 connector->display_info.height_mm = mode->height_mm;
433 static const struct drm_connector_helper_funcs mipi_dbi_connector_hfuncs = {
434 .get_modes = mipi_dbi_connector_get_modes,
437 static const struct drm_connector_funcs mipi_dbi_connector_funcs = {
438 .reset = drm_atomic_helper_connector_reset,
439 .fill_modes = drm_helper_probe_single_connector_modes,
440 .destroy = drm_connector_cleanup,
441 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
442 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
445 static int mipi_dbi_rotate_mode(struct drm_display_mode *mode,
446 unsigned int rotation)
448 if (rotation == 0 || rotation == 180) {
450 } else if (rotation == 90 || rotation == 270) {
451 swap(mode->hdisplay, mode->vdisplay);
452 swap(mode->hsync_start, mode->vsync_start);
453 swap(mode->hsync_end, mode->vsync_end);
454 swap(mode->htotal, mode->vtotal);
455 swap(mode->width_mm, mode->height_mm);
462 static const struct drm_mode_config_funcs mipi_dbi_mode_config_funcs = {
463 .fb_create = drm_gem_fb_create_with_dirty,
464 .atomic_check = drm_atomic_helper_check,
465 .atomic_commit = drm_atomic_helper_commit,
468 static const uint32_t mipi_dbi_formats[] = {
474 * mipi_dbi_dev_init_with_formats - MIPI DBI device initialization with custom formats
475 * @dbidev: MIPI DBI device structure to initialize
476 * @funcs: Display pipe functions
477 * @formats: Array of supported formats (DRM_FORMAT\_\*).
478 * @format_count: Number of elements in @formats
479 * @mode: Display mode
480 * @rotation: Initial rotation in degrees Counter Clock Wise
481 * @tx_buf_size: Allocate a transmit buffer of this size.
483 * This function sets up a &drm_simple_display_pipe with a &drm_connector that
484 * has one fixed &drm_display_mode which is rotated according to @rotation.
485 * This mode is used to set the mode config min/max width/height properties.
487 * Use mipi_dbi_dev_init() if you don't need custom formats.
490 * Some of the helper functions expects RGB565 to be the default format and the
491 * transmit buffer sized to fit that.
494 * Zero on success, negative error code on failure.
496 int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev,
497 const struct drm_simple_display_pipe_funcs *funcs,
498 const uint32_t *formats, unsigned int format_count,
499 const struct drm_display_mode *mode,
500 unsigned int rotation, size_t tx_buf_size)
502 static const uint64_t modifiers[] = {
503 DRM_FORMAT_MOD_LINEAR,
504 DRM_FORMAT_MOD_INVALID
506 struct drm_device *drm = &dbidev->drm;
509 if (!dbidev->dbi.command)
512 dbidev->tx_buf = devm_kmalloc(drm->dev, tx_buf_size, GFP_KERNEL);
516 drm_mode_copy(&dbidev->mode, mode);
517 ret = mipi_dbi_rotate_mode(&dbidev->mode, rotation);
519 DRM_ERROR("Illegal rotation value %u\n", rotation);
523 drm_connector_helper_add(&dbidev->connector, &mipi_dbi_connector_hfuncs);
524 ret = drm_connector_init(drm, &dbidev->connector, &mipi_dbi_connector_funcs,
525 DRM_MODE_CONNECTOR_SPI);
529 ret = drm_simple_display_pipe_init(drm, &dbidev->pipe, funcs, formats, format_count,
530 modifiers, &dbidev->connector);
534 drm_plane_enable_fb_damage_clips(&dbidev->pipe.plane);
536 drm->mode_config.funcs = &mipi_dbi_mode_config_funcs;
537 drm->mode_config.min_width = dbidev->mode.hdisplay;
538 drm->mode_config.max_width = dbidev->mode.hdisplay;
539 drm->mode_config.min_height = dbidev->mode.vdisplay;
540 drm->mode_config.max_height = dbidev->mode.vdisplay;
541 dbidev->rotation = rotation;
543 DRM_DEBUG_KMS("rotation = %u\n", rotation);
547 EXPORT_SYMBOL(mipi_dbi_dev_init_with_formats);
550 * mipi_dbi_dev_init - MIPI DBI device initialization
551 * @dbidev: MIPI DBI device structure to initialize
552 * @funcs: Display pipe functions
553 * @mode: Display mode
554 * @rotation: Initial rotation in degrees Counter Clock Wise
556 * This function sets up a &drm_simple_display_pipe with a &drm_connector that
557 * has one fixed &drm_display_mode which is rotated according to @rotation.
558 * This mode is used to set the mode config min/max width/height properties.
559 * Additionally &mipi_dbi.tx_buf is allocated.
561 * Supported formats: Native RGB565 and emulated XRGB8888.
564 * Zero on success, negative error code on failure.
566 int mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev,
567 const struct drm_simple_display_pipe_funcs *funcs,
568 const struct drm_display_mode *mode, unsigned int rotation)
570 size_t bufsize = mode->vdisplay * mode->hdisplay * sizeof(u16);
572 dbidev->drm.mode_config.preferred_depth = 16;
574 return mipi_dbi_dev_init_with_formats(dbidev, funcs, mipi_dbi_formats,
575 ARRAY_SIZE(mipi_dbi_formats), mode,
578 EXPORT_SYMBOL(mipi_dbi_dev_init);
581 * mipi_dbi_release - DRM driver release helper
584 * This function finalizes and frees &mipi_dbi.
586 * Drivers can use this as their &drm_driver->release callback.
588 void mipi_dbi_release(struct drm_device *drm)
590 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(drm);
592 DRM_DEBUG_DRIVER("\n");
594 drm_mode_config_cleanup(drm);
598 EXPORT_SYMBOL(mipi_dbi_release);
601 * mipi_dbi_hw_reset - Hardware reset of controller
602 * @dbi: MIPI DBI structure
604 * Reset controller if the &mipi_dbi->reset gpio is set.
606 void mipi_dbi_hw_reset(struct mipi_dbi *dbi)
611 gpiod_set_value_cansleep(dbi->reset, 0);
612 usleep_range(20, 1000);
613 gpiod_set_value_cansleep(dbi->reset, 1);
616 EXPORT_SYMBOL(mipi_dbi_hw_reset);
619 * mipi_dbi_display_is_on - Check if display is on
620 * @dbi: MIPI DBI structure
622 * This function checks the Power Mode register (if readable) to see if
623 * display output is turned on. This can be used to see if the bootloader
624 * has already turned on the display avoiding flicker when the pipeline is
628 * true if the display can be verified to be on, false otherwise.
630 bool mipi_dbi_display_is_on(struct mipi_dbi *dbi)
634 if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val))
637 val &= ~DCS_POWER_MODE_RESERVED_MASK;
639 /* The poweron/reset value is 08h DCS_POWER_MODE_DISPLAY_NORMAL_MODE */
640 if (val != (DCS_POWER_MODE_DISPLAY |
641 DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE))
644 DRM_DEBUG_DRIVER("Display is ON\n");
648 EXPORT_SYMBOL(mipi_dbi_display_is_on);
650 static int mipi_dbi_poweron_reset_conditional(struct mipi_dbi_dev *dbidev, bool cond)
652 struct device *dev = dbidev->drm.dev;
653 struct mipi_dbi *dbi = &dbidev->dbi;
656 if (dbidev->regulator) {
657 ret = regulator_enable(dbidev->regulator);
659 DRM_DEV_ERROR(dev, "Failed to enable regulator (%d)\n", ret);
664 if (cond && mipi_dbi_display_is_on(dbi))
667 mipi_dbi_hw_reset(dbi);
668 ret = mipi_dbi_command(dbi, MIPI_DCS_SOFT_RESET);
670 DRM_DEV_ERROR(dev, "Failed to send reset command (%d)\n", ret);
671 if (dbidev->regulator)
672 regulator_disable(dbidev->regulator);
677 * If we did a hw reset, we know the controller is in Sleep mode and
678 * per MIPI DSC spec should wait 5ms after soft reset. If we didn't,
679 * we assume worst case and wait 120ms.
682 usleep_range(5000, 20000);
690 * mipi_dbi_poweron_reset - MIPI DBI poweron and reset
691 * @dbidev: MIPI DBI device structure
693 * This function enables the regulator if used and does a hardware and software
697 * Zero on success, or a negative error code.
699 int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev)
701 return mipi_dbi_poweron_reset_conditional(dbidev, false);
703 EXPORT_SYMBOL(mipi_dbi_poweron_reset);
706 * mipi_dbi_poweron_conditional_reset - MIPI DBI poweron and conditional reset
707 * @dbidev: MIPI DBI device structure
709 * This function enables the regulator if used and if the display is off, it
710 * does a hardware and software reset. If mipi_dbi_display_is_on() determines
711 * that the display is on, no reset is performed.
714 * Zero if the controller was reset, 1 if the display was already on, or a
715 * negative error code.
717 int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev)
719 return mipi_dbi_poweron_reset_conditional(dbidev, true);
721 EXPORT_SYMBOL(mipi_dbi_poweron_conditional_reset);
723 #if IS_ENABLED(CONFIG_SPI)
726 * mipi_dbi_spi_cmd_max_speed - get the maximum SPI bus speed
728 * @len: The transfer buffer length.
730 * Many controllers have a max speed of 10MHz, but can be pushed way beyond
731 * that. Increase reliability by running pixel data at max speed and the rest
732 * at 10MHz, preventing transfer glitches from messing up the init settings.
734 u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len)
737 return 0; /* use default */
739 return min_t(u32, 10000000, spi->max_speed_hz);
741 EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed);
743 static bool mipi_dbi_machine_little_endian(void)
745 #if defined(__LITTLE_ENDIAN)
753 * MIPI DBI Type C Option 1
755 * If the SPI controller doesn't have 9 bits per word support,
756 * use blocks of 9 bytes to send 8x 9-bit words using a 8-bit SPI transfer.
757 * Pad partial blocks with MIPI_DCS_NOP (zero).
758 * This is how the D/C bit (x) is added:
770 static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc,
771 const void *buf, size_t len,
774 bool swap_bytes = (bpw == 16 && mipi_dbi_machine_little_endian());
775 size_t chunk, max_chunk = dbi->tx_buf9_len;
776 struct spi_device *spi = dbi->spi;
777 struct spi_transfer tr = {
778 .tx_buf = dbi->tx_buf9,
781 struct spi_message m;
786 if (drm_debug_enabled(DRM_UT_DRIVER))
787 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
788 __func__, dc, max_chunk);
790 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
791 spi_message_init_with_transfers(&m, &tr, 1);
794 if (WARN_ON_ONCE(len != 1))
797 /* Command: pad no-op's (zeroes) at beginning of block */
803 return spi_sync(spi, &m);
806 /* max with room for adding one bit per byte */
807 max_chunk = max_chunk / 9 * 8;
808 /* but no bigger than len */
809 max_chunk = min(max_chunk, len);
811 max_chunk = max_t(size_t, 8, max_chunk & ~0x7);
816 chunk = min(len, max_chunk);
823 /* Data: pad no-op's (zeroes) at end of block */
827 for (i = 1; i < (chunk + 1); i++) {
829 *dst++ = carry | BIT(8 - i) | (val >> i);
830 carry = val << (8 - i);
833 *dst++ = carry | BIT(8 - i) | (val >> i);
834 carry = val << (8 - i);
839 for (i = 1; i < (chunk + 1); i++) {
841 *dst++ = carry | BIT(8 - i) | (val >> i);
842 carry = val << (8 - i);
850 for (i = 0; i < chunk; i += 8) {
852 *dst++ = BIT(7) | (src[1] >> 1);
853 *dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2);
854 *dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3);
855 *dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4);
856 *dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5);
857 *dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6);
858 *dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7);
859 *dst++ = (src[7] << 1) | BIT(0);
862 *dst++ = BIT(7) | (src[0] >> 1);
863 *dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2);
864 *dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3);
865 *dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4);
866 *dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5);
867 *dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6);
868 *dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7);
869 *dst++ = (src[6] << 1) | BIT(0);
878 tr.len = chunk + added;
880 ret = spi_sync(spi, &m);
888 static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc,
889 const void *buf, size_t len,
892 struct spi_device *spi = dbi->spi;
893 struct spi_transfer tr = {
896 const u16 *src16 = buf;
897 const u8 *src8 = buf;
898 struct spi_message m;
903 if (!spi_is_bpw_supported(spi, 9))
904 return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw);
906 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
907 max_chunk = dbi->tx_buf9_len;
908 dst16 = dbi->tx_buf9;
910 if (drm_debug_enabled(DRM_UT_DRIVER))
911 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
912 __func__, dc, max_chunk);
914 max_chunk = min(max_chunk / 2, len);
916 spi_message_init_with_transfers(&m, &tr, 1);
920 size_t chunk = min(len, max_chunk);
923 if (bpw == 16 && mipi_dbi_machine_little_endian()) {
924 for (i = 0; i < (chunk * 2); i += 2) {
925 dst16[i] = *src16 >> 8;
926 dst16[i + 1] = *src16++ & 0xFF;
929 dst16[i + 1] |= 0x0100;
933 for (i = 0; i < chunk; i++) {
943 ret = spi_sync(spi, &m);
951 static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd,
952 u8 *parameters, size_t num)
954 unsigned int bpw = (*cmd == MIPI_DCS_WRITE_MEMORY_START) ? 16 : 8;
957 if (mipi_dbi_command_is_read(dbi, *cmd))
960 MIPI_DBI_DEBUG_COMMAND(*cmd, parameters, num);
962 ret = mipi_dbi_spi1_transfer(dbi, 0, cmd, 1, 8);
966 return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw);
969 /* MIPI DBI Type C Option 3 */
971 static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd,
972 u8 *data, size_t len)
974 struct spi_device *spi = dbi->spi;
975 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
976 spi->max_speed_hz / 2);
977 struct spi_transfer tr[2] = {
979 .speed_hz = speed_hz,
983 .speed_hz = speed_hz,
987 struct spi_message m;
995 * Support non-standard 24-bit and 32-bit Nokia read commands which
996 * start with a dummy clock, so we need to read an extra byte.
998 if (*cmd == MIPI_DCS_GET_DISPLAY_ID ||
999 *cmd == MIPI_DCS_GET_DISPLAY_STATUS) {
1000 if (!(len == 3 || len == 4))
1003 tr[1].len = len + 1;
1006 buf = kmalloc(tr[1].len, GFP_KERNEL);
1011 gpiod_set_value_cansleep(dbi->dc, 0);
1013 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
1014 ret = spi_sync(spi, &m);
1018 if (tr[1].len == len) {
1019 memcpy(data, buf, len);
1023 for (i = 0; i < len; i++)
1024 data[i] = (buf[i] << 1) | (buf[i + 1] >> 7);
1027 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len);
1035 static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd,
1036 u8 *par, size_t num)
1038 struct spi_device *spi = dbi->spi;
1039 unsigned int bpw = 8;
1043 if (mipi_dbi_command_is_read(dbi, *cmd))
1044 return mipi_dbi_typec3_command_read(dbi, cmd, par, num);
1046 MIPI_DBI_DEBUG_COMMAND(*cmd, par, num);
1048 gpiod_set_value_cansleep(dbi->dc, 0);
1049 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1);
1050 ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, cmd, 1);
1054 if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !dbi->swap_bytes)
1057 gpiod_set_value_cansleep(dbi->dc, 1);
1058 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num);
1060 return mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num);
1064 * mipi_dbi_spi_init - Initialize MIPI DBI SPI interface
1066 * @dbi: MIPI DBI structure to initialize
1067 * @dc: D/C gpio (optional)
1069 * This function sets &mipi_dbi->command, enables &mipi_dbi->read_commands for the
1070 * usual read commands. It should be followed by a call to mipi_dbi_dev_init() or
1071 * a driver-specific init.
1073 * If @dc is set, a Type C Option 3 interface is assumed, if not
1076 * If the SPI master driver doesn't support the necessary bits per word,
1077 * the following transformation is used:
1079 * - 9-bit: reorder buffer as 9x 8-bit words, padded with no-op command.
1080 * - 16-bit: if big endian send as 8-bit, if little endian swap bytes
1083 * Zero on success, negative error code on failure.
1085 int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi,
1086 struct gpio_desc *dc)
1088 struct device *dev = &spi->dev;
1092 * Even though it's not the SPI device that does DMA (the master does),
1093 * the dma mask is necessary for the dma_alloc_wc() in
1094 * drm_gem_cma_create(). The dma_addr returned will be a physical
1095 * address which might be different from the bus address, but this is
1096 * not a problem since the address will not be used.
1097 * The virtual address is used in the transfer and the SPI core
1098 * re-maps it on the SPI master device using the DMA streaming API
1101 if (!dev->coherent_dma_mask) {
1102 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
1104 dev_warn(dev, "Failed to set dma mask %d\n", ret);
1110 dbi->read_commands = mipi_dbi_dcs_read_commands;
1113 dbi->command = mipi_dbi_typec3_command;
1115 if (mipi_dbi_machine_little_endian() && !spi_is_bpw_supported(spi, 16))
1116 dbi->swap_bytes = true;
1118 dbi->command = mipi_dbi_typec1_command;
1119 dbi->tx_buf9_len = SZ_16K;
1120 dbi->tx_buf9 = devm_kmalloc(dev, dbi->tx_buf9_len, GFP_KERNEL);
1125 mutex_init(&dbi->cmdlock);
1127 DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000);
1131 EXPORT_SYMBOL(mipi_dbi_spi_init);
1134 * mipi_dbi_spi_transfer - SPI transfer helper
1136 * @speed_hz: Override speed (optional)
1137 * @bpw: Bits per word
1138 * @buf: Buffer to transfer
1139 * @len: Buffer length
1141 * This SPI transfer helper breaks up the transfer of @buf into chunks which
1142 * the SPI controller driver can handle.
1145 * Zero on success, negative error code on failure.
1147 int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz,
1148 u8 bpw, const void *buf, size_t len)
1150 size_t max_chunk = spi_max_transfer_size(spi);
1151 struct spi_transfer tr = {
1152 .bits_per_word = bpw,
1153 .speed_hz = speed_hz,
1155 struct spi_message m;
1159 spi_message_init_with_transfers(&m, &tr, 1);
1162 chunk = min(len, max_chunk);
1169 ret = spi_sync(spi, &m);
1176 EXPORT_SYMBOL(mipi_dbi_spi_transfer);
1178 #endif /* CONFIG_SPI */
1180 #ifdef CONFIG_DEBUG_FS
1182 static ssize_t mipi_dbi_debugfs_command_write(struct file *file,
1183 const char __user *ubuf,
1184 size_t count, loff_t *ppos)
1186 struct seq_file *m = file->private_data;
1187 struct mipi_dbi_dev *dbidev = m->private;
1188 u8 val, cmd = 0, parameters[64];
1189 char *buf, *pos, *token;
1192 if (!drm_dev_enter(&dbidev->drm, &idx))
1195 buf = memdup_user_nul(ubuf, count);
1201 /* strip trailing whitespace */
1202 for (i = count - 1; i > 0; i--)
1203 if (isspace(buf[i]))
1210 token = strsep(&pos, " ");
1216 ret = kstrtou8(token, 16, &val);
1223 parameters[i++] = val;
1231 ret = mipi_dbi_command_buf(&dbidev->dbi, cmd, parameters, i);
1238 return ret < 0 ? ret : count;
1241 static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused)
1243 struct mipi_dbi_dev *dbidev = m->private;
1244 struct mipi_dbi *dbi = &dbidev->dbi;
1249 if (!drm_dev_enter(&dbidev->drm, &idx))
1252 for (cmd = 0; cmd < 255; cmd++) {
1253 if (!mipi_dbi_command_is_read(dbi, cmd))
1257 case MIPI_DCS_READ_MEMORY_START:
1258 case MIPI_DCS_READ_MEMORY_CONTINUE:
1261 case MIPI_DCS_GET_DISPLAY_ID:
1264 case MIPI_DCS_GET_DISPLAY_STATUS:
1272 seq_printf(m, "%02x: ", cmd);
1273 ret = mipi_dbi_command_buf(dbi, cmd, val, len);
1275 seq_puts(m, "XX\n");
1278 seq_printf(m, "%*phN\n", (int)len, val);
1286 static int mipi_dbi_debugfs_command_open(struct inode *inode,
1289 return single_open(file, mipi_dbi_debugfs_command_show,
1293 static const struct file_operations mipi_dbi_debugfs_command_fops = {
1294 .owner = THIS_MODULE,
1295 .open = mipi_dbi_debugfs_command_open,
1297 .llseek = seq_lseek,
1298 .release = single_release,
1299 .write = mipi_dbi_debugfs_command_write,
1303 * mipi_dbi_debugfs_init - Create debugfs entries
1306 * This function creates a 'command' debugfs file for sending commands to the
1307 * controller or getting the read command values.
1308 * Drivers can use this as their &drm_driver->debugfs_init callback.
1311 * Zero on success, negative error code on failure.
1313 int mipi_dbi_debugfs_init(struct drm_minor *minor)
1315 struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(minor->dev);
1316 umode_t mode = S_IFREG | S_IWUSR;
1318 if (dbidev->dbi.read_commands)
1320 debugfs_create_file("command", mode, minor->debugfs_root, dbidev,
1321 &mipi_dbi_debugfs_command_fops);
1325 EXPORT_SYMBOL(mipi_dbi_debugfs_init);
1329 MODULE_LICENSE("GPL");