2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
35 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_displayid.h>
40 #include <drm/drm_scdc_helper.h>
42 #include "drm_crtc_internal.h"
44 #define version_greater(edid, maj, min) \
45 (((edid)->version > (maj)) || \
46 ((edid)->version == (maj) && (edid)->revision > (min)))
48 #define EDID_EST_TIMINGS 16
49 #define EDID_STD_TIMINGS 8
50 #define EDID_DETAILED_TIMINGS 4
53 * EDID blocks out in the wild have a variety of bugs, try to collect
54 * them here (note that userspace may work around broken monitors first,
55 * but fixes should make their way here so that the kernel "just works"
56 * on as many displays as possible).
59 /* First detailed mode wrong, use largest 60Hz mode */
60 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
61 /* Reported 135MHz pixel clock is too high, needs adjustment */
62 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
63 /* Prefer the largest mode at 75 Hz */
64 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
65 /* Detail timing is in cm not mm */
66 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
67 /* Detailed timing descriptors have bogus size values, so just take the
68 * maximum size and use that.
70 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
71 /* Monitor forgot to set the first detailed is preferred bit. */
72 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
73 /* use +hsync +vsync for detailed mode */
74 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
75 /* Force reduced-blanking timings for detailed modes */
76 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
78 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
80 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
82 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
84 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
85 /* Non desktop display (i.e. HMD) */
86 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
88 struct detailed_mode_closure {
89 struct drm_connector *connector;
101 static const struct edid_quirk {
105 } edid_quirk_list[] = {
107 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
109 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
111 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
113 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
114 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
116 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
117 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
119 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
120 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
122 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
123 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
125 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
126 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
128 /* Belinea 10 15 55 */
129 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
130 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
132 /* Envision Peripherals, Inc. EN-7100e */
133 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
134 /* Envision EN2028 */
135 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
137 /* Funai Electronics PM36B */
138 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
139 EDID_QUIRK_DETAILED_IN_CM },
141 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
142 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
144 /* LG Philips LCD LP154W01-A5 */
145 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
146 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
148 /* Philips 107p5 CRT */
149 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
152 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
154 /* Samsung SyncMaster 205BW. Note: irony */
155 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
156 /* Samsung SyncMaster 22[5-6]BW */
157 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
158 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
160 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
161 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
163 /* ViewSonic VA2026w */
164 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
166 /* Medion MD 30217 PG */
167 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
169 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
170 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
172 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
173 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
175 /* HTC Vive and Vive Pro VR Headsets */
176 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
177 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
179 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */
180 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
181 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
182 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
184 /* Windows Mixed Reality Headsets */
185 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
186 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
187 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
188 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
189 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
190 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
191 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
192 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
194 /* Sony PlayStation VR Headset */
195 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
199 * Autogenerated from the DMT spec.
200 * This table is copied from xfree86/modes/xf86EdidModes.c.
202 static const struct drm_display_mode drm_dmt_modes[] = {
203 /* 0x01 - 640x350@85Hz */
204 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
205 736, 832, 0, 350, 382, 385, 445, 0,
206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
207 /* 0x02 - 640x400@85Hz */
208 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
209 736, 832, 0, 400, 401, 404, 445, 0,
210 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
211 /* 0x03 - 720x400@85Hz */
212 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
213 828, 936, 0, 400, 401, 404, 446, 0,
214 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
215 /* 0x04 - 640x480@60Hz */
216 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
217 752, 800, 0, 480, 490, 492, 525, 0,
218 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
219 /* 0x05 - 640x480@72Hz */
220 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
221 704, 832, 0, 480, 489, 492, 520, 0,
222 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
223 /* 0x06 - 640x480@75Hz */
224 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
225 720, 840, 0, 480, 481, 484, 500, 0,
226 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
227 /* 0x07 - 640x480@85Hz */
228 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
229 752, 832, 0, 480, 481, 484, 509, 0,
230 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
231 /* 0x08 - 800x600@56Hz */
232 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
233 896, 1024, 0, 600, 601, 603, 625, 0,
234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
235 /* 0x09 - 800x600@60Hz */
236 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
237 968, 1056, 0, 600, 601, 605, 628, 0,
238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
239 /* 0x0a - 800x600@72Hz */
240 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
241 976, 1040, 0, 600, 637, 643, 666, 0,
242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
243 /* 0x0b - 800x600@75Hz */
244 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
245 896, 1056, 0, 600, 601, 604, 625, 0,
246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
247 /* 0x0c - 800x600@85Hz */
248 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
249 896, 1048, 0, 600, 601, 604, 631, 0,
250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
251 /* 0x0d - 800x600@120Hz RB */
252 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
253 880, 960, 0, 600, 603, 607, 636, 0,
254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
255 /* 0x0e - 848x480@60Hz */
256 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
257 976, 1088, 0, 480, 486, 494, 517, 0,
258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
259 /* 0x0f - 1024x768@43Hz, interlace */
260 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
261 1208, 1264, 0, 768, 768, 776, 817, 0,
262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
263 DRM_MODE_FLAG_INTERLACE) },
264 /* 0x10 - 1024x768@60Hz */
265 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
266 1184, 1344, 0, 768, 771, 777, 806, 0,
267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
268 /* 0x11 - 1024x768@70Hz */
269 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
270 1184, 1328, 0, 768, 771, 777, 806, 0,
271 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
272 /* 0x12 - 1024x768@75Hz */
273 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
274 1136, 1312, 0, 768, 769, 772, 800, 0,
275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
276 /* 0x13 - 1024x768@85Hz */
277 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
278 1168, 1376, 0, 768, 769, 772, 808, 0,
279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
280 /* 0x14 - 1024x768@120Hz RB */
281 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
282 1104, 1184, 0, 768, 771, 775, 813, 0,
283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
284 /* 0x15 - 1152x864@75Hz */
285 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
286 1344, 1600, 0, 864, 865, 868, 900, 0,
287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
288 /* 0x55 - 1280x720@60Hz */
289 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
290 1430, 1650, 0, 720, 725, 730, 750, 0,
291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
292 /* 0x16 - 1280x768@60Hz RB */
293 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
294 1360, 1440, 0, 768, 771, 778, 790, 0,
295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
296 /* 0x17 - 1280x768@60Hz */
297 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
298 1472, 1664, 0, 768, 771, 778, 798, 0,
299 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
300 /* 0x18 - 1280x768@75Hz */
301 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
302 1488, 1696, 0, 768, 771, 778, 805, 0,
303 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
304 /* 0x19 - 1280x768@85Hz */
305 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
306 1496, 1712, 0, 768, 771, 778, 809, 0,
307 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
308 /* 0x1a - 1280x768@120Hz RB */
309 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
310 1360, 1440, 0, 768, 771, 778, 813, 0,
311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
312 /* 0x1b - 1280x800@60Hz RB */
313 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
314 1360, 1440, 0, 800, 803, 809, 823, 0,
315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
316 /* 0x1c - 1280x800@60Hz */
317 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
318 1480, 1680, 0, 800, 803, 809, 831, 0,
319 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
320 /* 0x1d - 1280x800@75Hz */
321 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
322 1488, 1696, 0, 800, 803, 809, 838, 0,
323 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
324 /* 0x1e - 1280x800@85Hz */
325 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
326 1496, 1712, 0, 800, 803, 809, 843, 0,
327 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
328 /* 0x1f - 1280x800@120Hz RB */
329 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
330 1360, 1440, 0, 800, 803, 809, 847, 0,
331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
332 /* 0x20 - 1280x960@60Hz */
333 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
334 1488, 1800, 0, 960, 961, 964, 1000, 0,
335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
336 /* 0x21 - 1280x960@85Hz */
337 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
338 1504, 1728, 0, 960, 961, 964, 1011, 0,
339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
340 /* 0x22 - 1280x960@120Hz RB */
341 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
342 1360, 1440, 0, 960, 963, 967, 1017, 0,
343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
344 /* 0x23 - 1280x1024@60Hz */
345 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
346 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
348 /* 0x24 - 1280x1024@75Hz */
349 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
350 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
352 /* 0x25 - 1280x1024@85Hz */
353 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
354 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
356 /* 0x26 - 1280x1024@120Hz RB */
357 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
358 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
360 /* 0x27 - 1360x768@60Hz */
361 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
362 1536, 1792, 0, 768, 771, 777, 795, 0,
363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
364 /* 0x28 - 1360x768@120Hz RB */
365 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
366 1440, 1520, 0, 768, 771, 776, 813, 0,
367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
368 /* 0x51 - 1366x768@60Hz */
369 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
370 1579, 1792, 0, 768, 771, 774, 798, 0,
371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
372 /* 0x56 - 1366x768@60Hz */
373 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
374 1436, 1500, 0, 768, 769, 772, 800, 0,
375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
376 /* 0x29 - 1400x1050@60Hz RB */
377 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
378 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
380 /* 0x2a - 1400x1050@60Hz */
381 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
382 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
383 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
384 /* 0x2b - 1400x1050@75Hz */
385 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
386 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
387 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
388 /* 0x2c - 1400x1050@85Hz */
389 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
390 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
391 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
392 /* 0x2d - 1400x1050@120Hz RB */
393 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
394 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
396 /* 0x2e - 1440x900@60Hz RB */
397 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
398 1520, 1600, 0, 900, 903, 909, 926, 0,
399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
400 /* 0x2f - 1440x900@60Hz */
401 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
402 1672, 1904, 0, 900, 903, 909, 934, 0,
403 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
404 /* 0x30 - 1440x900@75Hz */
405 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
406 1688, 1936, 0, 900, 903, 909, 942, 0,
407 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
408 /* 0x31 - 1440x900@85Hz */
409 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
410 1696, 1952, 0, 900, 903, 909, 948, 0,
411 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
412 /* 0x32 - 1440x900@120Hz RB */
413 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
414 1520, 1600, 0, 900, 903, 909, 953, 0,
415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
416 /* 0x53 - 1600x900@60Hz */
417 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
418 1704, 1800, 0, 900, 901, 904, 1000, 0,
419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
420 /* 0x33 - 1600x1200@60Hz */
421 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
422 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
424 /* 0x34 - 1600x1200@65Hz */
425 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
426 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
428 /* 0x35 - 1600x1200@70Hz */
429 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
430 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
432 /* 0x36 - 1600x1200@75Hz */
433 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
434 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
436 /* 0x37 - 1600x1200@85Hz */
437 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
438 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
440 /* 0x38 - 1600x1200@120Hz RB */
441 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
442 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
444 /* 0x39 - 1680x1050@60Hz RB */
445 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
446 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
448 /* 0x3a - 1680x1050@60Hz */
449 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
450 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
451 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
452 /* 0x3b - 1680x1050@75Hz */
453 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
454 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
455 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
456 /* 0x3c - 1680x1050@85Hz */
457 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
458 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
459 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
460 /* 0x3d - 1680x1050@120Hz RB */
461 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
462 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
464 /* 0x3e - 1792x1344@60Hz */
465 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
466 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
467 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
468 /* 0x3f - 1792x1344@75Hz */
469 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
470 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
471 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
472 /* 0x40 - 1792x1344@120Hz RB */
473 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
474 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
476 /* 0x41 - 1856x1392@60Hz */
477 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
478 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
479 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
480 /* 0x42 - 1856x1392@75Hz */
481 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
482 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
483 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
484 /* 0x43 - 1856x1392@120Hz RB */
485 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
486 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
488 /* 0x52 - 1920x1080@60Hz */
489 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
490 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
491 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
492 /* 0x44 - 1920x1200@60Hz RB */
493 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
494 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
496 /* 0x45 - 1920x1200@60Hz */
497 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
498 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
499 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
500 /* 0x46 - 1920x1200@75Hz */
501 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
502 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
503 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
504 /* 0x47 - 1920x1200@85Hz */
505 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
506 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
507 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
508 /* 0x48 - 1920x1200@120Hz RB */
509 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
510 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
512 /* 0x49 - 1920x1440@60Hz */
513 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
514 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
515 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
516 /* 0x4a - 1920x1440@75Hz */
517 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
518 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
519 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
520 /* 0x4b - 1920x1440@120Hz RB */
521 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
522 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
524 /* 0x54 - 2048x1152@60Hz */
525 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
526 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
528 /* 0x4c - 2560x1600@60Hz RB */
529 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
530 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
532 /* 0x4d - 2560x1600@60Hz */
533 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
534 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
535 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
536 /* 0x4e - 2560x1600@75Hz */
537 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
538 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
539 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
540 /* 0x4f - 2560x1600@85Hz */
541 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
542 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
543 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
544 /* 0x50 - 2560x1600@120Hz RB */
545 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
546 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
548 /* 0x57 - 4096x2160@60Hz RB */
549 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
550 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
552 /* 0x58 - 4096x2160@59.94Hz RB */
553 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
554 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
559 * These more or less come from the DMT spec. The 720x400 modes are
560 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
561 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
562 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
565 * The DMT modes have been fact-checked; the rest are mild guesses.
567 static const struct drm_display_mode edid_est_modes[] = {
568 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
569 968, 1056, 0, 600, 601, 605, 628, 0,
570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
571 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
572 896, 1024, 0, 600, 601, 603, 625, 0,
573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
574 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
575 720, 840, 0, 480, 481, 484, 500, 0,
576 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
577 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
578 704, 832, 0, 480, 489, 492, 520, 0,
579 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
580 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
581 768, 864, 0, 480, 483, 486, 525, 0,
582 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
583 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
584 752, 800, 0, 480, 490, 492, 525, 0,
585 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
586 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
587 846, 900, 0, 400, 421, 423, 449, 0,
588 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
589 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
590 846, 900, 0, 400, 412, 414, 449, 0,
591 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
592 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
593 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
595 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
596 1136, 1312, 0, 768, 769, 772, 800, 0,
597 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
598 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
599 1184, 1328, 0, 768, 771, 777, 806, 0,
600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
601 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
602 1184, 1344, 0, 768, 771, 777, 806, 0,
603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
604 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
605 1208, 1264, 0, 768, 768, 776, 817, 0,
606 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
607 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
608 928, 1152, 0, 624, 625, 628, 667, 0,
609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
610 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
611 896, 1056, 0, 600, 601, 604, 625, 0,
612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
613 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
614 976, 1040, 0, 600, 637, 643, 666, 0,
615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
616 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
617 1344, 1600, 0, 864, 865, 868, 900, 0,
618 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
628 static const struct minimode est3_modes[] = {
636 { 1024, 768, 85, 0 },
637 { 1152, 864, 75, 0 },
639 { 1280, 768, 60, 1 },
640 { 1280, 768, 60, 0 },
641 { 1280, 768, 75, 0 },
642 { 1280, 768, 85, 0 },
643 { 1280, 960, 60, 0 },
644 { 1280, 960, 85, 0 },
645 { 1280, 1024, 60, 0 },
646 { 1280, 1024, 85, 0 },
648 { 1360, 768, 60, 0 },
649 { 1440, 900, 60, 1 },
650 { 1440, 900, 60, 0 },
651 { 1440, 900, 75, 0 },
652 { 1440, 900, 85, 0 },
653 { 1400, 1050, 60, 1 },
654 { 1400, 1050, 60, 0 },
655 { 1400, 1050, 75, 0 },
657 { 1400, 1050, 85, 0 },
658 { 1680, 1050, 60, 1 },
659 { 1680, 1050, 60, 0 },
660 { 1680, 1050, 75, 0 },
661 { 1680, 1050, 85, 0 },
662 { 1600, 1200, 60, 0 },
663 { 1600, 1200, 65, 0 },
664 { 1600, 1200, 70, 0 },
666 { 1600, 1200, 75, 0 },
667 { 1600, 1200, 85, 0 },
668 { 1792, 1344, 60, 0 },
669 { 1792, 1344, 75, 0 },
670 { 1856, 1392, 60, 0 },
671 { 1856, 1392, 75, 0 },
672 { 1920, 1200, 60, 1 },
673 { 1920, 1200, 60, 0 },
675 { 1920, 1200, 75, 0 },
676 { 1920, 1200, 85, 0 },
677 { 1920, 1440, 60, 0 },
678 { 1920, 1440, 75, 0 },
681 static const struct minimode extra_modes[] = {
682 { 1024, 576, 60, 0 },
683 { 1366, 768, 60, 0 },
684 { 1600, 900, 60, 0 },
685 { 1680, 945, 60, 0 },
686 { 1920, 1080, 60, 0 },
687 { 2048, 1152, 60, 0 },
688 { 2048, 1536, 60, 0 },
692 * Probably taken from CEA-861 spec.
693 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
695 * Index using the VIC.
697 static const struct drm_display_mode edid_cea_modes[] = {
698 /* 0 - dummy, VICs start at 1 */
700 /* 1 - 640x480@60Hz 4:3 */
701 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
702 752, 800, 0, 480, 490, 492, 525, 0,
703 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
704 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
705 /* 2 - 720x480@60Hz 4:3 */
706 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
707 798, 858, 0, 480, 489, 495, 525, 0,
708 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
709 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
710 /* 3 - 720x480@60Hz 16:9 */
711 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
712 798, 858, 0, 480, 489, 495, 525, 0,
713 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
714 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
715 /* 4 - 1280x720@60Hz 16:9 */
716 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
717 1430, 1650, 0, 720, 725, 730, 750, 0,
718 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
719 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
720 /* 5 - 1920x1080i@60Hz 16:9 */
721 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
722 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
723 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
724 DRM_MODE_FLAG_INTERLACE),
725 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
726 /* 6 - 720(1440)x480i@60Hz 4:3 */
727 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
728 801, 858, 0, 480, 488, 494, 525, 0,
729 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
730 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
731 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
732 /* 7 - 720(1440)x480i@60Hz 16:9 */
733 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
734 801, 858, 0, 480, 488, 494, 525, 0,
735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
736 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
737 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
738 /* 8 - 720(1440)x240@60Hz 4:3 */
739 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
740 801, 858, 0, 240, 244, 247, 262, 0,
741 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
742 DRM_MODE_FLAG_DBLCLK),
743 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
744 /* 9 - 720(1440)x240@60Hz 16:9 */
745 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
746 801, 858, 0, 240, 244, 247, 262, 0,
747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
748 DRM_MODE_FLAG_DBLCLK),
749 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
750 /* 10 - 2880x480i@60Hz 4:3 */
751 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
752 3204, 3432, 0, 480, 488, 494, 525, 0,
753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
754 DRM_MODE_FLAG_INTERLACE),
755 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
756 /* 11 - 2880x480i@60Hz 16:9 */
757 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
758 3204, 3432, 0, 480, 488, 494, 525, 0,
759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
760 DRM_MODE_FLAG_INTERLACE),
761 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
762 /* 12 - 2880x240@60Hz 4:3 */
763 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
764 3204, 3432, 0, 240, 244, 247, 262, 0,
765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
766 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
767 /* 13 - 2880x240@60Hz 16:9 */
768 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
769 3204, 3432, 0, 240, 244, 247, 262, 0,
770 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
771 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
772 /* 14 - 1440x480@60Hz 4:3 */
773 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
774 1596, 1716, 0, 480, 489, 495, 525, 0,
775 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
776 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
777 /* 15 - 1440x480@60Hz 16:9 */
778 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
779 1596, 1716, 0, 480, 489, 495, 525, 0,
780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
781 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
782 /* 16 - 1920x1080@60Hz 16:9 */
783 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
784 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
785 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
786 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
787 /* 17 - 720x576@50Hz 4:3 */
788 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
789 796, 864, 0, 576, 581, 586, 625, 0,
790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
791 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
792 /* 18 - 720x576@50Hz 16:9 */
793 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
794 796, 864, 0, 576, 581, 586, 625, 0,
795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
796 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
797 /* 19 - 1280x720@50Hz 16:9 */
798 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
799 1760, 1980, 0, 720, 725, 730, 750, 0,
800 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
801 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
802 /* 20 - 1920x1080i@50Hz 16:9 */
803 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
804 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
805 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
806 DRM_MODE_FLAG_INTERLACE),
807 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
808 /* 21 - 720(1440)x576i@50Hz 4:3 */
809 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
810 795, 864, 0, 576, 580, 586, 625, 0,
811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
812 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
813 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
814 /* 22 - 720(1440)x576i@50Hz 16:9 */
815 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
816 795, 864, 0, 576, 580, 586, 625, 0,
817 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
818 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
819 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
820 /* 23 - 720(1440)x288@50Hz 4:3 */
821 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
822 795, 864, 0, 288, 290, 293, 312, 0,
823 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
824 DRM_MODE_FLAG_DBLCLK),
825 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
826 /* 24 - 720(1440)x288@50Hz 16:9 */
827 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
828 795, 864, 0, 288, 290, 293, 312, 0,
829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
830 DRM_MODE_FLAG_DBLCLK),
831 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
832 /* 25 - 2880x576i@50Hz 4:3 */
833 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
834 3180, 3456, 0, 576, 580, 586, 625, 0,
835 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
836 DRM_MODE_FLAG_INTERLACE),
837 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
838 /* 26 - 2880x576i@50Hz 16:9 */
839 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
840 3180, 3456, 0, 576, 580, 586, 625, 0,
841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
842 DRM_MODE_FLAG_INTERLACE),
843 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
844 /* 27 - 2880x288@50Hz 4:3 */
845 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
846 3180, 3456, 0, 288, 290, 293, 312, 0,
847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
848 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
849 /* 28 - 2880x288@50Hz 16:9 */
850 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
851 3180, 3456, 0, 288, 290, 293, 312, 0,
852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
853 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
854 /* 29 - 1440x576@50Hz 4:3 */
855 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
856 1592, 1728, 0, 576, 581, 586, 625, 0,
857 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
858 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
859 /* 30 - 1440x576@50Hz 16:9 */
860 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
861 1592, 1728, 0, 576, 581, 586, 625, 0,
862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
863 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
864 /* 31 - 1920x1080@50Hz 16:9 */
865 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
866 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
867 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
868 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
869 /* 32 - 1920x1080@24Hz 16:9 */
870 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
871 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
872 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
873 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
874 /* 33 - 1920x1080@25Hz 16:9 */
875 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
876 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
877 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
878 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
879 /* 34 - 1920x1080@30Hz 16:9 */
880 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
881 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
882 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
883 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
884 /* 35 - 2880x480@60Hz 4:3 */
885 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
886 3192, 3432, 0, 480, 489, 495, 525, 0,
887 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
888 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
889 /* 36 - 2880x480@60Hz 16:9 */
890 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
891 3192, 3432, 0, 480, 489, 495, 525, 0,
892 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
893 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
894 /* 37 - 2880x576@50Hz 4:3 */
895 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
896 3184, 3456, 0, 576, 581, 586, 625, 0,
897 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
898 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
899 /* 38 - 2880x576@50Hz 16:9 */
900 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
901 3184, 3456, 0, 576, 581, 586, 625, 0,
902 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
903 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
904 /* 39 - 1920x1080i@50Hz 16:9 */
905 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
906 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
907 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
908 DRM_MODE_FLAG_INTERLACE),
909 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
910 /* 40 - 1920x1080i@100Hz 16:9 */
911 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
912 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
913 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
914 DRM_MODE_FLAG_INTERLACE),
915 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
916 /* 41 - 1280x720@100Hz 16:9 */
917 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
918 1760, 1980, 0, 720, 725, 730, 750, 0,
919 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
920 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
921 /* 42 - 720x576@100Hz 4:3 */
922 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
923 796, 864, 0, 576, 581, 586, 625, 0,
924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
925 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
926 /* 43 - 720x576@100Hz 16:9 */
927 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
928 796, 864, 0, 576, 581, 586, 625, 0,
929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
930 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
931 /* 44 - 720(1440)x576i@100Hz 4:3 */
932 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
933 795, 864, 0, 576, 580, 586, 625, 0,
934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
935 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
936 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
937 /* 45 - 720(1440)x576i@100Hz 16:9 */
938 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
939 795, 864, 0, 576, 580, 586, 625, 0,
940 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
941 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
942 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
943 /* 46 - 1920x1080i@120Hz 16:9 */
944 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
945 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
946 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
947 DRM_MODE_FLAG_INTERLACE),
948 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
949 /* 47 - 1280x720@120Hz 16:9 */
950 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
951 1430, 1650, 0, 720, 725, 730, 750, 0,
952 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
953 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
954 /* 48 - 720x480@120Hz 4:3 */
955 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
956 798, 858, 0, 480, 489, 495, 525, 0,
957 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
958 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
959 /* 49 - 720x480@120Hz 16:9 */
960 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
961 798, 858, 0, 480, 489, 495, 525, 0,
962 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
963 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
964 /* 50 - 720(1440)x480i@120Hz 4:3 */
965 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
966 801, 858, 0, 480, 488, 494, 525, 0,
967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
968 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
969 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
970 /* 51 - 720(1440)x480i@120Hz 16:9 */
971 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
972 801, 858, 0, 480, 488, 494, 525, 0,
973 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
974 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
975 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
976 /* 52 - 720x576@200Hz 4:3 */
977 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
978 796, 864, 0, 576, 581, 586, 625, 0,
979 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
980 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
981 /* 53 - 720x576@200Hz 16:9 */
982 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
983 796, 864, 0, 576, 581, 586, 625, 0,
984 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
986 /* 54 - 720(1440)x576i@200Hz 4:3 */
987 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
988 795, 864, 0, 576, 580, 586, 625, 0,
989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
990 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
991 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
992 /* 55 - 720(1440)x576i@200Hz 16:9 */
993 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
994 795, 864, 0, 576, 580, 586, 625, 0,
995 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
996 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
997 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
998 /* 56 - 720x480@240Hz 4:3 */
999 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1000 798, 858, 0, 480, 489, 495, 525, 0,
1001 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1002 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1003 /* 57 - 720x480@240Hz 16:9 */
1004 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1005 798, 858, 0, 480, 489, 495, 525, 0,
1006 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1007 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1008 /* 58 - 720(1440)x480i@240Hz 4:3 */
1009 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1010 801, 858, 0, 480, 488, 494, 525, 0,
1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1012 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1013 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1014 /* 59 - 720(1440)x480i@240Hz 16:9 */
1015 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1016 801, 858, 0, 480, 488, 494, 525, 0,
1017 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1018 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1019 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1020 /* 60 - 1280x720@24Hz 16:9 */
1021 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1022 3080, 3300, 0, 720, 725, 730, 750, 0,
1023 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1024 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1025 /* 61 - 1280x720@25Hz 16:9 */
1026 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1027 3740, 3960, 0, 720, 725, 730, 750, 0,
1028 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1029 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1030 /* 62 - 1280x720@30Hz 16:9 */
1031 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1032 3080, 3300, 0, 720, 725, 730, 750, 0,
1033 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1034 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1035 /* 63 - 1920x1080@120Hz 16:9 */
1036 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1037 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1038 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1039 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1040 /* 64 - 1920x1080@100Hz 16:9 */
1041 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1042 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1043 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1044 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1045 /* 65 - 1280x720@24Hz 64:27 */
1046 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1047 3080, 3300, 0, 720, 725, 730, 750, 0,
1048 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1049 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1050 /* 66 - 1280x720@25Hz 64:27 */
1051 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1052 3740, 3960, 0, 720, 725, 730, 750, 0,
1053 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1054 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1055 /* 67 - 1280x720@30Hz 64:27 */
1056 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1057 3080, 3300, 0, 720, 725, 730, 750, 0,
1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1059 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1060 /* 68 - 1280x720@50Hz 64:27 */
1061 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1062 1760, 1980, 0, 720, 725, 730, 750, 0,
1063 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1064 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1065 /* 69 - 1280x720@60Hz 64:27 */
1066 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1067 1430, 1650, 0, 720, 725, 730, 750, 0,
1068 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1069 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1070 /* 70 - 1280x720@100Hz 64:27 */
1071 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1072 1760, 1980, 0, 720, 725, 730, 750, 0,
1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1074 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1075 /* 71 - 1280x720@120Hz 64:27 */
1076 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1077 1430, 1650, 0, 720, 725, 730, 750, 0,
1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1079 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1080 /* 72 - 1920x1080@24Hz 64:27 */
1081 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1082 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1084 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1085 /* 73 - 1920x1080@25Hz 64:27 */
1086 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1087 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1089 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1090 /* 74 - 1920x1080@30Hz 64:27 */
1091 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1092 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1094 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1095 /* 75 - 1920x1080@50Hz 64:27 */
1096 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1097 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1099 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1100 /* 76 - 1920x1080@60Hz 64:27 */
1101 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1102 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1104 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1105 /* 77 - 1920x1080@100Hz 64:27 */
1106 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1107 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1109 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1110 /* 78 - 1920x1080@120Hz 64:27 */
1111 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1112 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1114 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1115 /* 79 - 1680x720@24Hz 64:27 */
1116 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1117 3080, 3300, 0, 720, 725, 730, 750, 0,
1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1119 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1120 /* 80 - 1680x720@25Hz 64:27 */
1121 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1122 2948, 3168, 0, 720, 725, 730, 750, 0,
1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1124 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1125 /* 81 - 1680x720@30Hz 64:27 */
1126 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1127 2420, 2640, 0, 720, 725, 730, 750, 0,
1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1129 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1130 /* 82 - 1680x720@50Hz 64:27 */
1131 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1132 1980, 2200, 0, 720, 725, 730, 750, 0,
1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1134 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1135 /* 83 - 1680x720@60Hz 64:27 */
1136 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1137 1980, 2200, 0, 720, 725, 730, 750, 0,
1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1139 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1140 /* 84 - 1680x720@100Hz 64:27 */
1141 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1142 1780, 2000, 0, 720, 725, 730, 825, 0,
1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1144 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1145 /* 85 - 1680x720@120Hz 64:27 */
1146 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1147 1780, 2000, 0, 720, 725, 730, 825, 0,
1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1149 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1150 /* 86 - 2560x1080@24Hz 64:27 */
1151 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1152 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1154 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1155 /* 87 - 2560x1080@25Hz 64:27 */
1156 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1157 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1159 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1160 /* 88 - 2560x1080@30Hz 64:27 */
1161 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1162 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1164 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1165 /* 89 - 2560x1080@50Hz 64:27 */
1166 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1167 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1169 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1170 /* 90 - 2560x1080@60Hz 64:27 */
1171 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1172 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1174 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1175 /* 91 - 2560x1080@100Hz 64:27 */
1176 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1177 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1179 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1180 /* 92 - 2560x1080@120Hz 64:27 */
1181 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1182 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1184 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1185 /* 93 - 3840x2160@24Hz 16:9 */
1186 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1187 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1189 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1190 /* 94 - 3840x2160@25Hz 16:9 */
1191 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1192 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1194 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1195 /* 95 - 3840x2160@30Hz 16:9 */
1196 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1197 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1199 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1200 /* 96 - 3840x2160@50Hz 16:9 */
1201 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1202 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1204 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1205 /* 97 - 3840x2160@60Hz 16:9 */
1206 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1207 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1209 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1210 /* 98 - 4096x2160@24Hz 256:135 */
1211 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1212 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1214 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1215 /* 99 - 4096x2160@25Hz 256:135 */
1216 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1217 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1219 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1220 /* 100 - 4096x2160@30Hz 256:135 */
1221 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1222 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1224 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1225 /* 101 - 4096x2160@50Hz 256:135 */
1226 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1227 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1229 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1230 /* 102 - 4096x2160@60Hz 256:135 */
1231 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1232 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1234 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1235 /* 103 - 3840x2160@24Hz 64:27 */
1236 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1237 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1239 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1240 /* 104 - 3840x2160@25Hz 64:27 */
1241 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1242 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1244 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1245 /* 105 - 3840x2160@30Hz 64:27 */
1246 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1247 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1249 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1250 /* 106 - 3840x2160@50Hz 64:27 */
1251 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1252 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1254 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1255 /* 107 - 3840x2160@60Hz 64:27 */
1256 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1257 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1259 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1263 * HDMI 1.4 4k modes. Index using the VIC.
1265 static const struct drm_display_mode edid_4k_modes[] = {
1266 /* 0 - dummy, VICs start at 1 */
1268 /* 1 - 3840x2160@30Hz */
1269 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1270 3840, 4016, 4104, 4400, 0,
1271 2160, 2168, 2178, 2250, 0,
1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1274 /* 2 - 3840x2160@25Hz */
1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1276 3840, 4896, 4984, 5280, 0,
1277 2160, 2168, 2178, 2250, 0,
1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1280 /* 3 - 3840x2160@24Hz */
1281 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1282 3840, 5116, 5204, 5500, 0,
1283 2160, 2168, 2178, 2250, 0,
1284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1286 /* 4 - 4096x2160@24Hz (SMPTE) */
1287 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1288 4096, 5116, 5204, 5500, 0,
1289 2160, 2168, 2178, 2250, 0,
1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1294 /*** DDC fetch and block validation ***/
1296 static const u8 edid_header[] = {
1297 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1301 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1302 * @raw_edid: pointer to raw base EDID block
1304 * Sanity check the header of the base EDID block.
1306 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1308 int drm_edid_header_is_valid(const u8 *raw_edid)
1312 for (i = 0; i < sizeof(edid_header); i++)
1313 if (raw_edid[i] == edid_header[i])
1318 EXPORT_SYMBOL(drm_edid_header_is_valid);
1320 static int edid_fixup __read_mostly = 6;
1321 module_param_named(edid_fixup, edid_fixup, int, 0400);
1322 MODULE_PARM_DESC(edid_fixup,
1323 "Minimum number of valid EDID header bytes (0-8, default 6)");
1325 static void drm_get_displayid(struct drm_connector *connector,
1328 static int drm_edid_block_checksum(const u8 *raw_edid)
1332 for (i = 0; i < EDID_LENGTH; i++)
1333 csum += raw_edid[i];
1338 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1340 if (memchr_inv(in_edid, 0, length))
1347 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1348 * @raw_edid: pointer to raw EDID block
1349 * @block: type of block to validate (0 for base, extension otherwise)
1350 * @print_bad_edid: if true, dump bad EDID blocks to the console
1351 * @edid_corrupt: if true, the header or checksum is invalid
1353 * Validate a base or extension EDID block and optionally dump bad blocks to
1356 * Return: True if the block is valid, false otherwise.
1358 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1362 struct edid *edid = (struct edid *)raw_edid;
1364 if (WARN_ON(!raw_edid))
1367 if (edid_fixup > 8 || edid_fixup < 0)
1371 int score = drm_edid_header_is_valid(raw_edid);
1374 *edid_corrupt = false;
1375 } else if (score >= edid_fixup) {
1376 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1377 * The corrupt flag needs to be set here otherwise, the
1378 * fix-up code here will correct the problem, the
1379 * checksum is correct and the test fails
1382 *edid_corrupt = true;
1383 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1384 memcpy(raw_edid, edid_header, sizeof(edid_header));
1387 *edid_corrupt = true;
1392 csum = drm_edid_block_checksum(raw_edid);
1395 *edid_corrupt = true;
1397 /* allow CEA to slide through, switches mangle this */
1398 if (raw_edid[0] == CEA_EXT) {
1399 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1400 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1403 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1409 /* per-block-type checks */
1410 switch (raw_edid[0]) {
1412 if (edid->version != 1) {
1413 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1417 if (edid->revision > 4)
1418 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1428 if (print_bad_edid) {
1429 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1430 pr_notice("EDID block is all zeroes\n");
1432 pr_notice("Raw EDID:\n");
1433 print_hex_dump(KERN_NOTICE,
1434 " \t", DUMP_PREFIX_NONE, 16, 1,
1435 raw_edid, EDID_LENGTH, false);
1440 EXPORT_SYMBOL(drm_edid_block_valid);
1443 * drm_edid_is_valid - sanity check EDID data
1446 * Sanity-check an entire EDID record (including extensions)
1448 * Return: True if the EDID data is valid, false otherwise.
1450 bool drm_edid_is_valid(struct edid *edid)
1453 u8 *raw = (u8 *)edid;
1458 for (i = 0; i <= edid->extensions; i++)
1459 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1464 EXPORT_SYMBOL(drm_edid_is_valid);
1466 #define DDC_SEGMENT_ADDR 0x30
1468 * drm_do_probe_ddc_edid() - get EDID information via I2C
1469 * @data: I2C device adapter
1470 * @buf: EDID data buffer to be filled
1471 * @block: 128 byte EDID block to start fetching from
1472 * @len: EDID data buffer length to fetch
1474 * Try to fetch EDID information by calling I2C driver functions.
1476 * Return: 0 on success or -1 on failure.
1479 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1481 struct i2c_adapter *adapter = data;
1482 unsigned char start = block * EDID_LENGTH;
1483 unsigned char segment = block >> 1;
1484 unsigned char xfers = segment ? 3 : 2;
1485 int ret, retries = 5;
1488 * The core I2C driver will automatically retry the transfer if the
1489 * adapter reports EAGAIN. However, we find that bit-banging transfers
1490 * are susceptible to errors under a heavily loaded machine and
1491 * generate spurious NAKs and timeouts. Retrying the transfer
1492 * of the individual block a few times seems to overcome this.
1495 struct i2c_msg msgs[] = {
1497 .addr = DDC_SEGMENT_ADDR,
1515 * Avoid sending the segment addr to not upset non-compliant
1518 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1520 if (ret == -ENXIO) {
1521 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1525 } while (ret != xfers && --retries);
1527 return ret == xfers ? 0 : -1;
1530 static void connector_bad_edid(struct drm_connector *connector,
1531 u8 *edid, int num_blocks)
1535 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1538 dev_warn(connector->dev->dev,
1539 "%s: EDID is invalid:\n",
1541 for (i = 0; i < num_blocks; i++) {
1542 u8 *block = edid + i * EDID_LENGTH;
1545 if (drm_edid_is_zero(block, EDID_LENGTH))
1546 sprintf(prefix, "\t[%02x] ZERO ", i);
1547 else if (!drm_edid_block_valid(block, i, false, NULL))
1548 sprintf(prefix, "\t[%02x] BAD ", i);
1550 sprintf(prefix, "\t[%02x] GOOD ", i);
1552 print_hex_dump(KERN_WARNING,
1553 prefix, DUMP_PREFIX_NONE, 16, 1,
1554 block, EDID_LENGTH, false);
1559 * drm_do_get_edid - get EDID data using a custom EDID block read function
1560 * @connector: connector we're probing
1561 * @get_edid_block: EDID block read function
1562 * @data: private data passed to the block read function
1564 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1565 * exposes a different interface to read EDID blocks this function can be used
1566 * to get EDID data using a custom block read function.
1568 * As in the general case the DDC bus is accessible by the kernel at the I2C
1569 * level, drivers must make all reasonable efforts to expose it as an I2C
1570 * adapter and use drm_get_edid() instead of abusing this function.
1572 * The EDID may be overridden using debugfs override_edid or firmare EDID
1573 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1574 * order. Having either of them bypasses actual EDID reads.
1576 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1578 struct edid *drm_do_get_edid(struct drm_connector *connector,
1579 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1583 int i, j = 0, valid_extensions = 0;
1585 struct edid *override = NULL;
1587 if (connector->override_edid)
1588 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1591 override = drm_load_edid_firmware(connector);
1593 if (!IS_ERR_OR_NULL(override))
1596 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1599 /* base block fetch */
1600 for (i = 0; i < 4; i++) {
1601 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1603 if (drm_edid_block_valid(edid, 0, false,
1604 &connector->edid_corrupt))
1606 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1607 connector->null_edid_counter++;
1614 /* if there's no extensions, we're done */
1615 valid_extensions = edid[0x7e];
1616 if (valid_extensions == 0)
1617 return (struct edid *)edid;
1619 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1624 for (j = 1; j <= edid[0x7e]; j++) {
1625 u8 *block = edid + j * EDID_LENGTH;
1627 for (i = 0; i < 4; i++) {
1628 if (get_edid_block(data, block, j, EDID_LENGTH))
1630 if (drm_edid_block_valid(block, j, false, NULL))
1638 if (valid_extensions != edid[0x7e]) {
1641 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1643 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1644 edid[0x7e] = valid_extensions;
1646 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1652 for (i = 0; i <= edid[0x7e]; i++) {
1653 u8 *block = edid + i * EDID_LENGTH;
1655 if (!drm_edid_block_valid(block, i, false, NULL))
1658 memcpy(base, block, EDID_LENGTH);
1659 base += EDID_LENGTH;
1666 return (struct edid *)edid;
1669 connector_bad_edid(connector, edid, 1);
1674 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1677 * drm_probe_ddc() - probe DDC presence
1678 * @adapter: I2C adapter to probe
1680 * Return: True on success, false on failure.
1683 drm_probe_ddc(struct i2c_adapter *adapter)
1687 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1689 EXPORT_SYMBOL(drm_probe_ddc);
1692 * drm_get_edid - get EDID data, if available
1693 * @connector: connector we're probing
1694 * @adapter: I2C adapter to use for DDC
1696 * Poke the given I2C channel to grab EDID data if possible. If found,
1697 * attach it to the connector.
1699 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1701 struct edid *drm_get_edid(struct drm_connector *connector,
1702 struct i2c_adapter *adapter)
1706 if (connector->force == DRM_FORCE_OFF)
1709 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1712 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1714 drm_get_displayid(connector, edid);
1717 EXPORT_SYMBOL(drm_get_edid);
1720 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1721 * @connector: connector we're probing
1722 * @adapter: I2C adapter to use for DDC
1724 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1725 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1726 * switch DDC to the GPU which is retrieving EDID.
1728 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1730 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1731 struct i2c_adapter *adapter)
1733 struct pci_dev *pdev = connector->dev->pdev;
1736 vga_switcheroo_lock_ddc(pdev);
1737 edid = drm_get_edid(connector, adapter);
1738 vga_switcheroo_unlock_ddc(pdev);
1742 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1745 * drm_edid_duplicate - duplicate an EDID and the extensions
1746 * @edid: EDID to duplicate
1748 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1750 struct edid *drm_edid_duplicate(const struct edid *edid)
1752 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1754 EXPORT_SYMBOL(drm_edid_duplicate);
1756 /*** EDID parsing ***/
1759 * edid_vendor - match a string against EDID's obfuscated vendor field
1760 * @edid: EDID to match
1761 * @vendor: vendor string
1763 * Returns true if @vendor is in @edid, false otherwise
1765 static bool edid_vendor(const struct edid *edid, const char *vendor)
1767 char edid_vendor[3];
1769 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1770 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1771 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1772 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1774 return !strncmp(edid_vendor, vendor, 3);
1778 * edid_get_quirks - return quirk flags for a given EDID
1779 * @edid: EDID to process
1781 * This tells subsequent routines what fixes they need to apply.
1783 static u32 edid_get_quirks(const struct edid *edid)
1785 const struct edid_quirk *quirk;
1788 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1789 quirk = &edid_quirk_list[i];
1791 if (edid_vendor(edid, quirk->vendor) &&
1792 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1793 return quirk->quirks;
1799 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1800 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1803 * edid_fixup_preferred - set preferred modes based on quirk list
1804 * @connector: has mode list to fix up
1805 * @quirks: quirks list
1807 * Walk the mode list for @connector, clearing the preferred status
1808 * on existing modes and setting it anew for the right mode ala @quirks.
1810 static void edid_fixup_preferred(struct drm_connector *connector,
1813 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1814 int target_refresh = 0;
1815 int cur_vrefresh, preferred_vrefresh;
1817 if (list_empty(&connector->probed_modes))
1820 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1821 target_refresh = 60;
1822 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1823 target_refresh = 75;
1825 preferred_mode = list_first_entry(&connector->probed_modes,
1826 struct drm_display_mode, head);
1828 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1829 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1831 if (cur_mode == preferred_mode)
1834 /* Largest mode is preferred */
1835 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1836 preferred_mode = cur_mode;
1838 cur_vrefresh = cur_mode->vrefresh ?
1839 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1840 preferred_vrefresh = preferred_mode->vrefresh ?
1841 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1842 /* At a given size, try to get closest to target refresh */
1843 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1844 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1845 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1846 preferred_mode = cur_mode;
1850 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1854 mode_is_rb(const struct drm_display_mode *mode)
1856 return (mode->htotal - mode->hdisplay == 160) &&
1857 (mode->hsync_end - mode->hdisplay == 80) &&
1858 (mode->hsync_end - mode->hsync_start == 32) &&
1859 (mode->vsync_start - mode->vdisplay == 3);
1863 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1864 * @dev: Device to duplicate against
1865 * @hsize: Mode width
1866 * @vsize: Mode height
1867 * @fresh: Mode refresh rate
1868 * @rb: Mode reduced-blanking-ness
1870 * Walk the DMT mode list looking for a match for the given parameters.
1872 * Return: A newly allocated copy of the mode, or NULL if not found.
1874 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1875 int hsize, int vsize, int fresh,
1880 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1881 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1882 if (hsize != ptr->hdisplay)
1884 if (vsize != ptr->vdisplay)
1886 if (fresh != drm_mode_vrefresh(ptr))
1888 if (rb != mode_is_rb(ptr))
1891 return drm_mode_duplicate(dev, ptr);
1896 EXPORT_SYMBOL(drm_mode_find_dmt);
1898 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1901 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1905 u8 *det_base = ext + d;
1908 for (i = 0; i < n; i++)
1909 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1913 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1915 unsigned int i, n = min((int)ext[0x02], 6);
1916 u8 *det_base = ext + 5;
1919 return; /* unknown version */
1921 for (i = 0; i < n; i++)
1922 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1926 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1929 struct edid *edid = (struct edid *)raw_edid;
1934 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1935 cb(&(edid->detailed_timings[i]), closure);
1937 for (i = 1; i <= raw_edid[0x7e]; i++) {
1938 u8 *ext = raw_edid + (i * EDID_LENGTH);
1941 cea_for_each_detailed_block(ext, cb, closure);
1944 vtb_for_each_detailed_block(ext, cb, closure);
1953 is_rb(struct detailed_timing *t, void *data)
1956 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1958 *(bool *)data = true;
1961 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1963 drm_monitor_supports_rb(struct edid *edid)
1965 if (edid->revision >= 4) {
1967 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1971 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1975 find_gtf2(struct detailed_timing *t, void *data)
1978 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1982 /* Secondary GTF curve kicks in above some break frequency */
1984 drm_gtf2_hbreak(struct edid *edid)
1987 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1988 return r ? (r[12] * 2) : 0;
1992 drm_gtf2_2c(struct edid *edid)
1995 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1996 return r ? r[13] : 0;
2000 drm_gtf2_m(struct edid *edid)
2003 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2004 return r ? (r[15] << 8) + r[14] : 0;
2008 drm_gtf2_k(struct edid *edid)
2011 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2012 return r ? r[16] : 0;
2016 drm_gtf2_2j(struct edid *edid)
2019 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2020 return r ? r[17] : 0;
2024 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2025 * @edid: EDID block to scan
2027 static int standard_timing_level(struct edid *edid)
2029 if (edid->revision >= 2) {
2030 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2032 if (drm_gtf2_hbreak(edid))
2040 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2041 * monitors fill with ascii space (0x20) instead.
2044 bad_std_timing(u8 a, u8 b)
2046 return (a == 0x00 && b == 0x00) ||
2047 (a == 0x01 && b == 0x01) ||
2048 (a == 0x20 && b == 0x20);
2052 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2053 * @connector: connector of for the EDID block
2054 * @edid: EDID block to scan
2055 * @t: standard timing params
2057 * Take the standard timing params (in this case width, aspect, and refresh)
2058 * and convert them into a real mode using CVT/GTF/DMT.
2060 static struct drm_display_mode *
2061 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2062 struct std_timing *t)
2064 struct drm_device *dev = connector->dev;
2065 struct drm_display_mode *m, *mode = NULL;
2068 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2069 >> EDID_TIMING_ASPECT_SHIFT;
2070 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2071 >> EDID_TIMING_VFREQ_SHIFT;
2072 int timing_level = standard_timing_level(edid);
2074 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2077 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2078 hsize = t->hsize * 8 + 248;
2079 /* vrefresh_rate = vfreq + 60 */
2080 vrefresh_rate = vfreq + 60;
2081 /* the vdisplay is calculated based on the aspect ratio */
2082 if (aspect_ratio == 0) {
2083 if (edid->revision < 3)
2086 vsize = (hsize * 10) / 16;
2087 } else if (aspect_ratio == 1)
2088 vsize = (hsize * 3) / 4;
2089 else if (aspect_ratio == 2)
2090 vsize = (hsize * 4) / 5;
2092 vsize = (hsize * 9) / 16;
2094 /* HDTV hack, part 1 */
2095 if (vrefresh_rate == 60 &&
2096 ((hsize == 1360 && vsize == 765) ||
2097 (hsize == 1368 && vsize == 769))) {
2103 * If this connector already has a mode for this size and refresh
2104 * rate (because it came from detailed or CVT info), use that
2105 * instead. This way we don't have to guess at interlace or
2108 list_for_each_entry(m, &connector->probed_modes, head)
2109 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2110 drm_mode_vrefresh(m) == vrefresh_rate)
2113 /* HDTV hack, part 2 */
2114 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2115 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2119 mode->hdisplay = 1366;
2120 mode->hsync_start = mode->hsync_start - 1;
2121 mode->hsync_end = mode->hsync_end - 1;
2125 /* check whether it can be found in default mode table */
2126 if (drm_monitor_supports_rb(edid)) {
2127 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2132 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2136 /* okay, generate it */
2137 switch (timing_level) {
2141 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2145 * This is potentially wrong if there's ever a monitor with
2146 * more than one ranges section, each claiming a different
2147 * secondary GTF curve. Please don't do that.
2149 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2152 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2153 drm_mode_destroy(dev, mode);
2154 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2155 vrefresh_rate, 0, 0,
2163 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2171 * EDID is delightfully ambiguous about how interlaced modes are to be
2172 * encoded. Our internal representation is of frame height, but some
2173 * HDTV detailed timings are encoded as field height.
2175 * The format list here is from CEA, in frame size. Technically we
2176 * should be checking refresh rate too. Whatever.
2179 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2180 struct detailed_pixel_timing *pt)
2183 static const struct {
2185 } cea_interlaced[] = {
2195 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2198 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2199 if ((mode->hdisplay == cea_interlaced[i].w) &&
2200 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2201 mode->vdisplay *= 2;
2202 mode->vsync_start *= 2;
2203 mode->vsync_end *= 2;
2209 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2213 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2214 * @dev: DRM device (needed to create new mode)
2216 * @timing: EDID detailed timing info
2217 * @quirks: quirks to apply
2219 * An EDID detailed timing block contains enough info for us to create and
2220 * return a new struct drm_display_mode.
2222 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2224 struct detailed_timing *timing,
2227 struct drm_display_mode *mode;
2228 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2229 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2230 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2231 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2232 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2233 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2234 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2235 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2236 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2238 /* ignore tiny modes */
2239 if (hactive < 64 || vactive < 64)
2242 if (pt->misc & DRM_EDID_PT_STEREO) {
2243 DRM_DEBUG_KMS("stereo mode not supported\n");
2246 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2247 DRM_DEBUG_KMS("composite sync not supported\n");
2250 /* it is incorrect if hsync/vsync width is zero */
2251 if (!hsync_pulse_width || !vsync_pulse_width) {
2252 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2253 "Wrong Hsync/Vsync pulse width\n");
2257 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2258 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2265 mode = drm_mode_create(dev);
2269 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2270 timing->pixel_clock = cpu_to_le16(1088);
2272 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2274 mode->hdisplay = hactive;
2275 mode->hsync_start = mode->hdisplay + hsync_offset;
2276 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2277 mode->htotal = mode->hdisplay + hblank;
2279 mode->vdisplay = vactive;
2280 mode->vsync_start = mode->vdisplay + vsync_offset;
2281 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2282 mode->vtotal = mode->vdisplay + vblank;
2284 /* Some EDIDs have bogus h/vtotal values */
2285 if (mode->hsync_end > mode->htotal)
2286 mode->htotal = mode->hsync_end + 1;
2287 if (mode->vsync_end > mode->vtotal)
2288 mode->vtotal = mode->vsync_end + 1;
2290 drm_mode_do_interlace_quirk(mode, pt);
2292 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2293 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2296 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2297 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2298 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2299 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2302 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2303 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2305 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2306 mode->width_mm *= 10;
2307 mode->height_mm *= 10;
2310 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2311 mode->width_mm = edid->width_cm * 10;
2312 mode->height_mm = edid->height_cm * 10;
2315 mode->type = DRM_MODE_TYPE_DRIVER;
2316 mode->vrefresh = drm_mode_vrefresh(mode);
2317 drm_mode_set_name(mode);
2323 mode_in_hsync_range(const struct drm_display_mode *mode,
2324 struct edid *edid, u8 *t)
2326 int hsync, hmin, hmax;
2329 if (edid->revision >= 4)
2330 hmin += ((t[4] & 0x04) ? 255 : 0);
2332 if (edid->revision >= 4)
2333 hmax += ((t[4] & 0x08) ? 255 : 0);
2334 hsync = drm_mode_hsync(mode);
2336 return (hsync <= hmax && hsync >= hmin);
2340 mode_in_vsync_range(const struct drm_display_mode *mode,
2341 struct edid *edid, u8 *t)
2343 int vsync, vmin, vmax;
2346 if (edid->revision >= 4)
2347 vmin += ((t[4] & 0x01) ? 255 : 0);
2349 if (edid->revision >= 4)
2350 vmax += ((t[4] & 0x02) ? 255 : 0);
2351 vsync = drm_mode_vrefresh(mode);
2353 return (vsync <= vmax && vsync >= vmin);
2357 range_pixel_clock(struct edid *edid, u8 *t)
2360 if (t[9] == 0 || t[9] == 255)
2363 /* 1.4 with CVT support gives us real precision, yay */
2364 if (edid->revision >= 4 && t[10] == 0x04)
2365 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2367 /* 1.3 is pathetic, so fuzz up a bit */
2368 return t[9] * 10000 + 5001;
2372 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2373 struct detailed_timing *timing)
2376 u8 *t = (u8 *)timing;
2378 if (!mode_in_hsync_range(mode, edid, t))
2381 if (!mode_in_vsync_range(mode, edid, t))
2384 if ((max_clock = range_pixel_clock(edid, t)))
2385 if (mode->clock > max_clock)
2388 /* 1.4 max horizontal check */
2389 if (edid->revision >= 4 && t[10] == 0x04)
2390 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2393 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2399 static bool valid_inferred_mode(const struct drm_connector *connector,
2400 const struct drm_display_mode *mode)
2402 const struct drm_display_mode *m;
2405 list_for_each_entry(m, &connector->probed_modes, head) {
2406 if (mode->hdisplay == m->hdisplay &&
2407 mode->vdisplay == m->vdisplay &&
2408 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2409 return false; /* duplicated */
2410 if (mode->hdisplay <= m->hdisplay &&
2411 mode->vdisplay <= m->vdisplay)
2418 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2419 struct detailed_timing *timing)
2422 struct drm_display_mode *newmode;
2423 struct drm_device *dev = connector->dev;
2425 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2426 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2427 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2428 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2430 drm_mode_probed_add(connector, newmode);
2439 /* fix up 1366x768 mode from 1368x768;
2440 * GFT/CVT can't express 1366 width which isn't dividable by 8
2442 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2444 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2445 mode->hdisplay = 1366;
2446 mode->hsync_start--;
2448 drm_mode_set_name(mode);
2453 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2454 struct detailed_timing *timing)
2457 struct drm_display_mode *newmode;
2458 struct drm_device *dev = connector->dev;
2460 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2461 const struct minimode *m = &extra_modes[i];
2462 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2466 drm_mode_fixup_1366x768(newmode);
2467 if (!mode_in_range(newmode, edid, timing) ||
2468 !valid_inferred_mode(connector, newmode)) {
2469 drm_mode_destroy(dev, newmode);
2473 drm_mode_probed_add(connector, newmode);
2481 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2482 struct detailed_timing *timing)
2485 struct drm_display_mode *newmode;
2486 struct drm_device *dev = connector->dev;
2487 bool rb = drm_monitor_supports_rb(edid);
2489 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2490 const struct minimode *m = &extra_modes[i];
2491 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2495 drm_mode_fixup_1366x768(newmode);
2496 if (!mode_in_range(newmode, edid, timing) ||
2497 !valid_inferred_mode(connector, newmode)) {
2498 drm_mode_destroy(dev, newmode);
2502 drm_mode_probed_add(connector, newmode);
2510 do_inferred_modes(struct detailed_timing *timing, void *c)
2512 struct detailed_mode_closure *closure = c;
2513 struct detailed_non_pixel *data = &timing->data.other_data;
2514 struct detailed_data_monitor_range *range = &data->data.range;
2516 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2519 closure->modes += drm_dmt_modes_for_range(closure->connector,
2523 if (!version_greater(closure->edid, 1, 1))
2524 return; /* GTF not defined yet */
2526 switch (range->flags) {
2527 case 0x02: /* secondary gtf, XXX could do more */
2528 case 0x00: /* default gtf */
2529 closure->modes += drm_gtf_modes_for_range(closure->connector,
2533 case 0x04: /* cvt, only in 1.4+ */
2534 if (!version_greater(closure->edid, 1, 3))
2537 closure->modes += drm_cvt_modes_for_range(closure->connector,
2541 case 0x01: /* just the ranges, no formula */
2548 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2550 struct detailed_mode_closure closure = {
2551 .connector = connector,
2555 if (version_greater(edid, 1, 0))
2556 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2559 return closure.modes;
2563 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2565 int i, j, m, modes = 0;
2566 struct drm_display_mode *mode;
2567 u8 *est = ((u8 *)timing) + 6;
2569 for (i = 0; i < 6; i++) {
2570 for (j = 7; j >= 0; j--) {
2571 m = (i * 8) + (7 - j);
2572 if (m >= ARRAY_SIZE(est3_modes))
2574 if (est[i] & (1 << j)) {
2575 mode = drm_mode_find_dmt(connector->dev,
2581 drm_mode_probed_add(connector, mode);
2592 do_established_modes(struct detailed_timing *timing, void *c)
2594 struct detailed_mode_closure *closure = c;
2595 struct detailed_non_pixel *data = &timing->data.other_data;
2597 if (data->type == EDID_DETAIL_EST_TIMINGS)
2598 closure->modes += drm_est3_modes(closure->connector, timing);
2602 * add_established_modes - get est. modes from EDID and add them
2603 * @connector: connector to add mode(s) to
2604 * @edid: EDID block to scan
2606 * Each EDID block contains a bitmap of the supported "established modes" list
2607 * (defined above). Tease them out and add them to the global modes list.
2610 add_established_modes(struct drm_connector *connector, struct edid *edid)
2612 struct drm_device *dev = connector->dev;
2613 unsigned long est_bits = edid->established_timings.t1 |
2614 (edid->established_timings.t2 << 8) |
2615 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2617 struct detailed_mode_closure closure = {
2618 .connector = connector,
2622 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2623 if (est_bits & (1<<i)) {
2624 struct drm_display_mode *newmode;
2625 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2627 drm_mode_probed_add(connector, newmode);
2633 if (version_greater(edid, 1, 0))
2634 drm_for_each_detailed_block((u8 *)edid,
2635 do_established_modes, &closure);
2637 return modes + closure.modes;
2641 do_standard_modes(struct detailed_timing *timing, void *c)
2643 struct detailed_mode_closure *closure = c;
2644 struct detailed_non_pixel *data = &timing->data.other_data;
2645 struct drm_connector *connector = closure->connector;
2646 struct edid *edid = closure->edid;
2648 if (data->type == EDID_DETAIL_STD_MODES) {
2650 for (i = 0; i < 6; i++) {
2651 struct std_timing *std;
2652 struct drm_display_mode *newmode;
2654 std = &data->data.timings[i];
2655 newmode = drm_mode_std(connector, edid, std);
2657 drm_mode_probed_add(connector, newmode);
2665 * add_standard_modes - get std. modes from EDID and add them
2666 * @connector: connector to add mode(s) to
2667 * @edid: EDID block to scan
2669 * Standard modes can be calculated using the appropriate standard (DMT,
2670 * GTF or CVT. Grab them from @edid and add them to the list.
2673 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2676 struct detailed_mode_closure closure = {
2677 .connector = connector,
2681 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2682 struct drm_display_mode *newmode;
2684 newmode = drm_mode_std(connector, edid,
2685 &edid->standard_timings[i]);
2687 drm_mode_probed_add(connector, newmode);
2692 if (version_greater(edid, 1, 0))
2693 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2696 /* XXX should also look for standard codes in VTB blocks */
2698 return modes + closure.modes;
2701 static int drm_cvt_modes(struct drm_connector *connector,
2702 struct detailed_timing *timing)
2704 int i, j, modes = 0;
2705 struct drm_display_mode *newmode;
2706 struct drm_device *dev = connector->dev;
2707 struct cvt_timing *cvt;
2708 const int rates[] = { 60, 85, 75, 60, 50 };
2709 const u8 empty[3] = { 0, 0, 0 };
2711 for (i = 0; i < 4; i++) {
2712 int uninitialized_var(width), height;
2713 cvt = &(timing->data.other_data.data.cvt[i]);
2715 if (!memcmp(cvt->code, empty, 3))
2718 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2719 switch (cvt->code[1] & 0x0c) {
2721 width = height * 4 / 3;
2724 width = height * 16 / 9;
2727 width = height * 16 / 10;
2730 width = height * 15 / 9;
2734 for (j = 1; j < 5; j++) {
2735 if (cvt->code[2] & (1 << j)) {
2736 newmode = drm_cvt_mode(dev, width, height,
2740 drm_mode_probed_add(connector, newmode);
2751 do_cvt_mode(struct detailed_timing *timing, void *c)
2753 struct detailed_mode_closure *closure = c;
2754 struct detailed_non_pixel *data = &timing->data.other_data;
2756 if (data->type == EDID_DETAIL_CVT_3BYTE)
2757 closure->modes += drm_cvt_modes(closure->connector, timing);
2761 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2763 struct detailed_mode_closure closure = {
2764 .connector = connector,
2768 if (version_greater(edid, 1, 2))
2769 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2771 /* XXX should also look for CVT codes in VTB blocks */
2773 return closure.modes;
2776 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2779 do_detailed_mode(struct detailed_timing *timing, void *c)
2781 struct detailed_mode_closure *closure = c;
2782 struct drm_display_mode *newmode;
2784 if (timing->pixel_clock) {
2785 newmode = drm_mode_detailed(closure->connector->dev,
2786 closure->edid, timing,
2791 if (closure->preferred)
2792 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2795 * Detailed modes are limited to 10kHz pixel clock resolution,
2796 * so fix up anything that looks like CEA/HDMI mode, but the clock
2797 * is just slightly off.
2799 fixup_detailed_cea_mode_clock(newmode);
2801 drm_mode_probed_add(closure->connector, newmode);
2803 closure->preferred = false;
2808 * add_detailed_modes - Add modes from detailed timings
2809 * @connector: attached connector
2810 * @edid: EDID block to scan
2811 * @quirks: quirks to apply
2814 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2817 struct detailed_mode_closure closure = {
2818 .connector = connector,
2824 if (closure.preferred && !version_greater(edid, 1, 3))
2826 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2828 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2830 return closure.modes;
2833 #define AUDIO_BLOCK 0x01
2834 #define VIDEO_BLOCK 0x02
2835 #define VENDOR_BLOCK 0x03
2836 #define SPEAKER_BLOCK 0x04
2837 #define USE_EXTENDED_TAG 0x07
2838 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
2839 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
2840 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
2841 #define EDID_BASIC_AUDIO (1 << 6)
2842 #define EDID_CEA_YCRCB444 (1 << 5)
2843 #define EDID_CEA_YCRCB422 (1 << 4)
2844 #define EDID_CEA_VCDB_QS (1 << 6)
2847 * Search EDID for CEA extension block.
2849 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
2851 u8 *edid_ext = NULL;
2854 /* No EDID or EDID extensions */
2855 if (edid == NULL || edid->extensions == 0)
2858 /* Find CEA extension */
2859 for (i = 0; i < edid->extensions; i++) {
2860 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2861 if (edid_ext[0] == ext_id)
2865 if (i == edid->extensions)
2871 static u8 *drm_find_cea_extension(const struct edid *edid)
2873 return drm_find_edid_extension(edid, CEA_EXT);
2876 static u8 *drm_find_displayid_extension(const struct edid *edid)
2878 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2882 * Calculate the alternate clock for the CEA mode
2883 * (60Hz vs. 59.94Hz etc.)
2886 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2888 unsigned int clock = cea_mode->clock;
2890 if (cea_mode->vrefresh % 6 != 0)
2894 * edid_cea_modes contains the 59.94Hz
2895 * variant for 240 and 480 line modes,
2896 * and the 60Hz variant otherwise.
2898 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2899 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2901 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2907 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2910 * For certain VICs the spec allows the vertical
2911 * front porch to vary by one or two lines.
2913 * cea_modes[] stores the variant with the shortest
2914 * vertical front porch. We can adjust the mode to
2915 * get the other variants by simply increasing the
2916 * vertical front porch length.
2918 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2919 edid_cea_modes[9].vtotal != 262 ||
2920 edid_cea_modes[12].vtotal != 262 ||
2921 edid_cea_modes[13].vtotal != 262 ||
2922 edid_cea_modes[23].vtotal != 312 ||
2923 edid_cea_modes[24].vtotal != 312 ||
2924 edid_cea_modes[27].vtotal != 312 ||
2925 edid_cea_modes[28].vtotal != 312);
2927 if (((vic == 8 || vic == 9 ||
2928 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2929 ((vic == 23 || vic == 24 ||
2930 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2931 mode->vsync_start++;
2941 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2942 unsigned int clock_tolerance)
2944 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
2947 if (!to_match->clock)
2950 if (to_match->picture_aspect_ratio)
2951 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
2953 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2954 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2955 unsigned int clock1, clock2;
2957 /* Check both 60Hz and 59.94Hz */
2958 clock1 = cea_mode.clock;
2959 clock2 = cea_mode_alternate_clock(&cea_mode);
2961 if (abs(to_match->clock - clock1) > clock_tolerance &&
2962 abs(to_match->clock - clock2) > clock_tolerance)
2966 if (drm_mode_match(to_match, &cea_mode, match_flags))
2968 } while (cea_mode_alternate_timings(vic, &cea_mode));
2975 * drm_match_cea_mode - look for a CEA mode matching given mode
2976 * @to_match: display mode
2978 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2981 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2983 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
2986 if (!to_match->clock)
2989 if (to_match->picture_aspect_ratio)
2990 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
2992 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2993 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2994 unsigned int clock1, clock2;
2996 /* Check both 60Hz and 59.94Hz */
2997 clock1 = cea_mode.clock;
2998 clock2 = cea_mode_alternate_clock(&cea_mode);
3000 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3001 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3005 if (drm_mode_match(to_match, &cea_mode, match_flags))
3007 } while (cea_mode_alternate_timings(vic, &cea_mode));
3012 EXPORT_SYMBOL(drm_match_cea_mode);
3014 static bool drm_valid_cea_vic(u8 vic)
3016 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
3020 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
3021 * the input VIC from the CEA mode list
3022 * @video_code: ID given to each of the CEA modes
3024 * Returns picture aspect ratio
3026 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3028 return edid_cea_modes[video_code].picture_aspect_ratio;
3030 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
3033 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3036 * It's almost like cea_mode_alternate_clock(), we just need to add an
3037 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
3041 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3043 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
3044 return hdmi_mode->clock;
3046 return cea_mode_alternate_clock(hdmi_mode);
3049 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3050 unsigned int clock_tolerance)
3052 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3055 if (!to_match->clock)
3058 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3059 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3060 unsigned int clock1, clock2;
3062 /* Make sure to also match alternate clocks */
3063 clock1 = hdmi_mode->clock;
3064 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3066 if (abs(to_match->clock - clock1) > clock_tolerance &&
3067 abs(to_match->clock - clock2) > clock_tolerance)
3070 if (drm_mode_match(to_match, hdmi_mode, match_flags))
3078 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3079 * @to_match: display mode
3081 * An HDMI mode is one defined in the HDMI vendor specific block.
3083 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3085 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3087 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3090 if (!to_match->clock)
3093 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3094 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3095 unsigned int clock1, clock2;
3097 /* Make sure to also match alternate clocks */
3098 clock1 = hdmi_mode->clock;
3099 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3101 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3102 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3103 drm_mode_match(to_match, hdmi_mode, match_flags))
3109 static bool drm_valid_hdmi_vic(u8 vic)
3111 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3115 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3117 struct drm_device *dev = connector->dev;
3118 struct drm_display_mode *mode, *tmp;
3122 /* Don't add CEA modes if the CEA extension block is missing */
3123 if (!drm_find_cea_extension(edid))
3127 * Go through all probed modes and create a new mode
3128 * with the alternate clock for certain CEA modes.
3130 list_for_each_entry(mode, &connector->probed_modes, head) {
3131 const struct drm_display_mode *cea_mode = NULL;
3132 struct drm_display_mode *newmode;
3133 u8 vic = drm_match_cea_mode(mode);
3134 unsigned int clock1, clock2;
3136 if (drm_valid_cea_vic(vic)) {
3137 cea_mode = &edid_cea_modes[vic];
3138 clock2 = cea_mode_alternate_clock(cea_mode);
3140 vic = drm_match_hdmi_mode(mode);
3141 if (drm_valid_hdmi_vic(vic)) {
3142 cea_mode = &edid_4k_modes[vic];
3143 clock2 = hdmi_mode_alternate_clock(cea_mode);
3150 clock1 = cea_mode->clock;
3152 if (clock1 == clock2)
3155 if (mode->clock != clock1 && mode->clock != clock2)
3158 newmode = drm_mode_duplicate(dev, cea_mode);
3162 /* Carry over the stereo flags */
3163 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3166 * The current mode could be either variant. Make
3167 * sure to pick the "other" clock for the new mode.
3169 if (mode->clock != clock1)
3170 newmode->clock = clock1;
3172 newmode->clock = clock2;
3174 list_add_tail(&newmode->head, &list);
3177 list_for_each_entry_safe(mode, tmp, &list, head) {
3178 list_del(&mode->head);
3179 drm_mode_probed_add(connector, mode);
3186 static u8 svd_to_vic(u8 svd)
3188 /* 0-6 bit vic, 7th bit native mode indicator */
3189 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3195 static struct drm_display_mode *
3196 drm_display_mode_from_vic_index(struct drm_connector *connector,
3197 const u8 *video_db, u8 video_len,
3200 struct drm_device *dev = connector->dev;
3201 struct drm_display_mode *newmode;
3204 if (video_db == NULL || video_index >= video_len)
3207 /* CEA modes are numbered 1..127 */
3208 vic = svd_to_vic(video_db[video_index]);
3209 if (!drm_valid_cea_vic(vic))
3212 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3216 newmode->vrefresh = 0;
3222 * do_y420vdb_modes - Parse YCBCR 420 only modes
3223 * @connector: connector corresponding to the HDMI sink
3224 * @svds: start of the data block of CEA YCBCR 420 VDB
3225 * @len: length of the CEA YCBCR 420 VDB
3227 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3228 * which contains modes which can be supported in YCBCR 420
3229 * output format only.
3231 static int do_y420vdb_modes(struct drm_connector *connector,
3232 const u8 *svds, u8 svds_len)
3235 struct drm_device *dev = connector->dev;
3236 struct drm_display_info *info = &connector->display_info;
3237 struct drm_hdmi_info *hdmi = &info->hdmi;
3239 for (i = 0; i < svds_len; i++) {
3240 u8 vic = svd_to_vic(svds[i]);
3241 struct drm_display_mode *newmode;
3243 if (!drm_valid_cea_vic(vic))
3246 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3249 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3250 drm_mode_probed_add(connector, newmode);
3255 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3260 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3261 * @connector: connector corresponding to the HDMI sink
3262 * @vic: CEA vic for the video mode to be added in the map
3264 * Makes an entry for a videomode in the YCBCR 420 bitmap
3267 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3269 u8 vic = svd_to_vic(svd);
3270 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3272 if (!drm_valid_cea_vic(vic))
3275 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3279 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3282 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3284 for (i = 0; i < len; i++) {
3285 struct drm_display_mode *mode;
3286 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3289 * YCBCR420 capability block contains a bitmap which
3290 * gives the index of CEA modes from CEA VDB, which
3291 * can support YCBCR 420 sampling output also (apart
3292 * from RGB/YCBCR444 etc).
3293 * For example, if the bit 0 in bitmap is set,
3294 * first mode in VDB can support YCBCR420 output too.
3295 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3297 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3298 drm_add_cmdb_modes(connector, db[i]);
3300 drm_mode_probed_add(connector, mode);
3308 struct stereo_mandatory_mode {
3309 int width, height, vrefresh;
3313 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3314 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3315 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3317 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3319 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3320 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3321 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3322 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3323 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3327 stereo_match_mandatory(const struct drm_display_mode *mode,
3328 const struct stereo_mandatory_mode *stereo_mode)
3330 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3332 return mode->hdisplay == stereo_mode->width &&
3333 mode->vdisplay == stereo_mode->height &&
3334 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3335 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3338 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3340 struct drm_device *dev = connector->dev;
3341 const struct drm_display_mode *mode;
3342 struct list_head stereo_modes;
3345 INIT_LIST_HEAD(&stereo_modes);
3347 list_for_each_entry(mode, &connector->probed_modes, head) {
3348 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3349 const struct stereo_mandatory_mode *mandatory;
3350 struct drm_display_mode *new_mode;
3352 if (!stereo_match_mandatory(mode,
3353 &stereo_mandatory_modes[i]))
3356 mandatory = &stereo_mandatory_modes[i];
3357 new_mode = drm_mode_duplicate(dev, mode);
3361 new_mode->flags |= mandatory->flags;
3362 list_add_tail(&new_mode->head, &stereo_modes);
3367 list_splice_tail(&stereo_modes, &connector->probed_modes);
3372 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3374 struct drm_device *dev = connector->dev;
3375 struct drm_display_mode *newmode;
3377 if (!drm_valid_hdmi_vic(vic)) {
3378 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3382 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3386 drm_mode_probed_add(connector, newmode);
3391 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3392 const u8 *video_db, u8 video_len, u8 video_index)
3394 struct drm_display_mode *newmode;
3397 if (structure & (1 << 0)) {
3398 newmode = drm_display_mode_from_vic_index(connector, video_db,
3402 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3403 drm_mode_probed_add(connector, newmode);
3407 if (structure & (1 << 6)) {
3408 newmode = drm_display_mode_from_vic_index(connector, video_db,
3412 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3413 drm_mode_probed_add(connector, newmode);
3417 if (structure & (1 << 8)) {
3418 newmode = drm_display_mode_from_vic_index(connector, video_db,
3422 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3423 drm_mode_probed_add(connector, newmode);
3432 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3433 * @connector: connector corresponding to the HDMI sink
3434 * @db: start of the CEA vendor specific block
3435 * @len: length of the CEA block payload, ie. one can access up to db[len]
3437 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3438 * also adds the stereo 3d modes when applicable.
3441 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3442 const u8 *video_db, u8 video_len)
3444 struct drm_display_info *info = &connector->display_info;
3445 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3446 u8 vic_len, hdmi_3d_len = 0;
3453 /* no HDMI_Video_Present */
3454 if (!(db[8] & (1 << 5)))
3457 /* Latency_Fields_Present */
3458 if (db[8] & (1 << 7))
3461 /* I_Latency_Fields_Present */
3462 if (db[8] & (1 << 6))
3465 /* the declared length is not long enough for the 2 first bytes
3466 * of additional video format capabilities */
3467 if (len < (8 + offset + 2))
3472 if (db[8 + offset] & (1 << 7)) {
3473 modes += add_hdmi_mandatory_stereo_modes(connector);
3475 /* 3D_Multi_present */
3476 multi_present = (db[8 + offset] & 0x60) >> 5;
3480 vic_len = db[8 + offset] >> 5;
3481 hdmi_3d_len = db[8 + offset] & 0x1f;
3483 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3486 vic = db[9 + offset + i];
3487 modes += add_hdmi_mode(connector, vic);
3489 offset += 1 + vic_len;
3491 if (multi_present == 1)
3493 else if (multi_present == 2)
3498 if (len < (8 + offset + hdmi_3d_len - 1))
3501 if (hdmi_3d_len < multi_len)
3504 if (multi_present == 1 || multi_present == 2) {
3505 /* 3D_Structure_ALL */
3506 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3508 /* check if 3D_MASK is present */
3509 if (multi_present == 2)
3510 mask = (db[10 + offset] << 8) | db[11 + offset];
3514 for (i = 0; i < 16; i++) {
3515 if (mask & (1 << i))
3516 modes += add_3d_struct_modes(connector,
3523 offset += multi_len;
3525 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3527 struct drm_display_mode *newmode = NULL;
3528 unsigned int newflag = 0;
3529 bool detail_present;
3531 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3533 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3536 /* 2D_VIC_order_X */
3537 vic_index = db[8 + offset + i] >> 4;
3539 /* 3D_Structure_X */
3540 switch (db[8 + offset + i] & 0x0f) {
3542 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3545 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3549 if ((db[9 + offset + i] >> 4) == 1)
3550 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3555 newmode = drm_display_mode_from_vic_index(connector,
3561 newmode->flags |= newflag;
3562 drm_mode_probed_add(connector, newmode);
3573 info->has_hdmi_infoframe = true;
3578 cea_db_payload_len(const u8 *db)
3580 return db[0] & 0x1f;
3584 cea_db_extended_tag(const u8 *db)
3590 cea_db_tag(const u8 *db)
3596 cea_revision(const u8 *cea)
3602 cea_db_offsets(const u8 *cea, int *start, int *end)
3604 /* Data block offset in CEA extension block */
3609 if (*end < 4 || *end > 127)
3614 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3618 if (cea_db_tag(db) != VENDOR_BLOCK)
3621 if (cea_db_payload_len(db) < 5)
3624 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3626 return hdmi_id == HDMI_IEEE_OUI;
3629 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3633 if (cea_db_tag(db) != VENDOR_BLOCK)
3636 if (cea_db_payload_len(db) < 7)
3639 oui = db[3] << 16 | db[2] << 8 | db[1];
3641 return oui == HDMI_FORUM_IEEE_OUI;
3644 static bool cea_db_is_y420cmdb(const u8 *db)
3646 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3649 if (!cea_db_payload_len(db))
3652 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3658 static bool cea_db_is_y420vdb(const u8 *db)
3660 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3663 if (!cea_db_payload_len(db))
3666 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3672 #define for_each_cea_db(cea, i, start, end) \
3673 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3675 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3678 struct drm_display_info *info = &connector->display_info;
3679 struct drm_hdmi_info *hdmi = &info->hdmi;
3680 u8 map_len = cea_db_payload_len(db) - 1;
3685 /* All CEA modes support ycbcr420 sampling also.*/
3686 hdmi->y420_cmdb_map = U64_MAX;
3687 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3692 * This map indicates which of the existing CEA block modes
3693 * from VDB can support YCBCR420 output too. So if bit=0 is
3694 * set, first mode from VDB can support YCBCR420 output too.
3695 * We will parse and keep this map, before parsing VDB itself
3696 * to avoid going through the same block again and again.
3698 * Spec is not clear about max possible size of this block.
3699 * Clamping max bitmap block size at 8 bytes. Every byte can
3700 * address 8 CEA modes, in this way this map can address
3701 * 8*8 = first 64 SVDs.
3703 if (WARN_ON_ONCE(map_len > 8))
3706 for (count = 0; count < map_len; count++)
3707 map |= (u64)db[2 + count] << (8 * count);
3710 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3712 hdmi->y420_cmdb_map = map;
3716 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3718 const u8 *cea = drm_find_cea_extension(edid);
3719 const u8 *db, *hdmi = NULL, *video = NULL;
3720 u8 dbl, hdmi_len, video_len = 0;
3723 if (cea && cea_revision(cea) >= 3) {
3726 if (cea_db_offsets(cea, &start, &end))
3729 for_each_cea_db(cea, i, start, end) {
3731 dbl = cea_db_payload_len(db);
3733 if (cea_db_tag(db) == VIDEO_BLOCK) {
3736 modes += do_cea_modes(connector, video, dbl);
3737 } else if (cea_db_is_hdmi_vsdb(db)) {
3740 } else if (cea_db_is_y420vdb(db)) {
3741 const u8 *vdb420 = &db[2];
3743 /* Add 4:2:0(only) modes present in EDID */
3744 modes += do_y420vdb_modes(connector,
3752 * We parse the HDMI VSDB after having added the cea modes as we will
3753 * be patching their flags when the sink supports stereo 3D.
3756 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3762 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3764 const struct drm_display_mode *cea_mode;
3765 int clock1, clock2, clock;
3770 * allow 5kHz clock difference either way to account for
3771 * the 10kHz clock resolution limit of detailed timings.
3773 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3774 if (drm_valid_cea_vic(vic)) {
3776 cea_mode = &edid_cea_modes[vic];
3777 clock1 = cea_mode->clock;
3778 clock2 = cea_mode_alternate_clock(cea_mode);
3780 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3781 if (drm_valid_hdmi_vic(vic)) {
3783 cea_mode = &edid_4k_modes[vic];
3784 clock1 = cea_mode->clock;
3785 clock2 = hdmi_mode_alternate_clock(cea_mode);
3791 /* pick whichever is closest */
3792 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3797 if (mode->clock == clock)
3800 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3801 type, vic, mode->clock, clock);
3802 mode->clock = clock;
3806 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3808 u8 len = cea_db_payload_len(db);
3810 if (len >= 6 && (db[6] & (1 << 7)))
3811 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
3813 connector->latency_present[0] = db[8] >> 7;
3814 connector->latency_present[1] = (db[8] >> 6) & 1;
3817 connector->video_latency[0] = db[9];
3819 connector->audio_latency[0] = db[10];
3821 connector->video_latency[1] = db[11];
3823 connector->audio_latency[1] = db[12];
3825 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3826 "video latency %d %d, "
3827 "audio latency %d %d\n",
3828 connector->latency_present[0],
3829 connector->latency_present[1],
3830 connector->video_latency[0],
3831 connector->video_latency[1],
3832 connector->audio_latency[0],
3833 connector->audio_latency[1]);
3837 monitor_name(struct detailed_timing *t, void *data)
3839 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3840 *(u8 **)data = t->data.other_data.data.str.str;
3843 static int get_monitor_name(struct edid *edid, char name[13])
3845 char *edid_name = NULL;
3851 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3852 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3853 if (edid_name[mnl] == 0x0a)
3856 name[mnl] = edid_name[mnl];
3863 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3864 * @edid: monitor EDID information
3865 * @name: pointer to a character array to hold the name of the monitor
3866 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3869 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3877 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3878 memcpy(name, buf, name_length);
3879 name[name_length] = '\0';
3881 EXPORT_SYMBOL(drm_edid_get_monitor_name);
3883 static void clear_eld(struct drm_connector *connector)
3885 memset(connector->eld, 0, sizeof(connector->eld));
3887 connector->latency_present[0] = false;
3888 connector->latency_present[1] = false;
3889 connector->video_latency[0] = 0;
3890 connector->audio_latency[0] = 0;
3891 connector->video_latency[1] = 0;
3892 connector->audio_latency[1] = 0;
3896 * drm_edid_to_eld - build ELD from EDID
3897 * @connector: connector corresponding to the HDMI/DP sink
3898 * @edid: EDID to parse
3900 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3901 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
3903 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3905 uint8_t *eld = connector->eld;
3908 int total_sad_count = 0;
3912 clear_eld(connector);
3917 cea = drm_find_cea_extension(edid);
3919 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3923 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
3924 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
3926 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
3927 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
3929 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
3931 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
3932 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
3933 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
3934 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
3936 if (cea_revision(cea) >= 3) {
3939 if (cea_db_offsets(cea, &start, &end)) {
3944 for_each_cea_db(cea, i, start, end) {
3946 dbl = cea_db_payload_len(db);
3948 switch (cea_db_tag(db)) {
3952 /* Audio Data Block, contains SADs */
3953 sad_count = min(dbl / 3, 15 - total_sad_count);
3955 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
3956 &db[1], sad_count * 3);
3957 total_sad_count += sad_count;
3960 /* Speaker Allocation Data Block */
3962 eld[DRM_ELD_SPEAKER] = db[1];
3965 /* HDMI Vendor-Specific Data Block */
3966 if (cea_db_is_hdmi_vsdb(db))
3967 drm_parse_hdmi_vsdb_audio(connector, db);
3974 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
3976 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3977 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3978 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
3980 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
3982 eld[DRM_ELD_BASELINE_ELD_LEN] =
3983 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3985 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3986 drm_eld_size(eld), total_sad_count);
3990 * drm_edid_to_sad - extracts SADs from EDID
3991 * @edid: EDID to parse
3992 * @sads: pointer that will be set to the extracted SADs
3994 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3996 * Note: The returned pointer needs to be freed using kfree().
3998 * Return: The number of found SADs or negative number on error.
4000 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4003 int i, start, end, dbl;
4006 cea = drm_find_cea_extension(edid);
4008 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4012 if (cea_revision(cea) < 3) {
4013 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4017 if (cea_db_offsets(cea, &start, &end)) {
4018 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4022 for_each_cea_db(cea, i, start, end) {
4025 if (cea_db_tag(db) == AUDIO_BLOCK) {
4027 dbl = cea_db_payload_len(db);
4029 count = dbl / 3; /* SAD is 3B */
4030 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4033 for (j = 0; j < count; j++) {
4034 u8 *sad = &db[1 + j * 3];
4036 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4037 (*sads)[j].channels = sad[0] & 0x7;
4038 (*sads)[j].freq = sad[1] & 0x7F;
4039 (*sads)[j].byte2 = sad[2];
4047 EXPORT_SYMBOL(drm_edid_to_sad);
4050 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4051 * @edid: EDID to parse
4052 * @sadb: pointer to the speaker block
4054 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4056 * Note: The returned pointer needs to be freed using kfree().
4058 * Return: The number of found Speaker Allocation Blocks or negative number on
4061 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4064 int i, start, end, dbl;
4067 cea = drm_find_cea_extension(edid);
4069 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4073 if (cea_revision(cea) < 3) {
4074 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4078 if (cea_db_offsets(cea, &start, &end)) {
4079 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4083 for_each_cea_db(cea, i, start, end) {
4084 const u8 *db = &cea[i];
4086 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4087 dbl = cea_db_payload_len(db);
4089 /* Speaker Allocation Data Block */
4091 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4102 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4105 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4106 * @connector: connector associated with the HDMI/DP sink
4107 * @mode: the display mode
4109 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4110 * the sink doesn't support audio or video.
4112 int drm_av_sync_delay(struct drm_connector *connector,
4113 const struct drm_display_mode *mode)
4115 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4118 if (!connector->latency_present[0])
4120 if (!connector->latency_present[1])
4123 a = connector->audio_latency[i];
4124 v = connector->video_latency[i];
4127 * HDMI/DP sink doesn't support audio or video?
4129 if (a == 255 || v == 255)
4133 * Convert raw EDID values to millisecond.
4134 * Treat unknown latency as 0ms.
4137 a = min(2 * (a - 1), 500);
4139 v = min(2 * (v - 1), 500);
4141 return max(v - a, 0);
4143 EXPORT_SYMBOL(drm_av_sync_delay);
4146 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4147 * @edid: monitor EDID information
4149 * Parse the CEA extension according to CEA-861-B.
4151 * Return: True if the monitor is HDMI, false if not or unknown.
4153 bool drm_detect_hdmi_monitor(struct edid *edid)
4157 int start_offset, end_offset;
4159 edid_ext = drm_find_cea_extension(edid);
4163 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4167 * Because HDMI identifier is in Vendor Specific Block,
4168 * search it from all data blocks of CEA extension.
4170 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4171 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4177 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4180 * drm_detect_monitor_audio - check monitor audio capability
4181 * @edid: EDID block to scan
4183 * Monitor should have CEA extension block.
4184 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4185 * audio' only. If there is any audio extension block and supported
4186 * audio format, assume at least 'basic audio' support, even if 'basic
4187 * audio' is not defined in EDID.
4189 * Return: True if the monitor supports audio, false otherwise.
4191 bool drm_detect_monitor_audio(struct edid *edid)
4195 bool has_audio = false;
4196 int start_offset, end_offset;
4198 edid_ext = drm_find_cea_extension(edid);
4202 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4205 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4209 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4212 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4213 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4215 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4216 DRM_DEBUG_KMS("CEA audio format %d\n",
4217 (edid_ext[i + j] >> 3) & 0xf);
4224 EXPORT_SYMBOL(drm_detect_monitor_audio);
4227 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
4228 * @edid: EDID block to scan
4230 * Check whether the monitor reports the RGB quantization range selection
4231 * as supported. The AVI infoframe can then be used to inform the monitor
4232 * which quantization range (full or limited) is used.
4234 * Return: True if the RGB quantization range is selectable, false otherwise.
4236 bool drm_rgb_quant_range_selectable(struct edid *edid)
4241 edid_ext = drm_find_cea_extension(edid);
4245 if (cea_db_offsets(edid_ext, &start, &end))
4248 for_each_cea_db(edid_ext, i, start, end) {
4249 if (cea_db_tag(&edid_ext[i]) == USE_EXTENDED_TAG &&
4250 cea_db_payload_len(&edid_ext[i]) == 2 &&
4251 cea_db_extended_tag(&edid_ext[i]) ==
4252 EXT_VIDEO_CAPABILITY_BLOCK) {
4253 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
4254 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
4260 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
4263 * drm_default_rgb_quant_range - default RGB quantization range
4264 * @mode: display mode
4266 * Determine the default RGB quantization range for the mode,
4267 * as specified in CEA-861.
4269 * Return: The default RGB quantization range for the mode
4271 enum hdmi_quantization_range
4272 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4274 /* All CEA modes other than VIC 1 use limited quantization range. */
4275 return drm_match_cea_mode(mode) > 1 ?
4276 HDMI_QUANTIZATION_RANGE_LIMITED :
4277 HDMI_QUANTIZATION_RANGE_FULL;
4279 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4281 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4285 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4287 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4288 hdmi->y420_dc_modes = dc_mask;
4291 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4294 struct drm_display_info *display = &connector->display_info;
4295 struct drm_hdmi_info *hdmi = &display->hdmi;
4297 display->has_hdmi_infoframe = true;
4299 if (hf_vsdb[6] & 0x80) {
4300 hdmi->scdc.supported = true;
4301 if (hf_vsdb[6] & 0x40)
4302 hdmi->scdc.read_request = true;
4306 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4307 * And as per the spec, three factors confirm this:
4308 * * Availability of a HF-VSDB block in EDID (check)
4309 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4310 * * SCDC support available (let's check)
4311 * Lets check it out.
4315 /* max clock is 5000 KHz times block value */
4316 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4317 struct drm_scdc *scdc = &hdmi->scdc;
4319 if (max_tmds_clock > 340000) {
4320 display->max_tmds_clock = max_tmds_clock;
4321 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4322 display->max_tmds_clock);
4325 if (scdc->supported) {
4326 scdc->scrambling.supported = true;
4328 /* Few sinks support scrambling for cloks < 340M */
4329 if ((hf_vsdb[6] & 0x8))
4330 scdc->scrambling.low_rates = true;
4334 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4337 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4340 struct drm_display_info *info = &connector->display_info;
4341 unsigned int dc_bpc = 0;
4343 /* HDMI supports at least 8 bpc */
4346 if (cea_db_payload_len(hdmi) < 6)
4349 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4351 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4352 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4356 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4358 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4359 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4363 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4365 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4366 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4371 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4376 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4377 connector->name, dc_bpc);
4381 * Deep color support mandates RGB444 support for all video
4382 * modes and forbids YCRCB422 support for all video modes per
4385 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4387 /* YCRCB444 is optional according to spec. */
4388 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4389 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4390 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4395 * Spec says that if any deep color mode is supported at all,
4396 * then deep color 36 bit must be supported.
4398 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4399 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4405 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4407 struct drm_display_info *info = &connector->display_info;
4408 u8 len = cea_db_payload_len(db);
4411 info->dvi_dual = db[6] & 1;
4413 info->max_tmds_clock = db[7] * 5000;
4415 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4416 "max TMDS clock %d kHz\n",
4418 info->max_tmds_clock);
4420 drm_parse_hdmi_deep_color_info(connector, db);
4423 static void drm_parse_cea_ext(struct drm_connector *connector,
4424 const struct edid *edid)
4426 struct drm_display_info *info = &connector->display_info;
4430 edid_ext = drm_find_cea_extension(edid);
4434 info->cea_rev = edid_ext[1];
4436 /* The existence of a CEA block should imply RGB support */
4437 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4438 if (edid_ext[3] & EDID_CEA_YCRCB444)
4439 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4440 if (edid_ext[3] & EDID_CEA_YCRCB422)
4441 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4443 if (cea_db_offsets(edid_ext, &start, &end))
4446 for_each_cea_db(edid_ext, i, start, end) {
4447 const u8 *db = &edid_ext[i];
4449 if (cea_db_is_hdmi_vsdb(db))
4450 drm_parse_hdmi_vsdb_video(connector, db);
4451 if (cea_db_is_hdmi_forum_vsdb(db))
4452 drm_parse_hdmi_forum_vsdb(connector, db);
4453 if (cea_db_is_y420cmdb(db))
4454 drm_parse_y420cmdb_bitmap(connector, db);
4458 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4459 * all of the values which would have been set from EDID
4462 drm_reset_display_info(struct drm_connector *connector)
4464 struct drm_display_info *info = &connector->display_info;
4467 info->height_mm = 0;
4470 info->color_formats = 0;
4472 info->max_tmds_clock = 0;
4473 info->dvi_dual = false;
4474 info->has_hdmi_infoframe = false;
4475 memset(&info->hdmi, 0, sizeof(info->hdmi));
4477 info->non_desktop = 0;
4480 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
4482 struct drm_display_info *info = &connector->display_info;
4484 u32 quirks = edid_get_quirks(edid);
4486 drm_reset_display_info(connector);
4488 info->width_mm = edid->width_cm * 10;
4489 info->height_mm = edid->height_cm * 10;
4491 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4493 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4495 if (edid->revision < 3)
4498 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4501 drm_parse_cea_ext(connector, edid);
4504 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4506 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4507 * tells us to assume 8 bpc color depth if the EDID doesn't have
4508 * extensions which tell otherwise.
4510 if ((info->bpc == 0) && (edid->revision < 4) &&
4511 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
4513 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4514 connector->name, info->bpc);
4517 /* Only defined for 1.4 with digital displays */
4518 if (edid->revision < 4)
4521 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4522 case DRM_EDID_DIGITAL_DEPTH_6:
4525 case DRM_EDID_DIGITAL_DEPTH_8:
4528 case DRM_EDID_DIGITAL_DEPTH_10:
4531 case DRM_EDID_DIGITAL_DEPTH_12:
4534 case DRM_EDID_DIGITAL_DEPTH_14:
4537 case DRM_EDID_DIGITAL_DEPTH_16:
4540 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4546 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4547 connector->name, info->bpc);
4549 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4550 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4551 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4552 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4553 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4557 static int validate_displayid(u8 *displayid, int length, int idx)
4561 struct displayid_hdr *base;
4563 base = (struct displayid_hdr *)&displayid[idx];
4565 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4566 base->rev, base->bytes, base->prod_id, base->ext_count);
4568 if (base->bytes + 5 > length - idx)
4570 for (i = idx; i <= base->bytes + 5; i++) {
4571 csum += displayid[i];
4574 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4580 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4581 struct displayid_detailed_timings_1 *timings)
4583 struct drm_display_mode *mode;
4584 unsigned pixel_clock = (timings->pixel_clock[0] |
4585 (timings->pixel_clock[1] << 8) |
4586 (timings->pixel_clock[2] << 16));
4587 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4588 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4589 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4590 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4591 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4592 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4593 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4594 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4595 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4596 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4597 mode = drm_mode_create(dev);
4601 mode->clock = pixel_clock * 10;
4602 mode->hdisplay = hactive;
4603 mode->hsync_start = mode->hdisplay + hsync;
4604 mode->hsync_end = mode->hsync_start + hsync_width;
4605 mode->htotal = mode->hdisplay + hblank;
4607 mode->vdisplay = vactive;
4608 mode->vsync_start = mode->vdisplay + vsync;
4609 mode->vsync_end = mode->vsync_start + vsync_width;
4610 mode->vtotal = mode->vdisplay + vblank;
4613 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4614 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4615 mode->type = DRM_MODE_TYPE_DRIVER;
4617 if (timings->flags & 0x80)
4618 mode->type |= DRM_MODE_TYPE_PREFERRED;
4619 mode->vrefresh = drm_mode_vrefresh(mode);
4620 drm_mode_set_name(mode);
4625 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4626 struct displayid_block *block)
4628 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4631 struct drm_display_mode *newmode;
4633 /* blocks must be multiple of 20 bytes length */
4634 if (block->num_bytes % 20)
4637 num_timings = block->num_bytes / 20;
4638 for (i = 0; i < num_timings; i++) {
4639 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4641 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4645 drm_mode_probed_add(connector, newmode);
4651 static int add_displayid_detailed_modes(struct drm_connector *connector,
4657 int length = EDID_LENGTH;
4658 struct displayid_block *block;
4661 displayid = drm_find_displayid_extension(edid);
4665 ret = validate_displayid(displayid, length, idx);
4669 idx += sizeof(struct displayid_hdr);
4670 while (block = (struct displayid_block *)&displayid[idx],
4671 idx + sizeof(struct displayid_block) <= length &&
4672 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4673 block->num_bytes > 0) {
4674 idx += block->num_bytes + sizeof(struct displayid_block);
4675 switch (block->tag) {
4676 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4677 num_modes += add_displayid_detailed_1_modes(connector, block);
4685 * drm_add_edid_modes - add modes from EDID data, if available
4686 * @connector: connector we're probing
4689 * Add the specified modes to the connector's mode list. Also fills out the
4690 * &drm_display_info structure and ELD in @connector with any information which
4691 * can be derived from the edid.
4693 * Return: The number of modes added or 0 if we couldn't find any.
4695 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4701 clear_eld(connector);
4704 if (!drm_edid_is_valid(edid)) {
4705 clear_eld(connector);
4706 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4711 drm_edid_to_eld(connector, edid);
4714 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4715 * To avoid multiple parsing of same block, lets parse that map
4716 * from sink info, before parsing CEA modes.
4718 quirks = drm_add_display_info(connector, edid);
4721 * EDID spec says modes should be preferred in this order:
4722 * - preferred detailed mode
4723 * - other detailed modes from base block
4724 * - detailed modes from extension blocks
4725 * - CVT 3-byte code modes
4726 * - standard timing codes
4727 * - established timing codes
4728 * - modes inferred from GTF or CVT range information
4730 * We get this pretty much right.
4732 * XXX order for additional mode types in extension blocks?
4734 num_modes += add_detailed_modes(connector, edid, quirks);
4735 num_modes += add_cvt_modes(connector, edid);
4736 num_modes += add_standard_modes(connector, edid);
4737 num_modes += add_established_modes(connector, edid);
4738 num_modes += add_cea_modes(connector, edid);
4739 num_modes += add_alternate_cea_modes(connector, edid);
4740 num_modes += add_displayid_detailed_modes(connector, edid);
4741 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4742 num_modes += add_inferred_modes(connector, edid);
4744 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4745 edid_fixup_preferred(connector, quirks);
4747 if (quirks & EDID_QUIRK_FORCE_6BPC)
4748 connector->display_info.bpc = 6;
4750 if (quirks & EDID_QUIRK_FORCE_8BPC)
4751 connector->display_info.bpc = 8;
4753 if (quirks & EDID_QUIRK_FORCE_10BPC)
4754 connector->display_info.bpc = 10;
4756 if (quirks & EDID_QUIRK_FORCE_12BPC)
4757 connector->display_info.bpc = 12;
4761 EXPORT_SYMBOL(drm_add_edid_modes);
4764 * drm_add_modes_noedid - add modes for the connectors without EDID
4765 * @connector: connector we're probing
4766 * @hdisplay: the horizontal display limit
4767 * @vdisplay: the vertical display limit
4769 * Add the specified modes to the connector's mode list. Only when the
4770 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4772 * Return: The number of modes added or 0 if we couldn't find any.
4774 int drm_add_modes_noedid(struct drm_connector *connector,
4775 int hdisplay, int vdisplay)
4777 int i, count, num_modes = 0;
4778 struct drm_display_mode *mode;
4779 struct drm_device *dev = connector->dev;
4781 count = ARRAY_SIZE(drm_dmt_modes);
4787 for (i = 0; i < count; i++) {
4788 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4789 if (hdisplay && vdisplay) {
4791 * Only when two are valid, they will be used to check
4792 * whether the mode should be added to the mode list of
4795 if (ptr->hdisplay > hdisplay ||
4796 ptr->vdisplay > vdisplay)
4799 if (drm_mode_vrefresh(ptr) > 61)
4801 mode = drm_mode_duplicate(dev, ptr);
4803 drm_mode_probed_add(connector, mode);
4809 EXPORT_SYMBOL(drm_add_modes_noedid);
4812 * drm_set_preferred_mode - Sets the preferred mode of a connector
4813 * @connector: connector whose mode list should be processed
4814 * @hpref: horizontal resolution of preferred mode
4815 * @vpref: vertical resolution of preferred mode
4817 * Marks a mode as preferred if it matches the resolution specified by @hpref
4820 void drm_set_preferred_mode(struct drm_connector *connector,
4821 int hpref, int vpref)
4823 struct drm_display_mode *mode;
4825 list_for_each_entry(mode, &connector->probed_modes, head) {
4826 if (mode->hdisplay == hpref &&
4827 mode->vdisplay == vpref)
4828 mode->type |= DRM_MODE_TYPE_PREFERRED;
4831 EXPORT_SYMBOL(drm_set_preferred_mode);
4834 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4835 * data from a DRM display mode
4836 * @frame: HDMI AVI infoframe
4837 * @mode: DRM display mode
4838 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant
4840 * Return: 0 on success or a negative error code on failure.
4843 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4844 const struct drm_display_mode *mode,
4847 enum hdmi_picture_aspect picture_aspect;
4850 if (!frame || !mode)
4853 err = hdmi_avi_infoframe_init(frame);
4857 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4858 frame->pixel_repeat = 1;
4860 frame->video_code = drm_match_cea_mode(mode);
4863 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4864 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4865 * have to make sure we dont break HDMI 1.4 sinks.
4867 if (!is_hdmi2_sink && frame->video_code > 64)
4868 frame->video_code = 0;
4871 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
4872 * we should send its VIC in vendor infoframes, else send the
4873 * VIC in AVI infoframes. Lets check if this mode is present in
4874 * HDMI 1.4b 4K modes
4876 if (frame->video_code) {
4877 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
4878 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
4880 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
4881 frame->video_code = 0;
4884 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4887 * As some drivers don't support atomic, we can't use connector state.
4888 * So just initialize the frame with default values, just the same way
4889 * as it's done with other properties here.
4891 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
4895 * Populate picture aspect ratio from either
4896 * user input (if specified) or from the CEA mode list.
4898 picture_aspect = mode->picture_aspect_ratio;
4899 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE)
4900 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code);
4903 * The infoframe can't convey anything but none, 4:3
4904 * and 16:9, so if the user has asked for anything else
4905 * we can only satisfy it by specifying the right VIC.
4907 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
4908 if (picture_aspect !=
4909 drm_get_cea_aspect_ratio(frame->video_code))
4911 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4914 frame->picture_aspect = picture_aspect;
4915 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4916 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4920 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4923 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
4924 * quantization range information
4925 * @frame: HDMI AVI infoframe
4926 * @mode: DRM display mode
4927 * @rgb_quant_range: RGB quantization range (Q)
4928 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
4929 * @is_hdmi2_sink: HDMI 2.0 sink, which has different default recommendations
4931 * Note that @is_hdmi2_sink can be derived by looking at the
4932 * &drm_scdc.supported flag stored in &drm_hdmi_info.scdc,
4933 * &drm_display_info.hdmi, which can be found in &drm_connector.display_info.
4936 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
4937 const struct drm_display_mode *mode,
4938 enum hdmi_quantization_range rgb_quant_range,
4939 bool rgb_quant_range_selectable,
4944 * "A Source shall not send a non-zero Q value that does not correspond
4945 * to the default RGB Quantization Range for the transmitted Picture
4946 * unless the Sink indicates support for the Q bit in a Video
4947 * Capabilities Data Block."
4949 * HDMI 2.0 recommends sending non-zero Q when it does match the
4950 * default RGB quantization range for the mode, even when QS=0.
4952 if (rgb_quant_range_selectable ||
4953 rgb_quant_range == drm_default_rgb_quant_range(mode))
4954 frame->quantization_range = rgb_quant_range;
4956 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
4960 * "When transmitting any RGB colorimetry, the Source should set the
4961 * YQ-field to match the RGB Quantization Range being transmitted
4962 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
4963 * set YQ=1) and the Sink shall ignore the YQ-field."
4965 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
4966 * by non-zero YQ when receiving RGB. There doesn't seem to be any
4967 * good way to tell which version of CEA-861 the sink supports, so
4968 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
4971 if (!is_hdmi2_sink ||
4972 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
4973 frame->ycc_quantization_range =
4974 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
4976 frame->ycc_quantization_range =
4977 HDMI_YCC_QUANTIZATION_RANGE_FULL;
4979 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
4981 static enum hdmi_3d_structure
4982 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4984 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4987 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4988 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4989 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4990 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4991 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4992 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4993 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4994 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4995 case DRM_MODE_FLAG_3D_L_DEPTH:
4996 return HDMI_3D_STRUCTURE_L_DEPTH;
4997 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4998 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4999 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5000 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5001 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5002 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5004 return HDMI_3D_STRUCTURE_INVALID;
5009 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5010 * data from a DRM display mode
5011 * @frame: HDMI vendor infoframe
5012 * @connector: the connector
5013 * @mode: DRM display mode
5015 * Note that there's is a need to send HDMI vendor infoframes only when using a
5016 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5017 * function will return -EINVAL, error that can be safely ignored.
5019 * Return: 0 on success or a negative error code on failure.
5022 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
5023 struct drm_connector *connector,
5024 const struct drm_display_mode *mode)
5027 * FIXME: sil-sii8620 doesn't have a connector around when
5028 * we need one, so we have to be prepared for a NULL connector.
5030 bool has_hdmi_infoframe = connector ?
5031 connector->display_info.has_hdmi_infoframe : false;
5036 if (!frame || !mode)
5039 if (!has_hdmi_infoframe)
5042 vic = drm_match_hdmi_mode(mode);
5043 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
5046 * Even if it's not absolutely necessary to send the infoframe
5047 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5048 * know that the sink can handle it. This is based on a
5049 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5050 * have trouble realizing that they shuld switch from 3D to 2D
5051 * mode if the source simply stops sending the infoframe when
5052 * it wants to switch from 3D to 2D.
5055 if (vic && s3d_flags)
5058 err = hdmi_vendor_infoframe_init(frame);
5063 frame->s3d_struct = s3d_structure_from_display_mode(mode);
5067 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
5069 static int drm_parse_tiled_block(struct drm_connector *connector,
5070 struct displayid_block *block)
5072 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5074 u8 tile_v_loc, tile_h_loc;
5075 u8 num_v_tile, num_h_tile;
5076 struct drm_tile_group *tg;
5078 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5079 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5081 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5082 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5083 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5084 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5086 connector->has_tile = true;
5087 if (tile->tile_cap & 0x80)
5088 connector->tile_is_single_monitor = true;
5090 connector->num_h_tile = num_h_tile + 1;
5091 connector->num_v_tile = num_v_tile + 1;
5092 connector->tile_h_loc = tile_h_loc;
5093 connector->tile_v_loc = tile_v_loc;
5094 connector->tile_h_size = w + 1;
5095 connector->tile_v_size = h + 1;
5097 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5098 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5099 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5100 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5101 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5103 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5105 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5110 if (connector->tile_group != tg) {
5111 /* if we haven't got a pointer,
5112 take the reference, drop ref to old tile group */
5113 if (connector->tile_group) {
5114 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5116 connector->tile_group = tg;
5118 /* if same tile group, then release the ref we just took. */
5119 drm_mode_put_tile_group(connector->dev, tg);
5123 static int drm_parse_display_id(struct drm_connector *connector,
5124 u8 *displayid, int length,
5125 bool is_edid_extension)
5127 /* if this is an EDID extension the first byte will be 0x70 */
5129 struct displayid_block *block;
5132 if (is_edid_extension)
5135 ret = validate_displayid(displayid, length, idx);
5139 idx += sizeof(struct displayid_hdr);
5140 while (block = (struct displayid_block *)&displayid[idx],
5141 idx + sizeof(struct displayid_block) <= length &&
5142 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
5143 block->num_bytes > 0) {
5144 idx += block->num_bytes + sizeof(struct displayid_block);
5145 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5146 block->tag, block->rev, block->num_bytes);
5148 switch (block->tag) {
5149 case DATA_BLOCK_TILED_DISPLAY:
5150 ret = drm_parse_tiled_block(connector, block);
5154 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5155 /* handled in mode gathering code. */
5158 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5165 static void drm_get_displayid(struct drm_connector *connector,
5168 void *displayid = NULL;
5170 connector->has_tile = false;
5171 displayid = drm_find_displayid_extension(edid);
5173 /* drop reference to any tile group we had */
5177 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5180 if (!connector->has_tile)
5184 if (connector->tile_group) {
5185 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5186 connector->tile_group = NULL;
projects / linux-2.6-microblaze.git / blob