2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
31 #include <linux/bitfield.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/slab.h>
38 #include <linux/vga_switcheroo.h>
40 #include <drm/drm_displayid.h>
41 #include <drm/drm_drv.h>
42 #include <drm/drm_edid.h>
43 #include <drm/drm_encoder.h>
44 #include <drm/drm_print.h>
46 #include "drm_crtc_internal.h"
48 #define version_greater(edid, maj, min) \
49 (((edid)->version > (maj)) || \
50 ((edid)->version == (maj) && (edid)->revision > (min)))
52 static int oui(u8 first, u8 second, u8 third)
54 return (first << 16) | (second << 8) | third;
57 #define EDID_EST_TIMINGS 16
58 #define EDID_STD_TIMINGS 8
59 #define EDID_DETAILED_TIMINGS 4
62 * EDID blocks out in the wild have a variety of bugs, try to collect
63 * them here (note that userspace may work around broken monitors first,
64 * but fixes should make their way here so that the kernel "just works"
65 * on as many displays as possible).
68 /* First detailed mode wrong, use largest 60Hz mode */
69 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
70 /* Reported 135MHz pixel clock is too high, needs adjustment */
71 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
72 /* Prefer the largest mode at 75 Hz */
73 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
74 /* Detail timing is in cm not mm */
75 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
76 /* Detailed timing descriptors have bogus size values, so just take the
77 * maximum size and use that.
79 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
80 /* use +hsync +vsync for detailed mode */
81 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
82 /* Force reduced-blanking timings for detailed modes */
83 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
85 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
87 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
89 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
91 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
92 /* Non desktop display (i.e. HMD) */
93 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
95 #define MICROSOFT_IEEE_OUI 0xca125c
97 struct detailed_mode_closure {
98 struct drm_connector *connector;
99 const struct drm_edid *drm_edid;
110 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
112 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
117 static const struct edid_quirk {
120 } edid_quirk_list[] = {
122 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
124 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
126 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
127 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
129 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
130 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
132 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
133 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
135 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
136 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
138 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
139 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
141 /* Belinea 10 15 55 */
142 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
143 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
145 /* Envision Peripherals, Inc. EN-7100e */
146 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
147 /* Envision EN2028 */
148 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
150 /* Funai Electronics PM36B */
151 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
152 EDID_QUIRK_DETAILED_IN_CM),
154 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
155 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
157 /* LG Philips LCD LP154W01-A5 */
158 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
159 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
161 /* Samsung SyncMaster 205BW. Note: irony */
162 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
163 /* Samsung SyncMaster 22[5-6]BW */
164 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
165 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
167 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
168 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
170 /* ViewSonic VA2026w */
171 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
173 /* Medion MD 30217 PG */
174 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
177 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
179 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
180 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
182 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
183 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
185 /* Valve Index Headset */
186 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
187 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
188 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
189 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
190 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
191 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
192 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
193 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
194 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
195 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
204 /* HTC Vive and Vive Pro VR Headsets */
205 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
208 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
209 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
210 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
211 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
212 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
214 /* Windows Mixed Reality Headsets */
215 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
216 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
217 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
218 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
219 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
220 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
222 /* Sony PlayStation VR Headset */
223 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
225 /* Sensics VR Headsets */
226 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
228 /* OSVR HDK and HDK2 VR Headsets */
229 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
233 * Autogenerated from the DMT spec.
234 * This table is copied from xfree86/modes/xf86EdidModes.c.
236 static const struct drm_display_mode drm_dmt_modes[] = {
237 /* 0x01 - 640x350@85Hz */
238 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
239 736, 832, 0, 350, 382, 385, 445, 0,
240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
241 /* 0x02 - 640x400@85Hz */
242 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
243 736, 832, 0, 400, 401, 404, 445, 0,
244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
245 /* 0x03 - 720x400@85Hz */
246 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
247 828, 936, 0, 400, 401, 404, 446, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
249 /* 0x04 - 640x480@60Hz */
250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
251 752, 800, 0, 480, 490, 492, 525, 0,
252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
253 /* 0x05 - 640x480@72Hz */
254 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
255 704, 832, 0, 480, 489, 492, 520, 0,
256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
257 /* 0x06 - 640x480@75Hz */
258 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
259 720, 840, 0, 480, 481, 484, 500, 0,
260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
261 /* 0x07 - 640x480@85Hz */
262 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
263 752, 832, 0, 480, 481, 484, 509, 0,
264 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
265 /* 0x08 - 800x600@56Hz */
266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
267 896, 1024, 0, 600, 601, 603, 625, 0,
268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
269 /* 0x09 - 800x600@60Hz */
270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
271 968, 1056, 0, 600, 601, 605, 628, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
273 /* 0x0a - 800x600@72Hz */
274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
275 976, 1040, 0, 600, 637, 643, 666, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
277 /* 0x0b - 800x600@75Hz */
278 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
279 896, 1056, 0, 600, 601, 604, 625, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
281 /* 0x0c - 800x600@85Hz */
282 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
283 896, 1048, 0, 600, 601, 604, 631, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
285 /* 0x0d - 800x600@120Hz RB */
286 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
287 880, 960, 0, 600, 603, 607, 636, 0,
288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
289 /* 0x0e - 848x480@60Hz */
290 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
291 976, 1088, 0, 480, 486, 494, 517, 0,
292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
293 /* 0x0f - 1024x768@43Hz, interlace */
294 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
295 1208, 1264, 0, 768, 768, 776, 817, 0,
296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
297 DRM_MODE_FLAG_INTERLACE) },
298 /* 0x10 - 1024x768@60Hz */
299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
300 1184, 1344, 0, 768, 771, 777, 806, 0,
301 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
302 /* 0x11 - 1024x768@70Hz */
303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
304 1184, 1328, 0, 768, 771, 777, 806, 0,
305 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
306 /* 0x12 - 1024x768@75Hz */
307 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
308 1136, 1312, 0, 768, 769, 772, 800, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
310 /* 0x13 - 1024x768@85Hz */
311 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
312 1168, 1376, 0, 768, 769, 772, 808, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
314 /* 0x14 - 1024x768@120Hz RB */
315 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
316 1104, 1184, 0, 768, 771, 775, 813, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
318 /* 0x15 - 1152x864@75Hz */
319 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
320 1344, 1600, 0, 864, 865, 868, 900, 0,
321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
322 /* 0x55 - 1280x720@60Hz */
323 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
324 1430, 1650, 0, 720, 725, 730, 750, 0,
325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
326 /* 0x16 - 1280x768@60Hz RB */
327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
328 1360, 1440, 0, 768, 771, 778, 790, 0,
329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
330 /* 0x17 - 1280x768@60Hz */
331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
332 1472, 1664, 0, 768, 771, 778, 798, 0,
333 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
334 /* 0x18 - 1280x768@75Hz */
335 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
336 1488, 1696, 0, 768, 771, 778, 805, 0,
337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
338 /* 0x19 - 1280x768@85Hz */
339 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
340 1496, 1712, 0, 768, 771, 778, 809, 0,
341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
342 /* 0x1a - 1280x768@120Hz RB */
343 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
344 1360, 1440, 0, 768, 771, 778, 813, 0,
345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
346 /* 0x1b - 1280x800@60Hz RB */
347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
348 1360, 1440, 0, 800, 803, 809, 823, 0,
349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
350 /* 0x1c - 1280x800@60Hz */
351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
352 1480, 1680, 0, 800, 803, 809, 831, 0,
353 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
354 /* 0x1d - 1280x800@75Hz */
355 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
356 1488, 1696, 0, 800, 803, 809, 838, 0,
357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
358 /* 0x1e - 1280x800@85Hz */
359 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
360 1496, 1712, 0, 800, 803, 809, 843, 0,
361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
362 /* 0x1f - 1280x800@120Hz RB */
363 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
364 1360, 1440, 0, 800, 803, 809, 847, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
366 /* 0x20 - 1280x960@60Hz */
367 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
368 1488, 1800, 0, 960, 961, 964, 1000, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
370 /* 0x21 - 1280x960@85Hz */
371 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
372 1504, 1728, 0, 960, 961, 964, 1011, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
374 /* 0x22 - 1280x960@120Hz RB */
375 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
376 1360, 1440, 0, 960, 963, 967, 1017, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
378 /* 0x23 - 1280x1024@60Hz */
379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
380 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
382 /* 0x24 - 1280x1024@75Hz */
383 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
384 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
386 /* 0x25 - 1280x1024@85Hz */
387 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
388 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
390 /* 0x26 - 1280x1024@120Hz RB */
391 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
392 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
394 /* 0x27 - 1360x768@60Hz */
395 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
396 1536, 1792, 0, 768, 771, 777, 795, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
398 /* 0x28 - 1360x768@120Hz RB */
399 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
400 1440, 1520, 0, 768, 771, 776, 813, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
402 /* 0x51 - 1366x768@60Hz */
403 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
404 1579, 1792, 0, 768, 771, 774, 798, 0,
405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
406 /* 0x56 - 1366x768@60Hz */
407 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
408 1436, 1500, 0, 768, 769, 772, 800, 0,
409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
410 /* 0x29 - 1400x1050@60Hz RB */
411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
412 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
414 /* 0x2a - 1400x1050@60Hz */
415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
416 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
417 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
418 /* 0x2b - 1400x1050@75Hz */
419 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
420 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
422 /* 0x2c - 1400x1050@85Hz */
423 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
424 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
426 /* 0x2d - 1400x1050@120Hz RB */
427 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
428 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
430 /* 0x2e - 1440x900@60Hz RB */
431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
432 1520, 1600, 0, 900, 903, 909, 926, 0,
433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
434 /* 0x2f - 1440x900@60Hz */
435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
436 1672, 1904, 0, 900, 903, 909, 934, 0,
437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
438 /* 0x30 - 1440x900@75Hz */
439 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
440 1688, 1936, 0, 900, 903, 909, 942, 0,
441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
442 /* 0x31 - 1440x900@85Hz */
443 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
444 1696, 1952, 0, 900, 903, 909, 948, 0,
445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
446 /* 0x32 - 1440x900@120Hz RB */
447 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
448 1520, 1600, 0, 900, 903, 909, 953, 0,
449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
450 /* 0x53 - 1600x900@60Hz */
451 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
452 1704, 1800, 0, 900, 901, 904, 1000, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
454 /* 0x33 - 1600x1200@60Hz */
455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
458 /* 0x34 - 1600x1200@65Hz */
459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 0x35 - 1600x1200@70Hz */
463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
464 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
466 /* 0x36 - 1600x1200@75Hz */
467 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
468 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
470 /* 0x37 - 1600x1200@85Hz */
471 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
472 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
474 /* 0x38 - 1600x1200@120Hz RB */
475 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
476 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
478 /* 0x39 - 1680x1050@60Hz RB */
479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
480 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
482 /* 0x3a - 1680x1050@60Hz */
483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
484 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
486 /* 0x3b - 1680x1050@75Hz */
487 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
488 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
490 /* 0x3c - 1680x1050@85Hz */
491 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
492 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
494 /* 0x3d - 1680x1050@120Hz RB */
495 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
496 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
498 /* 0x3e - 1792x1344@60Hz */
499 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
500 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
502 /* 0x3f - 1792x1344@75Hz */
503 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
504 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
506 /* 0x40 - 1792x1344@120Hz RB */
507 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
508 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
510 /* 0x41 - 1856x1392@60Hz */
511 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
512 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
514 /* 0x42 - 1856x1392@75Hz */
515 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
516 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
517 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
518 /* 0x43 - 1856x1392@120Hz RB */
519 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
520 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
522 /* 0x52 - 1920x1080@60Hz */
523 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
524 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
526 /* 0x44 - 1920x1200@60Hz RB */
527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
528 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
530 /* 0x45 - 1920x1200@60Hz */
531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
532 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
534 /* 0x46 - 1920x1200@75Hz */
535 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
536 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
538 /* 0x47 - 1920x1200@85Hz */
539 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
540 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
542 /* 0x48 - 1920x1200@120Hz RB */
543 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
544 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
546 /* 0x49 - 1920x1440@60Hz */
547 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
548 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
550 /* 0x4a - 1920x1440@75Hz */
551 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
552 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
553 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
554 /* 0x4b - 1920x1440@120Hz RB */
555 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
556 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
558 /* 0x54 - 2048x1152@60Hz */
559 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
560 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
562 /* 0x4c - 2560x1600@60Hz RB */
563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
564 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
566 /* 0x4d - 2560x1600@60Hz */
567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
568 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
569 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
570 /* 0x4e - 2560x1600@75Hz */
571 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
572 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
574 /* 0x4f - 2560x1600@85Hz */
575 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
576 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
577 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
578 /* 0x50 - 2560x1600@120Hz RB */
579 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
580 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
582 /* 0x57 - 4096x2160@60Hz RB */
583 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
584 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
586 /* 0x58 - 4096x2160@59.94Hz RB */
587 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
588 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
593 * These more or less come from the DMT spec. The 720x400 modes are
594 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
595 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
596 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
599 * The DMT modes have been fact-checked; the rest are mild guesses.
601 static const struct drm_display_mode edid_est_modes[] = {
602 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
603 968, 1056, 0, 600, 601, 605, 628, 0,
604 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
605 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
606 896, 1024, 0, 600, 601, 603, 625, 0,
607 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
608 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
609 720, 840, 0, 480, 481, 484, 500, 0,
610 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
611 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
612 704, 832, 0, 480, 489, 492, 520, 0,
613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
614 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
615 768, 864, 0, 480, 483, 486, 525, 0,
616 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
617 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
618 752, 800, 0, 480, 490, 492, 525, 0,
619 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
620 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
621 846, 900, 0, 400, 421, 423, 449, 0,
622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
623 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
624 846, 900, 0, 400, 412, 414, 449, 0,
625 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
626 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
627 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
628 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
629 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
630 1136, 1312, 0, 768, 769, 772, 800, 0,
631 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
632 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
633 1184, 1328, 0, 768, 771, 777, 806, 0,
634 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
635 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
636 1184, 1344, 0, 768, 771, 777, 806, 0,
637 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
638 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
639 1208, 1264, 0, 768, 768, 776, 817, 0,
640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
641 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
642 928, 1152, 0, 624, 625, 628, 667, 0,
643 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
644 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
645 896, 1056, 0, 600, 601, 604, 625, 0,
646 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
647 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
648 976, 1040, 0, 600, 637, 643, 666, 0,
649 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
650 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
651 1344, 1600, 0, 864, 865, 868, 900, 0,
652 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
662 static const struct minimode est3_modes[] = {
670 { 1024, 768, 85, 0 },
671 { 1152, 864, 75, 0 },
673 { 1280, 768, 60, 1 },
674 { 1280, 768, 60, 0 },
675 { 1280, 768, 75, 0 },
676 { 1280, 768, 85, 0 },
677 { 1280, 960, 60, 0 },
678 { 1280, 960, 85, 0 },
679 { 1280, 1024, 60, 0 },
680 { 1280, 1024, 85, 0 },
682 { 1360, 768, 60, 0 },
683 { 1440, 900, 60, 1 },
684 { 1440, 900, 60, 0 },
685 { 1440, 900, 75, 0 },
686 { 1440, 900, 85, 0 },
687 { 1400, 1050, 60, 1 },
688 { 1400, 1050, 60, 0 },
689 { 1400, 1050, 75, 0 },
691 { 1400, 1050, 85, 0 },
692 { 1680, 1050, 60, 1 },
693 { 1680, 1050, 60, 0 },
694 { 1680, 1050, 75, 0 },
695 { 1680, 1050, 85, 0 },
696 { 1600, 1200, 60, 0 },
697 { 1600, 1200, 65, 0 },
698 { 1600, 1200, 70, 0 },
700 { 1600, 1200, 75, 0 },
701 { 1600, 1200, 85, 0 },
702 { 1792, 1344, 60, 0 },
703 { 1792, 1344, 75, 0 },
704 { 1856, 1392, 60, 0 },
705 { 1856, 1392, 75, 0 },
706 { 1920, 1200, 60, 1 },
707 { 1920, 1200, 60, 0 },
709 { 1920, 1200, 75, 0 },
710 { 1920, 1200, 85, 0 },
711 { 1920, 1440, 60, 0 },
712 { 1920, 1440, 75, 0 },
715 static const struct minimode extra_modes[] = {
716 { 1024, 576, 60, 0 },
717 { 1366, 768, 60, 0 },
718 { 1600, 900, 60, 0 },
719 { 1680, 945, 60, 0 },
720 { 1920, 1080, 60, 0 },
721 { 2048, 1152, 60, 0 },
722 { 2048, 1536, 60, 0 },
726 * From CEA/CTA-861 spec.
728 * Do not access directly, instead always use cea_mode_for_vic().
730 static const struct drm_display_mode edid_cea_modes_1[] = {
731 /* 1 - 640x480@60Hz 4:3 */
732 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
733 752, 800, 0, 480, 490, 492, 525, 0,
734 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
735 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
736 /* 2 - 720x480@60Hz 4:3 */
737 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
738 798, 858, 0, 480, 489, 495, 525, 0,
739 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
740 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
741 /* 3 - 720x480@60Hz 16:9 */
742 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
743 798, 858, 0, 480, 489, 495, 525, 0,
744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
745 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
746 /* 4 - 1280x720@60Hz 16:9 */
747 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
748 1430, 1650, 0, 720, 725, 730, 750, 0,
749 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
750 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
751 /* 5 - 1920x1080i@60Hz 16:9 */
752 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
753 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
754 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
755 DRM_MODE_FLAG_INTERLACE),
756 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
757 /* 6 - 720(1440)x480i@60Hz 4:3 */
758 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
759 801, 858, 0, 480, 488, 494, 525, 0,
760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
761 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
762 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
763 /* 7 - 720(1440)x480i@60Hz 16:9 */
764 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
765 801, 858, 0, 480, 488, 494, 525, 0,
766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
767 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
768 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
769 /* 8 - 720(1440)x240@60Hz 4:3 */
770 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
771 801, 858, 0, 240, 244, 247, 262, 0,
772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
773 DRM_MODE_FLAG_DBLCLK),
774 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
775 /* 9 - 720(1440)x240@60Hz 16:9 */
776 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
777 801, 858, 0, 240, 244, 247, 262, 0,
778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
779 DRM_MODE_FLAG_DBLCLK),
780 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
781 /* 10 - 2880x480i@60Hz 4:3 */
782 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
783 3204, 3432, 0, 480, 488, 494, 525, 0,
784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
785 DRM_MODE_FLAG_INTERLACE),
786 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
787 /* 11 - 2880x480i@60Hz 16:9 */
788 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
789 3204, 3432, 0, 480, 488, 494, 525, 0,
790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
791 DRM_MODE_FLAG_INTERLACE),
792 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
793 /* 12 - 2880x240@60Hz 4:3 */
794 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
795 3204, 3432, 0, 240, 244, 247, 262, 0,
796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
797 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
798 /* 13 - 2880x240@60Hz 16:9 */
799 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
800 3204, 3432, 0, 240, 244, 247, 262, 0,
801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
802 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
803 /* 14 - 1440x480@60Hz 4:3 */
804 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
805 1596, 1716, 0, 480, 489, 495, 525, 0,
806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
807 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
808 /* 15 - 1440x480@60Hz 16:9 */
809 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
810 1596, 1716, 0, 480, 489, 495, 525, 0,
811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
812 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
813 /* 16 - 1920x1080@60Hz 16:9 */
814 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
815 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
816 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
817 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
818 /* 17 - 720x576@50Hz 4:3 */
819 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
820 796, 864, 0, 576, 581, 586, 625, 0,
821 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
822 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
823 /* 18 - 720x576@50Hz 16:9 */
824 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
825 796, 864, 0, 576, 581, 586, 625, 0,
826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
827 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
828 /* 19 - 1280x720@50Hz 16:9 */
829 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
830 1760, 1980, 0, 720, 725, 730, 750, 0,
831 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
832 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
833 /* 20 - 1920x1080i@50Hz 16:9 */
834 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
835 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
837 DRM_MODE_FLAG_INTERLACE),
838 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
839 /* 21 - 720(1440)x576i@50Hz 4:3 */
840 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
841 795, 864, 0, 576, 580, 586, 625, 0,
842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
843 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
844 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
845 /* 22 - 720(1440)x576i@50Hz 16:9 */
846 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
847 795, 864, 0, 576, 580, 586, 625, 0,
848 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
849 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
850 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
851 /* 23 - 720(1440)x288@50Hz 4:3 */
852 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
853 795, 864, 0, 288, 290, 293, 312, 0,
854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
855 DRM_MODE_FLAG_DBLCLK),
856 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
857 /* 24 - 720(1440)x288@50Hz 16:9 */
858 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
859 795, 864, 0, 288, 290, 293, 312, 0,
860 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
861 DRM_MODE_FLAG_DBLCLK),
862 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
863 /* 25 - 2880x576i@50Hz 4:3 */
864 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
865 3180, 3456, 0, 576, 580, 586, 625, 0,
866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
867 DRM_MODE_FLAG_INTERLACE),
868 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
869 /* 26 - 2880x576i@50Hz 16:9 */
870 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
871 3180, 3456, 0, 576, 580, 586, 625, 0,
872 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
873 DRM_MODE_FLAG_INTERLACE),
874 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
875 /* 27 - 2880x288@50Hz 4:3 */
876 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
877 3180, 3456, 0, 288, 290, 293, 312, 0,
878 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
879 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
880 /* 28 - 2880x288@50Hz 16:9 */
881 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
882 3180, 3456, 0, 288, 290, 293, 312, 0,
883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
884 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
885 /* 29 - 1440x576@50Hz 4:3 */
886 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
887 1592, 1728, 0, 576, 581, 586, 625, 0,
888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
889 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
890 /* 30 - 1440x576@50Hz 16:9 */
891 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
892 1592, 1728, 0, 576, 581, 586, 625, 0,
893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
894 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
895 /* 31 - 1920x1080@50Hz 16:9 */
896 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
897 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
898 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
899 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
900 /* 32 - 1920x1080@24Hz 16:9 */
901 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
902 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
903 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
904 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
905 /* 33 - 1920x1080@25Hz 16:9 */
906 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
907 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
908 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
909 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
910 /* 34 - 1920x1080@30Hz 16:9 */
911 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
912 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
913 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
914 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
915 /* 35 - 2880x480@60Hz 4:3 */
916 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
917 3192, 3432, 0, 480, 489, 495, 525, 0,
918 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
919 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
920 /* 36 - 2880x480@60Hz 16:9 */
921 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
922 3192, 3432, 0, 480, 489, 495, 525, 0,
923 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
924 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
925 /* 37 - 2880x576@50Hz 4:3 */
926 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
927 3184, 3456, 0, 576, 581, 586, 625, 0,
928 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
929 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
930 /* 38 - 2880x576@50Hz 16:9 */
931 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
932 3184, 3456, 0, 576, 581, 586, 625, 0,
933 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
934 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
935 /* 39 - 1920x1080i@50Hz 16:9 */
936 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
937 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
939 DRM_MODE_FLAG_INTERLACE),
940 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
941 /* 40 - 1920x1080i@100Hz 16:9 */
942 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
943 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
944 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
945 DRM_MODE_FLAG_INTERLACE),
946 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
947 /* 41 - 1280x720@100Hz 16:9 */
948 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
949 1760, 1980, 0, 720, 725, 730, 750, 0,
950 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
951 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
952 /* 42 - 720x576@100Hz 4:3 */
953 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
954 796, 864, 0, 576, 581, 586, 625, 0,
955 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
956 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
957 /* 43 - 720x576@100Hz 16:9 */
958 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
959 796, 864, 0, 576, 581, 586, 625, 0,
960 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
961 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
962 /* 44 - 720(1440)x576i@100Hz 4:3 */
963 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
964 795, 864, 0, 576, 580, 586, 625, 0,
965 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
966 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
967 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
968 /* 45 - 720(1440)x576i@100Hz 16:9 */
969 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
970 795, 864, 0, 576, 580, 586, 625, 0,
971 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
972 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
973 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
974 /* 46 - 1920x1080i@120Hz 16:9 */
975 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
976 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
978 DRM_MODE_FLAG_INTERLACE),
979 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
980 /* 47 - 1280x720@120Hz 16:9 */
981 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
982 1430, 1650, 0, 720, 725, 730, 750, 0,
983 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
984 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
985 /* 48 - 720x480@120Hz 4:3 */
986 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
987 798, 858, 0, 480, 489, 495, 525, 0,
988 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
989 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
990 /* 49 - 720x480@120Hz 16:9 */
991 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
992 798, 858, 0, 480, 489, 495, 525, 0,
993 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
994 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
995 /* 50 - 720(1440)x480i@120Hz 4:3 */
996 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
997 801, 858, 0, 480, 488, 494, 525, 0,
998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
999 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1000 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1001 /* 51 - 720(1440)x480i@120Hz 16:9 */
1002 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1003 801, 858, 0, 480, 488, 494, 525, 0,
1004 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1005 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1006 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1007 /* 52 - 720x576@200Hz 4:3 */
1008 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1009 796, 864, 0, 576, 581, 586, 625, 0,
1010 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1011 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1012 /* 53 - 720x576@200Hz 16:9 */
1013 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1014 796, 864, 0, 576, 581, 586, 625, 0,
1015 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1016 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1017 /* 54 - 720(1440)x576i@200Hz 4:3 */
1018 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1019 795, 864, 0, 576, 580, 586, 625, 0,
1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1021 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1022 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1023 /* 55 - 720(1440)x576i@200Hz 16:9 */
1024 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1025 795, 864, 0, 576, 580, 586, 625, 0,
1026 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1027 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1028 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1029 /* 56 - 720x480@240Hz 4:3 */
1030 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1031 798, 858, 0, 480, 489, 495, 525, 0,
1032 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1033 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1034 /* 57 - 720x480@240Hz 16:9 */
1035 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1036 798, 858, 0, 480, 489, 495, 525, 0,
1037 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1038 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1039 /* 58 - 720(1440)x480i@240Hz 4:3 */
1040 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1041 801, 858, 0, 480, 488, 494, 525, 0,
1042 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1043 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1044 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1045 /* 59 - 720(1440)x480i@240Hz 16:9 */
1046 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1047 801, 858, 0, 480, 488, 494, 525, 0,
1048 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1049 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1050 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1051 /* 60 - 1280x720@24Hz 16:9 */
1052 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1053 3080, 3300, 0, 720, 725, 730, 750, 0,
1054 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1055 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1056 /* 61 - 1280x720@25Hz 16:9 */
1057 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1058 3740, 3960, 0, 720, 725, 730, 750, 0,
1059 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1060 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1061 /* 62 - 1280x720@30Hz 16:9 */
1062 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1063 3080, 3300, 0, 720, 725, 730, 750, 0,
1064 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1065 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1066 /* 63 - 1920x1080@120Hz 16:9 */
1067 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1068 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1069 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1070 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1071 /* 64 - 1920x1080@100Hz 16:9 */
1072 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1073 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1075 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1076 /* 65 - 1280x720@24Hz 64:27 */
1077 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1078 3080, 3300, 0, 720, 725, 730, 750, 0,
1079 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1080 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1081 /* 66 - 1280x720@25Hz 64:27 */
1082 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1083 3740, 3960, 0, 720, 725, 730, 750, 0,
1084 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1085 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1086 /* 67 - 1280x720@30Hz 64:27 */
1087 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1088 3080, 3300, 0, 720, 725, 730, 750, 0,
1089 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1090 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1091 /* 68 - 1280x720@50Hz 64:27 */
1092 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1093 1760, 1980, 0, 720, 725, 730, 750, 0,
1094 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1095 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1096 /* 69 - 1280x720@60Hz 64:27 */
1097 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1098 1430, 1650, 0, 720, 725, 730, 750, 0,
1099 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1100 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1101 /* 70 - 1280x720@100Hz 64:27 */
1102 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1103 1760, 1980, 0, 720, 725, 730, 750, 0,
1104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1105 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1106 /* 71 - 1280x720@120Hz 64:27 */
1107 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1108 1430, 1650, 0, 720, 725, 730, 750, 0,
1109 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1110 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1111 /* 72 - 1920x1080@24Hz 64:27 */
1112 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1113 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1114 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1115 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1116 /* 73 - 1920x1080@25Hz 64:27 */
1117 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1118 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1119 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1120 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1121 /* 74 - 1920x1080@30Hz 64:27 */
1122 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1123 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1124 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1125 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1126 /* 75 - 1920x1080@50Hz 64:27 */
1127 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1128 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1129 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1130 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1131 /* 76 - 1920x1080@60Hz 64:27 */
1132 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1133 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1135 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1136 /* 77 - 1920x1080@100Hz 64:27 */
1137 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1138 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1139 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1140 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1141 /* 78 - 1920x1080@120Hz 64:27 */
1142 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1143 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1145 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1146 /* 79 - 1680x720@24Hz 64:27 */
1147 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1148 3080, 3300, 0, 720, 725, 730, 750, 0,
1149 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1150 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1151 /* 80 - 1680x720@25Hz 64:27 */
1152 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1153 2948, 3168, 0, 720, 725, 730, 750, 0,
1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1155 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1156 /* 81 - 1680x720@30Hz 64:27 */
1157 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1158 2420, 2640, 0, 720, 725, 730, 750, 0,
1159 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1160 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1161 /* 82 - 1680x720@50Hz 64:27 */
1162 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1163 1980, 2200, 0, 720, 725, 730, 750, 0,
1164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1165 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1166 /* 83 - 1680x720@60Hz 64:27 */
1167 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1168 1980, 2200, 0, 720, 725, 730, 750, 0,
1169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1170 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1171 /* 84 - 1680x720@100Hz 64:27 */
1172 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1173 1780, 2000, 0, 720, 725, 730, 825, 0,
1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1175 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1176 /* 85 - 1680x720@120Hz 64:27 */
1177 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1178 1780, 2000, 0, 720, 725, 730, 825, 0,
1179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1180 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1181 /* 86 - 2560x1080@24Hz 64:27 */
1182 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1183 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1185 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1186 /* 87 - 2560x1080@25Hz 64:27 */
1187 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1188 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1190 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1191 /* 88 - 2560x1080@30Hz 64:27 */
1192 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1193 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1195 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1196 /* 89 - 2560x1080@50Hz 64:27 */
1197 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1198 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1200 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1201 /* 90 - 2560x1080@60Hz 64:27 */
1202 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1203 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1205 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1206 /* 91 - 2560x1080@100Hz 64:27 */
1207 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1208 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1210 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1211 /* 92 - 2560x1080@120Hz 64:27 */
1212 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1213 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1215 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1216 /* 93 - 3840x2160@24Hz 16:9 */
1217 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1218 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1220 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1221 /* 94 - 3840x2160@25Hz 16:9 */
1222 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1223 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1225 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1226 /* 95 - 3840x2160@30Hz 16:9 */
1227 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1228 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1230 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1231 /* 96 - 3840x2160@50Hz 16:9 */
1232 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1233 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1235 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1236 /* 97 - 3840x2160@60Hz 16:9 */
1237 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1238 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1240 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1241 /* 98 - 4096x2160@24Hz 256:135 */
1242 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1243 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1245 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1246 /* 99 - 4096x2160@25Hz 256:135 */
1247 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1248 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1250 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1251 /* 100 - 4096x2160@30Hz 256:135 */
1252 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1253 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1255 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1256 /* 101 - 4096x2160@50Hz 256:135 */
1257 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1258 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1260 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1261 /* 102 - 4096x2160@60Hz 256:135 */
1262 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1263 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1265 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1266 /* 103 - 3840x2160@24Hz 64:27 */
1267 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1268 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1270 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1271 /* 104 - 3840x2160@25Hz 64:27 */
1272 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1273 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1275 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1276 /* 105 - 3840x2160@30Hz 64:27 */
1277 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1278 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1280 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1281 /* 106 - 3840x2160@50Hz 64:27 */
1282 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1283 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1285 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1286 /* 107 - 3840x2160@60Hz 64:27 */
1287 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1288 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1290 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1291 /* 108 - 1280x720@48Hz 16:9 */
1292 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1293 2280, 2500, 0, 720, 725, 730, 750, 0,
1294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1295 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1296 /* 109 - 1280x720@48Hz 64:27 */
1297 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1298 2280, 2500, 0, 720, 725, 730, 750, 0,
1299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1300 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1301 /* 110 - 1680x720@48Hz 64:27 */
1302 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1303 2530, 2750, 0, 720, 725, 730, 750, 0,
1304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1305 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1306 /* 111 - 1920x1080@48Hz 16:9 */
1307 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1308 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1310 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1311 /* 112 - 1920x1080@48Hz 64:27 */
1312 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1313 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1315 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1316 /* 113 - 2560x1080@48Hz 64:27 */
1317 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1318 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1320 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1321 /* 114 - 3840x2160@48Hz 16:9 */
1322 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1323 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1325 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1326 /* 115 - 4096x2160@48Hz 256:135 */
1327 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1328 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1330 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1331 /* 116 - 3840x2160@48Hz 64:27 */
1332 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1333 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1335 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1336 /* 117 - 3840x2160@100Hz 16:9 */
1337 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1338 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1340 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1341 /* 118 - 3840x2160@120Hz 16:9 */
1342 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1343 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1345 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1346 /* 119 - 3840x2160@100Hz 64:27 */
1347 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1348 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1350 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1351 /* 120 - 3840x2160@120Hz 64:27 */
1352 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1353 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1355 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1356 /* 121 - 5120x2160@24Hz 64:27 */
1357 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1358 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1360 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1361 /* 122 - 5120x2160@25Hz 64:27 */
1362 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1363 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1365 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1366 /* 123 - 5120x2160@30Hz 64:27 */
1367 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1368 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1370 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1371 /* 124 - 5120x2160@48Hz 64:27 */
1372 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1373 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1375 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1376 /* 125 - 5120x2160@50Hz 64:27 */
1377 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1378 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1380 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1381 /* 126 - 5120x2160@60Hz 64:27 */
1382 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1383 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1385 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1386 /* 127 - 5120x2160@100Hz 64:27 */
1387 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1388 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1390 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1394 * From CEA/CTA-861 spec.
1396 * Do not access directly, instead always use cea_mode_for_vic().
1398 static const struct drm_display_mode edid_cea_modes_193[] = {
1399 /* 193 - 5120x2160@120Hz 64:27 */
1400 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1401 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1403 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1404 /* 194 - 7680x4320@24Hz 16:9 */
1405 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1406 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1408 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1409 /* 195 - 7680x4320@25Hz 16:9 */
1410 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1411 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1413 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1414 /* 196 - 7680x4320@30Hz 16:9 */
1415 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1416 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1418 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1419 /* 197 - 7680x4320@48Hz 16:9 */
1420 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1421 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1423 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1424 /* 198 - 7680x4320@50Hz 16:9 */
1425 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1426 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1428 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1429 /* 199 - 7680x4320@60Hz 16:9 */
1430 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1431 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1433 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1434 /* 200 - 7680x4320@100Hz 16:9 */
1435 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1436 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1438 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1439 /* 201 - 7680x4320@120Hz 16:9 */
1440 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1441 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1443 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1444 /* 202 - 7680x4320@24Hz 64:27 */
1445 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1446 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1448 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1449 /* 203 - 7680x4320@25Hz 64:27 */
1450 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1451 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1453 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1454 /* 204 - 7680x4320@30Hz 64:27 */
1455 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1456 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1458 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1459 /* 205 - 7680x4320@48Hz 64:27 */
1460 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1461 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1463 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1464 /* 206 - 7680x4320@50Hz 64:27 */
1465 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1466 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1468 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1469 /* 207 - 7680x4320@60Hz 64:27 */
1470 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1471 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1473 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1474 /* 208 - 7680x4320@100Hz 64:27 */
1475 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1476 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1478 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1479 /* 209 - 7680x4320@120Hz 64:27 */
1480 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1481 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1483 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1484 /* 210 - 10240x4320@24Hz 64:27 */
1485 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1486 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1488 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1489 /* 211 - 10240x4320@25Hz 64:27 */
1490 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1491 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1493 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1494 /* 212 - 10240x4320@30Hz 64:27 */
1495 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1496 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1498 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1499 /* 213 - 10240x4320@48Hz 64:27 */
1500 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1501 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1503 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1504 /* 214 - 10240x4320@50Hz 64:27 */
1505 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1506 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1508 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1509 /* 215 - 10240x4320@60Hz 64:27 */
1510 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1511 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1513 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1514 /* 216 - 10240x4320@100Hz 64:27 */
1515 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1516 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1518 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1519 /* 217 - 10240x4320@120Hz 64:27 */
1520 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1521 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1523 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1524 /* 218 - 4096x2160@100Hz 256:135 */
1525 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1526 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1528 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1529 /* 219 - 4096x2160@120Hz 256:135 */
1530 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1531 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1533 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1537 * HDMI 1.4 4k modes. Index using the VIC.
1539 static const struct drm_display_mode edid_4k_modes[] = {
1540 /* 0 - dummy, VICs start at 1 */
1542 /* 1 - 3840x2160@30Hz */
1543 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1544 3840, 4016, 4104, 4400, 0,
1545 2160, 2168, 2178, 2250, 0,
1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1547 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1548 /* 2 - 3840x2160@25Hz */
1549 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1550 3840, 4896, 4984, 5280, 0,
1551 2160, 2168, 2178, 2250, 0,
1552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1553 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1554 /* 3 - 3840x2160@24Hz */
1555 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1556 3840, 5116, 5204, 5500, 0,
1557 2160, 2168, 2178, 2250, 0,
1558 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1559 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1560 /* 4 - 4096x2160@24Hz (SMPTE) */
1561 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1562 4096, 5116, 5204, 5500, 0,
1563 2160, 2168, 2178, 2250, 0,
1564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1565 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1568 /*** DDC fetch and block validation ***/
1571 * The opaque EDID type, internal to drm_edid.c.
1574 /* Size allocated for edid */
1576 const struct edid *edid;
1579 static int edid_extension_block_count(const struct edid *edid)
1581 return edid->extensions;
1584 static int edid_block_count(const struct edid *edid)
1586 return edid_extension_block_count(edid) + 1;
1589 static int edid_size_by_blocks(int num_blocks)
1591 return num_blocks * EDID_LENGTH;
1594 static int edid_size(const struct edid *edid)
1596 return edid_size_by_blocks(edid_block_count(edid));
1599 static const void *edid_block_data(const struct edid *edid, int index)
1601 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1603 return edid + index;
1606 static const void *edid_extension_block_data(const struct edid *edid, int index)
1608 return edid_block_data(edid, index + 1);
1612 * Initializer helper for legacy interfaces, where we have no choice but to
1613 * trust edid size. Not for general purpose use.
1615 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1616 const struct edid *edid)
1621 memset(drm_edid, 0, sizeof(*drm_edid));
1623 drm_edid->edid = edid;
1624 drm_edid->size = edid_size(edid);
1630 * EDID base and extension block iterator.
1632 * struct drm_edid_iter iter;
1635 * drm_edid_iter_begin(edid, &iter);
1636 * drm_edid_iter_for_each(block, &iter) {
1637 * // do stuff with block
1639 * drm_edid_iter_end(&iter);
1641 struct drm_edid_iter {
1642 const struct edid *edid;
1644 /* Current block index. */
1648 static void drm_edid_iter_begin(const struct edid *edid,
1649 struct drm_edid_iter *iter)
1651 memset(iter, 0, sizeof(*iter));
1656 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1658 const void *block = NULL;
1663 if (iter->index < edid_block_count(iter->edid))
1664 block = edid_block_data(iter->edid, iter->index++);
1669 #define drm_edid_iter_for_each(__block, __iter) \
1670 while (((__block) = __drm_edid_iter_next(__iter)))
1672 static void drm_edid_iter_end(struct drm_edid_iter *iter)
1674 memset(iter, 0, sizeof(*iter));
1677 static const u8 edid_header[] = {
1678 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1681 static void edid_header_fix(void *edid)
1683 memcpy(edid, edid_header, sizeof(edid_header));
1687 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1688 * @_edid: pointer to raw base EDID block
1690 * Sanity check the header of the base EDID block.
1692 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1694 int drm_edid_header_is_valid(const void *_edid)
1696 const struct edid *edid = _edid;
1699 for (i = 0; i < sizeof(edid_header); i++) {
1700 if (edid->header[i] == edid_header[i])
1706 EXPORT_SYMBOL(drm_edid_header_is_valid);
1708 static int edid_fixup __read_mostly = 6;
1709 module_param_named(edid_fixup, edid_fixup, int, 0400);
1710 MODULE_PARM_DESC(edid_fixup,
1711 "Minimum number of valid EDID header bytes (0-8, default 6)");
1713 static int edid_block_compute_checksum(const void *_block)
1715 const u8 *block = _block;
1717 u8 csum = 0, crc = 0;
1719 for (i = 0; i < EDID_LENGTH - 1; i++)
1727 static int edid_block_get_checksum(const void *_block)
1729 const struct edid *block = _block;
1731 return block->checksum;
1734 static int edid_block_tag(const void *_block)
1736 const u8 *block = _block;
1741 static bool edid_block_is_zero(const void *edid)
1743 return !memchr_inv(edid, 0, EDID_LENGTH);
1747 * drm_edid_are_equal - compare two edid blobs.
1748 * @edid1: pointer to first blob
1749 * @edid2: pointer to second blob
1750 * This helper can be used during probing to determine if
1753 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1755 int edid1_len, edid2_len;
1756 bool edid1_present = edid1 != NULL;
1757 bool edid2_present = edid2 != NULL;
1759 if (edid1_present != edid2_present)
1763 edid1_len = edid_size(edid1);
1764 edid2_len = edid_size(edid2);
1766 if (edid1_len != edid2_len)
1769 if (memcmp(edid1, edid2, edid1_len))
1775 EXPORT_SYMBOL(drm_edid_are_equal);
1777 enum edid_block_status {
1779 EDID_BLOCK_READ_FAIL,
1782 EDID_BLOCK_HEADER_CORRUPT,
1783 EDID_BLOCK_HEADER_REPAIR,
1784 EDID_BLOCK_HEADER_FIXED,
1785 EDID_BLOCK_CHECKSUM,
1789 static enum edid_block_status edid_block_check(const void *_block,
1792 const struct edid *block = _block;
1795 return EDID_BLOCK_NULL;
1797 if (is_base_block) {
1798 int score = drm_edid_header_is_valid(block);
1800 if (score < clamp(edid_fixup, 0, 8)) {
1801 if (edid_block_is_zero(block))
1802 return EDID_BLOCK_ZERO;
1804 return EDID_BLOCK_HEADER_CORRUPT;
1808 return EDID_BLOCK_HEADER_REPAIR;
1811 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1812 if (edid_block_is_zero(block))
1813 return EDID_BLOCK_ZERO;
1815 return EDID_BLOCK_CHECKSUM;
1818 if (is_base_block) {
1819 if (block->version != 1)
1820 return EDID_BLOCK_VERSION;
1823 return EDID_BLOCK_OK;
1826 static bool edid_block_status_valid(enum edid_block_status status, int tag)
1828 return status == EDID_BLOCK_OK ||
1829 status == EDID_BLOCK_HEADER_FIXED ||
1830 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1833 static bool edid_block_valid(const void *block, bool base)
1835 return edid_block_status_valid(edid_block_check(block, base),
1836 edid_block_tag(block));
1839 static void edid_block_status_print(enum edid_block_status status,
1840 const struct edid *block,
1846 case EDID_BLOCK_READ_FAIL:
1847 pr_debug("EDID block %d read failed\n", block_num);
1849 case EDID_BLOCK_NULL:
1850 pr_debug("EDID block %d pointer is NULL\n", block_num);
1852 case EDID_BLOCK_ZERO:
1853 pr_notice("EDID block %d is all zeroes\n", block_num);
1855 case EDID_BLOCK_HEADER_CORRUPT:
1856 pr_notice("EDID has corrupt header\n");
1858 case EDID_BLOCK_HEADER_REPAIR:
1859 pr_debug("EDID corrupt header needs repair\n");
1861 case EDID_BLOCK_HEADER_FIXED:
1862 pr_debug("EDID corrupt header fixed\n");
1864 case EDID_BLOCK_CHECKSUM:
1865 if (edid_block_status_valid(status, edid_block_tag(block))) {
1866 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1867 block_num, edid_block_tag(block),
1868 edid_block_compute_checksum(block));
1870 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1871 block_num, edid_block_tag(block),
1872 edid_block_compute_checksum(block));
1875 case EDID_BLOCK_VERSION:
1876 pr_notice("EDID has major version %d, instead of 1\n",
1880 WARN(1, "EDID block %d unknown edid block status code %d\n",
1886 static void edid_block_dump(const char *level, const void *block, int block_num)
1888 enum edid_block_status status;
1891 status = edid_block_check(block, block_num == 0);
1892 if (status == EDID_BLOCK_ZERO)
1893 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1894 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1895 sprintf(prefix, "\t[%02x] BAD ", block_num);
1897 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1899 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1900 block, EDID_LENGTH, false);
1904 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1905 * @_block: pointer to raw EDID block
1906 * @block_num: type of block to validate (0 for base, extension otherwise)
1907 * @print_bad_edid: if true, dump bad EDID blocks to the console
1908 * @edid_corrupt: if true, the header or checksum is invalid
1910 * Validate a base or extension EDID block and optionally dump bad blocks to
1913 * Return: True if the block is valid, false otherwise.
1915 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
1918 struct edid *block = (struct edid *)_block;
1919 enum edid_block_status status;
1920 bool is_base_block = block_num == 0;
1923 if (WARN_ON(!block))
1926 status = edid_block_check(block, is_base_block);
1927 if (status == EDID_BLOCK_HEADER_REPAIR) {
1928 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1929 edid_header_fix(block);
1931 /* Retry with fixed header, update status if that worked. */
1932 status = edid_block_check(block, is_base_block);
1933 if (status == EDID_BLOCK_OK)
1934 status = EDID_BLOCK_HEADER_FIXED;
1939 * Unknown major version isn't corrupt but we can't use it. Only
1940 * the base block can reset edid_corrupt to false.
1942 if (is_base_block &&
1943 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
1944 *edid_corrupt = false;
1945 else if (status != EDID_BLOCK_OK)
1946 *edid_corrupt = true;
1949 edid_block_status_print(status, block, block_num);
1951 /* Determine whether we can use this block with this status. */
1952 valid = edid_block_status_valid(status, edid_block_tag(block));
1954 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
1955 pr_notice("Raw EDID:\n");
1956 edid_block_dump(KERN_NOTICE, block, block_num);
1961 EXPORT_SYMBOL(drm_edid_block_valid);
1964 * drm_edid_is_valid - sanity check EDID data
1967 * Sanity-check an entire EDID record (including extensions)
1969 * Return: True if the EDID data is valid, false otherwise.
1971 bool drm_edid_is_valid(struct edid *edid)
1978 for (i = 0; i < edid_block_count(edid); i++) {
1979 void *block = (void *)edid_block_data(edid, i);
1981 if (!drm_edid_block_valid(block, i, true, NULL))
1987 EXPORT_SYMBOL(drm_edid_is_valid);
1989 static struct edid *edid_filter_invalid_blocks(const struct edid *edid,
1992 struct edid *new, *dest_block;
1993 int valid_extensions = edid->extensions - invalid_blocks;
1996 new = kmalloc(edid_size_by_blocks(valid_extensions + 1), GFP_KERNEL);
2001 for (i = 0; i < edid_block_count(edid); i++) {
2002 const void *block = edid_block_data(edid, i);
2004 if (edid_block_valid(block, i == 0))
2005 memcpy(dest_block++, block, EDID_LENGTH);
2008 new->extensions = valid_extensions;
2009 new->checksum = edid_block_compute_checksum(new);
2017 #define DDC_SEGMENT_ADDR 0x30
2019 * drm_do_probe_ddc_edid() - get EDID information via I2C
2020 * @data: I2C device adapter
2021 * @buf: EDID data buffer to be filled
2022 * @block: 128 byte EDID block to start fetching from
2023 * @len: EDID data buffer length to fetch
2025 * Try to fetch EDID information by calling I2C driver functions.
2027 * Return: 0 on success or -1 on failure.
2030 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2032 struct i2c_adapter *adapter = data;
2033 unsigned char start = block * EDID_LENGTH;
2034 unsigned char segment = block >> 1;
2035 unsigned char xfers = segment ? 3 : 2;
2036 int ret, retries = 5;
2039 * The core I2C driver will automatically retry the transfer if the
2040 * adapter reports EAGAIN. However, we find that bit-banging transfers
2041 * are susceptible to errors under a heavily loaded machine and
2042 * generate spurious NAKs and timeouts. Retrying the transfer
2043 * of the individual block a few times seems to overcome this.
2046 struct i2c_msg msgs[] = {
2048 .addr = DDC_SEGMENT_ADDR,
2066 * Avoid sending the segment addr to not upset non-compliant
2069 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2071 if (ret == -ENXIO) {
2072 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2076 } while (ret != xfers && --retries);
2078 return ret == xfers ? 0 : -1;
2081 static void connector_bad_edid(struct drm_connector *connector,
2082 const struct edid *edid, int num_blocks)
2088 * 0x7e in the EDID is the number of extension blocks. The EDID
2089 * is 1 (base block) + num_ext_blocks big. That means we can think
2090 * of 0x7e in the EDID of the _index_ of the last block in the
2091 * combined chunk of memory.
2093 last_block = edid->extensions;
2095 /* Calculate real checksum for the last edid extension block data */
2096 if (last_block < num_blocks)
2097 connector->real_edid_checksum =
2098 edid_block_compute_checksum(edid + last_block);
2100 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2103 drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name);
2104 for (i = 0; i < num_blocks; i++)
2105 edid_block_dump(KERN_DEBUG, edid + i, i);
2108 /* Get override or firmware EDID */
2109 static struct edid *drm_get_override_edid(struct drm_connector *connector)
2111 struct edid *override = NULL;
2113 if (connector->override_edid)
2114 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
2117 override = drm_load_edid_firmware(connector);
2119 return IS_ERR(override) ? NULL : override;
2123 * drm_add_override_edid_modes - add modes from override/firmware EDID
2124 * @connector: connector we're probing
2126 * Add modes from the override/firmware EDID, if available. Only to be used from
2127 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2128 * failed during drm_get_edid() and caused the override/firmware EDID to be
2131 * Return: The number of modes added or 0 if we couldn't find any.
2133 int drm_add_override_edid_modes(struct drm_connector *connector)
2135 struct edid *override;
2138 override = drm_get_override_edid(connector);
2140 drm_connector_update_edid_property(connector, override);
2141 num_modes = drm_add_edid_modes(connector, override);
2144 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2145 connector->base.id, connector->name, num_modes);
2150 EXPORT_SYMBOL(drm_add_override_edid_modes);
2152 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2154 static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2155 read_block_fn read_block,
2158 enum edid_block_status status;
2159 bool is_base_block = block_num == 0;
2162 for (try = 0; try < 4; try++) {
2163 if (read_block(context, block, block_num, EDID_LENGTH))
2164 return EDID_BLOCK_READ_FAIL;
2166 status = edid_block_check(block, is_base_block);
2167 if (status == EDID_BLOCK_HEADER_REPAIR) {
2168 edid_header_fix(block);
2170 /* Retry with fixed header, update status if that worked. */
2171 status = edid_block_check(block, is_base_block);
2172 if (status == EDID_BLOCK_OK)
2173 status = EDID_BLOCK_HEADER_FIXED;
2176 if (edid_block_status_valid(status, edid_block_tag(block)))
2179 /* Fail early for unrepairable base block all zeros. */
2180 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2188 * drm_do_get_edid - get EDID data using a custom EDID block read function
2189 * @connector: connector we're probing
2190 * @read_block: EDID block read function
2191 * @context: private data passed to the block read function
2193 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2194 * exposes a different interface to read EDID blocks this function can be used
2195 * to get EDID data using a custom block read function.
2197 * As in the general case the DDC bus is accessible by the kernel at the I2C
2198 * level, drivers must make all reasonable efforts to expose it as an I2C
2199 * adapter and use drm_get_edid() instead of abusing this function.
2201 * The EDID may be overridden using debugfs override_edid or firmware EDID
2202 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
2203 * order. Having either of them bypasses actual EDID reads.
2205 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2207 struct edid *drm_do_get_edid(struct drm_connector *connector,
2208 read_block_fn read_block,
2211 enum edid_block_status status;
2212 int i, invalid_blocks = 0;
2213 struct edid *edid, *new;
2215 edid = drm_get_override_edid(connector);
2219 edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
2223 status = edid_block_read(edid, 0, read_block, context);
2225 edid_block_status_print(status, edid, 0);
2227 if (status == EDID_BLOCK_READ_FAIL)
2230 /* FIXME: Clarify what a corrupt EDID actually means. */
2231 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2232 connector->edid_corrupt = false;
2234 connector->edid_corrupt = true;
2236 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2237 if (status == EDID_BLOCK_ZERO)
2238 connector->null_edid_counter++;
2240 connector_bad_edid(connector, edid, 1);
2244 if (!edid_extension_block_count(edid))
2247 new = krealloc(edid, edid_size(edid), GFP_KERNEL);
2252 for (i = 1; i < edid_block_count(edid); i++) {
2253 void *block = (void *)edid_block_data(edid, i);
2255 status = edid_block_read(block, i, read_block, context);
2257 edid_block_status_print(status, block, i);
2259 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2260 if (status == EDID_BLOCK_READ_FAIL)
2266 if (invalid_blocks) {
2267 connector_bad_edid(connector, edid, edid_block_count(edid));
2269 edid = edid_filter_invalid_blocks(edid, invalid_blocks);
2279 EXPORT_SYMBOL_GPL(drm_do_get_edid);
2282 * drm_probe_ddc() - probe DDC presence
2283 * @adapter: I2C adapter to probe
2285 * Return: True on success, false on failure.
2288 drm_probe_ddc(struct i2c_adapter *adapter)
2292 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2294 EXPORT_SYMBOL(drm_probe_ddc);
2297 * drm_get_edid - get EDID data, if available
2298 * @connector: connector we're probing
2299 * @adapter: I2C adapter to use for DDC
2301 * Poke the given I2C channel to grab EDID data if possible. If found,
2302 * attach it to the connector.
2304 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2306 struct edid *drm_get_edid(struct drm_connector *connector,
2307 struct i2c_adapter *adapter)
2311 if (connector->force == DRM_FORCE_OFF)
2314 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2317 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
2318 drm_connector_update_edid_property(connector, edid);
2321 EXPORT_SYMBOL(drm_get_edid);
2323 static u32 edid_extract_panel_id(const struct edid *edid)
2326 * We represent the ID as a 32-bit number so it can easily be compared
2329 * NOTE that we deal with endianness differently for the top half
2330 * of this ID than for the bottom half. The bottom half (the product
2331 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2332 * that's how everyone seems to interpret it. The top half (the mfg_id)
2333 * gets stored as big endian because that makes
2334 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2335 * to write (it's easier to extract the ASCII). It doesn't really
2336 * matter, though, as long as the number here is unique.
2338 return (u32)edid->mfg_id[0] << 24 |
2339 (u32)edid->mfg_id[1] << 16 |
2340 (u32)EDID_PRODUCT_ID(edid);
2344 * drm_edid_get_panel_id - Get a panel's ID through DDC
2345 * @adapter: I2C adapter to use for DDC
2347 * This function reads the first block of the EDID of a panel and (assuming
2348 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2349 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2350 * supposed to be different for each different modem of panel.
2352 * This function is intended to be used during early probing on devices where
2353 * more than one panel might be present. Because of its intended use it must
2354 * assume that the EDID of the panel is correct, at least as far as the ID
2355 * is concerned (in other words, we don't process any overrides here).
2357 * NOTE: it's expected that this function and drm_do_get_edid() will both
2358 * be read the EDID, but there is no caching between them. Since we're only
2359 * reading the first block, hopefully this extra overhead won't be too big.
2361 * Return: A 32-bit ID that should be different for each make/model of panel.
2362 * See the functions drm_edid_encode_panel_id() and
2363 * drm_edid_decode_panel_id() for some details on the structure of this
2367 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2369 enum edid_block_status status;
2374 * There are no manufacturer IDs of 0, so if there is a problem reading
2375 * the EDID then we'll just return 0.
2378 base_block = kmalloc(EDID_LENGTH, GFP_KERNEL);
2382 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2384 edid_block_status_print(status, base_block, 0);
2386 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2387 panel_id = edid_extract_panel_id(base_block);
2393 EXPORT_SYMBOL(drm_edid_get_panel_id);
2396 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2397 * @connector: connector we're probing
2398 * @adapter: I2C adapter to use for DDC
2400 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2401 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2402 * switch DDC to the GPU which is retrieving EDID.
2404 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2406 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2407 struct i2c_adapter *adapter)
2409 struct drm_device *dev = connector->dev;
2410 struct pci_dev *pdev = to_pci_dev(dev->dev);
2413 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2416 vga_switcheroo_lock_ddc(pdev);
2417 edid = drm_get_edid(connector, adapter);
2418 vga_switcheroo_unlock_ddc(pdev);
2422 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2425 * drm_edid_duplicate - duplicate an EDID and the extensions
2426 * @edid: EDID to duplicate
2428 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2430 struct edid *drm_edid_duplicate(const struct edid *edid)
2432 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2434 EXPORT_SYMBOL(drm_edid_duplicate);
2436 /*** EDID parsing ***/
2439 * edid_get_quirks - return quirk flags for a given EDID
2440 * @drm_edid: EDID to process
2442 * This tells subsequent routines what fixes they need to apply.
2444 static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2446 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
2447 const struct edid_quirk *quirk;
2450 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2451 quirk = &edid_quirk_list[i];
2452 if (quirk->panel_id == panel_id)
2453 return quirk->quirks;
2459 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2460 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2463 * Walk the mode list for connector, clearing the preferred status on existing
2464 * modes and setting it anew for the right mode ala quirks.
2466 static void edid_fixup_preferred(struct drm_connector *connector,
2469 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2470 int target_refresh = 0;
2471 int cur_vrefresh, preferred_vrefresh;
2473 if (list_empty(&connector->probed_modes))
2476 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2477 target_refresh = 60;
2478 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2479 target_refresh = 75;
2481 preferred_mode = list_first_entry(&connector->probed_modes,
2482 struct drm_display_mode, head);
2484 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2485 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2487 if (cur_mode == preferred_mode)
2490 /* Largest mode is preferred */
2491 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2492 preferred_mode = cur_mode;
2494 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2495 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2496 /* At a given size, try to get closest to target refresh */
2497 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2498 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2499 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2500 preferred_mode = cur_mode;
2504 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2508 mode_is_rb(const struct drm_display_mode *mode)
2510 return (mode->htotal - mode->hdisplay == 160) &&
2511 (mode->hsync_end - mode->hdisplay == 80) &&
2512 (mode->hsync_end - mode->hsync_start == 32) &&
2513 (mode->vsync_start - mode->vdisplay == 3);
2517 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2518 * @dev: Device to duplicate against
2519 * @hsize: Mode width
2520 * @vsize: Mode height
2521 * @fresh: Mode refresh rate
2522 * @rb: Mode reduced-blanking-ness
2524 * Walk the DMT mode list looking for a match for the given parameters.
2526 * Return: A newly allocated copy of the mode, or NULL if not found.
2528 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2529 int hsize, int vsize, int fresh,
2534 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2535 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2537 if (hsize != ptr->hdisplay)
2539 if (vsize != ptr->vdisplay)
2541 if (fresh != drm_mode_vrefresh(ptr))
2543 if (rb != mode_is_rb(ptr))
2546 return drm_mode_duplicate(dev, ptr);
2551 EXPORT_SYMBOL(drm_mode_find_dmt);
2553 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
2555 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2556 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
2557 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
2559 return descriptor->pixel_clock == 0 &&
2560 descriptor->data.other_data.pad1 == 0 &&
2561 descriptor->data.other_data.type == type;
2564 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
2566 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
2568 return descriptor->pixel_clock != 0;
2571 typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
2574 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
2578 const u8 *det_base = ext + d;
2580 if (d < 4 || d > 127)
2584 for (i = 0; i < n; i++)
2585 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
2589 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
2591 unsigned int i, n = min((int)ext[0x02], 6);
2592 const u8 *det_base = ext + 5;
2595 return; /* unknown version */
2597 for (i = 0; i < n; i++)
2598 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
2602 drm_for_each_detailed_block(const struct edid *edid, detailed_cb *cb, void *closure)
2604 struct drm_edid_iter edid_iter;
2611 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2612 cb(&(edid->detailed_timings[i]), closure);
2614 drm_edid_iter_begin(edid, &edid_iter);
2615 drm_edid_iter_for_each(ext, &edid_iter) {
2618 cea_for_each_detailed_block(ext, cb, closure);
2621 vtb_for_each_detailed_block(ext, cb, closure);
2627 drm_edid_iter_end(&edid_iter);
2631 is_rb(const struct detailed_timing *descriptor, void *data)
2635 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
2638 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
2639 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
2641 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
2642 descriptor->data.other_data.data.range.formula.cvt.flags & 0x10)
2646 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2648 drm_monitor_supports_rb(const struct edid *edid)
2650 if (edid->revision >= 4) {
2653 drm_for_each_detailed_block(edid, is_rb, &ret);
2657 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2661 find_gtf2(const struct detailed_timing *descriptor, void *data)
2663 const struct detailed_timing **res = data;
2665 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
2668 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
2670 if (descriptor->data.other_data.data.range.flags == 0x02)
2674 /* Secondary GTF curve kicks in above some break frequency */
2676 drm_gtf2_hbreak(const struct edid *edid)
2678 const struct detailed_timing *descriptor = NULL;
2680 drm_for_each_detailed_block(edid, find_gtf2, &descriptor);
2682 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
2684 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
2688 drm_gtf2_2c(const struct edid *edid)
2690 const struct detailed_timing *descriptor = NULL;
2692 drm_for_each_detailed_block(edid, find_gtf2, &descriptor);
2694 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
2696 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
2700 drm_gtf2_m(const struct edid *edid)
2702 const struct detailed_timing *descriptor = NULL;
2704 drm_for_each_detailed_block(edid, find_gtf2, &descriptor);
2706 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
2708 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
2712 drm_gtf2_k(const struct edid *edid)
2714 const struct detailed_timing *descriptor = NULL;
2716 drm_for_each_detailed_block(edid, find_gtf2, &descriptor);
2718 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
2720 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
2724 drm_gtf2_2j(const struct edid *edid)
2726 const struct detailed_timing *descriptor = NULL;
2728 drm_for_each_detailed_block(edid, find_gtf2, &descriptor);
2730 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
2732 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
2735 /* Get standard timing level (CVT/GTF/DMT). */
2736 static int standard_timing_level(const struct edid *edid)
2738 if (edid->revision >= 2) {
2739 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2741 if (drm_gtf2_hbreak(edid))
2743 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
2750 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2751 * monitors fill with ascii space (0x20) instead.
2754 bad_std_timing(u8 a, u8 b)
2756 return (a == 0x00 && b == 0x00) ||
2757 (a == 0x01 && b == 0x01) ||
2758 (a == 0x20 && b == 0x20);
2761 static int drm_mode_hsync(const struct drm_display_mode *mode)
2763 if (mode->htotal <= 0)
2766 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
2770 * Take the standard timing params (in this case width, aspect, and refresh)
2771 * and convert them into a real mode using CVT/GTF/DMT.
2773 static struct drm_display_mode *
2774 drm_mode_std(struct drm_connector *connector, const struct edid *edid,
2775 const struct std_timing *t)
2777 struct drm_device *dev = connector->dev;
2778 struct drm_display_mode *m, *mode = NULL;
2781 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2782 >> EDID_TIMING_ASPECT_SHIFT;
2783 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2784 >> EDID_TIMING_VFREQ_SHIFT;
2785 int timing_level = standard_timing_level(edid);
2787 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2790 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2791 hsize = t->hsize * 8 + 248;
2792 /* vrefresh_rate = vfreq + 60 */
2793 vrefresh_rate = vfreq + 60;
2794 /* the vdisplay is calculated based on the aspect ratio */
2795 if (aspect_ratio == 0) {
2796 if (edid->revision < 3)
2799 vsize = (hsize * 10) / 16;
2800 } else if (aspect_ratio == 1)
2801 vsize = (hsize * 3) / 4;
2802 else if (aspect_ratio == 2)
2803 vsize = (hsize * 4) / 5;
2805 vsize = (hsize * 9) / 16;
2807 /* HDTV hack, part 1 */
2808 if (vrefresh_rate == 60 &&
2809 ((hsize == 1360 && vsize == 765) ||
2810 (hsize == 1368 && vsize == 769))) {
2816 * If this connector already has a mode for this size and refresh
2817 * rate (because it came from detailed or CVT info), use that
2818 * instead. This way we don't have to guess at interlace or
2821 list_for_each_entry(m, &connector->probed_modes, head)
2822 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2823 drm_mode_vrefresh(m) == vrefresh_rate)
2826 /* HDTV hack, part 2 */
2827 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2828 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2832 mode->hdisplay = 1366;
2833 mode->hsync_start = mode->hsync_start - 1;
2834 mode->hsync_end = mode->hsync_end - 1;
2838 /* check whether it can be found in default mode table */
2839 if (drm_monitor_supports_rb(edid)) {
2840 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2845 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2849 /* okay, generate it */
2850 switch (timing_level) {
2854 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2858 * This is potentially wrong if there's ever a monitor with
2859 * more than one ranges section, each claiming a different
2860 * secondary GTF curve. Please don't do that.
2862 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2865 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2866 drm_mode_destroy(dev, mode);
2867 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2868 vrefresh_rate, 0, 0,
2876 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2884 * EDID is delightfully ambiguous about how interlaced modes are to be
2885 * encoded. Our internal representation is of frame height, but some
2886 * HDTV detailed timings are encoded as field height.
2888 * The format list here is from CEA, in frame size. Technically we
2889 * should be checking refresh rate too. Whatever.
2892 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2893 const struct detailed_pixel_timing *pt)
2896 static const struct {
2898 } cea_interlaced[] = {
2908 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2911 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2912 if ((mode->hdisplay == cea_interlaced[i].w) &&
2913 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2914 mode->vdisplay *= 2;
2915 mode->vsync_start *= 2;
2916 mode->vsync_end *= 2;
2922 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2926 * Create a new mode from an EDID detailed timing section. An EDID detailed
2927 * timing block contains enough info for us to create and return a new struct
2930 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2931 const struct edid *edid,
2932 const struct detailed_timing *timing,
2935 struct drm_display_mode *mode;
2936 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2937 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2938 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2939 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2940 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2941 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2942 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2943 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2944 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2946 /* ignore tiny modes */
2947 if (hactive < 64 || vactive < 64)
2950 if (pt->misc & DRM_EDID_PT_STEREO) {
2951 DRM_DEBUG_KMS("stereo mode not supported\n");
2954 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2955 DRM_DEBUG_KMS("composite sync not supported\n");
2958 /* it is incorrect if hsync/vsync width is zero */
2959 if (!hsync_pulse_width || !vsync_pulse_width) {
2960 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2961 "Wrong Hsync/Vsync pulse width\n");
2965 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2966 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2973 mode = drm_mode_create(dev);
2977 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2978 mode->clock = 1088 * 10;
2980 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2982 mode->hdisplay = hactive;
2983 mode->hsync_start = mode->hdisplay + hsync_offset;
2984 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2985 mode->htotal = mode->hdisplay + hblank;
2987 mode->vdisplay = vactive;
2988 mode->vsync_start = mode->vdisplay + vsync_offset;
2989 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2990 mode->vtotal = mode->vdisplay + vblank;
2992 /* Some EDIDs have bogus h/vtotal values */
2993 if (mode->hsync_end > mode->htotal)
2994 mode->htotal = mode->hsync_end + 1;
2995 if (mode->vsync_end > mode->vtotal)
2996 mode->vtotal = mode->vsync_end + 1;
2998 drm_mode_do_interlace_quirk(mode, pt);
3000 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
3001 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3003 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3004 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3005 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3006 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3010 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3011 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3013 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
3014 mode->width_mm *= 10;
3015 mode->height_mm *= 10;
3018 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
3019 mode->width_mm = edid->width_cm * 10;
3020 mode->height_mm = edid->height_cm * 10;
3023 mode->type = DRM_MODE_TYPE_DRIVER;
3024 drm_mode_set_name(mode);
3030 mode_in_hsync_range(const struct drm_display_mode *mode,
3031 const struct edid *edid, const u8 *t)
3033 int hsync, hmin, hmax;
3036 if (edid->revision >= 4)
3037 hmin += ((t[4] & 0x04) ? 255 : 0);
3039 if (edid->revision >= 4)
3040 hmax += ((t[4] & 0x08) ? 255 : 0);
3041 hsync = drm_mode_hsync(mode);
3043 return (hsync <= hmax && hsync >= hmin);
3047 mode_in_vsync_range(const struct drm_display_mode *mode,
3048 const struct edid *edid, const u8 *t)
3050 int vsync, vmin, vmax;
3053 if (edid->revision >= 4)
3054 vmin += ((t[4] & 0x01) ? 255 : 0);
3056 if (edid->revision >= 4)
3057 vmax += ((t[4] & 0x02) ? 255 : 0);
3058 vsync = drm_mode_vrefresh(mode);
3060 return (vsync <= vmax && vsync >= vmin);
3064 range_pixel_clock(const struct edid *edid, const u8 *t)
3067 if (t[9] == 0 || t[9] == 255)
3070 /* 1.4 with CVT support gives us real precision, yay */
3071 if (edid->revision >= 4 && t[10] == 0x04)
3072 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3074 /* 1.3 is pathetic, so fuzz up a bit */
3075 return t[9] * 10000 + 5001;
3079 mode_in_range(const struct drm_display_mode *mode, const struct edid *edid,
3080 const struct detailed_timing *timing)
3083 const u8 *t = (const u8 *)timing;
3085 if (!mode_in_hsync_range(mode, edid, t))
3088 if (!mode_in_vsync_range(mode, edid, t))
3091 if ((max_clock = range_pixel_clock(edid, t)))
3092 if (mode->clock > max_clock)
3095 /* 1.4 max horizontal check */
3096 if (edid->revision >= 4 && t[10] == 0x04)
3097 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3100 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
3106 static bool valid_inferred_mode(const struct drm_connector *connector,
3107 const struct drm_display_mode *mode)
3109 const struct drm_display_mode *m;
3112 list_for_each_entry(m, &connector->probed_modes, head) {
3113 if (mode->hdisplay == m->hdisplay &&
3114 mode->vdisplay == m->vdisplay &&
3115 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3116 return false; /* duplicated */
3117 if (mode->hdisplay <= m->hdisplay &&
3118 mode->vdisplay <= m->vdisplay)
3125 drm_dmt_modes_for_range(struct drm_connector *connector, const struct edid *edid,
3126 const struct detailed_timing *timing)
3129 struct drm_display_mode *newmode;
3130 struct drm_device *dev = connector->dev;
3132 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3133 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
3134 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3135 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3137 drm_mode_probed_add(connector, newmode);
3146 /* fix up 1366x768 mode from 1368x768;
3147 * GFT/CVT can't express 1366 width which isn't dividable by 8
3149 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3151 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3152 mode->hdisplay = 1366;
3153 mode->hsync_start--;
3155 drm_mode_set_name(mode);
3160 drm_gtf_modes_for_range(struct drm_connector *connector, const struct edid *edid,
3161 const struct detailed_timing *timing)
3164 struct drm_display_mode *newmode;
3165 struct drm_device *dev = connector->dev;
3167 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3168 const struct minimode *m = &extra_modes[i];
3170 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3174 drm_mode_fixup_1366x768(newmode);
3175 if (!mode_in_range(newmode, edid, timing) ||
3176 !valid_inferred_mode(connector, newmode)) {
3177 drm_mode_destroy(dev, newmode);
3181 drm_mode_probed_add(connector, newmode);
3189 drm_cvt_modes_for_range(struct drm_connector *connector, const struct edid *edid,
3190 const struct detailed_timing *timing)
3193 struct drm_display_mode *newmode;
3194 struct drm_device *dev = connector->dev;
3195 bool rb = drm_monitor_supports_rb(edid);
3197 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3198 const struct minimode *m = &extra_modes[i];
3200 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3204 drm_mode_fixup_1366x768(newmode);
3205 if (!mode_in_range(newmode, edid, timing) ||
3206 !valid_inferred_mode(connector, newmode)) {
3207 drm_mode_destroy(dev, newmode);
3211 drm_mode_probed_add(connector, newmode);
3219 do_inferred_modes(const struct detailed_timing *timing, void *c)
3221 struct detailed_mode_closure *closure = c;
3222 const struct detailed_non_pixel *data = &timing->data.other_data;
3223 const struct detailed_data_monitor_range *range = &data->data.range;
3225 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3228 closure->modes += drm_dmt_modes_for_range(closure->connector,
3229 closure->drm_edid->edid,
3232 if (!version_greater(closure->drm_edid->edid, 1, 1))
3233 return; /* GTF not defined yet */
3235 switch (range->flags) {
3236 case 0x02: /* secondary gtf, XXX could do more */
3237 case 0x00: /* default gtf */
3238 closure->modes += drm_gtf_modes_for_range(closure->connector,
3239 closure->drm_edid->edid,
3242 case 0x04: /* cvt, only in 1.4+ */
3243 if (!version_greater(closure->drm_edid->edid, 1, 3))
3246 closure->modes += drm_cvt_modes_for_range(closure->connector,
3247 closure->drm_edid->edid,
3250 case 0x01: /* just the ranges, no formula */
3256 static int add_inferred_modes(struct drm_connector *connector,
3257 const struct drm_edid *drm_edid)
3259 struct detailed_mode_closure closure = {
3260 .connector = connector,
3261 .drm_edid = drm_edid,
3264 if (version_greater(drm_edid->edid, 1, 0))
3265 drm_for_each_detailed_block(drm_edid->edid, do_inferred_modes, &closure);
3267 return closure.modes;
3271 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3273 int i, j, m, modes = 0;
3274 struct drm_display_mode *mode;
3275 const u8 *est = ((const u8 *)timing) + 6;
3277 for (i = 0; i < 6; i++) {
3278 for (j = 7; j >= 0; j--) {
3279 m = (i * 8) + (7 - j);
3280 if (m >= ARRAY_SIZE(est3_modes))
3282 if (est[i] & (1 << j)) {
3283 mode = drm_mode_find_dmt(connector->dev,
3289 drm_mode_probed_add(connector, mode);
3300 do_established_modes(const struct detailed_timing *timing, void *c)
3302 struct detailed_mode_closure *closure = c;
3304 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3307 closure->modes += drm_est3_modes(closure->connector, timing);
3311 * Get established modes from EDID and add them. Each EDID block contains a
3312 * bitmap of the supported "established modes" list (defined above). Tease them
3313 * out and add them to the global modes list.
3315 static int add_established_modes(struct drm_connector *connector,
3316 const struct drm_edid *drm_edid)
3318 struct drm_device *dev = connector->dev;
3319 const struct edid *edid = drm_edid->edid;
3320 unsigned long est_bits = edid->established_timings.t1 |
3321 (edid->established_timings.t2 << 8) |
3322 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3324 struct detailed_mode_closure closure = {
3325 .connector = connector,
3326 .drm_edid = drm_edid,
3329 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3330 if (est_bits & (1<<i)) {
3331 struct drm_display_mode *newmode;
3333 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3335 drm_mode_probed_add(connector, newmode);
3341 if (version_greater(edid, 1, 0))
3342 drm_for_each_detailed_block(drm_edid->edid, do_established_modes,
3345 return modes + closure.modes;
3349 do_standard_modes(const struct detailed_timing *timing, void *c)
3351 struct detailed_mode_closure *closure = c;
3352 const struct detailed_non_pixel *data = &timing->data.other_data;
3353 struct drm_connector *connector = closure->connector;
3356 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3359 for (i = 0; i < 6; i++) {
3360 const struct std_timing *std = &data->data.timings[i];
3361 struct drm_display_mode *newmode;
3363 newmode = drm_mode_std(connector, closure->drm_edid->edid, std);
3365 drm_mode_probed_add(connector, newmode);
3372 * Get standard modes from EDID and add them. Standard modes can be calculated
3373 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3374 * add them to the list.
3376 static int add_standard_modes(struct drm_connector *connector,
3377 const struct drm_edid *drm_edid)
3380 struct detailed_mode_closure closure = {
3381 .connector = connector,
3382 .drm_edid = drm_edid,
3385 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3386 struct drm_display_mode *newmode;
3388 newmode = drm_mode_std(connector, drm_edid->edid,
3389 &drm_edid->edid->standard_timings[i]);
3391 drm_mode_probed_add(connector, newmode);
3396 if (version_greater(drm_edid->edid, 1, 0))
3397 drm_for_each_detailed_block(drm_edid->edid, do_standard_modes,
3400 /* XXX should also look for standard codes in VTB blocks */
3402 return modes + closure.modes;
3405 static int drm_cvt_modes(struct drm_connector *connector,
3406 const struct detailed_timing *timing)
3408 int i, j, modes = 0;
3409 struct drm_display_mode *newmode;
3410 struct drm_device *dev = connector->dev;
3411 const struct cvt_timing *cvt;
3412 const int rates[] = { 60, 85, 75, 60, 50 };
3413 const u8 empty[3] = { 0, 0, 0 };
3415 for (i = 0; i < 4; i++) {
3418 cvt = &(timing->data.other_data.data.cvt[i]);
3420 if (!memcmp(cvt->code, empty, 3))
3423 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3424 switch (cvt->code[1] & 0x0c) {
3425 /* default - because compiler doesn't see that we've enumerated all cases */
3428 width = height * 4 / 3;
3431 width = height * 16 / 9;
3434 width = height * 16 / 10;
3437 width = height * 15 / 9;
3441 for (j = 1; j < 5; j++) {
3442 if (cvt->code[2] & (1 << j)) {
3443 newmode = drm_cvt_mode(dev, width, height,
3447 drm_mode_probed_add(connector, newmode);
3458 do_cvt_mode(const struct detailed_timing *timing, void *c)
3460 struct detailed_mode_closure *closure = c;
3462 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
3465 closure->modes += drm_cvt_modes(closure->connector, timing);
3469 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
3471 struct detailed_mode_closure closure = {
3472 .connector = connector,
3473 .drm_edid = drm_edid,
3476 if (version_greater(drm_edid->edid, 1, 2))
3477 drm_for_each_detailed_block(drm_edid->edid, do_cvt_mode, &closure);
3479 /* XXX should also look for CVT codes in VTB blocks */
3481 return closure.modes;
3484 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3487 do_detailed_mode(const struct detailed_timing *timing, void *c)
3489 struct detailed_mode_closure *closure = c;
3490 struct drm_display_mode *newmode;
3492 if (!is_detailed_timing_descriptor(timing))
3495 newmode = drm_mode_detailed(closure->connector->dev,
3496 closure->drm_edid->edid, timing,
3501 if (closure->preferred)
3502 newmode->type |= DRM_MODE_TYPE_PREFERRED;
3505 * Detailed modes are limited to 10kHz pixel clock resolution,
3506 * so fix up anything that looks like CEA/HDMI mode, but the clock
3507 * is just slightly off.
3509 fixup_detailed_cea_mode_clock(newmode);
3511 drm_mode_probed_add(closure->connector, newmode);
3513 closure->preferred = false;
3517 * add_detailed_modes - Add modes from detailed timings
3518 * @connector: attached connector
3519 * @drm_edid: EDID block to scan
3520 * @quirks: quirks to apply
3522 static int add_detailed_modes(struct drm_connector *connector,
3523 const struct drm_edid *drm_edid, u32 quirks)
3525 struct detailed_mode_closure closure = {
3526 .connector = connector,
3527 .drm_edid = drm_edid,
3532 if (closure.preferred && !version_greater(drm_edid->edid, 1, 3))
3534 (drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3536 drm_for_each_detailed_block(drm_edid->edid, do_detailed_mode, &closure);
3538 return closure.modes;
3541 /* CTA-861-H Table 60 - CTA Tag Codes */
3542 #define CTA_DB_AUDIO 1
3543 #define CTA_DB_VIDEO 2
3544 #define CTA_DB_VENDOR 3
3545 #define CTA_DB_SPEAKER 4
3546 #define CTA_DB_EXTENDED_TAG 7
3548 /* CTA-861-H Table 62 - CTA Extended Tag Codes */
3549 #define CTA_EXT_DB_VIDEO_CAP 0
3550 #define CTA_EXT_DB_VENDOR 1
3551 #define CTA_EXT_DB_HDR_STATIC_METADATA 6
3552 #define CTA_EXT_DB_420_VIDEO_DATA 14
3553 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
3554 #define CTA_EXT_DB_HF_SCDB 0x79
3556 #define EDID_BASIC_AUDIO (1 << 6)
3557 #define EDID_CEA_YCRCB444 (1 << 5)
3558 #define EDID_CEA_YCRCB422 (1 << 4)
3559 #define EDID_CEA_VCDB_QS (1 << 6)
3562 * Search EDID for CEA extension block.
3564 const u8 *drm_find_edid_extension(const struct edid *edid,
3565 int ext_id, int *ext_index)
3567 const u8 *edid_ext = NULL;
3570 /* No EDID or EDID extensions */
3571 if (!edid || !edid_extension_block_count(edid))
3574 /* Find CEA extension */
3575 for (i = *ext_index; i < edid_extension_block_count(edid); i++) {
3576 edid_ext = edid_extension_block_data(edid, i);
3577 if (edid_block_tag(edid_ext) == ext_id)
3581 if (i >= edid_extension_block_count(edid))
3589 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
3590 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
3592 const struct displayid_block *block;
3593 struct displayid_iter iter;
3597 /* Look for a top level CEA extension block */
3598 if (drm_find_edid_extension(drm_edid->edid, CEA_EXT, &ext_index))
3601 /* CEA blocks can also be found embedded in a DisplayID block */
3602 displayid_iter_edid_begin(drm_edid->edid, &iter);
3603 displayid_iter_for_each(block, &iter) {
3604 if (block->tag == DATA_BLOCK_CTA) {
3609 displayid_iter_end(&iter);
3614 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
3616 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3617 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3619 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3620 return &edid_cea_modes_1[vic - 1];
3621 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3622 return &edid_cea_modes_193[vic - 193];
3626 static u8 cea_num_vics(void)
3628 return 193 + ARRAY_SIZE(edid_cea_modes_193);
3631 static u8 cea_next_vic(u8 vic)
3633 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
3639 * Calculate the alternate clock for the CEA mode
3640 * (60Hz vs. 59.94Hz etc.)
3643 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3645 unsigned int clock = cea_mode->clock;
3647 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
3651 * edid_cea_modes contains the 59.94Hz
3652 * variant for 240 and 480 line modes,
3653 * and the 60Hz variant otherwise.
3655 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
3656 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
3658 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
3664 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3667 * For certain VICs the spec allows the vertical
3668 * front porch to vary by one or two lines.
3670 * cea_modes[] stores the variant with the shortest
3671 * vertical front porch. We can adjust the mode to
3672 * get the other variants by simply increasing the
3673 * vertical front porch length.
3675 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3676 cea_mode_for_vic(9)->vtotal != 262 ||
3677 cea_mode_for_vic(12)->vtotal != 262 ||
3678 cea_mode_for_vic(13)->vtotal != 262 ||
3679 cea_mode_for_vic(23)->vtotal != 312 ||
3680 cea_mode_for_vic(24)->vtotal != 312 ||
3681 cea_mode_for_vic(27)->vtotal != 312 ||
3682 cea_mode_for_vic(28)->vtotal != 312);
3684 if (((vic == 8 || vic == 9 ||
3685 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3686 ((vic == 23 || vic == 24 ||
3687 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3688 mode->vsync_start++;
3698 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3699 unsigned int clock_tolerance)
3701 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3704 if (!to_match->clock)
3707 if (to_match->picture_aspect_ratio)
3708 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3710 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3711 struct drm_display_mode cea_mode;
3712 unsigned int clock1, clock2;
3714 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
3716 /* Check both 60Hz and 59.94Hz */
3717 clock1 = cea_mode.clock;
3718 clock2 = cea_mode_alternate_clock(&cea_mode);
3720 if (abs(to_match->clock - clock1) > clock_tolerance &&
3721 abs(to_match->clock - clock2) > clock_tolerance)
3725 if (drm_mode_match(to_match, &cea_mode, match_flags))
3727 } while (cea_mode_alternate_timings(vic, &cea_mode));
3734 * drm_match_cea_mode - look for a CEA mode matching given mode
3735 * @to_match: display mode
3737 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
3740 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
3742 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3745 if (!to_match->clock)
3748 if (to_match->picture_aspect_ratio)
3749 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3751 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3752 struct drm_display_mode cea_mode;
3753 unsigned int clock1, clock2;
3755 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
3757 /* Check both 60Hz and 59.94Hz */
3758 clock1 = cea_mode.clock;
3759 clock2 = cea_mode_alternate_clock(&cea_mode);
3761 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3762 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3766 if (drm_mode_match(to_match, &cea_mode, match_flags))
3768 } while (cea_mode_alternate_timings(vic, &cea_mode));
3773 EXPORT_SYMBOL(drm_match_cea_mode);
3775 static bool drm_valid_cea_vic(u8 vic)
3777 return cea_mode_for_vic(vic) != NULL;
3780 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3782 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
3785 return mode->picture_aspect_ratio;
3787 return HDMI_PICTURE_ASPECT_NONE;
3790 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
3792 return edid_4k_modes[video_code].picture_aspect_ratio;
3796 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3800 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3802 return cea_mode_alternate_clock(hdmi_mode);
3805 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3806 unsigned int clock_tolerance)
3808 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3811 if (!to_match->clock)
3814 if (to_match->picture_aspect_ratio)
3815 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3817 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3818 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3819 unsigned int clock1, clock2;
3821 /* Make sure to also match alternate clocks */
3822 clock1 = hdmi_mode->clock;
3823 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3825 if (abs(to_match->clock - clock1) > clock_tolerance &&
3826 abs(to_match->clock - clock2) > clock_tolerance)
3829 if (drm_mode_match(to_match, hdmi_mode, match_flags))
3837 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3838 * @to_match: display mode
3840 * An HDMI mode is one defined in the HDMI vendor specific block.
3842 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3844 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3846 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3849 if (!to_match->clock)
3852 if (to_match->picture_aspect_ratio)
3853 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3855 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3856 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3857 unsigned int clock1, clock2;
3859 /* Make sure to also match alternate clocks */
3860 clock1 = hdmi_mode->clock;
3861 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3863 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3864 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3865 drm_mode_match(to_match, hdmi_mode, match_flags))
3871 static bool drm_valid_hdmi_vic(u8 vic)
3873 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3876 static int add_alternate_cea_modes(struct drm_connector *connector,
3877 const struct drm_edid *drm_edid)
3879 struct drm_device *dev = connector->dev;
3880 struct drm_display_mode *mode, *tmp;
3884 /* Don't add CTA modes if the CTA extension block is missing */
3885 if (!drm_edid_has_cta_extension(drm_edid))
3889 * Go through all probed modes and create a new mode
3890 * with the alternate clock for certain CEA modes.
3892 list_for_each_entry(mode, &connector->probed_modes, head) {
3893 const struct drm_display_mode *cea_mode = NULL;
3894 struct drm_display_mode *newmode;
3895 u8 vic = drm_match_cea_mode(mode);
3896 unsigned int clock1, clock2;
3898 if (drm_valid_cea_vic(vic)) {
3899 cea_mode = cea_mode_for_vic(vic);
3900 clock2 = cea_mode_alternate_clock(cea_mode);
3902 vic = drm_match_hdmi_mode(mode);
3903 if (drm_valid_hdmi_vic(vic)) {
3904 cea_mode = &edid_4k_modes[vic];
3905 clock2 = hdmi_mode_alternate_clock(cea_mode);
3912 clock1 = cea_mode->clock;
3914 if (clock1 == clock2)
3917 if (mode->clock != clock1 && mode->clock != clock2)
3920 newmode = drm_mode_duplicate(dev, cea_mode);
3924 /* Carry over the stereo flags */
3925 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3928 * The current mode could be either variant. Make
3929 * sure to pick the "other" clock for the new mode.
3931 if (mode->clock != clock1)
3932 newmode->clock = clock1;
3934 newmode->clock = clock2;
3936 list_add_tail(&newmode->head, &list);
3939 list_for_each_entry_safe(mode, tmp, &list, head) {
3940 list_del(&mode->head);
3941 drm_mode_probed_add(connector, mode);
3948 static u8 svd_to_vic(u8 svd)
3950 /* 0-6 bit vic, 7th bit native mode indicator */
3951 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3957 static struct drm_display_mode *
3958 drm_display_mode_from_vic_index(struct drm_connector *connector,
3959 const u8 *video_db, u8 video_len,
3962 struct drm_device *dev = connector->dev;
3963 struct drm_display_mode *newmode;
3966 if (video_db == NULL || video_index >= video_len)
3969 /* CEA modes are numbered 1..127 */
3970 vic = svd_to_vic(video_db[video_index]);
3971 if (!drm_valid_cea_vic(vic))
3974 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3982 * do_y420vdb_modes - Parse YCBCR 420 only modes
3983 * @connector: connector corresponding to the HDMI sink
3984 * @svds: start of the data block of CEA YCBCR 420 VDB
3985 * @len: length of the CEA YCBCR 420 VDB
3987 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3988 * which contains modes which can be supported in YCBCR 420
3989 * output format only.
3991 static int do_y420vdb_modes(struct drm_connector *connector,
3992 const u8 *svds, u8 svds_len)
3995 struct drm_device *dev = connector->dev;
3996 struct drm_display_info *info = &connector->display_info;
3997 struct drm_hdmi_info *hdmi = &info->hdmi;
3999 for (i = 0; i < svds_len; i++) {
4000 u8 vic = svd_to_vic(svds[i]);
4001 struct drm_display_mode *newmode;
4003 if (!drm_valid_cea_vic(vic))
4006 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4009 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
4010 drm_mode_probed_add(connector, newmode);
4015 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
4020 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
4021 * @connector: connector corresponding to the HDMI sink
4022 * @vic: CEA vic for the video mode to be added in the map
4024 * Makes an entry for a videomode in the YCBCR 420 bitmap
4027 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
4029 u8 vic = svd_to_vic(svd);
4030 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4032 if (!drm_valid_cea_vic(vic))
4035 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
4039 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4041 * @video_code: CEA VIC of the mode
4043 * Creates a new mode matching the specified CEA VIC.
4045 * Returns: A new drm_display_mode on success or NULL on failure
4047 struct drm_display_mode *
4048 drm_display_mode_from_cea_vic(struct drm_device *dev,
4051 const struct drm_display_mode *cea_mode;
4052 struct drm_display_mode *newmode;
4054 cea_mode = cea_mode_for_vic(video_code);
4058 newmode = drm_mode_duplicate(dev, cea_mode);
4064 EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4067 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
4070 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4072 for (i = 0; i < len; i++) {
4073 struct drm_display_mode *mode;
4075 mode = drm_display_mode_from_vic_index(connector, db, len, i);
4078 * YCBCR420 capability block contains a bitmap which
4079 * gives the index of CEA modes from CEA VDB, which
4080 * can support YCBCR 420 sampling output also (apart
4081 * from RGB/YCBCR444 etc).
4082 * For example, if the bit 0 in bitmap is set,
4083 * first mode in VDB can support YCBCR420 output too.
4084 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
4086 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
4087 drm_add_cmdb_modes(connector, db[i]);
4089 drm_mode_probed_add(connector, mode);
4097 struct stereo_mandatory_mode {
4098 int width, height, vrefresh;
4102 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4103 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4104 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4106 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4108 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4109 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4110 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4111 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4112 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4116 stereo_match_mandatory(const struct drm_display_mode *mode,
4117 const struct stereo_mandatory_mode *stereo_mode)
4119 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4121 return mode->hdisplay == stereo_mode->width &&
4122 mode->vdisplay == stereo_mode->height &&
4123 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4124 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4127 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4129 struct drm_device *dev = connector->dev;
4130 const struct drm_display_mode *mode;
4131 struct list_head stereo_modes;
4134 INIT_LIST_HEAD(&stereo_modes);
4136 list_for_each_entry(mode, &connector->probed_modes, head) {
4137 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4138 const struct stereo_mandatory_mode *mandatory;
4139 struct drm_display_mode *new_mode;
4141 if (!stereo_match_mandatory(mode,
4142 &stereo_mandatory_modes[i]))
4145 mandatory = &stereo_mandatory_modes[i];
4146 new_mode = drm_mode_duplicate(dev, mode);
4150 new_mode->flags |= mandatory->flags;
4151 list_add_tail(&new_mode->head, &stereo_modes);
4156 list_splice_tail(&stereo_modes, &connector->probed_modes);
4161 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4163 struct drm_device *dev = connector->dev;
4164 struct drm_display_mode *newmode;
4166 if (!drm_valid_hdmi_vic(vic)) {
4167 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
4171 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4175 drm_mode_probed_add(connector, newmode);
4180 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4181 const u8 *video_db, u8 video_len, u8 video_index)
4183 struct drm_display_mode *newmode;
4186 if (structure & (1 << 0)) {
4187 newmode = drm_display_mode_from_vic_index(connector, video_db,
4191 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4192 drm_mode_probed_add(connector, newmode);
4196 if (structure & (1 << 6)) {
4197 newmode = drm_display_mode_from_vic_index(connector, video_db,
4201 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4202 drm_mode_probed_add(connector, newmode);
4206 if (structure & (1 << 8)) {
4207 newmode = drm_display_mode_from_vic_index(connector, video_db,
4211 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4212 drm_mode_probed_add(connector, newmode);
4221 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4222 * @connector: connector corresponding to the HDMI sink
4223 * @db: start of the CEA vendor specific block
4224 * @len: length of the CEA block payload, ie. one can access up to db[len]
4226 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4227 * also adds the stereo 3d modes when applicable.
4230 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
4231 const u8 *video_db, u8 video_len)
4233 struct drm_display_info *info = &connector->display_info;
4234 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4235 u8 vic_len, hdmi_3d_len = 0;
4242 /* no HDMI_Video_Present */
4243 if (!(db[8] & (1 << 5)))
4246 /* Latency_Fields_Present */
4247 if (db[8] & (1 << 7))
4250 /* I_Latency_Fields_Present */
4251 if (db[8] & (1 << 6))
4254 /* the declared length is not long enough for the 2 first bytes
4255 * of additional video format capabilities */
4256 if (len < (8 + offset + 2))
4261 if (db[8 + offset] & (1 << 7)) {
4262 modes += add_hdmi_mandatory_stereo_modes(connector);
4264 /* 3D_Multi_present */
4265 multi_present = (db[8 + offset] & 0x60) >> 5;
4269 vic_len = db[8 + offset] >> 5;
4270 hdmi_3d_len = db[8 + offset] & 0x1f;
4272 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4275 vic = db[9 + offset + i];
4276 modes += add_hdmi_mode(connector, vic);
4278 offset += 1 + vic_len;
4280 if (multi_present == 1)
4282 else if (multi_present == 2)
4287 if (len < (8 + offset + hdmi_3d_len - 1))
4290 if (hdmi_3d_len < multi_len)
4293 if (multi_present == 1 || multi_present == 2) {
4294 /* 3D_Structure_ALL */
4295 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4297 /* check if 3D_MASK is present */
4298 if (multi_present == 2)
4299 mask = (db[10 + offset] << 8) | db[11 + offset];
4303 for (i = 0; i < 16; i++) {
4304 if (mask & (1 << i))
4305 modes += add_3d_struct_modes(connector,
4312 offset += multi_len;
4314 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4316 struct drm_display_mode *newmode = NULL;
4317 unsigned int newflag = 0;
4318 bool detail_present;
4320 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4322 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4325 /* 2D_VIC_order_X */
4326 vic_index = db[8 + offset + i] >> 4;
4328 /* 3D_Structure_X */
4329 switch (db[8 + offset + i] & 0x0f) {
4331 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4334 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4338 if ((db[9 + offset + i] >> 4) == 1)
4339 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4344 newmode = drm_display_mode_from_vic_index(connector,
4350 newmode->flags |= newflag;
4351 drm_mode_probed_add(connector, newmode);
4362 info->has_hdmi_infoframe = true;
4367 cea_revision(const u8 *cea)
4370 * FIXME is this correct for the DispID variant?
4371 * The DispID spec doesn't really specify whether
4372 * this is the revision of the CEA extension or
4373 * the DispID CEA data block. And the only value
4374 * given as an example is 0.
4380 * CTA Data Block iterator.
4382 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4385 * struct cea_db *db:
4386 * struct cea_db_iter iter;
4388 * cea_db_iter_edid_begin(edid, &iter);
4389 * cea_db_iter_for_each(db, &iter) {
4390 * // do stuff with db
4392 * cea_db_iter_end(&iter);
4394 struct cea_db_iter {
4395 struct drm_edid_iter edid_iter;
4396 struct displayid_iter displayid_iter;
4398 /* Current Data Block Collection. */
4399 const u8 *collection;
4401 /* Current Data Block index in current collection. */
4404 /* End index in current collection. */
4408 /* CTA-861-H section 7.4 CTA Data BLock Collection */
4414 static int cea_db_tag(const struct cea_db *db)
4416 return db->tag_length >> 5;
4419 static int cea_db_payload_len(const void *_db)
4421 /* FIXME: Transition to passing struct cea_db * everywhere. */
4422 const struct cea_db *db = _db;
4424 return db->tag_length & 0x1f;
4427 static const void *cea_db_data(const struct cea_db *db)
4432 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4434 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4435 cea_db_payload_len(db) >= 1 &&
4439 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4441 const u8 *data = cea_db_data(db);
4443 return cea_db_tag(db) == CTA_DB_VENDOR &&
4444 cea_db_payload_len(db) >= 3 &&
4445 oui(data[2], data[1], data[0]) == vendor_oui;
4448 static void cea_db_iter_edid_begin(const struct edid *edid, struct cea_db_iter *iter)
4450 memset(iter, 0, sizeof(*iter));
4452 drm_edid_iter_begin(edid, &iter->edid_iter);
4453 displayid_iter_edid_begin(edid, &iter->displayid_iter);
4456 static const struct cea_db *
4457 __cea_db_iter_current_block(const struct cea_db_iter *iter)
4459 const struct cea_db *db;
4461 if (!iter->collection)
4464 db = (const struct cea_db *)&iter->collection[iter->index];
4466 if (iter->index + sizeof(*db) <= iter->end &&
4467 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
4475 * - VESA E-EDID v1.4
4476 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4478 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
4482 drm_edid_iter_for_each(ext, &iter->edid_iter) {
4483 /* Only support CTA Extension revision 3+ */
4484 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
4491 if (iter->end < 4 || iter->end > 127)
4502 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
4503 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
4505 * Note that the above do not specify any connection between DisplayID Data
4506 * Block revision and CTA Extension versions.
4508 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
4510 const struct displayid_block *block;
4512 displayid_iter_for_each(block, &iter->displayid_iter) {
4513 if (block->tag != DATA_BLOCK_CTA)
4517 * The displayid iterator has already verified the block bounds
4518 * in displayid_iter_block().
4520 iter->index = sizeof(*block);
4521 iter->end = iter->index + block->num_bytes;
4529 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
4531 const struct cea_db *db;
4533 if (iter->collection) {
4534 /* Current collection should always be valid. */
4535 db = __cea_db_iter_current_block(iter);
4537 iter->collection = NULL;
4541 /* Next block in CTA Data Block Collection */
4542 iter->index += sizeof(*db) + cea_db_payload_len(db);
4544 db = __cea_db_iter_current_block(iter);
4551 * Find the next CTA Data Block Collection. First iterate all
4552 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
4554 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
4555 * Extension, it's recommended that DisplayID extensions are
4556 * exposed after all of the CTA Extensions.
4558 iter->collection = __cea_db_iter_edid_next(iter);
4559 if (!iter->collection)
4560 iter->collection = __cea_db_iter_displayid_next(iter);
4562 if (!iter->collection)
4565 db = __cea_db_iter_current_block(iter);
4571 #define cea_db_iter_for_each(__db, __iter) \
4572 while (((__db) = __cea_db_iter_next(__iter)))
4574 static void cea_db_iter_end(struct cea_db_iter *iter)
4576 displayid_iter_end(&iter->displayid_iter);
4577 drm_edid_iter_end(&iter->edid_iter);
4579 memset(iter, 0, sizeof(*iter));
4582 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
4584 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
4585 cea_db_payload_len(db) >= 5;
4588 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
4590 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
4591 cea_db_payload_len(db) >= 7;
4594 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
4596 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
4597 cea_db_payload_len(db) == 21;
4600 static bool cea_db_is_vcdb(const struct cea_db *db)
4602 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
4603 cea_db_payload_len(db) == 2;
4606 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
4608 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
4609 cea_db_payload_len(db) >= 7;
4612 static bool cea_db_is_y420cmdb(const struct cea_db *db)
4614 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
4617 static bool cea_db_is_y420vdb(const struct cea_db *db)
4619 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
4622 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
4624 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
4625 cea_db_payload_len(db) >= 3;
4628 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
4631 struct drm_display_info *info = &connector->display_info;
4632 struct drm_hdmi_info *hdmi = &info->hdmi;
4633 u8 map_len = cea_db_payload_len(db) - 1;
4638 /* All CEA modes support ycbcr420 sampling also.*/
4639 hdmi->y420_cmdb_map = U64_MAX;
4640 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
4645 * This map indicates which of the existing CEA block modes
4646 * from VDB can support YCBCR420 output too. So if bit=0 is
4647 * set, first mode from VDB can support YCBCR420 output too.
4648 * We will parse and keep this map, before parsing VDB itself
4649 * to avoid going through the same block again and again.
4651 * Spec is not clear about max possible size of this block.
4652 * Clamping max bitmap block size at 8 bytes. Every byte can
4653 * address 8 CEA modes, in this way this map can address
4654 * 8*8 = first 64 SVDs.
4656 if (WARN_ON_ONCE(map_len > 8))
4659 for (count = 0; count < map_len; count++)
4660 map |= (u64)db[2 + count] << (8 * count);
4663 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
4665 hdmi->y420_cmdb_map = map;
4668 static int add_cea_modes(struct drm_connector *connector,
4669 const struct drm_edid *drm_edid)
4671 const struct cea_db *db;
4672 struct cea_db_iter iter;
4675 cea_db_iter_edid_begin(drm_edid->edid, &iter);
4676 cea_db_iter_for_each(db, &iter) {
4677 const u8 *hdmi = NULL, *video = NULL;
4678 u8 hdmi_len = 0, video_len = 0;
4680 if (cea_db_tag(db) == CTA_DB_VIDEO) {
4681 video = cea_db_data(db);
4682 video_len = cea_db_payload_len(db);
4683 modes += do_cea_modes(connector, video, video_len);
4684 } else if (cea_db_is_hdmi_vsdb(db)) {
4685 /* FIXME: Switch to use cea_db_data() */
4686 hdmi = (const u8 *)db;
4687 hdmi_len = cea_db_payload_len(db);
4688 } else if (cea_db_is_y420vdb(db)) {
4689 const u8 *vdb420 = cea_db_data(db) + 1;
4691 /* Add 4:2:0(only) modes present in EDID */
4692 modes += do_y420vdb_modes(connector, vdb420,
4693 cea_db_payload_len(db) - 1);
4697 * We parse the HDMI VSDB after having added the cea modes as we
4698 * will be patching their flags when the sink supports stereo
4702 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len,
4705 cea_db_iter_end(&iter);
4710 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
4712 const struct drm_display_mode *cea_mode;
4713 int clock1, clock2, clock;
4718 * allow 5kHz clock difference either way to account for
4719 * the 10kHz clock resolution limit of detailed timings.
4721 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4722 if (drm_valid_cea_vic(vic)) {
4724 cea_mode = cea_mode_for_vic(vic);
4725 clock1 = cea_mode->clock;
4726 clock2 = cea_mode_alternate_clock(cea_mode);
4728 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4729 if (drm_valid_hdmi_vic(vic)) {
4731 cea_mode = &edid_4k_modes[vic];
4732 clock1 = cea_mode->clock;
4733 clock2 = hdmi_mode_alternate_clock(cea_mode);
4739 /* pick whichever is closest */
4740 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
4745 if (mode->clock == clock)
4748 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
4749 type, vic, mode->clock, clock);
4750 mode->clock = clock;
4753 static uint8_t eotf_supported(const u8 *edid_ext)
4755 return edid_ext[2] &
4756 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
4757 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
4758 BIT(HDMI_EOTF_SMPTE_ST2084) |
4759 BIT(HDMI_EOTF_BT_2100_HLG));
4762 static uint8_t hdr_metadata_type(const u8 *edid_ext)
4764 return edid_ext[3] &
4765 BIT(HDMI_STATIC_METADATA_TYPE1);
4769 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4773 len = cea_db_payload_len(db);
4775 connector->hdr_sink_metadata.hdmi_type1.eotf =
4777 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
4778 hdr_metadata_type(db);
4781 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
4783 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
4785 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
4789 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
4791 u8 len = cea_db_payload_len(db);
4793 if (len >= 6 && (db[6] & (1 << 7)))
4794 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
4796 connector->latency_present[0] = db[8] >> 7;
4797 connector->latency_present[1] = (db[8] >> 6) & 1;
4800 connector->video_latency[0] = db[9];
4802 connector->audio_latency[0] = db[10];
4804 connector->video_latency[1] = db[11];
4806 connector->audio_latency[1] = db[12];
4808 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4809 "video latency %d %d, "
4810 "audio latency %d %d\n",
4811 connector->latency_present[0],
4812 connector->latency_present[1],
4813 connector->video_latency[0],
4814 connector->video_latency[1],
4815 connector->audio_latency[0],
4816 connector->audio_latency[1]);
4820 monitor_name(const struct detailed_timing *timing, void *data)
4822 const char **res = data;
4824 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
4827 *res = timing->data.other_data.data.str.str;
4830 static int get_monitor_name(const struct edid *edid, char name[13])
4832 const char *edid_name = NULL;
4838 drm_for_each_detailed_block(edid, monitor_name, &edid_name);
4839 for (mnl = 0; edid_name && mnl < 13; mnl++) {
4840 if (edid_name[mnl] == 0x0a)
4843 name[mnl] = edid_name[mnl];
4850 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4851 * @edid: monitor EDID information
4852 * @name: pointer to a character array to hold the name of the monitor
4853 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4856 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
4864 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4865 memcpy(name, buf, name_length);
4866 name[name_length] = '\0';
4868 EXPORT_SYMBOL(drm_edid_get_monitor_name);
4870 static void clear_eld(struct drm_connector *connector)
4872 memset(connector->eld, 0, sizeof(connector->eld));
4874 connector->latency_present[0] = false;
4875 connector->latency_present[1] = false;
4876 connector->video_latency[0] = 0;
4877 connector->audio_latency[0] = 0;
4878 connector->video_latency[1] = 0;
4879 connector->audio_latency[1] = 0;
4883 * drm_edid_to_eld - build ELD from EDID
4884 * @connector: connector corresponding to the HDMI/DP sink
4885 * @drm_edid: EDID to parse
4887 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
4888 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
4890 static void drm_edid_to_eld(struct drm_connector *connector,
4891 const struct drm_edid *drm_edid)
4893 const struct drm_display_info *info = &connector->display_info;
4894 const struct cea_db *db;
4895 struct cea_db_iter iter;
4896 uint8_t *eld = connector->eld;
4897 int total_sad_count = 0;
4900 clear_eld(connector);
4905 mnl = get_monitor_name(drm_edid->edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4906 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
4908 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
4909 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
4911 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
4913 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
4914 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
4915 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
4916 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
4918 cea_db_iter_edid_begin(drm_edid->edid, &iter);
4919 cea_db_iter_for_each(db, &iter) {
4920 const u8 *data = cea_db_data(db);
4921 int len = cea_db_payload_len(db);
4924 switch (cea_db_tag(db)) {
4926 /* Audio Data Block, contains SADs */
4927 sad_count = min(len / 3, 15 - total_sad_count);
4929 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
4930 data, sad_count * 3);
4931 total_sad_count += sad_count;
4933 case CTA_DB_SPEAKER:
4934 /* Speaker Allocation Data Block */
4936 eld[DRM_ELD_SPEAKER] = data[0];
4939 /* HDMI Vendor-Specific Data Block */
4940 if (cea_db_is_hdmi_vsdb(db))
4941 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
4947 cea_db_iter_end(&iter);
4949 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
4951 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4952 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4953 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4955 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
4957 eld[DRM_ELD_BASELINE_ELD_LEN] =
4958 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4960 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
4961 drm_eld_size(eld), total_sad_count);
4965 * drm_edid_to_sad - extracts SADs from EDID
4966 * @edid: EDID to parse
4967 * @sads: pointer that will be set to the extracted SADs
4969 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
4971 * Note: The returned pointer needs to be freed using kfree().
4973 * Return: The number of found SADs or negative number on error.
4975 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
4977 const struct cea_db *db;
4978 struct cea_db_iter iter;
4981 cea_db_iter_edid_begin(edid, &iter);
4982 cea_db_iter_for_each(db, &iter) {
4983 if (cea_db_tag(db) == CTA_DB_AUDIO) {
4986 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
4987 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4990 for (j = 0; j < count; j++) {
4991 const u8 *sad = &db->data[j * 3];
4993 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4994 (*sads)[j].channels = sad[0] & 0x7;
4995 (*sads)[j].freq = sad[1] & 0x7F;
4996 (*sads)[j].byte2 = sad[2];
5001 cea_db_iter_end(&iter);
5003 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5007 EXPORT_SYMBOL(drm_edid_to_sad);
5010 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5011 * @edid: EDID to parse
5012 * @sadb: pointer to the speaker block
5014 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5016 * Note: The returned pointer needs to be freed using kfree().
5018 * Return: The number of found Speaker Allocation Blocks or negative number on
5021 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5023 const struct cea_db *db;
5024 struct cea_db_iter iter;
5027 cea_db_iter_edid_begin(edid, &iter);
5028 cea_db_iter_for_each(db, &iter) {
5029 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5030 cea_db_payload_len(db) == 3) {
5031 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5035 count = cea_db_payload_len(db);
5039 cea_db_iter_end(&iter);
5041 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5045 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5048 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5049 * @connector: connector associated with the HDMI/DP sink
5050 * @mode: the display mode
5052 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5053 * the sink doesn't support audio or video.
5055 int drm_av_sync_delay(struct drm_connector *connector,
5056 const struct drm_display_mode *mode)
5058 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5061 if (!connector->latency_present[0])
5063 if (!connector->latency_present[1])
5066 a = connector->audio_latency[i];
5067 v = connector->video_latency[i];
5070 * HDMI/DP sink doesn't support audio or video?
5072 if (a == 255 || v == 255)
5076 * Convert raw EDID values to millisecond.
5077 * Treat unknown latency as 0ms.
5080 a = min(2 * (a - 1), 500);
5082 v = min(2 * (v - 1), 500);
5084 return max(v - a, 0);
5086 EXPORT_SYMBOL(drm_av_sync_delay);
5089 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5090 * @edid: monitor EDID information
5092 * Parse the CEA extension according to CEA-861-B.
5094 * Drivers that have added the modes parsed from EDID to drm_display_info
5095 * should use &drm_display_info.is_hdmi instead of calling this function.
5097 * Return: True if the monitor is HDMI, false if not or unknown.
5099 bool drm_detect_hdmi_monitor(const struct edid *edid)
5101 const struct cea_db *db;
5102 struct cea_db_iter iter;
5106 * Because HDMI identifier is in Vendor Specific Block,
5107 * search it from all data blocks of CEA extension.
5109 cea_db_iter_edid_begin(edid, &iter);
5110 cea_db_iter_for_each(db, &iter) {
5111 if (cea_db_is_hdmi_vsdb(db)) {
5116 cea_db_iter_end(&iter);
5120 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5123 * drm_detect_monitor_audio - check monitor audio capability
5124 * @edid: EDID block to scan
5126 * Monitor should have CEA extension block.
5127 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5128 * audio' only. If there is any audio extension block and supported
5129 * audio format, assume at least 'basic audio' support, even if 'basic
5130 * audio' is not defined in EDID.
5132 * Return: True if the monitor supports audio, false otherwise.
5134 bool drm_detect_monitor_audio(const struct edid *edid)
5136 struct drm_edid_iter edid_iter;
5137 const struct cea_db *db;
5138 struct cea_db_iter iter;
5140 bool has_audio = false;
5142 drm_edid_iter_begin(edid, &edid_iter);
5143 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5144 if (edid_ext[0] == CEA_EXT) {
5145 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5150 drm_edid_iter_end(&edid_iter);
5153 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5157 cea_db_iter_edid_begin(edid, &iter);
5158 cea_db_iter_for_each(db, &iter) {
5159 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5160 const u8 *data = cea_db_data(db);
5163 for (i = 0; i < cea_db_payload_len(db); i += 3)
5164 DRM_DEBUG_KMS("CEA audio format %d\n",
5165 (data[i] >> 3) & 0xf);
5170 cea_db_iter_end(&iter);
5175 EXPORT_SYMBOL(drm_detect_monitor_audio);
5179 * drm_default_rgb_quant_range - default RGB quantization range
5180 * @mode: display mode
5182 * Determine the default RGB quantization range for the mode,
5183 * as specified in CEA-861.
5185 * Return: The default RGB quantization range for the mode
5187 enum hdmi_quantization_range
5188 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5190 /* All CEA modes other than VIC 1 use limited quantization range. */
5191 return drm_match_cea_mode(mode) > 1 ?
5192 HDMI_QUANTIZATION_RANGE_LIMITED :
5193 HDMI_QUANTIZATION_RANGE_FULL;
5195 EXPORT_SYMBOL(drm_default_rgb_quant_range);
5197 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5199 struct drm_display_info *info = &connector->display_info;
5201 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
5203 if (db[2] & EDID_CEA_VCDB_QS)
5204 info->rgb_quant_range_selectable = true;
5208 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5210 switch (max_frl_rate) {
5213 *max_rate_per_lane = 3;
5217 *max_rate_per_lane = 6;
5221 *max_rate_per_lane = 6;
5225 *max_rate_per_lane = 8;
5229 *max_rate_per_lane = 10;
5233 *max_rate_per_lane = 12;
5238 *max_rate_per_lane = 0;
5242 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
5246 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
5248 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
5249 hdmi->y420_dc_modes = dc_mask;
5252 /* Sink Capability Data Structure */
5253 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
5256 struct drm_display_info *display = &connector->display_info;
5257 struct drm_hdmi_info *hdmi = &display->hdmi;
5259 display->has_hdmi_infoframe = true;
5261 if (hf_scds[6] & 0x80) {
5262 hdmi->scdc.supported = true;
5263 if (hf_scds[6] & 0x40)
5264 hdmi->scdc.read_request = true;
5268 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
5269 * And as per the spec, three factors confirm this:
5270 * * Availability of a HF-VSDB block in EDID (check)
5271 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
5272 * * SCDC support available (let's check)
5273 * Lets check it out.
5277 /* max clock is 5000 KHz times block value */
5278 u32 max_tmds_clock = hf_scds[5] * 5000;
5279 struct drm_scdc *scdc = &hdmi->scdc;
5281 if (max_tmds_clock > 340000) {
5282 display->max_tmds_clock = max_tmds_clock;
5283 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
5284 display->max_tmds_clock);
5287 if (scdc->supported) {
5288 scdc->scrambling.supported = true;
5290 /* Few sinks support scrambling for clocks < 340M */
5291 if ((hf_scds[6] & 0x8))
5292 scdc->scrambling.low_rates = true;
5298 u8 dsc_max_frl_rate;
5300 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
5302 DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n");
5303 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
5304 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
5305 &hdmi->max_frl_rate_per_lane);
5306 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
5308 if (hdmi_dsc->v_1p2) {
5309 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
5310 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
5312 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
5313 hdmi_dsc->bpc_supported = 16;
5314 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
5315 hdmi_dsc->bpc_supported = 12;
5316 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
5317 hdmi_dsc->bpc_supported = 10;
5319 hdmi_dsc->bpc_supported = 0;
5321 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
5322 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
5323 &hdmi_dsc->max_frl_rate_per_lane);
5324 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
5326 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
5327 switch (dsc_max_slices) {
5329 hdmi_dsc->max_slices = 1;
5330 hdmi_dsc->clk_per_slice = 340;
5333 hdmi_dsc->max_slices = 2;
5334 hdmi_dsc->clk_per_slice = 340;
5337 hdmi_dsc->max_slices = 4;
5338 hdmi_dsc->clk_per_slice = 340;
5341 hdmi_dsc->max_slices = 8;
5342 hdmi_dsc->clk_per_slice = 340;
5345 hdmi_dsc->max_slices = 8;
5346 hdmi_dsc->clk_per_slice = 400;
5349 hdmi_dsc->max_slices = 12;
5350 hdmi_dsc->clk_per_slice = 400;
5353 hdmi_dsc->max_slices = 16;
5354 hdmi_dsc->clk_per_slice = 400;
5358 hdmi_dsc->max_slices = 0;
5359 hdmi_dsc->clk_per_slice = 0;
5364 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
5367 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
5370 struct drm_display_info *info = &connector->display_info;
5371 unsigned int dc_bpc = 0;
5373 /* HDMI supports at least 8 bpc */
5376 if (cea_db_payload_len(hdmi) < 6)
5379 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
5381 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
5382 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
5386 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
5388 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
5389 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
5393 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
5395 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
5396 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
5401 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
5406 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
5407 connector->name, dc_bpc);
5410 /* YCRCB444 is optional according to spec. */
5411 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
5412 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
5413 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
5418 * Spec says that if any deep color mode is supported at all,
5419 * then deep color 36 bit must be supported.
5421 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
5422 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
5428 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
5430 struct drm_display_info *info = &connector->display_info;
5431 u8 len = cea_db_payload_len(db);
5433 info->is_hdmi = true;
5436 info->dvi_dual = db[6] & 1;
5438 info->max_tmds_clock = db[7] * 5000;
5440 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
5441 "max TMDS clock %d kHz\n",
5443 info->max_tmds_clock);
5445 drm_parse_hdmi_deep_color_info(connector, db);
5449 * See EDID extension for head-mounted and specialized monitors, specified at:
5450 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
5452 static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
5455 struct drm_display_info *info = &connector->display_info;
5457 bool desktop_usage = db[5] & BIT(6);
5459 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
5460 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
5461 info->non_desktop = true;
5463 drm_dbg_kms(connector->dev, "HMD or specialized display VSDB version %u: 0x%02x\n",
5467 static void drm_parse_cea_ext(struct drm_connector *connector,
5468 const struct drm_edid *drm_edid)
5470 struct drm_display_info *info = &connector->display_info;
5471 struct drm_edid_iter edid_iter;
5472 const struct cea_db *db;
5473 struct cea_db_iter iter;
5476 drm_edid_iter_begin(drm_edid->edid, &edid_iter);
5477 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5478 if (edid_ext[0] != CEA_EXT)
5482 info->cea_rev = edid_ext[1];
5484 if (info->cea_rev != edid_ext[1])
5485 DRM_DEBUG_KMS("CEA extension version mismatch %u != %u\n",
5486 info->cea_rev, edid_ext[1]);
5488 /* The existence of a CTA extension should imply RGB support */
5489 info->color_formats = DRM_COLOR_FORMAT_RGB444;
5490 if (edid_ext[3] & EDID_CEA_YCRCB444)
5491 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
5492 if (edid_ext[3] & EDID_CEA_YCRCB422)
5493 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
5495 drm_edid_iter_end(&edid_iter);
5497 cea_db_iter_edid_begin(drm_edid->edid, &iter);
5498 cea_db_iter_for_each(db, &iter) {
5499 /* FIXME: convert parsers to use struct cea_db */
5500 const u8 *data = (const u8 *)db;
5502 if (cea_db_is_hdmi_vsdb(db))
5503 drm_parse_hdmi_vsdb_video(connector, data);
5504 else if (cea_db_is_hdmi_forum_vsdb(db) ||
5505 cea_db_is_hdmi_forum_scdb(db))
5506 drm_parse_hdmi_forum_scds(connector, data);
5507 else if (cea_db_is_microsoft_vsdb(db))
5508 drm_parse_microsoft_vsdb(connector, data);
5509 else if (cea_db_is_y420cmdb(db))
5510 drm_parse_y420cmdb_bitmap(connector, data);
5511 else if (cea_db_is_vcdb(db))
5512 drm_parse_vcdb(connector, data);
5513 else if (cea_db_is_hdmi_hdr_metadata_block(db))
5514 drm_parse_hdr_metadata_block(connector, data);
5516 cea_db_iter_end(&iter);
5520 void get_monitor_range(const struct detailed_timing *timing,
5521 void *info_monitor_range)
5523 struct drm_monitor_range_info *monitor_range = info_monitor_range;
5524 const struct detailed_non_pixel *data = &timing->data.other_data;
5525 const struct detailed_data_monitor_range *range = &data->data.range;
5527 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
5531 * Check for flag range limits only. If flag == 1 then
5532 * no additional timing information provided.
5533 * Default GTF, GTF Secondary curve and CVT are not
5536 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
5539 monitor_range->min_vfreq = range->min_vfreq;
5540 monitor_range->max_vfreq = range->max_vfreq;
5543 static void drm_get_monitor_range(struct drm_connector *connector,
5544 const struct drm_edid *drm_edid)
5546 struct drm_display_info *info = &connector->display_info;
5548 if (!version_greater(drm_edid->edid, 1, 1))
5551 drm_for_each_detailed_block(drm_edid->edid, get_monitor_range,
5552 &info->monitor_range);
5554 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
5555 info->monitor_range.min_vfreq,
5556 info->monitor_range.max_vfreq);
5559 static void drm_parse_vesa_mso_data(struct drm_connector *connector,
5560 const struct displayid_block *block)
5562 struct displayid_vesa_vendor_specific_block *vesa =
5563 (struct displayid_vesa_vendor_specific_block *)block;
5564 struct drm_display_info *info = &connector->display_info;
5566 if (block->num_bytes < 3) {
5567 drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n",
5572 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
5575 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
5576 drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");
5580 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
5582 drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");
5585 info->mso_stream_count = 0;
5588 info->mso_stream_count = 2; /* 2 or 4 links */
5591 info->mso_stream_count = 4; /* 4 links */
5595 if (!info->mso_stream_count) {
5596 info->mso_pixel_overlap = 0;
5600 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
5601 if (info->mso_pixel_overlap > 8) {
5602 drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",
5603 info->mso_pixel_overlap);
5604 info->mso_pixel_overlap = 8;
5607 drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",
5608 info->mso_stream_count, info->mso_pixel_overlap);
5611 static void drm_update_mso(struct drm_connector *connector,
5612 const struct drm_edid *drm_edid)
5614 const struct displayid_block *block;
5615 struct displayid_iter iter;
5617 displayid_iter_edid_begin(drm_edid->edid, &iter);
5618 displayid_iter_for_each(block, &iter) {
5619 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
5620 drm_parse_vesa_mso_data(connector, block);
5622 displayid_iter_end(&iter);
5625 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
5626 * all of the values which would have been set from EDID
5629 drm_reset_display_info(struct drm_connector *connector)
5631 struct drm_display_info *info = &connector->display_info;
5634 info->height_mm = 0;
5637 info->color_formats = 0;
5639 info->max_tmds_clock = 0;
5640 info->dvi_dual = false;
5641 info->is_hdmi = false;
5642 info->has_hdmi_infoframe = false;
5643 info->rgb_quant_range_selectable = false;
5644 memset(&info->hdmi, 0, sizeof(info->hdmi));
5646 info->edid_hdmi_rgb444_dc_modes = 0;
5647 info->edid_hdmi_ycbcr444_dc_modes = 0;
5649 info->non_desktop = 0;
5650 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
5652 info->mso_stream_count = 0;
5653 info->mso_pixel_overlap = 0;
5656 static u32 update_display_info(struct drm_connector *connector,
5657 const struct drm_edid *drm_edid)
5659 struct drm_display_info *info = &connector->display_info;
5660 const struct edid *edid = drm_edid->edid;
5662 u32 quirks = edid_get_quirks(drm_edid);
5664 drm_reset_display_info(connector);
5666 info->width_mm = edid->width_cm * 10;
5667 info->height_mm = edid->height_cm * 10;
5669 drm_get_monitor_range(connector, drm_edid);
5671 if (edid->revision < 3)
5674 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
5677 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
5678 drm_parse_cea_ext(connector, drm_edid);
5681 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
5683 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
5684 * tells us to assume 8 bpc color depth if the EDID doesn't have
5685 * extensions which tell otherwise.
5687 if (info->bpc == 0 && edid->revision == 3 &&
5688 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
5690 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
5691 connector->name, info->bpc);
5694 /* Only defined for 1.4 with digital displays */
5695 if (edid->revision < 4)
5698 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
5699 case DRM_EDID_DIGITAL_DEPTH_6:
5702 case DRM_EDID_DIGITAL_DEPTH_8:
5705 case DRM_EDID_DIGITAL_DEPTH_10:
5708 case DRM_EDID_DIGITAL_DEPTH_12:
5711 case DRM_EDID_DIGITAL_DEPTH_14:
5714 case DRM_EDID_DIGITAL_DEPTH_16:
5717 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
5723 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
5724 connector->name, info->bpc);
5726 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
5727 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
5728 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
5729 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
5731 drm_update_mso(connector, drm_edid);
5734 if (quirks & EDID_QUIRK_NON_DESKTOP) {
5735 drm_dbg_kms(connector->dev, "Non-desktop display%s\n",
5736 info->non_desktop ? " (redundant quirk)" : "");
5737 info->non_desktop = true;
5743 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
5745 struct drm_edid drm_edid;
5747 return update_display_info(connector,
5748 drm_edid_legacy_init(&drm_edid, edid));
5751 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
5752 struct displayid_detailed_timings_1 *timings,
5755 struct drm_display_mode *mode;
5756 unsigned pixel_clock = (timings->pixel_clock[0] |
5757 (timings->pixel_clock[1] << 8) |
5758 (timings->pixel_clock[2] << 16)) + 1;
5759 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
5760 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
5761 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
5762 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
5763 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
5764 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
5765 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
5766 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
5767 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
5768 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
5770 mode = drm_mode_create(dev);
5774 /* resolution is kHz for type VII, and 10 kHz for type I */
5775 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
5776 mode->hdisplay = hactive;
5777 mode->hsync_start = mode->hdisplay + hsync;
5778 mode->hsync_end = mode->hsync_start + hsync_width;
5779 mode->htotal = mode->hdisplay + hblank;
5781 mode->vdisplay = vactive;
5782 mode->vsync_start = mode->vdisplay + vsync;
5783 mode->vsync_end = mode->vsync_start + vsync_width;
5784 mode->vtotal = mode->vdisplay + vblank;
5787 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
5788 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
5789 mode->type = DRM_MODE_TYPE_DRIVER;
5791 if (timings->flags & 0x80)
5792 mode->type |= DRM_MODE_TYPE_PREFERRED;
5793 drm_mode_set_name(mode);
5798 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
5799 const struct displayid_block *block)
5801 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
5804 struct drm_display_mode *newmode;
5806 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
5807 /* blocks must be multiple of 20 bytes length */
5808 if (block->num_bytes % 20)
5811 num_timings = block->num_bytes / 20;
5812 for (i = 0; i < num_timings; i++) {
5813 struct displayid_detailed_timings_1 *timings = &det->timings[i];
5815 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
5819 drm_mode_probed_add(connector, newmode);
5825 static int add_displayid_detailed_modes(struct drm_connector *connector,
5826 const struct drm_edid *drm_edid)
5828 const struct displayid_block *block;
5829 struct displayid_iter iter;
5832 displayid_iter_edid_begin(drm_edid->edid, &iter);
5833 displayid_iter_for_each(block, &iter) {
5834 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
5835 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
5836 num_modes += add_displayid_detailed_1_modes(connector, block);
5838 displayid_iter_end(&iter);
5843 static int drm_edid_connector_update(struct drm_connector *connector,
5844 const struct drm_edid *drm_edid)
5850 drm_reset_display_info(connector);
5851 clear_eld(connector);
5856 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
5857 * To avoid multiple parsing of same block, lets parse that map
5858 * from sink info, before parsing CEA modes.
5860 quirks = update_display_info(connector, drm_edid);
5862 /* Depends on info->cea_rev set by update_display_info() above */
5863 drm_edid_to_eld(connector, drm_edid);
5866 * EDID spec says modes should be preferred in this order:
5867 * - preferred detailed mode
5868 * - other detailed modes from base block
5869 * - detailed modes from extension blocks
5870 * - CVT 3-byte code modes
5871 * - standard timing codes
5872 * - established timing codes
5873 * - modes inferred from GTF or CVT range information
5875 * We get this pretty much right.
5877 * XXX order for additional mode types in extension blocks?
5879 num_modes += add_detailed_modes(connector, drm_edid, quirks);
5880 num_modes += add_cvt_modes(connector, drm_edid);
5881 num_modes += add_standard_modes(connector, drm_edid);
5882 num_modes += add_established_modes(connector, drm_edid);
5883 num_modes += add_cea_modes(connector, drm_edid);
5884 num_modes += add_alternate_cea_modes(connector, drm_edid);
5885 num_modes += add_displayid_detailed_modes(connector, drm_edid);
5886 if (drm_edid->edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
5887 num_modes += add_inferred_modes(connector, drm_edid);
5889 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
5890 edid_fixup_preferred(connector, quirks);
5892 if (quirks & EDID_QUIRK_FORCE_6BPC)
5893 connector->display_info.bpc = 6;
5895 if (quirks & EDID_QUIRK_FORCE_8BPC)
5896 connector->display_info.bpc = 8;
5898 if (quirks & EDID_QUIRK_FORCE_10BPC)
5899 connector->display_info.bpc = 10;
5901 if (quirks & EDID_QUIRK_FORCE_12BPC)
5902 connector->display_info.bpc = 12;
5908 * drm_add_edid_modes - add modes from EDID data, if available
5909 * @connector: connector we're probing
5912 * Add the specified modes to the connector's mode list. Also fills out the
5913 * &drm_display_info structure and ELD in @connector with any information which
5914 * can be derived from the edid.
5916 * Return: The number of modes added or 0 if we couldn't find any.
5918 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
5920 struct drm_edid drm_edid;
5922 if (edid && !drm_edid_is_valid(edid)) {
5923 drm_warn(connector->dev, "%s: EDID invalid.\n",
5928 return drm_edid_connector_update(connector,
5929 drm_edid_legacy_init(&drm_edid, edid));
5931 EXPORT_SYMBOL(drm_add_edid_modes);
5934 * drm_add_modes_noedid - add modes for the connectors without EDID
5935 * @connector: connector we're probing
5936 * @hdisplay: the horizontal display limit
5937 * @vdisplay: the vertical display limit
5939 * Add the specified modes to the connector's mode list. Only when the
5940 * hdisplay/vdisplay is not beyond the given limit, it will be added.
5942 * Return: The number of modes added or 0 if we couldn't find any.
5944 int drm_add_modes_noedid(struct drm_connector *connector,
5945 int hdisplay, int vdisplay)
5947 int i, count, num_modes = 0;
5948 struct drm_display_mode *mode;
5949 struct drm_device *dev = connector->dev;
5951 count = ARRAY_SIZE(drm_dmt_modes);
5957 for (i = 0; i < count; i++) {
5958 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
5960 if (hdisplay && vdisplay) {
5962 * Only when two are valid, they will be used to check
5963 * whether the mode should be added to the mode list of
5966 if (ptr->hdisplay > hdisplay ||
5967 ptr->vdisplay > vdisplay)
5970 if (drm_mode_vrefresh(ptr) > 61)
5972 mode = drm_mode_duplicate(dev, ptr);
5974 drm_mode_probed_add(connector, mode);
5980 EXPORT_SYMBOL(drm_add_modes_noedid);
5983 * drm_set_preferred_mode - Sets the preferred mode of a connector
5984 * @connector: connector whose mode list should be processed
5985 * @hpref: horizontal resolution of preferred mode
5986 * @vpref: vertical resolution of preferred mode
5988 * Marks a mode as preferred if it matches the resolution specified by @hpref
5991 void drm_set_preferred_mode(struct drm_connector *connector,
5992 int hpref, int vpref)
5994 struct drm_display_mode *mode;
5996 list_for_each_entry(mode, &connector->probed_modes, head) {
5997 if (mode->hdisplay == hpref &&
5998 mode->vdisplay == vpref)
5999 mode->type |= DRM_MODE_TYPE_PREFERRED;
6002 EXPORT_SYMBOL(drm_set_preferred_mode);
6004 static bool is_hdmi2_sink(const struct drm_connector *connector)
6007 * FIXME: sil-sii8620 doesn't have a connector around when
6008 * we need one, so we have to be prepared for a NULL connector.
6013 return connector->display_info.hdmi.scdc.supported ||
6014 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
6017 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
6018 const struct drm_display_mode *mode)
6020 bool has_hdmi_infoframe = connector ?
6021 connector->display_info.has_hdmi_infoframe : false;
6023 if (!has_hdmi_infoframe)
6026 /* No HDMI VIC when signalling 3D video format */
6027 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
6030 return drm_match_hdmi_mode(mode);
6033 static u8 drm_mode_cea_vic(const struct drm_connector *connector,
6034 const struct drm_display_mode *mode)
6039 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
6040 * we should send its VIC in vendor infoframes, else send the
6041 * VIC in AVI infoframes. Lets check if this mode is present in
6042 * HDMI 1.4b 4K modes
6044 if (drm_mode_hdmi_vic(connector, mode))
6047 vic = drm_match_cea_mode(mode);
6050 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
6051 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
6052 * have to make sure we dont break HDMI 1.4 sinks.
6054 if (!is_hdmi2_sink(connector) && vic > 64)
6061 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
6062 * data from a DRM display mode
6063 * @frame: HDMI AVI infoframe
6064 * @connector: the connector
6065 * @mode: DRM display mode
6067 * Return: 0 on success or a negative error code on failure.
6070 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
6071 const struct drm_connector *connector,
6072 const struct drm_display_mode *mode)
6074 enum hdmi_picture_aspect picture_aspect;
6077 if (!frame || !mode)
6080 hdmi_avi_infoframe_init(frame);
6082 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
6083 frame->pixel_repeat = 1;
6085 vic = drm_mode_cea_vic(connector, mode);
6086 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
6088 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
6091 * As some drivers don't support atomic, we can't use connector state.
6092 * So just initialize the frame with default values, just the same way
6093 * as it's done with other properties here.
6095 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
6099 * Populate picture aspect ratio from either
6100 * user input (if specified) or from the CEA/HDMI mode lists.
6102 picture_aspect = mode->picture_aspect_ratio;
6103 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
6105 picture_aspect = drm_get_cea_aspect_ratio(vic);
6107 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
6111 * The infoframe can't convey anything but none, 4:3
6112 * and 16:9, so if the user has asked for anything else
6113 * we can only satisfy it by specifying the right VIC.
6115 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
6117 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
6119 } else if (hdmi_vic) {
6120 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
6126 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
6129 frame->video_code = vic;
6130 frame->picture_aspect = picture_aspect;
6131 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
6132 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
6136 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
6139 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
6140 * quantization range information
6141 * @frame: HDMI AVI infoframe
6142 * @connector: the connector
6143 * @mode: DRM display mode
6144 * @rgb_quant_range: RGB quantization range (Q)
6147 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
6148 const struct drm_connector *connector,
6149 const struct drm_display_mode *mode,
6150 enum hdmi_quantization_range rgb_quant_range)
6152 const struct drm_display_info *info = &connector->display_info;
6156 * "A Source shall not send a non-zero Q value that does not correspond
6157 * to the default RGB Quantization Range for the transmitted Picture
6158 * unless the Sink indicates support for the Q bit in a Video
6159 * Capabilities Data Block."
6161 * HDMI 2.0 recommends sending non-zero Q when it does match the
6162 * default RGB quantization range for the mode, even when QS=0.
6164 if (info->rgb_quant_range_selectable ||
6165 rgb_quant_range == drm_default_rgb_quant_range(mode))
6166 frame->quantization_range = rgb_quant_range;
6168 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
6172 * "When transmitting any RGB colorimetry, the Source should set the
6173 * YQ-field to match the RGB Quantization Range being transmitted
6174 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
6175 * set YQ=1) and the Sink shall ignore the YQ-field."
6177 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
6178 * by non-zero YQ when receiving RGB. There doesn't seem to be any
6179 * good way to tell which version of CEA-861 the sink supports, so
6180 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
6183 if (!is_hdmi2_sink(connector) ||
6184 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
6185 frame->ycc_quantization_range =
6186 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
6188 frame->ycc_quantization_range =
6189 HDMI_YCC_QUANTIZATION_RANGE_FULL;
6191 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
6193 static enum hdmi_3d_structure
6194 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
6196 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
6199 case DRM_MODE_FLAG_3D_FRAME_PACKING:
6200 return HDMI_3D_STRUCTURE_FRAME_PACKING;
6201 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
6202 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
6203 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
6204 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
6205 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
6206 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
6207 case DRM_MODE_FLAG_3D_L_DEPTH:
6208 return HDMI_3D_STRUCTURE_L_DEPTH;
6209 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
6210 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
6211 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
6212 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
6213 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
6214 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
6216 return HDMI_3D_STRUCTURE_INVALID;
6221 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
6222 * data from a DRM display mode
6223 * @frame: HDMI vendor infoframe
6224 * @connector: the connector
6225 * @mode: DRM display mode
6227 * Note that there's is a need to send HDMI vendor infoframes only when using a
6228 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
6229 * function will return -EINVAL, error that can be safely ignored.
6231 * Return: 0 on success or a negative error code on failure.
6234 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
6235 const struct drm_connector *connector,
6236 const struct drm_display_mode *mode)
6239 * FIXME: sil-sii8620 doesn't have a connector around when
6240 * we need one, so we have to be prepared for a NULL connector.
6242 bool has_hdmi_infoframe = connector ?
6243 connector->display_info.has_hdmi_infoframe : false;
6246 if (!frame || !mode)
6249 if (!has_hdmi_infoframe)
6252 err = hdmi_vendor_infoframe_init(frame);
6257 * Even if it's not absolutely necessary to send the infoframe
6258 * (ie.vic==0 and s3d_struct==0) we will still send it if we
6259 * know that the sink can handle it. This is based on a
6260 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
6261 * have trouble realizing that they should switch from 3D to 2D
6262 * mode if the source simply stops sending the infoframe when
6263 * it wants to switch from 3D to 2D.
6265 frame->vic = drm_mode_hdmi_vic(connector, mode);
6266 frame->s3d_struct = s3d_structure_from_display_mode(mode);
6270 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
6272 static void drm_parse_tiled_block(struct drm_connector *connector,
6273 const struct displayid_block *block)
6275 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
6277 u8 tile_v_loc, tile_h_loc;
6278 u8 num_v_tile, num_h_tile;
6279 struct drm_tile_group *tg;
6281 w = tile->tile_size[0] | tile->tile_size[1] << 8;
6282 h = tile->tile_size[2] | tile->tile_size[3] << 8;
6284 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
6285 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
6286 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
6287 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
6289 connector->has_tile = true;
6290 if (tile->tile_cap & 0x80)
6291 connector->tile_is_single_monitor = true;
6293 connector->num_h_tile = num_h_tile + 1;
6294 connector->num_v_tile = num_v_tile + 1;
6295 connector->tile_h_loc = tile_h_loc;
6296 connector->tile_v_loc = tile_v_loc;
6297 connector->tile_h_size = w + 1;
6298 connector->tile_v_size = h + 1;
6300 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
6301 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
6302 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
6303 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
6304 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
6306 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
6308 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
6312 if (connector->tile_group != tg) {
6313 /* if we haven't got a pointer,
6314 take the reference, drop ref to old tile group */
6315 if (connector->tile_group)
6316 drm_mode_put_tile_group(connector->dev, connector->tile_group);
6317 connector->tile_group = tg;
6319 /* if same tile group, then release the ref we just took. */
6320 drm_mode_put_tile_group(connector->dev, tg);
6324 void drm_update_tile_info(struct drm_connector *connector,
6325 const struct edid *edid)
6327 const struct displayid_block *block;
6328 struct displayid_iter iter;
6330 connector->has_tile = false;
6332 displayid_iter_edid_begin(edid, &iter);
6333 displayid_iter_for_each(block, &iter) {
6334 if (block->tag == DATA_BLOCK_TILED_DISPLAY)
6335 drm_parse_tiled_block(connector, block);
6337 displayid_iter_end(&iter);
6339 if (!connector->has_tile && connector->tile_group) {
6340 drm_mode_put_tile_group(connector->dev, connector->tile_group);
6341 connector->tile_group = NULL;
projects / linux-2.6-microblaze.git / blob