2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
31 #include <linux/hdmi.h>
32 #include <linux/i2c.h>
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/slab.h>
36 #include <linux/vga_switcheroo.h>
38 #include <drm/drm_displayid.h>
39 #include <drm/drm_drv.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_encoder.h>
42 #include <drm/drm_print.h>
43 #include <drm/drm_scdc_helper.h>
45 #include "drm_crtc_internal.h"
47 #define version_greater(edid, maj, min) \
48 (((edid)->version > (maj)) || \
49 ((edid)->version == (maj) && (edid)->revision > (min)))
51 #define EDID_EST_TIMINGS 16
52 #define EDID_STD_TIMINGS 8
53 #define EDID_DETAILED_TIMINGS 4
56 * EDID blocks out in the wild have a variety of bugs, try to collect
57 * them here (note that userspace may work around broken monitors first,
58 * but fixes should make their way here so that the kernel "just works"
59 * on as many displays as possible).
62 /* First detailed mode wrong, use largest 60Hz mode */
63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
64 /* Reported 135MHz pixel clock is too high, needs adjustment */
65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
66 /* Prefer the largest mode at 75 Hz */
67 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
68 /* Detail timing is in cm not mm */
69 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
70 /* Detailed timing descriptors have bogus size values, so just take the
71 * maximum size and use that.
73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
74 /* use +hsync +vsync for detailed mode */
75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
76 /* Force reduced-blanking timings for detailed modes */
77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
79 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
81 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
83 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
85 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
86 /* Non desktop display (i.e. HMD) */
87 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
89 struct detailed_mode_closure {
90 struct drm_connector *connector;
102 static const struct edid_quirk {
106 } edid_quirk_list[] = {
108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
127 /* Belinea 10 15 55 */
128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
131 /* Envision Peripherals, Inc. EN-7100e */
132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
133 /* Envision EN2028 */
134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
136 /* Funai Electronics PM36B */
137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
138 EDID_QUIRK_DETAILED_IN_CM },
140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
143 /* LG Philips LCD LP154W01-A5 */
144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
147 /* Samsung SyncMaster 205BW. Note: irony */
148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
149 /* Samsung SyncMaster 22[5-6]BW */
150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
156 /* ViewSonic VA2026w */
157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
159 /* Medion MD 30217 PG */
160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
163 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC },
165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
171 /* Valve Index Headset */
172 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
173 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
174 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
175 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
176 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
177 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
178 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
179 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
180 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
181 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
182 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
183 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
184 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
185 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
186 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
187 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
188 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
190 /* HTC Vive and Vive Pro VR Headsets */
191 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
192 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
194 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */
195 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
196 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
197 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
199 /* Windows Mixed Reality Headsets */
200 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
201 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
202 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
203 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
204 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
205 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
206 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
207 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
209 /* Sony PlayStation VR Headset */
210 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
212 /* Sensics VR Headsets */
213 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
215 /* OSVR HDK and HDK2 VR Headsets */
216 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
220 * Autogenerated from the DMT spec.
221 * This table is copied from xfree86/modes/xf86EdidModes.c.
223 static const struct drm_display_mode drm_dmt_modes[] = {
224 /* 0x01 - 640x350@85Hz */
225 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
226 736, 832, 0, 350, 382, 385, 445, 0,
227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
228 /* 0x02 - 640x400@85Hz */
229 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
230 736, 832, 0, 400, 401, 404, 445, 0,
231 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
232 /* 0x03 - 720x400@85Hz */
233 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
234 828, 936, 0, 400, 401, 404, 446, 0,
235 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
236 /* 0x04 - 640x480@60Hz */
237 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
238 752, 800, 0, 480, 490, 492, 525, 0,
239 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
240 /* 0x05 - 640x480@72Hz */
241 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
242 704, 832, 0, 480, 489, 492, 520, 0,
243 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
244 /* 0x06 - 640x480@75Hz */
245 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
246 720, 840, 0, 480, 481, 484, 500, 0,
247 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
248 /* 0x07 - 640x480@85Hz */
249 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
250 752, 832, 0, 480, 481, 484, 509, 0,
251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
252 /* 0x08 - 800x600@56Hz */
253 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
254 896, 1024, 0, 600, 601, 603, 625, 0,
255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
256 /* 0x09 - 800x600@60Hz */
257 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
258 968, 1056, 0, 600, 601, 605, 628, 0,
259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
260 /* 0x0a - 800x600@72Hz */
261 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
262 976, 1040, 0, 600, 637, 643, 666, 0,
263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
264 /* 0x0b - 800x600@75Hz */
265 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
266 896, 1056, 0, 600, 601, 604, 625, 0,
267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
268 /* 0x0c - 800x600@85Hz */
269 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
270 896, 1048, 0, 600, 601, 604, 631, 0,
271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
272 /* 0x0d - 800x600@120Hz RB */
273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
274 880, 960, 0, 600, 603, 607, 636, 0,
275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
276 /* 0x0e - 848x480@60Hz */
277 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
278 976, 1088, 0, 480, 486, 494, 517, 0,
279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
280 /* 0x0f - 1024x768@43Hz, interlace */
281 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
282 1208, 1264, 0, 768, 768, 776, 817, 0,
283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
284 DRM_MODE_FLAG_INTERLACE) },
285 /* 0x10 - 1024x768@60Hz */
286 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
287 1184, 1344, 0, 768, 771, 777, 806, 0,
288 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
289 /* 0x11 - 1024x768@70Hz */
290 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
291 1184, 1328, 0, 768, 771, 777, 806, 0,
292 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
293 /* 0x12 - 1024x768@75Hz */
294 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
295 1136, 1312, 0, 768, 769, 772, 800, 0,
296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
297 /* 0x13 - 1024x768@85Hz */
298 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
299 1168, 1376, 0, 768, 769, 772, 808, 0,
300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
301 /* 0x14 - 1024x768@120Hz RB */
302 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
303 1104, 1184, 0, 768, 771, 775, 813, 0,
304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
305 /* 0x15 - 1152x864@75Hz */
306 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
307 1344, 1600, 0, 864, 865, 868, 900, 0,
308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
309 /* 0x55 - 1280x720@60Hz */
310 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
311 1430, 1650, 0, 720, 725, 730, 750, 0,
312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
313 /* 0x16 - 1280x768@60Hz RB */
314 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
315 1360, 1440, 0, 768, 771, 778, 790, 0,
316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
317 /* 0x17 - 1280x768@60Hz */
318 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
319 1472, 1664, 0, 768, 771, 778, 798, 0,
320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
321 /* 0x18 - 1280x768@75Hz */
322 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
323 1488, 1696, 0, 768, 771, 778, 805, 0,
324 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
325 /* 0x19 - 1280x768@85Hz */
326 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
327 1496, 1712, 0, 768, 771, 778, 809, 0,
328 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
329 /* 0x1a - 1280x768@120Hz RB */
330 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
331 1360, 1440, 0, 768, 771, 778, 813, 0,
332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
333 /* 0x1b - 1280x800@60Hz RB */
334 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
335 1360, 1440, 0, 800, 803, 809, 823, 0,
336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
337 /* 0x1c - 1280x800@60Hz */
338 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
339 1480, 1680, 0, 800, 803, 809, 831, 0,
340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
341 /* 0x1d - 1280x800@75Hz */
342 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
343 1488, 1696, 0, 800, 803, 809, 838, 0,
344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
345 /* 0x1e - 1280x800@85Hz */
346 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
347 1496, 1712, 0, 800, 803, 809, 843, 0,
348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
349 /* 0x1f - 1280x800@120Hz RB */
350 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
351 1360, 1440, 0, 800, 803, 809, 847, 0,
352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
353 /* 0x20 - 1280x960@60Hz */
354 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
355 1488, 1800, 0, 960, 961, 964, 1000, 0,
356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
357 /* 0x21 - 1280x960@85Hz */
358 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
359 1504, 1728, 0, 960, 961, 964, 1011, 0,
360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
361 /* 0x22 - 1280x960@120Hz RB */
362 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
363 1360, 1440, 0, 960, 963, 967, 1017, 0,
364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
365 /* 0x23 - 1280x1024@60Hz */
366 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
367 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
369 /* 0x24 - 1280x1024@75Hz */
370 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
371 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
373 /* 0x25 - 1280x1024@85Hz */
374 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
375 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
377 /* 0x26 - 1280x1024@120Hz RB */
378 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
379 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
381 /* 0x27 - 1360x768@60Hz */
382 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
383 1536, 1792, 0, 768, 771, 777, 795, 0,
384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
385 /* 0x28 - 1360x768@120Hz RB */
386 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
387 1440, 1520, 0, 768, 771, 776, 813, 0,
388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
389 /* 0x51 - 1366x768@60Hz */
390 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
391 1579, 1792, 0, 768, 771, 774, 798, 0,
392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
393 /* 0x56 - 1366x768@60Hz */
394 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
395 1436, 1500, 0, 768, 769, 772, 800, 0,
396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
397 /* 0x29 - 1400x1050@60Hz RB */
398 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
399 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
401 /* 0x2a - 1400x1050@60Hz */
402 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
403 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
404 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
405 /* 0x2b - 1400x1050@75Hz */
406 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
407 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
408 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
409 /* 0x2c - 1400x1050@85Hz */
410 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
411 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
412 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
413 /* 0x2d - 1400x1050@120Hz RB */
414 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
415 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
417 /* 0x2e - 1440x900@60Hz RB */
418 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
419 1520, 1600, 0, 900, 903, 909, 926, 0,
420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
421 /* 0x2f - 1440x900@60Hz */
422 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
423 1672, 1904, 0, 900, 903, 909, 934, 0,
424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
425 /* 0x30 - 1440x900@75Hz */
426 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
427 1688, 1936, 0, 900, 903, 909, 942, 0,
428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
429 /* 0x31 - 1440x900@85Hz */
430 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
431 1696, 1952, 0, 900, 903, 909, 948, 0,
432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
433 /* 0x32 - 1440x900@120Hz RB */
434 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
435 1520, 1600, 0, 900, 903, 909, 953, 0,
436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
437 /* 0x53 - 1600x900@60Hz */
438 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
439 1704, 1800, 0, 900, 901, 904, 1000, 0,
440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
441 /* 0x33 - 1600x1200@60Hz */
442 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
443 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
445 /* 0x34 - 1600x1200@65Hz */
446 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
447 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
449 /* 0x35 - 1600x1200@70Hz */
450 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
451 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
453 /* 0x36 - 1600x1200@75Hz */
454 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
455 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
457 /* 0x37 - 1600x1200@85Hz */
458 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
459 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
461 /* 0x38 - 1600x1200@120Hz RB */
462 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
463 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
465 /* 0x39 - 1680x1050@60Hz RB */
466 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
467 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
469 /* 0x3a - 1680x1050@60Hz */
470 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
471 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
472 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
473 /* 0x3b - 1680x1050@75Hz */
474 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
475 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
477 /* 0x3c - 1680x1050@85Hz */
478 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
479 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
480 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
481 /* 0x3d - 1680x1050@120Hz RB */
482 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
483 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
485 /* 0x3e - 1792x1344@60Hz */
486 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
487 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
489 /* 0x3f - 1792x1344@75Hz */
490 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
491 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
493 /* 0x40 - 1792x1344@120Hz RB */
494 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
495 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
497 /* 0x41 - 1856x1392@60Hz */
498 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
499 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
500 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
501 /* 0x42 - 1856x1392@75Hz */
502 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
503 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
505 /* 0x43 - 1856x1392@120Hz RB */
506 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
507 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
509 /* 0x52 - 1920x1080@60Hz */
510 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
511 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
513 /* 0x44 - 1920x1200@60Hz RB */
514 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
515 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
517 /* 0x45 - 1920x1200@60Hz */
518 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
519 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
521 /* 0x46 - 1920x1200@75Hz */
522 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
523 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
525 /* 0x47 - 1920x1200@85Hz */
526 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
527 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
528 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
529 /* 0x48 - 1920x1200@120Hz RB */
530 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
531 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
533 /* 0x49 - 1920x1440@60Hz */
534 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
535 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
537 /* 0x4a - 1920x1440@75Hz */
538 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
539 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
541 /* 0x4b - 1920x1440@120Hz RB */
542 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
543 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
544 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
545 /* 0x54 - 2048x1152@60Hz */
546 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
547 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
549 /* 0x4c - 2560x1600@60Hz RB */
550 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
551 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
553 /* 0x4d - 2560x1600@60Hz */
554 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
555 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
557 /* 0x4e - 2560x1600@75Hz */
558 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
559 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
561 /* 0x4f - 2560x1600@85Hz */
562 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
563 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
564 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
565 /* 0x50 - 2560x1600@120Hz RB */
566 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
567 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
569 /* 0x57 - 4096x2160@60Hz RB */
570 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
571 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
573 /* 0x58 - 4096x2160@59.94Hz RB */
574 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
575 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
580 * These more or less come from the DMT spec. The 720x400 modes are
581 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
582 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
583 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
586 * The DMT modes have been fact-checked; the rest are mild guesses.
588 static const struct drm_display_mode edid_est_modes[] = {
589 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
590 968, 1056, 0, 600, 601, 605, 628, 0,
591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
592 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
593 896, 1024, 0, 600, 601, 603, 625, 0,
594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
595 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
596 720, 840, 0, 480, 481, 484, 500, 0,
597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
598 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
599 704, 832, 0, 480, 489, 492, 520, 0,
600 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
601 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
602 768, 864, 0, 480, 483, 486, 525, 0,
603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
604 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
605 752, 800, 0, 480, 490, 492, 525, 0,
606 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
607 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
608 846, 900, 0, 400, 421, 423, 449, 0,
609 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
610 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
611 846, 900, 0, 400, 412, 414, 449, 0,
612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
613 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
614 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
616 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
617 1136, 1312, 0, 768, 769, 772, 800, 0,
618 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
619 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
620 1184, 1328, 0, 768, 771, 777, 806, 0,
621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
622 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
623 1184, 1344, 0, 768, 771, 777, 806, 0,
624 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
625 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
626 1208, 1264, 0, 768, 768, 776, 817, 0,
627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
628 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
629 928, 1152, 0, 624, 625, 628, 667, 0,
630 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
631 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
632 896, 1056, 0, 600, 601, 604, 625, 0,
633 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
634 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
635 976, 1040, 0, 600, 637, 643, 666, 0,
636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
637 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
638 1344, 1600, 0, 864, 865, 868, 900, 0,
639 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
649 static const struct minimode est3_modes[] = {
657 { 1024, 768, 85, 0 },
658 { 1152, 864, 75, 0 },
660 { 1280, 768, 60, 1 },
661 { 1280, 768, 60, 0 },
662 { 1280, 768, 75, 0 },
663 { 1280, 768, 85, 0 },
664 { 1280, 960, 60, 0 },
665 { 1280, 960, 85, 0 },
666 { 1280, 1024, 60, 0 },
667 { 1280, 1024, 85, 0 },
669 { 1360, 768, 60, 0 },
670 { 1440, 900, 60, 1 },
671 { 1440, 900, 60, 0 },
672 { 1440, 900, 75, 0 },
673 { 1440, 900, 85, 0 },
674 { 1400, 1050, 60, 1 },
675 { 1400, 1050, 60, 0 },
676 { 1400, 1050, 75, 0 },
678 { 1400, 1050, 85, 0 },
679 { 1680, 1050, 60, 1 },
680 { 1680, 1050, 60, 0 },
681 { 1680, 1050, 75, 0 },
682 { 1680, 1050, 85, 0 },
683 { 1600, 1200, 60, 0 },
684 { 1600, 1200, 65, 0 },
685 { 1600, 1200, 70, 0 },
687 { 1600, 1200, 75, 0 },
688 { 1600, 1200, 85, 0 },
689 { 1792, 1344, 60, 0 },
690 { 1792, 1344, 75, 0 },
691 { 1856, 1392, 60, 0 },
692 { 1856, 1392, 75, 0 },
693 { 1920, 1200, 60, 1 },
694 { 1920, 1200, 60, 0 },
696 { 1920, 1200, 75, 0 },
697 { 1920, 1200, 85, 0 },
698 { 1920, 1440, 60, 0 },
699 { 1920, 1440, 75, 0 },
702 static const struct minimode extra_modes[] = {
703 { 1024, 576, 60, 0 },
704 { 1366, 768, 60, 0 },
705 { 1600, 900, 60, 0 },
706 { 1680, 945, 60, 0 },
707 { 1920, 1080, 60, 0 },
708 { 2048, 1152, 60, 0 },
709 { 2048, 1536, 60, 0 },
713 * From CEA/CTA-861 spec.
715 * Do not access directly, instead always use cea_mode_for_vic().
717 static const struct drm_display_mode edid_cea_modes_1[] = {
718 /* 1 - 640x480@60Hz 4:3 */
719 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
720 752, 800, 0, 480, 490, 492, 525, 0,
721 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
722 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
723 /* 2 - 720x480@60Hz 4:3 */
724 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
725 798, 858, 0, 480, 489, 495, 525, 0,
726 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
727 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
728 /* 3 - 720x480@60Hz 16:9 */
729 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
730 798, 858, 0, 480, 489, 495, 525, 0,
731 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
732 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
733 /* 4 - 1280x720@60Hz 16:9 */
734 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
735 1430, 1650, 0, 720, 725, 730, 750, 0,
736 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
737 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
738 /* 5 - 1920x1080i@60Hz 16:9 */
739 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
740 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
741 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
742 DRM_MODE_FLAG_INTERLACE),
743 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
744 /* 6 - 720(1440)x480i@60Hz 4:3 */
745 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
746 801, 858, 0, 480, 488, 494, 525, 0,
747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
748 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
749 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
750 /* 7 - 720(1440)x480i@60Hz 16:9 */
751 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
752 801, 858, 0, 480, 488, 494, 525, 0,
753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
754 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
755 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
756 /* 8 - 720(1440)x240@60Hz 4:3 */
757 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
758 801, 858, 0, 240, 244, 247, 262, 0,
759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
760 DRM_MODE_FLAG_DBLCLK),
761 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
762 /* 9 - 720(1440)x240@60Hz 16:9 */
763 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
764 801, 858, 0, 240, 244, 247, 262, 0,
765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
766 DRM_MODE_FLAG_DBLCLK),
767 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
768 /* 10 - 2880x480i@60Hz 4:3 */
769 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
770 3204, 3432, 0, 480, 488, 494, 525, 0,
771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
772 DRM_MODE_FLAG_INTERLACE),
773 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
774 /* 11 - 2880x480i@60Hz 16:9 */
775 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
776 3204, 3432, 0, 480, 488, 494, 525, 0,
777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
778 DRM_MODE_FLAG_INTERLACE),
779 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
780 /* 12 - 2880x240@60Hz 4:3 */
781 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
782 3204, 3432, 0, 240, 244, 247, 262, 0,
783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
784 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
785 /* 13 - 2880x240@60Hz 16:9 */
786 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
787 3204, 3432, 0, 240, 244, 247, 262, 0,
788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
789 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
790 /* 14 - 1440x480@60Hz 4:3 */
791 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
792 1596, 1716, 0, 480, 489, 495, 525, 0,
793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
794 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
795 /* 15 - 1440x480@60Hz 16:9 */
796 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
797 1596, 1716, 0, 480, 489, 495, 525, 0,
798 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
799 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
800 /* 16 - 1920x1080@60Hz 16:9 */
801 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
802 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
803 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
804 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
805 /* 17 - 720x576@50Hz 4:3 */
806 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
807 796, 864, 0, 576, 581, 586, 625, 0,
808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
809 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
810 /* 18 - 720x576@50Hz 16:9 */
811 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
812 796, 864, 0, 576, 581, 586, 625, 0,
813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
814 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
815 /* 19 - 1280x720@50Hz 16:9 */
816 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
817 1760, 1980, 0, 720, 725, 730, 750, 0,
818 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
819 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
820 /* 20 - 1920x1080i@50Hz 16:9 */
821 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
822 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
824 DRM_MODE_FLAG_INTERLACE),
825 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
826 /* 21 - 720(1440)x576i@50Hz 4:3 */
827 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
828 795, 864, 0, 576, 580, 586, 625, 0,
829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
830 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
831 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
832 /* 22 - 720(1440)x576i@50Hz 16:9 */
833 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
834 795, 864, 0, 576, 580, 586, 625, 0,
835 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
836 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
837 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
838 /* 23 - 720(1440)x288@50Hz 4:3 */
839 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
840 795, 864, 0, 288, 290, 293, 312, 0,
841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
842 DRM_MODE_FLAG_DBLCLK),
843 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
844 /* 24 - 720(1440)x288@50Hz 16:9 */
845 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
846 795, 864, 0, 288, 290, 293, 312, 0,
847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
848 DRM_MODE_FLAG_DBLCLK),
849 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
850 /* 25 - 2880x576i@50Hz 4:3 */
851 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
852 3180, 3456, 0, 576, 580, 586, 625, 0,
853 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
854 DRM_MODE_FLAG_INTERLACE),
855 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
856 /* 26 - 2880x576i@50Hz 16:9 */
857 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
858 3180, 3456, 0, 576, 580, 586, 625, 0,
859 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
860 DRM_MODE_FLAG_INTERLACE),
861 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
862 /* 27 - 2880x288@50Hz 4:3 */
863 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
864 3180, 3456, 0, 288, 290, 293, 312, 0,
865 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
866 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
867 /* 28 - 2880x288@50Hz 16:9 */
868 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
869 3180, 3456, 0, 288, 290, 293, 312, 0,
870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
871 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
872 /* 29 - 1440x576@50Hz 4:3 */
873 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
874 1592, 1728, 0, 576, 581, 586, 625, 0,
875 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
876 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
877 /* 30 - 1440x576@50Hz 16:9 */
878 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
879 1592, 1728, 0, 576, 581, 586, 625, 0,
880 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
881 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
882 /* 31 - 1920x1080@50Hz 16:9 */
883 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
884 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
885 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
886 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
887 /* 32 - 1920x1080@24Hz 16:9 */
888 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
889 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
890 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
891 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
892 /* 33 - 1920x1080@25Hz 16:9 */
893 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
894 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
895 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
896 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
897 /* 34 - 1920x1080@30Hz 16:9 */
898 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
899 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
900 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
901 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
902 /* 35 - 2880x480@60Hz 4:3 */
903 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
904 3192, 3432, 0, 480, 489, 495, 525, 0,
905 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
906 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
907 /* 36 - 2880x480@60Hz 16:9 */
908 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
909 3192, 3432, 0, 480, 489, 495, 525, 0,
910 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
911 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
912 /* 37 - 2880x576@50Hz 4:3 */
913 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
914 3184, 3456, 0, 576, 581, 586, 625, 0,
915 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
916 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
917 /* 38 - 2880x576@50Hz 16:9 */
918 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
919 3184, 3456, 0, 576, 581, 586, 625, 0,
920 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
921 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
922 /* 39 - 1920x1080i@50Hz 16:9 */
923 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
924 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
925 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
926 DRM_MODE_FLAG_INTERLACE),
927 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
928 /* 40 - 1920x1080i@100Hz 16:9 */
929 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
930 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
931 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
932 DRM_MODE_FLAG_INTERLACE),
933 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
934 /* 41 - 1280x720@100Hz 16:9 */
935 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
936 1760, 1980, 0, 720, 725, 730, 750, 0,
937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
938 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
939 /* 42 - 720x576@100Hz 4:3 */
940 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
941 796, 864, 0, 576, 581, 586, 625, 0,
942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
943 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
944 /* 43 - 720x576@100Hz 16:9 */
945 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
946 796, 864, 0, 576, 581, 586, 625, 0,
947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
948 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
949 /* 44 - 720(1440)x576i@100Hz 4:3 */
950 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
951 795, 864, 0, 576, 580, 586, 625, 0,
952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
953 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
954 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
955 /* 45 - 720(1440)x576i@100Hz 16:9 */
956 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
957 795, 864, 0, 576, 580, 586, 625, 0,
958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
959 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
960 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
961 /* 46 - 1920x1080i@120Hz 16:9 */
962 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
963 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
964 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
965 DRM_MODE_FLAG_INTERLACE),
966 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
967 /* 47 - 1280x720@120Hz 16:9 */
968 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
969 1430, 1650, 0, 720, 725, 730, 750, 0,
970 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
971 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
972 /* 48 - 720x480@120Hz 4:3 */
973 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
974 798, 858, 0, 480, 489, 495, 525, 0,
975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
976 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
977 /* 49 - 720x480@120Hz 16:9 */
978 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
979 798, 858, 0, 480, 489, 495, 525, 0,
980 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
981 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
982 /* 50 - 720(1440)x480i@120Hz 4:3 */
983 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
984 801, 858, 0, 480, 488, 494, 525, 0,
985 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
986 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
987 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
988 /* 51 - 720(1440)x480i@120Hz 16:9 */
989 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
990 801, 858, 0, 480, 488, 494, 525, 0,
991 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
992 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
993 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
994 /* 52 - 720x576@200Hz 4:3 */
995 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
996 796, 864, 0, 576, 581, 586, 625, 0,
997 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
998 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
999 /* 53 - 720x576@200Hz 16:9 */
1000 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1001 796, 864, 0, 576, 581, 586, 625, 0,
1002 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1003 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1004 /* 54 - 720(1440)x576i@200Hz 4:3 */
1005 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1006 795, 864, 0, 576, 580, 586, 625, 0,
1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1008 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1009 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1010 /* 55 - 720(1440)x576i@200Hz 16:9 */
1011 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1012 795, 864, 0, 576, 580, 586, 625, 0,
1013 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1014 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1015 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1016 /* 56 - 720x480@240Hz 4:3 */
1017 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1018 798, 858, 0, 480, 489, 495, 525, 0,
1019 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1020 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1021 /* 57 - 720x480@240Hz 16:9 */
1022 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1023 798, 858, 0, 480, 489, 495, 525, 0,
1024 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1025 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1026 /* 58 - 720(1440)x480i@240Hz 4:3 */
1027 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1028 801, 858, 0, 480, 488, 494, 525, 0,
1029 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1030 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1031 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1032 /* 59 - 720(1440)x480i@240Hz 16:9 */
1033 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1034 801, 858, 0, 480, 488, 494, 525, 0,
1035 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1036 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1037 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1038 /* 60 - 1280x720@24Hz 16:9 */
1039 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1040 3080, 3300, 0, 720, 725, 730, 750, 0,
1041 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1042 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1043 /* 61 - 1280x720@25Hz 16:9 */
1044 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1045 3740, 3960, 0, 720, 725, 730, 750, 0,
1046 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1047 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1048 /* 62 - 1280x720@30Hz 16:9 */
1049 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1050 3080, 3300, 0, 720, 725, 730, 750, 0,
1051 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1052 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1053 /* 63 - 1920x1080@120Hz 16:9 */
1054 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1055 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1056 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1057 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1058 /* 64 - 1920x1080@100Hz 16:9 */
1059 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1060 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1061 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1062 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1063 /* 65 - 1280x720@24Hz 64:27 */
1064 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1065 3080, 3300, 0, 720, 725, 730, 750, 0,
1066 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1067 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1068 /* 66 - 1280x720@25Hz 64:27 */
1069 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1070 3740, 3960, 0, 720, 725, 730, 750, 0,
1071 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1072 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1073 /* 67 - 1280x720@30Hz 64:27 */
1074 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1075 3080, 3300, 0, 720, 725, 730, 750, 0,
1076 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1077 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1078 /* 68 - 1280x720@50Hz 64:27 */
1079 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1080 1760, 1980, 0, 720, 725, 730, 750, 0,
1081 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1082 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1083 /* 69 - 1280x720@60Hz 64:27 */
1084 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1085 1430, 1650, 0, 720, 725, 730, 750, 0,
1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1087 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1088 /* 70 - 1280x720@100Hz 64:27 */
1089 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1090 1760, 1980, 0, 720, 725, 730, 750, 0,
1091 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1092 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1093 /* 71 - 1280x720@120Hz 64:27 */
1094 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1095 1430, 1650, 0, 720, 725, 730, 750, 0,
1096 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1097 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1098 /* 72 - 1920x1080@24Hz 64:27 */
1099 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1100 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1101 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1102 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1103 /* 73 - 1920x1080@25Hz 64:27 */
1104 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1105 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1107 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1108 /* 74 - 1920x1080@30Hz 64:27 */
1109 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1110 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1111 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1112 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1113 /* 75 - 1920x1080@50Hz 64:27 */
1114 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1115 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1116 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1117 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1118 /* 76 - 1920x1080@60Hz 64:27 */
1119 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1120 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1121 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1122 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1123 /* 77 - 1920x1080@100Hz 64:27 */
1124 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1125 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1127 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1128 /* 78 - 1920x1080@120Hz 64:27 */
1129 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1130 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1131 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1132 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1133 /* 79 - 1680x720@24Hz 64:27 */
1134 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1135 3080, 3300, 0, 720, 725, 730, 750, 0,
1136 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1137 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1138 /* 80 - 1680x720@25Hz 64:27 */
1139 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1140 2948, 3168, 0, 720, 725, 730, 750, 0,
1141 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1142 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1143 /* 81 - 1680x720@30Hz 64:27 */
1144 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1145 2420, 2640, 0, 720, 725, 730, 750, 0,
1146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1147 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1148 /* 82 - 1680x720@50Hz 64:27 */
1149 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1150 1980, 2200, 0, 720, 725, 730, 750, 0,
1151 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1152 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1153 /* 83 - 1680x720@60Hz 64:27 */
1154 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1155 1980, 2200, 0, 720, 725, 730, 750, 0,
1156 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1157 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1158 /* 84 - 1680x720@100Hz 64:27 */
1159 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1160 1780, 2000, 0, 720, 725, 730, 825, 0,
1161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1162 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1163 /* 85 - 1680x720@120Hz 64:27 */
1164 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1165 1780, 2000, 0, 720, 725, 730, 825, 0,
1166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1167 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1168 /* 86 - 2560x1080@24Hz 64:27 */
1169 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1170 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1171 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1172 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1173 /* 87 - 2560x1080@25Hz 64:27 */
1174 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1175 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1176 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1177 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1178 /* 88 - 2560x1080@30Hz 64:27 */
1179 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1180 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1182 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1183 /* 89 - 2560x1080@50Hz 64:27 */
1184 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1185 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1187 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1188 /* 90 - 2560x1080@60Hz 64:27 */
1189 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1190 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1192 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1193 /* 91 - 2560x1080@100Hz 64:27 */
1194 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1195 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1197 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1198 /* 92 - 2560x1080@120Hz 64:27 */
1199 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1200 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1202 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1203 /* 93 - 3840x2160@24Hz 16:9 */
1204 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1205 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1207 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1208 /* 94 - 3840x2160@25Hz 16:9 */
1209 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1210 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1212 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1213 /* 95 - 3840x2160@30Hz 16:9 */
1214 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1215 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1217 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1218 /* 96 - 3840x2160@50Hz 16:9 */
1219 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1220 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1222 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1223 /* 97 - 3840x2160@60Hz 16:9 */
1224 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1225 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1227 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1228 /* 98 - 4096x2160@24Hz 256:135 */
1229 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1230 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1232 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1233 /* 99 - 4096x2160@25Hz 256:135 */
1234 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1235 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1237 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1238 /* 100 - 4096x2160@30Hz 256:135 */
1239 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1240 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1242 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1243 /* 101 - 4096x2160@50Hz 256:135 */
1244 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1245 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1247 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1248 /* 102 - 4096x2160@60Hz 256:135 */
1249 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1250 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1252 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1253 /* 103 - 3840x2160@24Hz 64:27 */
1254 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1255 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1257 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1258 /* 104 - 3840x2160@25Hz 64:27 */
1259 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1260 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1262 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1263 /* 105 - 3840x2160@30Hz 64:27 */
1264 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1265 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1267 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1268 /* 106 - 3840x2160@50Hz 64:27 */
1269 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1270 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1272 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1273 /* 107 - 3840x2160@60Hz 64:27 */
1274 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1275 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1277 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1278 /* 108 - 1280x720@48Hz 16:9 */
1279 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1280 2280, 2500, 0, 720, 725, 730, 750, 0,
1281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1282 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1283 /* 109 - 1280x720@48Hz 64:27 */
1284 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1285 2280, 2500, 0, 720, 725, 730, 750, 0,
1286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1287 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1288 /* 110 - 1680x720@48Hz 64:27 */
1289 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1290 2530, 2750, 0, 720, 725, 730, 750, 0,
1291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1292 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1293 /* 111 - 1920x1080@48Hz 16:9 */
1294 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1295 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1297 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1298 /* 112 - 1920x1080@48Hz 64:27 */
1299 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1300 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1302 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1303 /* 113 - 2560x1080@48Hz 64:27 */
1304 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1305 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1307 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1308 /* 114 - 3840x2160@48Hz 16:9 */
1309 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1310 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1312 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1313 /* 115 - 4096x2160@48Hz 256:135 */
1314 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1315 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1317 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1318 /* 116 - 3840x2160@48Hz 64:27 */
1319 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1320 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1322 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1323 /* 117 - 3840x2160@100Hz 16:9 */
1324 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1325 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1327 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1328 /* 118 - 3840x2160@120Hz 16:9 */
1329 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1330 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1332 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1333 /* 119 - 3840x2160@100Hz 64:27 */
1334 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1335 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1337 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1338 /* 120 - 3840x2160@120Hz 64:27 */
1339 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1340 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1342 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1343 /* 121 - 5120x2160@24Hz 64:27 */
1344 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1345 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1347 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1348 /* 122 - 5120x2160@25Hz 64:27 */
1349 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1350 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1352 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1353 /* 123 - 5120x2160@30Hz 64:27 */
1354 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1355 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1357 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1358 /* 124 - 5120x2160@48Hz 64:27 */
1359 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1360 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1362 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1363 /* 125 - 5120x2160@50Hz 64:27 */
1364 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1365 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1367 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1368 /* 126 - 5120x2160@60Hz 64:27 */
1369 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1370 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1372 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1373 /* 127 - 5120x2160@100Hz 64:27 */
1374 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1375 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1377 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1381 * From CEA/CTA-861 spec.
1383 * Do not access directly, instead always use cea_mode_for_vic().
1385 static const struct drm_display_mode edid_cea_modes_193[] = {
1386 /* 193 - 5120x2160@120Hz 64:27 */
1387 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1388 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1390 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1391 /* 194 - 7680x4320@24Hz 16:9 */
1392 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1393 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1395 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1396 /* 195 - 7680x4320@25Hz 16:9 */
1397 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1398 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1400 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1401 /* 196 - 7680x4320@30Hz 16:9 */
1402 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1403 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1405 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1406 /* 197 - 7680x4320@48Hz 16:9 */
1407 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1408 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1410 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1411 /* 198 - 7680x4320@50Hz 16:9 */
1412 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1413 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1415 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1416 /* 199 - 7680x4320@60Hz 16:9 */
1417 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1418 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1420 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1421 /* 200 - 7680x4320@100Hz 16:9 */
1422 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1423 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1425 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1426 /* 201 - 7680x4320@120Hz 16:9 */
1427 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1428 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1430 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1431 /* 202 - 7680x4320@24Hz 64:27 */
1432 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1433 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1435 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1436 /* 203 - 7680x4320@25Hz 64:27 */
1437 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1438 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1440 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1441 /* 204 - 7680x4320@30Hz 64:27 */
1442 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1443 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1445 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1446 /* 205 - 7680x4320@48Hz 64:27 */
1447 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1448 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1450 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1451 /* 206 - 7680x4320@50Hz 64:27 */
1452 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1453 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1455 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1456 /* 207 - 7680x4320@60Hz 64:27 */
1457 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1458 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1460 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1461 /* 208 - 7680x4320@100Hz 64:27 */
1462 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1463 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1465 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1466 /* 209 - 7680x4320@120Hz 64:27 */
1467 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1468 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1470 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1471 /* 210 - 10240x4320@24Hz 64:27 */
1472 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1473 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1475 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1476 /* 211 - 10240x4320@25Hz 64:27 */
1477 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1478 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1479 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1480 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1481 /* 212 - 10240x4320@30Hz 64:27 */
1482 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1483 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1485 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1486 /* 213 - 10240x4320@48Hz 64:27 */
1487 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1488 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1490 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1491 /* 214 - 10240x4320@50Hz 64:27 */
1492 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1493 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1494 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1495 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1496 /* 215 - 10240x4320@60Hz 64:27 */
1497 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1498 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1500 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1501 /* 216 - 10240x4320@100Hz 64:27 */
1502 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1503 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1505 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1506 /* 217 - 10240x4320@120Hz 64:27 */
1507 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1508 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1510 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1511 /* 218 - 4096x2160@100Hz 256:135 */
1512 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1513 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1515 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1516 /* 219 - 4096x2160@120Hz 256:135 */
1517 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1518 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1520 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1524 * HDMI 1.4 4k modes. Index using the VIC.
1526 static const struct drm_display_mode edid_4k_modes[] = {
1527 /* 0 - dummy, VICs start at 1 */
1529 /* 1 - 3840x2160@30Hz */
1530 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1531 3840, 4016, 4104, 4400, 0,
1532 2160, 2168, 2178, 2250, 0,
1533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1534 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1535 /* 2 - 3840x2160@25Hz */
1536 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1537 3840, 4896, 4984, 5280, 0,
1538 2160, 2168, 2178, 2250, 0,
1539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1540 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1541 /* 3 - 3840x2160@24Hz */
1542 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1543 3840, 5116, 5204, 5500, 0,
1544 2160, 2168, 2178, 2250, 0,
1545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1546 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1547 /* 4 - 4096x2160@24Hz (SMPTE) */
1548 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1549 4096, 5116, 5204, 5500, 0,
1550 2160, 2168, 2178, 2250, 0,
1551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1552 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1555 /*** DDC fetch and block validation ***/
1557 static const u8 edid_header[] = {
1558 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1562 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1563 * @raw_edid: pointer to raw base EDID block
1565 * Sanity check the header of the base EDID block.
1567 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1569 int drm_edid_header_is_valid(const u8 *raw_edid)
1573 for (i = 0; i < sizeof(edid_header); i++)
1574 if (raw_edid[i] == edid_header[i])
1579 EXPORT_SYMBOL(drm_edid_header_is_valid);
1581 static int edid_fixup __read_mostly = 6;
1582 module_param_named(edid_fixup, edid_fixup, int, 0400);
1583 MODULE_PARM_DESC(edid_fixup,
1584 "Minimum number of valid EDID header bytes (0-8, default 6)");
1586 static int validate_displayid(u8 *displayid, int length, int idx);
1588 static int drm_edid_block_checksum(const u8 *raw_edid)
1591 u8 csum = 0, crc = 0;
1593 for (i = 0; i < EDID_LENGTH - 1; i++)
1594 csum += raw_edid[i];
1601 static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum)
1603 if (raw_edid[EDID_LENGTH - 1] != real_checksum)
1609 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1611 if (memchr_inv(in_edid, 0, length))
1618 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1619 * @raw_edid: pointer to raw EDID block
1620 * @block: type of block to validate (0 for base, extension otherwise)
1621 * @print_bad_edid: if true, dump bad EDID blocks to the console
1622 * @edid_corrupt: if true, the header or checksum is invalid
1624 * Validate a base or extension EDID block and optionally dump bad blocks to
1627 * Return: True if the block is valid, false otherwise.
1629 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1633 struct edid *edid = (struct edid *)raw_edid;
1635 if (WARN_ON(!raw_edid))
1638 if (edid_fixup > 8 || edid_fixup < 0)
1642 int score = drm_edid_header_is_valid(raw_edid);
1645 *edid_corrupt = false;
1646 } else if (score >= edid_fixup) {
1647 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1648 * The corrupt flag needs to be set here otherwise, the
1649 * fix-up code here will correct the problem, the
1650 * checksum is correct and the test fails
1653 *edid_corrupt = true;
1654 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1655 memcpy(raw_edid, edid_header, sizeof(edid_header));
1658 *edid_corrupt = true;
1663 csum = drm_edid_block_checksum(raw_edid);
1664 if (drm_edid_block_checksum_diff(raw_edid, csum)) {
1666 *edid_corrupt = true;
1668 /* allow CEA to slide through, switches mangle this */
1669 if (raw_edid[0] == CEA_EXT) {
1670 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1671 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1674 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1680 /* per-block-type checks */
1681 switch (raw_edid[0]) {
1683 if (edid->version != 1) {
1684 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1688 if (edid->revision > 4)
1689 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1699 if (print_bad_edid) {
1700 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1701 pr_notice("EDID block is all zeroes\n");
1703 pr_notice("Raw EDID:\n");
1704 print_hex_dump(KERN_NOTICE,
1705 " \t", DUMP_PREFIX_NONE, 16, 1,
1706 raw_edid, EDID_LENGTH, false);
1711 EXPORT_SYMBOL(drm_edid_block_valid);
1714 * drm_edid_is_valid - sanity check EDID data
1717 * Sanity-check an entire EDID record (including extensions)
1719 * Return: True if the EDID data is valid, false otherwise.
1721 bool drm_edid_is_valid(struct edid *edid)
1724 u8 *raw = (u8 *)edid;
1729 for (i = 0; i <= edid->extensions; i++)
1730 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1735 EXPORT_SYMBOL(drm_edid_is_valid);
1737 #define DDC_SEGMENT_ADDR 0x30
1739 * drm_do_probe_ddc_edid() - get EDID information via I2C
1740 * @data: I2C device adapter
1741 * @buf: EDID data buffer to be filled
1742 * @block: 128 byte EDID block to start fetching from
1743 * @len: EDID data buffer length to fetch
1745 * Try to fetch EDID information by calling I2C driver functions.
1747 * Return: 0 on success or -1 on failure.
1750 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1752 struct i2c_adapter *adapter = data;
1753 unsigned char start = block * EDID_LENGTH;
1754 unsigned char segment = block >> 1;
1755 unsigned char xfers = segment ? 3 : 2;
1756 int ret, retries = 5;
1759 * The core I2C driver will automatically retry the transfer if the
1760 * adapter reports EAGAIN. However, we find that bit-banging transfers
1761 * are susceptible to errors under a heavily loaded machine and
1762 * generate spurious NAKs and timeouts. Retrying the transfer
1763 * of the individual block a few times seems to overcome this.
1766 struct i2c_msg msgs[] = {
1768 .addr = DDC_SEGMENT_ADDR,
1786 * Avoid sending the segment addr to not upset non-compliant
1789 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1791 if (ret == -ENXIO) {
1792 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1796 } while (ret != xfers && --retries);
1798 return ret == xfers ? 0 : -1;
1801 static void connector_bad_edid(struct drm_connector *connector,
1802 u8 *edid, int num_blocks)
1805 u8 num_of_ext = edid[0x7e];
1807 /* Calculate real checksum for the last edid extension block data */
1808 connector->real_edid_checksum =
1809 drm_edid_block_checksum(edid + num_of_ext * EDID_LENGTH);
1811 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
1814 dev_warn(connector->dev->dev,
1815 "%s: EDID is invalid:\n",
1817 for (i = 0; i < num_blocks; i++) {
1818 u8 *block = edid + i * EDID_LENGTH;
1821 if (drm_edid_is_zero(block, EDID_LENGTH))
1822 sprintf(prefix, "\t[%02x] ZERO ", i);
1823 else if (!drm_edid_block_valid(block, i, false, NULL))
1824 sprintf(prefix, "\t[%02x] BAD ", i);
1826 sprintf(prefix, "\t[%02x] GOOD ", i);
1828 print_hex_dump(KERN_WARNING,
1829 prefix, DUMP_PREFIX_NONE, 16, 1,
1830 block, EDID_LENGTH, false);
1834 /* Get override or firmware EDID */
1835 static struct edid *drm_get_override_edid(struct drm_connector *connector)
1837 struct edid *override = NULL;
1839 if (connector->override_edid)
1840 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1843 override = drm_load_edid_firmware(connector);
1845 return IS_ERR(override) ? NULL : override;
1849 * drm_add_override_edid_modes - add modes from override/firmware EDID
1850 * @connector: connector we're probing
1852 * Add modes from the override/firmware EDID, if available. Only to be used from
1853 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1854 * failed during drm_get_edid() and caused the override/firmware EDID to be
1857 * Return: The number of modes added or 0 if we couldn't find any.
1859 int drm_add_override_edid_modes(struct drm_connector *connector)
1861 struct edid *override;
1864 override = drm_get_override_edid(connector);
1866 drm_connector_update_edid_property(connector, override);
1867 num_modes = drm_add_edid_modes(connector, override);
1870 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1871 connector->base.id, connector->name, num_modes);
1876 EXPORT_SYMBOL(drm_add_override_edid_modes);
1879 * drm_do_get_edid - get EDID data using a custom EDID block read function
1880 * @connector: connector we're probing
1881 * @get_edid_block: EDID block read function
1882 * @data: private data passed to the block read function
1884 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1885 * exposes a different interface to read EDID blocks this function can be used
1886 * to get EDID data using a custom block read function.
1888 * As in the general case the DDC bus is accessible by the kernel at the I2C
1889 * level, drivers must make all reasonable efforts to expose it as an I2C
1890 * adapter and use drm_get_edid() instead of abusing this function.
1892 * The EDID may be overridden using debugfs override_edid or firmare EDID
1893 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1894 * order. Having either of them bypasses actual EDID reads.
1896 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1898 struct edid *drm_do_get_edid(struct drm_connector *connector,
1899 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1903 int i, j = 0, valid_extensions = 0;
1905 struct edid *override;
1907 override = drm_get_override_edid(connector);
1911 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1914 /* base block fetch */
1915 for (i = 0; i < 4; i++) {
1916 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1918 if (drm_edid_block_valid(edid, 0, false,
1919 &connector->edid_corrupt))
1921 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1922 connector->null_edid_counter++;
1929 /* if there's no extensions, we're done */
1930 valid_extensions = edid[0x7e];
1931 if (valid_extensions == 0)
1932 return (struct edid *)edid;
1934 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1939 for (j = 1; j <= edid[0x7e]; j++) {
1940 u8 *block = edid + j * EDID_LENGTH;
1942 for (i = 0; i < 4; i++) {
1943 if (get_edid_block(data, block, j, EDID_LENGTH))
1945 if (drm_edid_block_valid(block, j, false, NULL))
1953 if (valid_extensions != edid[0x7e]) {
1956 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1958 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1959 edid[0x7e] = valid_extensions;
1961 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1967 for (i = 0; i <= edid[0x7e]; i++) {
1968 u8 *block = edid + i * EDID_LENGTH;
1970 if (!drm_edid_block_valid(block, i, false, NULL))
1973 memcpy(base, block, EDID_LENGTH);
1974 base += EDID_LENGTH;
1981 return (struct edid *)edid;
1984 connector_bad_edid(connector, edid, 1);
1989 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1992 * drm_probe_ddc() - probe DDC presence
1993 * @adapter: I2C adapter to probe
1995 * Return: True on success, false on failure.
1998 drm_probe_ddc(struct i2c_adapter *adapter)
2002 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2004 EXPORT_SYMBOL(drm_probe_ddc);
2007 * drm_get_edid - get EDID data, if available
2008 * @connector: connector we're probing
2009 * @adapter: I2C adapter to use for DDC
2011 * Poke the given I2C channel to grab EDID data if possible. If found,
2012 * attach it to the connector.
2014 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2016 struct edid *drm_get_edid(struct drm_connector *connector,
2017 struct i2c_adapter *adapter)
2019 if (connector->force == DRM_FORCE_OFF)
2022 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2025 return drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
2027 EXPORT_SYMBOL(drm_get_edid);
2030 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2031 * @connector: connector we're probing
2032 * @adapter: I2C adapter to use for DDC
2034 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2035 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2036 * switch DDC to the GPU which is retrieving EDID.
2038 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2040 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2041 struct i2c_adapter *adapter)
2043 struct pci_dev *pdev = connector->dev->pdev;
2046 vga_switcheroo_lock_ddc(pdev);
2047 edid = drm_get_edid(connector, adapter);
2048 vga_switcheroo_unlock_ddc(pdev);
2052 EXPORT_SYMBOL(drm_get_edid_switcheroo);
2055 * drm_edid_duplicate - duplicate an EDID and the extensions
2056 * @edid: EDID to duplicate
2058 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2060 struct edid *drm_edid_duplicate(const struct edid *edid)
2062 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2064 EXPORT_SYMBOL(drm_edid_duplicate);
2066 /*** EDID parsing ***/
2069 * edid_vendor - match a string against EDID's obfuscated vendor field
2070 * @edid: EDID to match
2071 * @vendor: vendor string
2073 * Returns true if @vendor is in @edid, false otherwise
2075 static bool edid_vendor(const struct edid *edid, const char *vendor)
2077 char edid_vendor[3];
2079 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
2080 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
2081 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
2082 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
2084 return !strncmp(edid_vendor, vendor, 3);
2088 * edid_get_quirks - return quirk flags for a given EDID
2089 * @edid: EDID to process
2091 * This tells subsequent routines what fixes they need to apply.
2093 static u32 edid_get_quirks(const struct edid *edid)
2095 const struct edid_quirk *quirk;
2098 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2099 quirk = &edid_quirk_list[i];
2101 if (edid_vendor(edid, quirk->vendor) &&
2102 (EDID_PRODUCT_ID(edid) == quirk->product_id))
2103 return quirk->quirks;
2109 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2110 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2113 * edid_fixup_preferred - set preferred modes based on quirk list
2114 * @connector: has mode list to fix up
2115 * @quirks: quirks list
2117 * Walk the mode list for @connector, clearing the preferred status
2118 * on existing modes and setting it anew for the right mode ala @quirks.
2120 static void edid_fixup_preferred(struct drm_connector *connector,
2123 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2124 int target_refresh = 0;
2125 int cur_vrefresh, preferred_vrefresh;
2127 if (list_empty(&connector->probed_modes))
2130 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2131 target_refresh = 60;
2132 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2133 target_refresh = 75;
2135 preferred_mode = list_first_entry(&connector->probed_modes,
2136 struct drm_display_mode, head);
2138 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2139 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2141 if (cur_mode == preferred_mode)
2144 /* Largest mode is preferred */
2145 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2146 preferred_mode = cur_mode;
2148 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2149 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2150 /* At a given size, try to get closest to target refresh */
2151 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2152 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2153 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2154 preferred_mode = cur_mode;
2158 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2162 mode_is_rb(const struct drm_display_mode *mode)
2164 return (mode->htotal - mode->hdisplay == 160) &&
2165 (mode->hsync_end - mode->hdisplay == 80) &&
2166 (mode->hsync_end - mode->hsync_start == 32) &&
2167 (mode->vsync_start - mode->vdisplay == 3);
2171 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2172 * @dev: Device to duplicate against
2173 * @hsize: Mode width
2174 * @vsize: Mode height
2175 * @fresh: Mode refresh rate
2176 * @rb: Mode reduced-blanking-ness
2178 * Walk the DMT mode list looking for a match for the given parameters.
2180 * Return: A newly allocated copy of the mode, or NULL if not found.
2182 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2183 int hsize, int vsize, int fresh,
2188 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2189 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2190 if (hsize != ptr->hdisplay)
2192 if (vsize != ptr->vdisplay)
2194 if (fresh != drm_mode_vrefresh(ptr))
2196 if (rb != mode_is_rb(ptr))
2199 return drm_mode_duplicate(dev, ptr);
2204 EXPORT_SYMBOL(drm_mode_find_dmt);
2206 static bool is_display_descriptor(const u8 d[18], u8 tag)
2208 return d[0] == 0x00 && d[1] == 0x00 &&
2209 d[2] == 0x00 && d[3] == tag;
2212 static bool is_detailed_timing_descriptor(const u8 d[18])
2214 return d[0] != 0x00 || d[1] != 0x00;
2217 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
2220 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2224 u8 *det_base = ext + d;
2226 if (d < 4 || d > 127)
2230 for (i = 0; i < n; i++)
2231 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2235 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2237 unsigned int i, n = min((int)ext[0x02], 6);
2238 u8 *det_base = ext + 5;
2241 return; /* unknown version */
2243 for (i = 0; i < n; i++)
2244 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2248 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
2251 struct edid *edid = (struct edid *)raw_edid;
2256 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2257 cb(&(edid->detailed_timings[i]), closure);
2259 for (i = 1; i <= raw_edid[0x7e]; i++) {
2260 u8 *ext = raw_edid + (i * EDID_LENGTH);
2263 cea_for_each_detailed_block(ext, cb, closure);
2266 vtb_for_each_detailed_block(ext, cb, closure);
2275 is_rb(struct detailed_timing *t, void *data)
2279 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2283 *(bool *)data = true;
2286 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2288 drm_monitor_supports_rb(struct edid *edid)
2290 if (edid->revision >= 4) {
2292 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2296 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2300 find_gtf2(struct detailed_timing *t, void *data)
2304 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2311 /* Secondary GTF curve kicks in above some break frequency */
2313 drm_gtf2_hbreak(struct edid *edid)
2316 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2317 return r ? (r[12] * 2) : 0;
2321 drm_gtf2_2c(struct edid *edid)
2324 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2325 return r ? r[13] : 0;
2329 drm_gtf2_m(struct edid *edid)
2332 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2333 return r ? (r[15] << 8) + r[14] : 0;
2337 drm_gtf2_k(struct edid *edid)
2340 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2341 return r ? r[16] : 0;
2345 drm_gtf2_2j(struct edid *edid)
2348 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2349 return r ? r[17] : 0;
2353 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2354 * @edid: EDID block to scan
2356 static int standard_timing_level(struct edid *edid)
2358 if (edid->revision >= 2) {
2359 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2361 if (drm_gtf2_hbreak(edid))
2363 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
2370 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2371 * monitors fill with ascii space (0x20) instead.
2374 bad_std_timing(u8 a, u8 b)
2376 return (a == 0x00 && b == 0x00) ||
2377 (a == 0x01 && b == 0x01) ||
2378 (a == 0x20 && b == 0x20);
2381 static int drm_mode_hsync(const struct drm_display_mode *mode)
2383 if (mode->htotal <= 0)
2386 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
2390 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2391 * @connector: connector of for the EDID block
2392 * @edid: EDID block to scan
2393 * @t: standard timing params
2395 * Take the standard timing params (in this case width, aspect, and refresh)
2396 * and convert them into a real mode using CVT/GTF/DMT.
2398 static struct drm_display_mode *
2399 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2400 struct std_timing *t)
2402 struct drm_device *dev = connector->dev;
2403 struct drm_display_mode *m, *mode = NULL;
2406 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2407 >> EDID_TIMING_ASPECT_SHIFT;
2408 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2409 >> EDID_TIMING_VFREQ_SHIFT;
2410 int timing_level = standard_timing_level(edid);
2412 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2415 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2416 hsize = t->hsize * 8 + 248;
2417 /* vrefresh_rate = vfreq + 60 */
2418 vrefresh_rate = vfreq + 60;
2419 /* the vdisplay is calculated based on the aspect ratio */
2420 if (aspect_ratio == 0) {
2421 if (edid->revision < 3)
2424 vsize = (hsize * 10) / 16;
2425 } else if (aspect_ratio == 1)
2426 vsize = (hsize * 3) / 4;
2427 else if (aspect_ratio == 2)
2428 vsize = (hsize * 4) / 5;
2430 vsize = (hsize * 9) / 16;
2432 /* HDTV hack, part 1 */
2433 if (vrefresh_rate == 60 &&
2434 ((hsize == 1360 && vsize == 765) ||
2435 (hsize == 1368 && vsize == 769))) {
2441 * If this connector already has a mode for this size and refresh
2442 * rate (because it came from detailed or CVT info), use that
2443 * instead. This way we don't have to guess at interlace or
2446 list_for_each_entry(m, &connector->probed_modes, head)
2447 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2448 drm_mode_vrefresh(m) == vrefresh_rate)
2451 /* HDTV hack, part 2 */
2452 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2453 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2457 mode->hdisplay = 1366;
2458 mode->hsync_start = mode->hsync_start - 1;
2459 mode->hsync_end = mode->hsync_end - 1;
2463 /* check whether it can be found in default mode table */
2464 if (drm_monitor_supports_rb(edid)) {
2465 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2470 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2474 /* okay, generate it */
2475 switch (timing_level) {
2479 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2483 * This is potentially wrong if there's ever a monitor with
2484 * more than one ranges section, each claiming a different
2485 * secondary GTF curve. Please don't do that.
2487 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2490 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2491 drm_mode_destroy(dev, mode);
2492 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2493 vrefresh_rate, 0, 0,
2501 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2509 * EDID is delightfully ambiguous about how interlaced modes are to be
2510 * encoded. Our internal representation is of frame height, but some
2511 * HDTV detailed timings are encoded as field height.
2513 * The format list here is from CEA, in frame size. Technically we
2514 * should be checking refresh rate too. Whatever.
2517 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2518 struct detailed_pixel_timing *pt)
2521 static const struct {
2523 } cea_interlaced[] = {
2533 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2536 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2537 if ((mode->hdisplay == cea_interlaced[i].w) &&
2538 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2539 mode->vdisplay *= 2;
2540 mode->vsync_start *= 2;
2541 mode->vsync_end *= 2;
2547 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2551 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2552 * @dev: DRM device (needed to create new mode)
2554 * @timing: EDID detailed timing info
2555 * @quirks: quirks to apply
2557 * An EDID detailed timing block contains enough info for us to create and
2558 * return a new struct drm_display_mode.
2560 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2562 struct detailed_timing *timing,
2565 struct drm_display_mode *mode;
2566 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2567 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2568 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2569 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2570 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2571 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2572 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2573 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2574 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2576 /* ignore tiny modes */
2577 if (hactive < 64 || vactive < 64)
2580 if (pt->misc & DRM_EDID_PT_STEREO) {
2581 DRM_DEBUG_KMS("stereo mode not supported\n");
2584 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2585 DRM_DEBUG_KMS("composite sync not supported\n");
2588 /* it is incorrect if hsync/vsync width is zero */
2589 if (!hsync_pulse_width || !vsync_pulse_width) {
2590 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2591 "Wrong Hsync/Vsync pulse width\n");
2595 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2596 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2603 mode = drm_mode_create(dev);
2607 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2608 timing->pixel_clock = cpu_to_le16(1088);
2610 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2612 mode->hdisplay = hactive;
2613 mode->hsync_start = mode->hdisplay + hsync_offset;
2614 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2615 mode->htotal = mode->hdisplay + hblank;
2617 mode->vdisplay = vactive;
2618 mode->vsync_start = mode->vdisplay + vsync_offset;
2619 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2620 mode->vtotal = mode->vdisplay + vblank;
2622 /* Some EDIDs have bogus h/vtotal values */
2623 if (mode->hsync_end > mode->htotal)
2624 mode->htotal = mode->hsync_end + 1;
2625 if (mode->vsync_end > mode->vtotal)
2626 mode->vtotal = mode->vsync_end + 1;
2628 drm_mode_do_interlace_quirk(mode, pt);
2630 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2631 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2634 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2635 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2636 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2637 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2640 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2641 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2643 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2644 mode->width_mm *= 10;
2645 mode->height_mm *= 10;
2648 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2649 mode->width_mm = edid->width_cm * 10;
2650 mode->height_mm = edid->height_cm * 10;
2653 mode->type = DRM_MODE_TYPE_DRIVER;
2654 drm_mode_set_name(mode);
2660 mode_in_hsync_range(const struct drm_display_mode *mode,
2661 struct edid *edid, u8 *t)
2663 int hsync, hmin, hmax;
2666 if (edid->revision >= 4)
2667 hmin += ((t[4] & 0x04) ? 255 : 0);
2669 if (edid->revision >= 4)
2670 hmax += ((t[4] & 0x08) ? 255 : 0);
2671 hsync = drm_mode_hsync(mode);
2673 return (hsync <= hmax && hsync >= hmin);
2677 mode_in_vsync_range(const struct drm_display_mode *mode,
2678 struct edid *edid, u8 *t)
2680 int vsync, vmin, vmax;
2683 if (edid->revision >= 4)
2684 vmin += ((t[4] & 0x01) ? 255 : 0);
2686 if (edid->revision >= 4)
2687 vmax += ((t[4] & 0x02) ? 255 : 0);
2688 vsync = drm_mode_vrefresh(mode);
2690 return (vsync <= vmax && vsync >= vmin);
2694 range_pixel_clock(struct edid *edid, u8 *t)
2697 if (t[9] == 0 || t[9] == 255)
2700 /* 1.4 with CVT support gives us real precision, yay */
2701 if (edid->revision >= 4 && t[10] == 0x04)
2702 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2704 /* 1.3 is pathetic, so fuzz up a bit */
2705 return t[9] * 10000 + 5001;
2709 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2710 struct detailed_timing *timing)
2713 u8 *t = (u8 *)timing;
2715 if (!mode_in_hsync_range(mode, edid, t))
2718 if (!mode_in_vsync_range(mode, edid, t))
2721 if ((max_clock = range_pixel_clock(edid, t)))
2722 if (mode->clock > max_clock)
2725 /* 1.4 max horizontal check */
2726 if (edid->revision >= 4 && t[10] == 0x04)
2727 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2730 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2736 static bool valid_inferred_mode(const struct drm_connector *connector,
2737 const struct drm_display_mode *mode)
2739 const struct drm_display_mode *m;
2742 list_for_each_entry(m, &connector->probed_modes, head) {
2743 if (mode->hdisplay == m->hdisplay &&
2744 mode->vdisplay == m->vdisplay &&
2745 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2746 return false; /* duplicated */
2747 if (mode->hdisplay <= m->hdisplay &&
2748 mode->vdisplay <= m->vdisplay)
2755 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2756 struct detailed_timing *timing)
2759 struct drm_display_mode *newmode;
2760 struct drm_device *dev = connector->dev;
2762 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2763 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2764 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2765 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2767 drm_mode_probed_add(connector, newmode);
2776 /* fix up 1366x768 mode from 1368x768;
2777 * GFT/CVT can't express 1366 width which isn't dividable by 8
2779 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2781 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2782 mode->hdisplay = 1366;
2783 mode->hsync_start--;
2785 drm_mode_set_name(mode);
2790 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2791 struct detailed_timing *timing)
2794 struct drm_display_mode *newmode;
2795 struct drm_device *dev = connector->dev;
2797 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2798 const struct minimode *m = &extra_modes[i];
2799 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2803 drm_mode_fixup_1366x768(newmode);
2804 if (!mode_in_range(newmode, edid, timing) ||
2805 !valid_inferred_mode(connector, newmode)) {
2806 drm_mode_destroy(dev, newmode);
2810 drm_mode_probed_add(connector, newmode);
2818 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2819 struct detailed_timing *timing)
2822 struct drm_display_mode *newmode;
2823 struct drm_device *dev = connector->dev;
2824 bool rb = drm_monitor_supports_rb(edid);
2826 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2827 const struct minimode *m = &extra_modes[i];
2828 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2832 drm_mode_fixup_1366x768(newmode);
2833 if (!mode_in_range(newmode, edid, timing) ||
2834 !valid_inferred_mode(connector, newmode)) {
2835 drm_mode_destroy(dev, newmode);
2839 drm_mode_probed_add(connector, newmode);
2847 do_inferred_modes(struct detailed_timing *timing, void *c)
2849 struct detailed_mode_closure *closure = c;
2850 struct detailed_non_pixel *data = &timing->data.other_data;
2851 struct detailed_data_monitor_range *range = &data->data.range;
2853 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
2856 closure->modes += drm_dmt_modes_for_range(closure->connector,
2860 if (!version_greater(closure->edid, 1, 1))
2861 return; /* GTF not defined yet */
2863 switch (range->flags) {
2864 case 0x02: /* secondary gtf, XXX could do more */
2865 case 0x00: /* default gtf */
2866 closure->modes += drm_gtf_modes_for_range(closure->connector,
2870 case 0x04: /* cvt, only in 1.4+ */
2871 if (!version_greater(closure->edid, 1, 3))
2874 closure->modes += drm_cvt_modes_for_range(closure->connector,
2878 case 0x01: /* just the ranges, no formula */
2885 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2887 struct detailed_mode_closure closure = {
2888 .connector = connector,
2892 if (version_greater(edid, 1, 0))
2893 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2896 return closure.modes;
2900 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2902 int i, j, m, modes = 0;
2903 struct drm_display_mode *mode;
2904 u8 *est = ((u8 *)timing) + 6;
2906 for (i = 0; i < 6; i++) {
2907 for (j = 7; j >= 0; j--) {
2908 m = (i * 8) + (7 - j);
2909 if (m >= ARRAY_SIZE(est3_modes))
2911 if (est[i] & (1 << j)) {
2912 mode = drm_mode_find_dmt(connector->dev,
2918 drm_mode_probed_add(connector, mode);
2929 do_established_modes(struct detailed_timing *timing, void *c)
2931 struct detailed_mode_closure *closure = c;
2933 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS))
2936 closure->modes += drm_est3_modes(closure->connector, timing);
2940 * add_established_modes - get est. modes from EDID and add them
2941 * @connector: connector to add mode(s) to
2942 * @edid: EDID block to scan
2944 * Each EDID block contains a bitmap of the supported "established modes" list
2945 * (defined above). Tease them out and add them to the global modes list.
2948 add_established_modes(struct drm_connector *connector, struct edid *edid)
2950 struct drm_device *dev = connector->dev;
2951 unsigned long est_bits = edid->established_timings.t1 |
2952 (edid->established_timings.t2 << 8) |
2953 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2955 struct detailed_mode_closure closure = {
2956 .connector = connector,
2960 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2961 if (est_bits & (1<<i)) {
2962 struct drm_display_mode *newmode;
2963 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2965 drm_mode_probed_add(connector, newmode);
2971 if (version_greater(edid, 1, 0))
2972 drm_for_each_detailed_block((u8 *)edid,
2973 do_established_modes, &closure);
2975 return modes + closure.modes;
2979 do_standard_modes(struct detailed_timing *timing, void *c)
2981 struct detailed_mode_closure *closure = c;
2982 struct detailed_non_pixel *data = &timing->data.other_data;
2983 struct drm_connector *connector = closure->connector;
2984 struct edid *edid = closure->edid;
2987 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES))
2990 for (i = 0; i < 6; i++) {
2991 struct std_timing *std = &data->data.timings[i];
2992 struct drm_display_mode *newmode;
2994 newmode = drm_mode_std(connector, edid, std);
2996 drm_mode_probed_add(connector, newmode);
3003 * add_standard_modes - get std. modes from EDID and add them
3004 * @connector: connector to add mode(s) to
3005 * @edid: EDID block to scan
3007 * Standard modes can be calculated using the appropriate standard (DMT,
3008 * GTF or CVT. Grab them from @edid and add them to the list.
3011 add_standard_modes(struct drm_connector *connector, struct edid *edid)
3014 struct detailed_mode_closure closure = {
3015 .connector = connector,
3019 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3020 struct drm_display_mode *newmode;
3022 newmode = drm_mode_std(connector, edid,
3023 &edid->standard_timings[i]);
3025 drm_mode_probed_add(connector, newmode);
3030 if (version_greater(edid, 1, 0))
3031 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
3034 /* XXX should also look for standard codes in VTB blocks */
3036 return modes + closure.modes;
3039 static int drm_cvt_modes(struct drm_connector *connector,
3040 struct detailed_timing *timing)
3042 int i, j, modes = 0;
3043 struct drm_display_mode *newmode;
3044 struct drm_device *dev = connector->dev;
3045 struct cvt_timing *cvt;
3046 const int rates[] = { 60, 85, 75, 60, 50 };
3047 const u8 empty[3] = { 0, 0, 0 };
3049 for (i = 0; i < 4; i++) {
3050 int uninitialized_var(width), height;
3051 cvt = &(timing->data.other_data.data.cvt[i]);
3053 if (!memcmp(cvt->code, empty, 3))
3056 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3057 switch (cvt->code[1] & 0x0c) {
3059 width = height * 4 / 3;
3062 width = height * 16 / 9;
3065 width = height * 16 / 10;
3068 width = height * 15 / 9;
3072 for (j = 1; j < 5; j++) {
3073 if (cvt->code[2] & (1 << j)) {
3074 newmode = drm_cvt_mode(dev, width, height,
3078 drm_mode_probed_add(connector, newmode);
3089 do_cvt_mode(struct detailed_timing *timing, void *c)
3091 struct detailed_mode_closure *closure = c;
3093 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE))
3096 closure->modes += drm_cvt_modes(closure->connector, timing);
3100 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
3102 struct detailed_mode_closure closure = {
3103 .connector = connector,
3107 if (version_greater(edid, 1, 2))
3108 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
3110 /* XXX should also look for CVT codes in VTB blocks */
3112 return closure.modes;
3115 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3118 do_detailed_mode(struct detailed_timing *timing, void *c)
3120 struct detailed_mode_closure *closure = c;
3121 struct drm_display_mode *newmode;
3123 if (!is_detailed_timing_descriptor((const u8 *)timing))
3126 newmode = drm_mode_detailed(closure->connector->dev,
3127 closure->edid, timing,
3132 if (closure->preferred)
3133 newmode->type |= DRM_MODE_TYPE_PREFERRED;
3136 * Detailed modes are limited to 10kHz pixel clock resolution,
3137 * so fix up anything that looks like CEA/HDMI mode, but the clock
3138 * is just slightly off.
3140 fixup_detailed_cea_mode_clock(newmode);
3142 drm_mode_probed_add(closure->connector, newmode);
3144 closure->preferred = false;
3148 * add_detailed_modes - Add modes from detailed timings
3149 * @connector: attached connector
3150 * @edid: EDID block to scan
3151 * @quirks: quirks to apply
3154 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
3157 struct detailed_mode_closure closure = {
3158 .connector = connector,
3164 if (closure.preferred && !version_greater(edid, 1, 3))
3166 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3168 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
3170 return closure.modes;
3173 #define AUDIO_BLOCK 0x01
3174 #define VIDEO_BLOCK 0x02
3175 #define VENDOR_BLOCK 0x03
3176 #define SPEAKER_BLOCK 0x04
3177 #define HDR_STATIC_METADATA_BLOCK 0x6
3178 #define USE_EXTENDED_TAG 0x07
3179 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
3180 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
3181 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
3182 #define EDID_BASIC_AUDIO (1 << 6)
3183 #define EDID_CEA_YCRCB444 (1 << 5)
3184 #define EDID_CEA_YCRCB422 (1 << 4)
3185 #define EDID_CEA_VCDB_QS (1 << 6)
3188 * Search EDID for CEA extension block.
3190 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
3192 u8 *edid_ext = NULL;
3195 /* No EDID or EDID extensions */
3196 if (edid == NULL || edid->extensions == 0)
3199 /* Find CEA extension */
3200 for (i = 0; i < edid->extensions; i++) {
3201 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
3202 if (edid_ext[0] == ext_id)
3206 if (i == edid->extensions)
3213 static u8 *drm_find_displayid_extension(const struct edid *edid,
3214 int *length, int *idx)
3216 u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT);
3217 struct displayid_hdr *base;
3223 /* EDID extensions block checksum isn't for us */
3224 *length = EDID_LENGTH - 1;
3227 ret = validate_displayid(displayid, *length, *idx);
3231 base = (struct displayid_hdr *)&displayid[*idx];
3232 *length = *idx + sizeof(*base) + base->bytes;
3237 static u8 *drm_find_cea_extension(const struct edid *edid)
3240 struct displayid_block *block;
3244 /* Look for a top level CEA extension block */
3245 cea = drm_find_edid_extension(edid, CEA_EXT);
3249 /* CEA blocks can also be found embedded in a DisplayID block */
3250 displayid = drm_find_displayid_extension(edid, &length, &idx);
3254 idx += sizeof(struct displayid_hdr);
3255 for_each_displayid_db(displayid, block, idx, length) {
3256 if (block->tag == DATA_BLOCK_CTA) {
3265 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
3267 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3268 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3270 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3271 return &edid_cea_modes_1[vic - 1];
3272 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3273 return &edid_cea_modes_193[vic - 193];
3277 static u8 cea_num_vics(void)
3279 return 193 + ARRAY_SIZE(edid_cea_modes_193);
3282 static u8 cea_next_vic(u8 vic)
3284 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
3290 * Calculate the alternate clock for the CEA mode
3291 * (60Hz vs. 59.94Hz etc.)
3294 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3296 unsigned int clock = cea_mode->clock;
3298 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
3302 * edid_cea_modes contains the 59.94Hz
3303 * variant for 240 and 480 line modes,
3304 * and the 60Hz variant otherwise.
3306 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
3307 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
3309 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
3315 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3318 * For certain VICs the spec allows the vertical
3319 * front porch to vary by one or two lines.
3321 * cea_modes[] stores the variant with the shortest
3322 * vertical front porch. We can adjust the mode to
3323 * get the other variants by simply increasing the
3324 * vertical front porch length.
3326 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3327 cea_mode_for_vic(9)->vtotal != 262 ||
3328 cea_mode_for_vic(12)->vtotal != 262 ||
3329 cea_mode_for_vic(13)->vtotal != 262 ||
3330 cea_mode_for_vic(23)->vtotal != 312 ||
3331 cea_mode_for_vic(24)->vtotal != 312 ||
3332 cea_mode_for_vic(27)->vtotal != 312 ||
3333 cea_mode_for_vic(28)->vtotal != 312);
3335 if (((vic == 8 || vic == 9 ||
3336 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3337 ((vic == 23 || vic == 24 ||
3338 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3339 mode->vsync_start++;
3349 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3350 unsigned int clock_tolerance)
3352 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3355 if (!to_match->clock)
3358 if (to_match->picture_aspect_ratio)
3359 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3361 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3362 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3363 unsigned int clock1, clock2;
3365 /* Check both 60Hz and 59.94Hz */
3366 clock1 = cea_mode.clock;
3367 clock2 = cea_mode_alternate_clock(&cea_mode);
3369 if (abs(to_match->clock - clock1) > clock_tolerance &&
3370 abs(to_match->clock - clock2) > clock_tolerance)
3374 if (drm_mode_match(to_match, &cea_mode, match_flags))
3376 } while (cea_mode_alternate_timings(vic, &cea_mode));
3383 * drm_match_cea_mode - look for a CEA mode matching given mode
3384 * @to_match: display mode
3386 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
3389 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
3391 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3394 if (!to_match->clock)
3397 if (to_match->picture_aspect_ratio)
3398 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3400 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3401 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3402 unsigned int clock1, clock2;
3404 /* Check both 60Hz and 59.94Hz */
3405 clock1 = cea_mode.clock;
3406 clock2 = cea_mode_alternate_clock(&cea_mode);
3408 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3409 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3413 if (drm_mode_match(to_match, &cea_mode, match_flags))
3415 } while (cea_mode_alternate_timings(vic, &cea_mode));
3420 EXPORT_SYMBOL(drm_match_cea_mode);
3422 static bool drm_valid_cea_vic(u8 vic)
3424 return cea_mode_for_vic(vic) != NULL;
3427 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3429 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
3432 return mode->picture_aspect_ratio;
3434 return HDMI_PICTURE_ASPECT_NONE;
3437 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
3439 return edid_4k_modes[video_code].picture_aspect_ratio;
3443 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3447 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3449 return cea_mode_alternate_clock(hdmi_mode);
3452 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3453 unsigned int clock_tolerance)
3455 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3458 if (!to_match->clock)
3461 if (to_match->picture_aspect_ratio)
3462 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3464 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3465 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3466 unsigned int clock1, clock2;
3468 /* Make sure to also match alternate clocks */
3469 clock1 = hdmi_mode->clock;
3470 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3472 if (abs(to_match->clock - clock1) > clock_tolerance &&
3473 abs(to_match->clock - clock2) > clock_tolerance)
3476 if (drm_mode_match(to_match, hdmi_mode, match_flags))
3484 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3485 * @to_match: display mode
3487 * An HDMI mode is one defined in the HDMI vendor specific block.
3489 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3491 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3493 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3496 if (!to_match->clock)
3499 if (to_match->picture_aspect_ratio)
3500 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3502 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3503 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3504 unsigned int clock1, clock2;
3506 /* Make sure to also match alternate clocks */
3507 clock1 = hdmi_mode->clock;
3508 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3510 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3511 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3512 drm_mode_match(to_match, hdmi_mode, match_flags))
3518 static bool drm_valid_hdmi_vic(u8 vic)
3520 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3524 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3526 struct drm_device *dev = connector->dev;
3527 struct drm_display_mode *mode, *tmp;
3531 /* Don't add CEA modes if the CEA extension block is missing */
3532 if (!drm_find_cea_extension(edid))
3536 * Go through all probed modes and create a new mode
3537 * with the alternate clock for certain CEA modes.
3539 list_for_each_entry(mode, &connector->probed_modes, head) {
3540 const struct drm_display_mode *cea_mode = NULL;
3541 struct drm_display_mode *newmode;
3542 u8 vic = drm_match_cea_mode(mode);
3543 unsigned int clock1, clock2;
3545 if (drm_valid_cea_vic(vic)) {
3546 cea_mode = cea_mode_for_vic(vic);
3547 clock2 = cea_mode_alternate_clock(cea_mode);
3549 vic = drm_match_hdmi_mode(mode);
3550 if (drm_valid_hdmi_vic(vic)) {
3551 cea_mode = &edid_4k_modes[vic];
3552 clock2 = hdmi_mode_alternate_clock(cea_mode);
3559 clock1 = cea_mode->clock;
3561 if (clock1 == clock2)
3564 if (mode->clock != clock1 && mode->clock != clock2)
3567 newmode = drm_mode_duplicate(dev, cea_mode);
3571 /* Carry over the stereo flags */
3572 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3575 * The current mode could be either variant. Make
3576 * sure to pick the "other" clock for the new mode.
3578 if (mode->clock != clock1)
3579 newmode->clock = clock1;
3581 newmode->clock = clock2;
3583 list_add_tail(&newmode->head, &list);
3586 list_for_each_entry_safe(mode, tmp, &list, head) {
3587 list_del(&mode->head);
3588 drm_mode_probed_add(connector, mode);
3595 static u8 svd_to_vic(u8 svd)
3597 /* 0-6 bit vic, 7th bit native mode indicator */
3598 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3604 static struct drm_display_mode *
3605 drm_display_mode_from_vic_index(struct drm_connector *connector,
3606 const u8 *video_db, u8 video_len,
3609 struct drm_device *dev = connector->dev;
3610 struct drm_display_mode *newmode;
3613 if (video_db == NULL || video_index >= video_len)
3616 /* CEA modes are numbered 1..127 */
3617 vic = svd_to_vic(video_db[video_index]);
3618 if (!drm_valid_cea_vic(vic))
3621 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3629 * do_y420vdb_modes - Parse YCBCR 420 only modes
3630 * @connector: connector corresponding to the HDMI sink
3631 * @svds: start of the data block of CEA YCBCR 420 VDB
3632 * @len: length of the CEA YCBCR 420 VDB
3634 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3635 * which contains modes which can be supported in YCBCR 420
3636 * output format only.
3638 static int do_y420vdb_modes(struct drm_connector *connector,
3639 const u8 *svds, u8 svds_len)
3642 struct drm_device *dev = connector->dev;
3643 struct drm_display_info *info = &connector->display_info;
3644 struct drm_hdmi_info *hdmi = &info->hdmi;
3646 for (i = 0; i < svds_len; i++) {
3647 u8 vic = svd_to_vic(svds[i]);
3648 struct drm_display_mode *newmode;
3650 if (!drm_valid_cea_vic(vic))
3653 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3656 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3657 drm_mode_probed_add(connector, newmode);
3662 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3667 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3668 * @connector: connector corresponding to the HDMI sink
3669 * @vic: CEA vic for the video mode to be added in the map
3671 * Makes an entry for a videomode in the YCBCR 420 bitmap
3674 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3676 u8 vic = svd_to_vic(svd);
3677 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3679 if (!drm_valid_cea_vic(vic))
3682 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3686 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3689 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3691 for (i = 0; i < len; i++) {
3692 struct drm_display_mode *mode;
3693 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3696 * YCBCR420 capability block contains a bitmap which
3697 * gives the index of CEA modes from CEA VDB, which
3698 * can support YCBCR 420 sampling output also (apart
3699 * from RGB/YCBCR444 etc).
3700 * For example, if the bit 0 in bitmap is set,
3701 * first mode in VDB can support YCBCR420 output too.
3702 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3704 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3705 drm_add_cmdb_modes(connector, db[i]);
3707 drm_mode_probed_add(connector, mode);
3715 struct stereo_mandatory_mode {
3716 int width, height, vrefresh;
3720 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3721 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3722 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3724 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3726 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3727 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3728 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3729 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3730 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3734 stereo_match_mandatory(const struct drm_display_mode *mode,
3735 const struct stereo_mandatory_mode *stereo_mode)
3737 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3739 return mode->hdisplay == stereo_mode->width &&
3740 mode->vdisplay == stereo_mode->height &&
3741 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3742 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3745 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3747 struct drm_device *dev = connector->dev;
3748 const struct drm_display_mode *mode;
3749 struct list_head stereo_modes;
3752 INIT_LIST_HEAD(&stereo_modes);
3754 list_for_each_entry(mode, &connector->probed_modes, head) {
3755 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3756 const struct stereo_mandatory_mode *mandatory;
3757 struct drm_display_mode *new_mode;
3759 if (!stereo_match_mandatory(mode,
3760 &stereo_mandatory_modes[i]))
3763 mandatory = &stereo_mandatory_modes[i];
3764 new_mode = drm_mode_duplicate(dev, mode);
3768 new_mode->flags |= mandatory->flags;
3769 list_add_tail(&new_mode->head, &stereo_modes);
3774 list_splice_tail(&stereo_modes, &connector->probed_modes);
3779 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3781 struct drm_device *dev = connector->dev;
3782 struct drm_display_mode *newmode;
3784 if (!drm_valid_hdmi_vic(vic)) {
3785 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3789 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3793 drm_mode_probed_add(connector, newmode);
3798 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3799 const u8 *video_db, u8 video_len, u8 video_index)
3801 struct drm_display_mode *newmode;
3804 if (structure & (1 << 0)) {
3805 newmode = drm_display_mode_from_vic_index(connector, video_db,
3809 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3810 drm_mode_probed_add(connector, newmode);
3814 if (structure & (1 << 6)) {
3815 newmode = drm_display_mode_from_vic_index(connector, video_db,
3819 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3820 drm_mode_probed_add(connector, newmode);
3824 if (structure & (1 << 8)) {
3825 newmode = drm_display_mode_from_vic_index(connector, video_db,
3829 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3830 drm_mode_probed_add(connector, newmode);
3839 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3840 * @connector: connector corresponding to the HDMI sink
3841 * @db: start of the CEA vendor specific block
3842 * @len: length of the CEA block payload, ie. one can access up to db[len]
3844 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3845 * also adds the stereo 3d modes when applicable.
3848 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3849 const u8 *video_db, u8 video_len)
3851 struct drm_display_info *info = &connector->display_info;
3852 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3853 u8 vic_len, hdmi_3d_len = 0;
3860 /* no HDMI_Video_Present */
3861 if (!(db[8] & (1 << 5)))
3864 /* Latency_Fields_Present */
3865 if (db[8] & (1 << 7))
3868 /* I_Latency_Fields_Present */
3869 if (db[8] & (1 << 6))
3872 /* the declared length is not long enough for the 2 first bytes
3873 * of additional video format capabilities */
3874 if (len < (8 + offset + 2))
3879 if (db[8 + offset] & (1 << 7)) {
3880 modes += add_hdmi_mandatory_stereo_modes(connector);
3882 /* 3D_Multi_present */
3883 multi_present = (db[8 + offset] & 0x60) >> 5;
3887 vic_len = db[8 + offset] >> 5;
3888 hdmi_3d_len = db[8 + offset] & 0x1f;
3890 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3893 vic = db[9 + offset + i];
3894 modes += add_hdmi_mode(connector, vic);
3896 offset += 1 + vic_len;
3898 if (multi_present == 1)
3900 else if (multi_present == 2)
3905 if (len < (8 + offset + hdmi_3d_len - 1))
3908 if (hdmi_3d_len < multi_len)
3911 if (multi_present == 1 || multi_present == 2) {
3912 /* 3D_Structure_ALL */
3913 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3915 /* check if 3D_MASK is present */
3916 if (multi_present == 2)
3917 mask = (db[10 + offset] << 8) | db[11 + offset];
3921 for (i = 0; i < 16; i++) {
3922 if (mask & (1 << i))
3923 modes += add_3d_struct_modes(connector,
3930 offset += multi_len;
3932 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3934 struct drm_display_mode *newmode = NULL;
3935 unsigned int newflag = 0;
3936 bool detail_present;
3938 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3940 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3943 /* 2D_VIC_order_X */
3944 vic_index = db[8 + offset + i] >> 4;
3946 /* 3D_Structure_X */
3947 switch (db[8 + offset + i] & 0x0f) {
3949 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3952 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3956 if ((db[9 + offset + i] >> 4) == 1)
3957 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3962 newmode = drm_display_mode_from_vic_index(connector,
3968 newmode->flags |= newflag;
3969 drm_mode_probed_add(connector, newmode);
3980 info->has_hdmi_infoframe = true;
3985 cea_db_payload_len(const u8 *db)
3987 return db[0] & 0x1f;
3991 cea_db_extended_tag(const u8 *db)
3997 cea_db_tag(const u8 *db)
4003 cea_revision(const u8 *cea)
4006 * FIXME is this correct for the DispID variant?
4007 * The DispID spec doesn't really specify whether
4008 * this is the revision of the CEA extension or
4009 * the DispID CEA data block. And the only value
4010 * given as an example is 0.
4016 cea_db_offsets(const u8 *cea, int *start, int *end)
4018 /* DisplayID CTA extension blocks and top-level CEA EDID
4019 * block header definitions differ in the following bytes:
4020 * 1) Byte 2 of the header specifies length differently,
4021 * 2) Byte 3 is only present in the CEA top level block.
4023 * The different definitions for byte 2 follow.
4025 * DisplayID CTA extension block defines byte 2 as:
4026 * Number of payload bytes
4028 * CEA EDID block defines byte 2 as:
4029 * Byte number (decimal) within this block where the 18-byte
4030 * DTDs begin. If no non-DTD data is present in this extension
4031 * block, the value should be set to 04h (the byte after next).
4032 * If set to 00h, there are no DTDs present in this block and
4035 if (cea[0] == DATA_BLOCK_CTA) {
4037 * for_each_displayid_db() has already verified
4038 * that these stay within expected bounds.
4041 *end = *start + cea[2];
4042 } else if (cea[0] == CEA_EXT) {
4043 /* Data block offset in CEA extension block */
4048 if (*end < 4 || *end > 127)
4057 static bool cea_db_is_hdmi_vsdb(const u8 *db)
4061 if (cea_db_tag(db) != VENDOR_BLOCK)
4064 if (cea_db_payload_len(db) < 5)
4067 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
4069 return hdmi_id == HDMI_IEEE_OUI;
4072 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
4076 if (cea_db_tag(db) != VENDOR_BLOCK)
4079 if (cea_db_payload_len(db) < 7)
4082 oui = db[3] << 16 | db[2] << 8 | db[1];
4084 return oui == HDMI_FORUM_IEEE_OUI;
4087 static bool cea_db_is_vcdb(const u8 *db)
4089 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4092 if (cea_db_payload_len(db) != 2)
4095 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
4101 static bool cea_db_is_y420cmdb(const u8 *db)
4103 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4106 if (!cea_db_payload_len(db))
4109 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
4115 static bool cea_db_is_y420vdb(const u8 *db)
4117 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4120 if (!cea_db_payload_len(db))
4123 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
4129 #define for_each_cea_db(cea, i, start, end) \
4130 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
4132 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
4135 struct drm_display_info *info = &connector->display_info;
4136 struct drm_hdmi_info *hdmi = &info->hdmi;
4137 u8 map_len = cea_db_payload_len(db) - 1;
4142 /* All CEA modes support ycbcr420 sampling also.*/
4143 hdmi->y420_cmdb_map = U64_MAX;
4144 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4149 * This map indicates which of the existing CEA block modes
4150 * from VDB can support YCBCR420 output too. So if bit=0 is
4151 * set, first mode from VDB can support YCBCR420 output too.
4152 * We will parse and keep this map, before parsing VDB itself
4153 * to avoid going through the same block again and again.
4155 * Spec is not clear about max possible size of this block.
4156 * Clamping max bitmap block size at 8 bytes. Every byte can
4157 * address 8 CEA modes, in this way this map can address
4158 * 8*8 = first 64 SVDs.
4160 if (WARN_ON_ONCE(map_len > 8))
4163 for (count = 0; count < map_len; count++)
4164 map |= (u64)db[2 + count] << (8 * count);
4167 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4169 hdmi->y420_cmdb_map = map;
4173 add_cea_modes(struct drm_connector *connector, struct edid *edid)
4175 const u8 *cea = drm_find_cea_extension(edid);
4176 const u8 *db, *hdmi = NULL, *video = NULL;
4177 u8 dbl, hdmi_len, video_len = 0;
4180 if (cea && cea_revision(cea) >= 3) {
4183 if (cea_db_offsets(cea, &start, &end))
4186 for_each_cea_db(cea, i, start, end) {
4188 dbl = cea_db_payload_len(db);
4190 if (cea_db_tag(db) == VIDEO_BLOCK) {
4193 modes += do_cea_modes(connector, video, dbl);
4194 } else if (cea_db_is_hdmi_vsdb(db)) {
4197 } else if (cea_db_is_y420vdb(db)) {
4198 const u8 *vdb420 = &db[2];
4200 /* Add 4:2:0(only) modes present in EDID */
4201 modes += do_y420vdb_modes(connector,
4209 * We parse the HDMI VSDB after having added the cea modes as we will
4210 * be patching their flags when the sink supports stereo 3D.
4213 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
4219 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
4221 const struct drm_display_mode *cea_mode;
4222 int clock1, clock2, clock;
4227 * allow 5kHz clock difference either way to account for
4228 * the 10kHz clock resolution limit of detailed timings.
4230 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4231 if (drm_valid_cea_vic(vic)) {
4233 cea_mode = cea_mode_for_vic(vic);
4234 clock1 = cea_mode->clock;
4235 clock2 = cea_mode_alternate_clock(cea_mode);
4237 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4238 if (drm_valid_hdmi_vic(vic)) {
4240 cea_mode = &edid_4k_modes[vic];
4241 clock1 = cea_mode->clock;
4242 clock2 = hdmi_mode_alternate_clock(cea_mode);
4248 /* pick whichever is closest */
4249 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
4254 if (mode->clock == clock)
4257 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
4258 type, vic, mode->clock, clock);
4259 mode->clock = clock;
4262 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
4264 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4267 if (db[1] != HDR_STATIC_METADATA_BLOCK)
4270 if (cea_db_payload_len(db) < 3)
4276 static uint8_t eotf_supported(const u8 *edid_ext)
4278 return edid_ext[2] &
4279 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
4280 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
4281 BIT(HDMI_EOTF_SMPTE_ST2084) |
4282 BIT(HDMI_EOTF_BT_2100_HLG));
4285 static uint8_t hdr_metadata_type(const u8 *edid_ext)
4287 return edid_ext[3] &
4288 BIT(HDMI_STATIC_METADATA_TYPE1);
4292 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4296 len = cea_db_payload_len(db);
4298 connector->hdr_sink_metadata.hdmi_type1.eotf =
4300 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
4301 hdr_metadata_type(db);
4304 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
4306 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
4308 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
4312 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
4314 u8 len = cea_db_payload_len(db);
4316 if (len >= 6 && (db[6] & (1 << 7)))
4317 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
4319 connector->latency_present[0] = db[8] >> 7;
4320 connector->latency_present[1] = (db[8] >> 6) & 1;
4323 connector->video_latency[0] = db[9];
4325 connector->audio_latency[0] = db[10];
4327 connector->video_latency[1] = db[11];
4329 connector->audio_latency[1] = db[12];
4331 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4332 "video latency %d %d, "
4333 "audio latency %d %d\n",
4334 connector->latency_present[0],
4335 connector->latency_present[1],
4336 connector->video_latency[0],
4337 connector->video_latency[1],
4338 connector->audio_latency[0],
4339 connector->audio_latency[1]);
4343 monitor_name(struct detailed_timing *t, void *data)
4345 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME))
4348 *(u8 **)data = t->data.other_data.data.str.str;
4351 static int get_monitor_name(struct edid *edid, char name[13])
4353 char *edid_name = NULL;
4359 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4360 for (mnl = 0; edid_name && mnl < 13; mnl++) {
4361 if (edid_name[mnl] == 0x0a)
4364 name[mnl] = edid_name[mnl];
4371 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4372 * @edid: monitor EDID information
4373 * @name: pointer to a character array to hold the name of the monitor
4374 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4377 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4385 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4386 memcpy(name, buf, name_length);
4387 name[name_length] = '\0';
4389 EXPORT_SYMBOL(drm_edid_get_monitor_name);
4391 static void clear_eld(struct drm_connector *connector)
4393 memset(connector->eld, 0, sizeof(connector->eld));
4395 connector->latency_present[0] = false;
4396 connector->latency_present[1] = false;
4397 connector->video_latency[0] = 0;
4398 connector->audio_latency[0] = 0;
4399 connector->video_latency[1] = 0;
4400 connector->audio_latency[1] = 0;
4404 * drm_edid_to_eld - build ELD from EDID
4405 * @connector: connector corresponding to the HDMI/DP sink
4406 * @edid: EDID to parse
4408 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
4409 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
4411 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
4413 uint8_t *eld = connector->eld;
4416 int total_sad_count = 0;
4420 clear_eld(connector);
4425 cea = drm_find_cea_extension(edid);
4427 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4431 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4432 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
4434 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4435 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
4437 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
4439 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4440 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4441 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4442 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
4444 if (cea_revision(cea) >= 3) {
4448 if (cea_db_offsets(cea, &start, &end)) {
4453 for_each_cea_db(cea, i, start, end) {
4455 dbl = cea_db_payload_len(db);
4457 switch (cea_db_tag(db)) {
4459 /* Audio Data Block, contains SADs */
4460 sad_count = min(dbl / 3, 15 - total_sad_count);
4462 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
4463 &db[1], sad_count * 3);
4464 total_sad_count += sad_count;
4467 /* Speaker Allocation Data Block */
4469 eld[DRM_ELD_SPEAKER] = db[1];
4472 /* HDMI Vendor-Specific Data Block */
4473 if (cea_db_is_hdmi_vsdb(db))
4474 drm_parse_hdmi_vsdb_audio(connector, db);
4481 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
4483 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4484 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4485 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4487 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
4489 eld[DRM_ELD_BASELINE_ELD_LEN] =
4490 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4492 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
4493 drm_eld_size(eld), total_sad_count);
4497 * drm_edid_to_sad - extracts SADs from EDID
4498 * @edid: EDID to parse
4499 * @sads: pointer that will be set to the extracted SADs
4501 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
4503 * Note: The returned pointer needs to be freed using kfree().
4505 * Return: The number of found SADs or negative number on error.
4507 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4510 int i, start, end, dbl;
4513 cea = drm_find_cea_extension(edid);
4515 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4519 if (cea_revision(cea) < 3) {
4520 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4524 if (cea_db_offsets(cea, &start, &end)) {
4525 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4529 for_each_cea_db(cea, i, start, end) {
4532 if (cea_db_tag(db) == AUDIO_BLOCK) {
4534 dbl = cea_db_payload_len(db);
4536 count = dbl / 3; /* SAD is 3B */
4537 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4540 for (j = 0; j < count; j++) {
4541 u8 *sad = &db[1 + j * 3];
4543 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4544 (*sads)[j].channels = sad[0] & 0x7;
4545 (*sads)[j].freq = sad[1] & 0x7F;
4546 (*sads)[j].byte2 = sad[2];
4554 EXPORT_SYMBOL(drm_edid_to_sad);
4557 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4558 * @edid: EDID to parse
4559 * @sadb: pointer to the speaker block
4561 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4563 * Note: The returned pointer needs to be freed using kfree().
4565 * Return: The number of found Speaker Allocation Blocks or negative number on
4568 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4571 int i, start, end, dbl;
4574 cea = drm_find_cea_extension(edid);
4576 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4580 if (cea_revision(cea) < 3) {
4581 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4585 if (cea_db_offsets(cea, &start, &end)) {
4586 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4590 for_each_cea_db(cea, i, start, end) {
4591 const u8 *db = &cea[i];
4593 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4594 dbl = cea_db_payload_len(db);
4596 /* Speaker Allocation Data Block */
4598 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4609 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4612 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4613 * @connector: connector associated with the HDMI/DP sink
4614 * @mode: the display mode
4616 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4617 * the sink doesn't support audio or video.
4619 int drm_av_sync_delay(struct drm_connector *connector,
4620 const struct drm_display_mode *mode)
4622 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4625 if (!connector->latency_present[0])
4627 if (!connector->latency_present[1])
4630 a = connector->audio_latency[i];
4631 v = connector->video_latency[i];
4634 * HDMI/DP sink doesn't support audio or video?
4636 if (a == 255 || v == 255)
4640 * Convert raw EDID values to millisecond.
4641 * Treat unknown latency as 0ms.
4644 a = min(2 * (a - 1), 500);
4646 v = min(2 * (v - 1), 500);
4648 return max(v - a, 0);
4650 EXPORT_SYMBOL(drm_av_sync_delay);
4653 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4654 * @edid: monitor EDID information
4656 * Parse the CEA extension according to CEA-861-B.
4658 * Drivers that have added the modes parsed from EDID to drm_display_info
4659 * should use &drm_display_info.is_hdmi instead of calling this function.
4661 * Return: True if the monitor is HDMI, false if not or unknown.
4663 bool drm_detect_hdmi_monitor(struct edid *edid)
4667 int start_offset, end_offset;
4669 edid_ext = drm_find_cea_extension(edid);
4673 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4677 * Because HDMI identifier is in Vendor Specific Block,
4678 * search it from all data blocks of CEA extension.
4680 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4681 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4687 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4690 * drm_detect_monitor_audio - check monitor audio capability
4691 * @edid: EDID block to scan
4693 * Monitor should have CEA extension block.
4694 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4695 * audio' only. If there is any audio extension block and supported
4696 * audio format, assume at least 'basic audio' support, even if 'basic
4697 * audio' is not defined in EDID.
4699 * Return: True if the monitor supports audio, false otherwise.
4701 bool drm_detect_monitor_audio(struct edid *edid)
4705 bool has_audio = false;
4706 int start_offset, end_offset;
4708 edid_ext = drm_find_cea_extension(edid);
4712 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4715 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4719 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4722 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4723 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4725 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4726 DRM_DEBUG_KMS("CEA audio format %d\n",
4727 (edid_ext[i + j] >> 3) & 0xf);
4734 EXPORT_SYMBOL(drm_detect_monitor_audio);
4738 * drm_default_rgb_quant_range - default RGB quantization range
4739 * @mode: display mode
4741 * Determine the default RGB quantization range for the mode,
4742 * as specified in CEA-861.
4744 * Return: The default RGB quantization range for the mode
4746 enum hdmi_quantization_range
4747 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4749 /* All CEA modes other than VIC 1 use limited quantization range. */
4750 return drm_match_cea_mode(mode) > 1 ?
4751 HDMI_QUANTIZATION_RANGE_LIMITED :
4752 HDMI_QUANTIZATION_RANGE_FULL;
4754 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4756 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4758 struct drm_display_info *info = &connector->display_info;
4760 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4762 if (db[2] & EDID_CEA_VCDB_QS)
4763 info->rgb_quant_range_selectable = true;
4766 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4770 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4772 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4773 hdmi->y420_dc_modes = dc_mask;
4776 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4779 struct drm_display_info *display = &connector->display_info;
4780 struct drm_hdmi_info *hdmi = &display->hdmi;
4782 display->has_hdmi_infoframe = true;
4784 if (hf_vsdb[6] & 0x80) {
4785 hdmi->scdc.supported = true;
4786 if (hf_vsdb[6] & 0x40)
4787 hdmi->scdc.read_request = true;
4791 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4792 * And as per the spec, three factors confirm this:
4793 * * Availability of a HF-VSDB block in EDID (check)
4794 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4795 * * SCDC support available (let's check)
4796 * Lets check it out.
4800 /* max clock is 5000 KHz times block value */
4801 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4802 struct drm_scdc *scdc = &hdmi->scdc;
4804 if (max_tmds_clock > 340000) {
4805 display->max_tmds_clock = max_tmds_clock;
4806 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4807 display->max_tmds_clock);
4810 if (scdc->supported) {
4811 scdc->scrambling.supported = true;
4813 /* Few sinks support scrambling for clocks < 340M */
4814 if ((hf_vsdb[6] & 0x8))
4815 scdc->scrambling.low_rates = true;
4819 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4822 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4825 struct drm_display_info *info = &connector->display_info;
4826 unsigned int dc_bpc = 0;
4828 /* HDMI supports at least 8 bpc */
4831 if (cea_db_payload_len(hdmi) < 6)
4834 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4836 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4837 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4841 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4843 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4844 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4848 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4850 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4851 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4856 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4861 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4862 connector->name, dc_bpc);
4866 * Deep color support mandates RGB444 support for all video
4867 * modes and forbids YCRCB422 support for all video modes per
4870 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4872 /* YCRCB444 is optional according to spec. */
4873 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4874 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4875 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4880 * Spec says that if any deep color mode is supported at all,
4881 * then deep color 36 bit must be supported.
4883 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4884 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4890 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4892 struct drm_display_info *info = &connector->display_info;
4893 u8 len = cea_db_payload_len(db);
4895 info->is_hdmi = true;
4898 info->dvi_dual = db[6] & 1;
4900 info->max_tmds_clock = db[7] * 5000;
4902 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4903 "max TMDS clock %d kHz\n",
4905 info->max_tmds_clock);
4907 drm_parse_hdmi_deep_color_info(connector, db);
4910 static void drm_parse_cea_ext(struct drm_connector *connector,
4911 const struct edid *edid)
4913 struct drm_display_info *info = &connector->display_info;
4917 edid_ext = drm_find_cea_extension(edid);
4921 info->cea_rev = edid_ext[1];
4923 /* The existence of a CEA block should imply RGB support */
4924 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4925 if (edid_ext[3] & EDID_CEA_YCRCB444)
4926 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4927 if (edid_ext[3] & EDID_CEA_YCRCB422)
4928 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4930 if (cea_db_offsets(edid_ext, &start, &end))
4933 for_each_cea_db(edid_ext, i, start, end) {
4934 const u8 *db = &edid_ext[i];
4936 if (cea_db_is_hdmi_vsdb(db))
4937 drm_parse_hdmi_vsdb_video(connector, db);
4938 if (cea_db_is_hdmi_forum_vsdb(db))
4939 drm_parse_hdmi_forum_vsdb(connector, db);
4940 if (cea_db_is_y420cmdb(db))
4941 drm_parse_y420cmdb_bitmap(connector, db);
4942 if (cea_db_is_vcdb(db))
4943 drm_parse_vcdb(connector, db);
4944 if (cea_db_is_hdmi_hdr_metadata_block(db))
4945 drm_parse_hdr_metadata_block(connector, db);
4950 void get_monitor_range(struct detailed_timing *timing,
4951 void *info_monitor_range)
4953 struct drm_monitor_range_info *monitor_range = info_monitor_range;
4954 const struct detailed_non_pixel *data = &timing->data.other_data;
4955 const struct detailed_data_monitor_range *range = &data->data.range;
4957 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
4961 * Check for flag range limits only. If flag == 1 then
4962 * no additional timing information provided.
4963 * Default GTF, GTF Secondary curve and CVT are not
4966 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
4969 monitor_range->min_vfreq = range->min_vfreq;
4970 monitor_range->max_vfreq = range->max_vfreq;
4974 void drm_get_monitor_range(struct drm_connector *connector,
4975 const struct edid *edid)
4977 struct drm_display_info *info = &connector->display_info;
4979 if (!version_greater(edid, 1, 1))
4982 drm_for_each_detailed_block((u8 *)edid, get_monitor_range,
4983 &info->monitor_range);
4985 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
4986 info->monitor_range.min_vfreq,
4987 info->monitor_range.max_vfreq);
4990 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4991 * all of the values which would have been set from EDID
4994 drm_reset_display_info(struct drm_connector *connector)
4996 struct drm_display_info *info = &connector->display_info;
4999 info->height_mm = 0;
5002 info->color_formats = 0;
5004 info->max_tmds_clock = 0;
5005 info->dvi_dual = false;
5006 info->is_hdmi = false;
5007 info->has_hdmi_infoframe = false;
5008 info->rgb_quant_range_selectable = false;
5009 memset(&info->hdmi, 0, sizeof(info->hdmi));
5011 info->non_desktop = 0;
5012 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
5015 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
5017 struct drm_display_info *info = &connector->display_info;
5019 u32 quirks = edid_get_quirks(edid);
5021 drm_reset_display_info(connector);
5023 info->width_mm = edid->width_cm * 10;
5024 info->height_mm = edid->height_cm * 10;
5026 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
5028 drm_get_monitor_range(connector, edid);
5030 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
5032 if (edid->revision < 3)
5035 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
5038 drm_parse_cea_ext(connector, edid);
5041 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
5043 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
5044 * tells us to assume 8 bpc color depth if the EDID doesn't have
5045 * extensions which tell otherwise.
5047 if (info->bpc == 0 && edid->revision == 3 &&
5048 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
5050 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
5051 connector->name, info->bpc);
5054 /* Only defined for 1.4 with digital displays */
5055 if (edid->revision < 4)
5058 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
5059 case DRM_EDID_DIGITAL_DEPTH_6:
5062 case DRM_EDID_DIGITAL_DEPTH_8:
5065 case DRM_EDID_DIGITAL_DEPTH_10:
5068 case DRM_EDID_DIGITAL_DEPTH_12:
5071 case DRM_EDID_DIGITAL_DEPTH_14:
5074 case DRM_EDID_DIGITAL_DEPTH_16:
5077 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
5083 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
5084 connector->name, info->bpc);
5086 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
5087 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
5088 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5089 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
5090 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
5094 static int validate_displayid(u8 *displayid, int length, int idx)
5096 int i, dispid_length;
5098 struct displayid_hdr *base;
5100 base = (struct displayid_hdr *)&displayid[idx];
5102 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
5103 base->rev, base->bytes, base->prod_id, base->ext_count);
5105 /* +1 for DispID checksum */
5106 dispid_length = sizeof(*base) + base->bytes + 1;
5107 if (dispid_length > length - idx)
5110 for (i = 0; i < dispid_length; i++)
5111 csum += displayid[idx + i];
5113 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
5120 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
5121 struct displayid_detailed_timings_1 *timings)
5123 struct drm_display_mode *mode;
5124 unsigned pixel_clock = (timings->pixel_clock[0] |
5125 (timings->pixel_clock[1] << 8) |
5126 (timings->pixel_clock[2] << 16));
5127 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
5128 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
5129 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
5130 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
5131 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
5132 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
5133 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
5134 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
5135 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
5136 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
5137 mode = drm_mode_create(dev);
5141 mode->clock = pixel_clock * 10;
5142 mode->hdisplay = hactive;
5143 mode->hsync_start = mode->hdisplay + hsync;
5144 mode->hsync_end = mode->hsync_start + hsync_width;
5145 mode->htotal = mode->hdisplay + hblank;
5147 mode->vdisplay = vactive;
5148 mode->vsync_start = mode->vdisplay + vsync;
5149 mode->vsync_end = mode->vsync_start + vsync_width;
5150 mode->vtotal = mode->vdisplay + vblank;
5153 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
5154 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
5155 mode->type = DRM_MODE_TYPE_DRIVER;
5157 if (timings->flags & 0x80)
5158 mode->type |= DRM_MODE_TYPE_PREFERRED;
5159 drm_mode_set_name(mode);
5164 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
5165 struct displayid_block *block)
5167 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
5170 struct drm_display_mode *newmode;
5172 /* blocks must be multiple of 20 bytes length */
5173 if (block->num_bytes % 20)
5176 num_timings = block->num_bytes / 20;
5177 for (i = 0; i < num_timings; i++) {
5178 struct displayid_detailed_timings_1 *timings = &det->timings[i];
5180 newmode = drm_mode_displayid_detailed(connector->dev, timings);
5184 drm_mode_probed_add(connector, newmode);
5190 static int add_displayid_detailed_modes(struct drm_connector *connector,
5195 struct displayid_block *block;
5198 displayid = drm_find_displayid_extension(edid, &length, &idx);
5202 idx += sizeof(struct displayid_hdr);
5203 for_each_displayid_db(displayid, block, idx, length) {
5204 switch (block->tag) {
5205 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5206 num_modes += add_displayid_detailed_1_modes(connector, block);
5214 * drm_add_edid_modes - add modes from EDID data, if available
5215 * @connector: connector we're probing
5218 * Add the specified modes to the connector's mode list. Also fills out the
5219 * &drm_display_info structure and ELD in @connector with any information which
5220 * can be derived from the edid.
5222 * Return: The number of modes added or 0 if we couldn't find any.
5224 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
5230 clear_eld(connector);
5233 if (!drm_edid_is_valid(edid)) {
5234 clear_eld(connector);
5235 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
5240 drm_edid_to_eld(connector, edid);
5243 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
5244 * To avoid multiple parsing of same block, lets parse that map
5245 * from sink info, before parsing CEA modes.
5247 quirks = drm_add_display_info(connector, edid);
5250 * EDID spec says modes should be preferred in this order:
5251 * - preferred detailed mode
5252 * - other detailed modes from base block
5253 * - detailed modes from extension blocks
5254 * - CVT 3-byte code modes
5255 * - standard timing codes
5256 * - established timing codes
5257 * - modes inferred from GTF or CVT range information
5259 * We get this pretty much right.
5261 * XXX order for additional mode types in extension blocks?
5263 num_modes += add_detailed_modes(connector, edid, quirks);
5264 num_modes += add_cvt_modes(connector, edid);
5265 num_modes += add_standard_modes(connector, edid);
5266 num_modes += add_established_modes(connector, edid);
5267 num_modes += add_cea_modes(connector, edid);
5268 num_modes += add_alternate_cea_modes(connector, edid);
5269 num_modes += add_displayid_detailed_modes(connector, edid);
5270 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
5271 num_modes += add_inferred_modes(connector, edid);
5273 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
5274 edid_fixup_preferred(connector, quirks);
5276 if (quirks & EDID_QUIRK_FORCE_6BPC)
5277 connector->display_info.bpc = 6;
5279 if (quirks & EDID_QUIRK_FORCE_8BPC)
5280 connector->display_info.bpc = 8;
5282 if (quirks & EDID_QUIRK_FORCE_10BPC)
5283 connector->display_info.bpc = 10;
5285 if (quirks & EDID_QUIRK_FORCE_12BPC)
5286 connector->display_info.bpc = 12;
5290 EXPORT_SYMBOL(drm_add_edid_modes);
5293 * drm_add_modes_noedid - add modes for the connectors without EDID
5294 * @connector: connector we're probing
5295 * @hdisplay: the horizontal display limit
5296 * @vdisplay: the vertical display limit
5298 * Add the specified modes to the connector's mode list. Only when the
5299 * hdisplay/vdisplay is not beyond the given limit, it will be added.
5301 * Return: The number of modes added or 0 if we couldn't find any.
5303 int drm_add_modes_noedid(struct drm_connector *connector,
5304 int hdisplay, int vdisplay)
5306 int i, count, num_modes = 0;
5307 struct drm_display_mode *mode;
5308 struct drm_device *dev = connector->dev;
5310 count = ARRAY_SIZE(drm_dmt_modes);
5316 for (i = 0; i < count; i++) {
5317 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
5318 if (hdisplay && vdisplay) {
5320 * Only when two are valid, they will be used to check
5321 * whether the mode should be added to the mode list of
5324 if (ptr->hdisplay > hdisplay ||
5325 ptr->vdisplay > vdisplay)
5328 if (drm_mode_vrefresh(ptr) > 61)
5330 mode = drm_mode_duplicate(dev, ptr);
5332 drm_mode_probed_add(connector, mode);
5338 EXPORT_SYMBOL(drm_add_modes_noedid);
5341 * drm_set_preferred_mode - Sets the preferred mode of a connector
5342 * @connector: connector whose mode list should be processed
5343 * @hpref: horizontal resolution of preferred mode
5344 * @vpref: vertical resolution of preferred mode
5346 * Marks a mode as preferred if it matches the resolution specified by @hpref
5349 void drm_set_preferred_mode(struct drm_connector *connector,
5350 int hpref, int vpref)
5352 struct drm_display_mode *mode;
5354 list_for_each_entry(mode, &connector->probed_modes, head) {
5355 if (mode->hdisplay == hpref &&
5356 mode->vdisplay == vpref)
5357 mode->type |= DRM_MODE_TYPE_PREFERRED;
5360 EXPORT_SYMBOL(drm_set_preferred_mode);
5362 static bool is_hdmi2_sink(struct drm_connector *connector)
5365 * FIXME: sil-sii8620 doesn't have a connector around when
5366 * we need one, so we have to be prepared for a NULL connector.
5371 return connector->display_info.hdmi.scdc.supported ||
5372 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
5375 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5377 return sink_eotf & BIT(output_eotf);
5381 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5382 * HDR metadata from userspace
5383 * @frame: HDMI DRM infoframe
5384 * @conn_state: Connector state containing HDR metadata
5386 * Return: 0 on success or a negative error code on failure.
5389 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5390 const struct drm_connector_state *conn_state)
5392 struct drm_connector *connector;
5393 struct hdr_output_metadata *hdr_metadata;
5396 if (!frame || !conn_state)
5399 connector = conn_state->connector;
5401 if (!conn_state->hdr_output_metadata)
5404 hdr_metadata = conn_state->hdr_output_metadata->data;
5406 if (!hdr_metadata || !connector)
5409 /* Sink EOTF is Bit map while infoframe is absolute values */
5410 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5411 connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5412 DRM_DEBUG_KMS("EOTF Not Supported\n");
5416 err = hdmi_drm_infoframe_init(frame);
5420 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5421 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5423 BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5424 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5425 BUILD_BUG_ON(sizeof(frame->white_point) !=
5426 sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5428 memcpy(&frame->display_primaries,
5429 &hdr_metadata->hdmi_metadata_type1.display_primaries,
5430 sizeof(frame->display_primaries));
5432 memcpy(&frame->white_point,
5433 &hdr_metadata->hdmi_metadata_type1.white_point,
5434 sizeof(frame->white_point));
5436 frame->max_display_mastering_luminance =
5437 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5438 frame->min_display_mastering_luminance =
5439 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5440 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5441 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5445 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5447 static u8 drm_mode_hdmi_vic(struct drm_connector *connector,
5448 const struct drm_display_mode *mode)
5450 bool has_hdmi_infoframe = connector ?
5451 connector->display_info.has_hdmi_infoframe : false;
5453 if (!has_hdmi_infoframe)
5456 /* No HDMI VIC when signalling 3D video format */
5457 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
5460 return drm_match_hdmi_mode(mode);
5463 static u8 drm_mode_cea_vic(struct drm_connector *connector,
5464 const struct drm_display_mode *mode)
5469 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5470 * we should send its VIC in vendor infoframes, else send the
5471 * VIC in AVI infoframes. Lets check if this mode is present in
5472 * HDMI 1.4b 4K modes
5474 if (drm_mode_hdmi_vic(connector, mode))
5477 vic = drm_match_cea_mode(mode);
5480 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5481 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5482 * have to make sure we dont break HDMI 1.4 sinks.
5484 if (!is_hdmi2_sink(connector) && vic > 64)
5491 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5492 * data from a DRM display mode
5493 * @frame: HDMI AVI infoframe
5494 * @connector: the connector
5495 * @mode: DRM display mode
5497 * Return: 0 on success or a negative error code on failure.
5500 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
5501 struct drm_connector *connector,
5502 const struct drm_display_mode *mode)
5504 enum hdmi_picture_aspect picture_aspect;
5507 if (!frame || !mode)
5510 hdmi_avi_infoframe_init(frame);
5512 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5513 frame->pixel_repeat = 1;
5515 vic = drm_mode_cea_vic(connector, mode);
5516 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
5518 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5521 * As some drivers don't support atomic, we can't use connector state.
5522 * So just initialize the frame with default values, just the same way
5523 * as it's done with other properties here.
5525 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5529 * Populate picture aspect ratio from either
5530 * user input (if specified) or from the CEA/HDMI mode lists.
5532 picture_aspect = mode->picture_aspect_ratio;
5533 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
5535 picture_aspect = drm_get_cea_aspect_ratio(vic);
5537 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
5541 * The infoframe can't convey anything but none, 4:3
5542 * and 16:9, so if the user has asked for anything else
5543 * we can only satisfy it by specifying the right VIC.
5545 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
5547 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
5549 } else if (hdmi_vic) {
5550 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
5556 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5559 frame->video_code = vic;
5560 frame->picture_aspect = picture_aspect;
5561 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
5562 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
5566 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
5568 /* HDMI Colorspace Spec Definitions */
5569 #define FULL_COLORIMETRY_MASK 0x1FF
5570 #define NORMAL_COLORIMETRY_MASK 0x3
5571 #define EXTENDED_COLORIMETRY_MASK 0x7
5572 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF
5574 #define C(x) ((x) << 0)
5575 #define EC(x) ((x) << 2)
5576 #define ACE(x) ((x) << 5)
5578 #define HDMI_COLORIMETRY_NO_DATA 0x0
5579 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
5580 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
5581 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
5582 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
5583 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
5584 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
5585 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
5586 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
5587 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
5588 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
5589 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
5590 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
5592 static const u32 hdmi_colorimetry_val[] = {
5593 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5594 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5595 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5596 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5597 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5598 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5599 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5600 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5601 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5602 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5603 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5611 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
5612 * colorspace information
5613 * @frame: HDMI AVI infoframe
5614 * @conn_state: connector state
5617 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
5618 const struct drm_connector_state *conn_state)
5620 u32 colorimetry_val;
5621 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5623 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
5624 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5626 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5628 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5630 * ToDo: Extend it for ACE formats as well. Modify the infoframe
5631 * structure and extend it in drivers/video/hdmi
5633 frame->extended_colorimetry = (colorimetry_val >> 2) &
5634 EXTENDED_COLORIMETRY_MASK;
5636 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5639 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5640 * quantization range information
5641 * @frame: HDMI AVI infoframe
5642 * @connector: the connector
5643 * @mode: DRM display mode
5644 * @rgb_quant_range: RGB quantization range (Q)
5647 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
5648 struct drm_connector *connector,
5649 const struct drm_display_mode *mode,
5650 enum hdmi_quantization_range rgb_quant_range)
5652 const struct drm_display_info *info = &connector->display_info;
5656 * "A Source shall not send a non-zero Q value that does not correspond
5657 * to the default RGB Quantization Range for the transmitted Picture
5658 * unless the Sink indicates support for the Q bit in a Video
5659 * Capabilities Data Block."
5661 * HDMI 2.0 recommends sending non-zero Q when it does match the
5662 * default RGB quantization range for the mode, even when QS=0.
5664 if (info->rgb_quant_range_selectable ||
5665 rgb_quant_range == drm_default_rgb_quant_range(mode))
5666 frame->quantization_range = rgb_quant_range;
5668 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
5672 * "When transmitting any RGB colorimetry, the Source should set the
5673 * YQ-field to match the RGB Quantization Range being transmitted
5674 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5675 * set YQ=1) and the Sink shall ignore the YQ-field."
5677 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5678 * by non-zero YQ when receiving RGB. There doesn't seem to be any
5679 * good way to tell which version of CEA-861 the sink supports, so
5680 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5683 if (!is_hdmi2_sink(connector) ||
5684 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
5685 frame->ycc_quantization_range =
5686 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5688 frame->ycc_quantization_range =
5689 HDMI_YCC_QUANTIZATION_RANGE_FULL;
5691 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5694 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
5696 * @frame: HDMI AVI infoframe
5697 * @conn_state: connector state
5700 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
5701 const struct drm_connector_state *conn_state)
5703 frame->right_bar = conn_state->tv.margins.right;
5704 frame->left_bar = conn_state->tv.margins.left;
5705 frame->top_bar = conn_state->tv.margins.top;
5706 frame->bottom_bar = conn_state->tv.margins.bottom;
5708 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
5710 static enum hdmi_3d_structure
5711 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5713 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5716 case DRM_MODE_FLAG_3D_FRAME_PACKING:
5717 return HDMI_3D_STRUCTURE_FRAME_PACKING;
5718 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
5719 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
5720 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
5721 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
5722 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
5723 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
5724 case DRM_MODE_FLAG_3D_L_DEPTH:
5725 return HDMI_3D_STRUCTURE_L_DEPTH;
5726 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
5727 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
5728 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5729 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5730 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5731 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5733 return HDMI_3D_STRUCTURE_INVALID;
5738 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5739 * data from a DRM display mode
5740 * @frame: HDMI vendor infoframe
5741 * @connector: the connector
5742 * @mode: DRM display mode
5744 * Note that there's is a need to send HDMI vendor infoframes only when using a
5745 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5746 * function will return -EINVAL, error that can be safely ignored.
5748 * Return: 0 on success or a negative error code on failure.
5751 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
5752 struct drm_connector *connector,
5753 const struct drm_display_mode *mode)
5756 * FIXME: sil-sii8620 doesn't have a connector around when
5757 * we need one, so we have to be prepared for a NULL connector.
5759 bool has_hdmi_infoframe = connector ?
5760 connector->display_info.has_hdmi_infoframe : false;
5763 if (!frame || !mode)
5766 if (!has_hdmi_infoframe)
5769 err = hdmi_vendor_infoframe_init(frame);
5774 * Even if it's not absolutely necessary to send the infoframe
5775 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5776 * know that the sink can handle it. This is based on a
5777 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5778 * have trouble realizing that they shuld switch from 3D to 2D
5779 * mode if the source simply stops sending the infoframe when
5780 * it wants to switch from 3D to 2D.
5782 frame->vic = drm_mode_hdmi_vic(connector, mode);
5783 frame->s3d_struct = s3d_structure_from_display_mode(mode);
5787 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
5789 static int drm_parse_tiled_block(struct drm_connector *connector,
5790 const struct displayid_block *block)
5792 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5794 u8 tile_v_loc, tile_h_loc;
5795 u8 num_v_tile, num_h_tile;
5796 struct drm_tile_group *tg;
5798 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5799 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5801 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5802 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5803 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5804 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5806 connector->has_tile = true;
5807 if (tile->tile_cap & 0x80)
5808 connector->tile_is_single_monitor = true;
5810 connector->num_h_tile = num_h_tile + 1;
5811 connector->num_v_tile = num_v_tile + 1;
5812 connector->tile_h_loc = tile_h_loc;
5813 connector->tile_v_loc = tile_v_loc;
5814 connector->tile_h_size = w + 1;
5815 connector->tile_v_size = h + 1;
5817 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5818 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5819 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5820 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5821 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5823 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5825 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5830 if (connector->tile_group != tg) {
5831 /* if we haven't got a pointer,
5832 take the reference, drop ref to old tile group */
5833 if (connector->tile_group) {
5834 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5836 connector->tile_group = tg;
5838 /* if same tile group, then release the ref we just took. */
5839 drm_mode_put_tile_group(connector->dev, tg);
5843 static int drm_displayid_parse_tiled(struct drm_connector *connector,
5844 const u8 *displayid, int length, int idx)
5846 const struct displayid_block *block;
5849 idx += sizeof(struct displayid_hdr);
5850 for_each_displayid_db(displayid, block, idx, length) {
5851 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5852 block->tag, block->rev, block->num_bytes);
5854 switch (block->tag) {
5855 case DATA_BLOCK_TILED_DISPLAY:
5856 ret = drm_parse_tiled_block(connector, block);
5861 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5868 void drm_update_tile_info(struct drm_connector *connector,
5869 const struct edid *edid)
5871 const void *displayid = NULL;
5875 connector->has_tile = false;
5876 displayid = drm_find_displayid_extension(edid, &length, &idx);
5878 /* drop reference to any tile group we had */
5882 ret = drm_displayid_parse_tiled(connector, displayid, length, idx);
5885 if (!connector->has_tile)
5889 if (connector->tile_group) {
5890 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5891 connector->tile_group = NULL;
projects / linux-2.6-microblaze.git / blob