2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
35 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_displayid.h>
40 #include <drm/drm_scdc_helper.h>
42 #include "drm_crtc_internal.h"
44 #define version_greater(edid, maj, min) \
45 (((edid)->version > (maj)) || \
46 ((edid)->version == (maj) && (edid)->revision > (min)))
48 #define EDID_EST_TIMINGS 16
49 #define EDID_STD_TIMINGS 8
50 #define EDID_DETAILED_TIMINGS 4
53 * EDID blocks out in the wild have a variety of bugs, try to collect
54 * them here (note that userspace may work around broken monitors first,
55 * but fixes should make their way here so that the kernel "just works"
56 * on as many displays as possible).
59 /* First detailed mode wrong, use largest 60Hz mode */
60 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
61 /* Reported 135MHz pixel clock is too high, needs adjustment */
62 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
63 /* Prefer the largest mode at 75 Hz */
64 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
65 /* Detail timing is in cm not mm */
66 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
67 /* Detailed timing descriptors have bogus size values, so just take the
68 * maximum size and use that.
70 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
71 /* Monitor forgot to set the first detailed is preferred bit. */
72 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
73 /* use +hsync +vsync for detailed mode */
74 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
75 /* Force reduced-blanking timings for detailed modes */
76 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
78 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
80 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
82 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
84 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
85 /* Non desktop display (i.e. HMD) */
86 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
88 struct detailed_mode_closure {
89 struct drm_connector *connector;
101 static const struct edid_quirk {
105 } edid_quirk_list[] = {
107 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
109 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
111 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
113 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
114 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
116 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
117 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
119 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
120 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
122 /* Belinea 10 15 55 */
123 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
124 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
126 /* Envision Peripherals, Inc. EN-7100e */
127 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
128 /* Envision EN2028 */
129 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
131 /* Funai Electronics PM36B */
132 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
133 EDID_QUIRK_DETAILED_IN_CM },
135 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
136 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
138 /* LG Philips LCD LP154W01-A5 */
139 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
140 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
142 /* Philips 107p5 CRT */
143 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
146 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
148 /* Samsung SyncMaster 205BW. Note: irony */
149 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
150 /* Samsung SyncMaster 22[5-6]BW */
151 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
152 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
154 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
155 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
157 /* ViewSonic VA2026w */
158 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
160 /* Medion MD 30217 PG */
161 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
163 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
164 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
166 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
167 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
169 /* HTC Vive and Vive Pro VR Headsets */
170 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
171 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
173 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */
174 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
175 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
176 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
178 /* Windows Mixed Reality Headsets */
179 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
180 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
181 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
182 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
183 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
184 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
185 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
186 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
188 /* Sony PlayStation VR Headset */
189 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
193 * Autogenerated from the DMT spec.
194 * This table is copied from xfree86/modes/xf86EdidModes.c.
196 static const struct drm_display_mode drm_dmt_modes[] = {
197 /* 0x01 - 640x350@85Hz */
198 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
199 736, 832, 0, 350, 382, 385, 445, 0,
200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
201 /* 0x02 - 640x400@85Hz */
202 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
203 736, 832, 0, 400, 401, 404, 445, 0,
204 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
205 /* 0x03 - 720x400@85Hz */
206 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
207 828, 936, 0, 400, 401, 404, 446, 0,
208 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
209 /* 0x04 - 640x480@60Hz */
210 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
211 752, 800, 0, 480, 490, 492, 525, 0,
212 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
213 /* 0x05 - 640x480@72Hz */
214 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
215 704, 832, 0, 480, 489, 492, 520, 0,
216 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
217 /* 0x06 - 640x480@75Hz */
218 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
219 720, 840, 0, 480, 481, 484, 500, 0,
220 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
221 /* 0x07 - 640x480@85Hz */
222 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
223 752, 832, 0, 480, 481, 484, 509, 0,
224 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
225 /* 0x08 - 800x600@56Hz */
226 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
227 896, 1024, 0, 600, 601, 603, 625, 0,
228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
229 /* 0x09 - 800x600@60Hz */
230 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
231 968, 1056, 0, 600, 601, 605, 628, 0,
232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
233 /* 0x0a - 800x600@72Hz */
234 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
235 976, 1040, 0, 600, 637, 643, 666, 0,
236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
237 /* 0x0b - 800x600@75Hz */
238 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
239 896, 1056, 0, 600, 601, 604, 625, 0,
240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
241 /* 0x0c - 800x600@85Hz */
242 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
243 896, 1048, 0, 600, 601, 604, 631, 0,
244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
245 /* 0x0d - 800x600@120Hz RB */
246 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
247 880, 960, 0, 600, 603, 607, 636, 0,
248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
249 /* 0x0e - 848x480@60Hz */
250 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
251 976, 1088, 0, 480, 486, 494, 517, 0,
252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
253 /* 0x0f - 1024x768@43Hz, interlace */
254 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
255 1208, 1264, 0, 768, 768, 776, 817, 0,
256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
257 DRM_MODE_FLAG_INTERLACE) },
258 /* 0x10 - 1024x768@60Hz */
259 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
260 1184, 1344, 0, 768, 771, 777, 806, 0,
261 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
262 /* 0x11 - 1024x768@70Hz */
263 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
264 1184, 1328, 0, 768, 771, 777, 806, 0,
265 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
266 /* 0x12 - 1024x768@75Hz */
267 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
268 1136, 1312, 0, 768, 769, 772, 800, 0,
269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
270 /* 0x13 - 1024x768@85Hz */
271 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
272 1168, 1376, 0, 768, 769, 772, 808, 0,
273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
274 /* 0x14 - 1024x768@120Hz RB */
275 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
276 1104, 1184, 0, 768, 771, 775, 813, 0,
277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
278 /* 0x15 - 1152x864@75Hz */
279 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
280 1344, 1600, 0, 864, 865, 868, 900, 0,
281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
282 /* 0x55 - 1280x720@60Hz */
283 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
284 1430, 1650, 0, 720, 725, 730, 750, 0,
285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
286 /* 0x16 - 1280x768@60Hz RB */
287 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
288 1360, 1440, 0, 768, 771, 778, 790, 0,
289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
290 /* 0x17 - 1280x768@60Hz */
291 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
292 1472, 1664, 0, 768, 771, 778, 798, 0,
293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
294 /* 0x18 - 1280x768@75Hz */
295 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
296 1488, 1696, 0, 768, 771, 778, 805, 0,
297 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
298 /* 0x19 - 1280x768@85Hz */
299 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
300 1496, 1712, 0, 768, 771, 778, 809, 0,
301 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
302 /* 0x1a - 1280x768@120Hz RB */
303 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
304 1360, 1440, 0, 768, 771, 778, 813, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
306 /* 0x1b - 1280x800@60Hz RB */
307 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
308 1360, 1440, 0, 800, 803, 809, 823, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
310 /* 0x1c - 1280x800@60Hz */
311 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
312 1480, 1680, 0, 800, 803, 809, 831, 0,
313 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
314 /* 0x1d - 1280x800@75Hz */
315 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
316 1488, 1696, 0, 800, 803, 809, 838, 0,
317 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
318 /* 0x1e - 1280x800@85Hz */
319 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
320 1496, 1712, 0, 800, 803, 809, 843, 0,
321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
322 /* 0x1f - 1280x800@120Hz RB */
323 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
324 1360, 1440, 0, 800, 803, 809, 847, 0,
325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
326 /* 0x20 - 1280x960@60Hz */
327 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
328 1488, 1800, 0, 960, 961, 964, 1000, 0,
329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
330 /* 0x21 - 1280x960@85Hz */
331 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
332 1504, 1728, 0, 960, 961, 964, 1011, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
334 /* 0x22 - 1280x960@120Hz RB */
335 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
336 1360, 1440, 0, 960, 963, 967, 1017, 0,
337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
338 /* 0x23 - 1280x1024@60Hz */
339 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
340 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
342 /* 0x24 - 1280x1024@75Hz */
343 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
344 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
346 /* 0x25 - 1280x1024@85Hz */
347 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
348 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
350 /* 0x26 - 1280x1024@120Hz RB */
351 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
352 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
354 /* 0x27 - 1360x768@60Hz */
355 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
356 1536, 1792, 0, 768, 771, 777, 795, 0,
357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
358 /* 0x28 - 1360x768@120Hz RB */
359 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
360 1440, 1520, 0, 768, 771, 776, 813, 0,
361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
362 /* 0x51 - 1366x768@60Hz */
363 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
364 1579, 1792, 0, 768, 771, 774, 798, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
366 /* 0x56 - 1366x768@60Hz */
367 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
368 1436, 1500, 0, 768, 769, 772, 800, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
370 /* 0x29 - 1400x1050@60Hz RB */
371 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
372 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
374 /* 0x2a - 1400x1050@60Hz */
375 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
376 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
377 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
378 /* 0x2b - 1400x1050@75Hz */
379 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
380 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
381 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
382 /* 0x2c - 1400x1050@85Hz */
383 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
384 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
385 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
386 /* 0x2d - 1400x1050@120Hz RB */
387 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
388 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
390 /* 0x2e - 1440x900@60Hz RB */
391 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
392 1520, 1600, 0, 900, 903, 909, 926, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
394 /* 0x2f - 1440x900@60Hz */
395 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
396 1672, 1904, 0, 900, 903, 909, 934, 0,
397 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
398 /* 0x30 - 1440x900@75Hz */
399 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
400 1688, 1936, 0, 900, 903, 909, 942, 0,
401 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
402 /* 0x31 - 1440x900@85Hz */
403 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
404 1696, 1952, 0, 900, 903, 909, 948, 0,
405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
406 /* 0x32 - 1440x900@120Hz RB */
407 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
408 1520, 1600, 0, 900, 903, 909, 953, 0,
409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
410 /* 0x53 - 1600x900@60Hz */
411 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
412 1704, 1800, 0, 900, 901, 904, 1000, 0,
413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
414 /* 0x33 - 1600x1200@60Hz */
415 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
416 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
418 /* 0x34 - 1600x1200@65Hz */
419 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
420 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
422 /* 0x35 - 1600x1200@70Hz */
423 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
424 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
426 /* 0x36 - 1600x1200@75Hz */
427 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
428 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
430 /* 0x37 - 1600x1200@85Hz */
431 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
432 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
434 /* 0x38 - 1600x1200@120Hz RB */
435 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
436 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
438 /* 0x39 - 1680x1050@60Hz RB */
439 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
440 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
442 /* 0x3a - 1680x1050@60Hz */
443 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
444 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
446 /* 0x3b - 1680x1050@75Hz */
447 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
448 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
449 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
450 /* 0x3c - 1680x1050@85Hz */
451 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
452 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
453 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
454 /* 0x3d - 1680x1050@120Hz RB */
455 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
456 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
458 /* 0x3e - 1792x1344@60Hz */
459 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
460 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
461 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 0x3f - 1792x1344@75Hz */
463 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
464 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
465 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
466 /* 0x40 - 1792x1344@120Hz RB */
467 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
468 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
470 /* 0x41 - 1856x1392@60Hz */
471 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
472 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
474 /* 0x42 - 1856x1392@75Hz */
475 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
476 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
478 /* 0x43 - 1856x1392@120Hz RB */
479 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
480 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
482 /* 0x52 - 1920x1080@60Hz */
483 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
484 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
486 /* 0x44 - 1920x1200@60Hz RB */
487 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
488 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
490 /* 0x45 - 1920x1200@60Hz */
491 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
492 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
494 /* 0x46 - 1920x1200@75Hz */
495 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
496 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
498 /* 0x47 - 1920x1200@85Hz */
499 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
500 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
502 /* 0x48 - 1920x1200@120Hz RB */
503 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
504 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
506 /* 0x49 - 1920x1440@60Hz */
507 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
508 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
510 /* 0x4a - 1920x1440@75Hz */
511 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
512 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
514 /* 0x4b - 1920x1440@120Hz RB */
515 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
516 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
518 /* 0x54 - 2048x1152@60Hz */
519 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
520 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
522 /* 0x4c - 2560x1600@60Hz RB */
523 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
524 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
526 /* 0x4d - 2560x1600@60Hz */
527 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
528 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
530 /* 0x4e - 2560x1600@75Hz */
531 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
532 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
534 /* 0x4f - 2560x1600@85Hz */
535 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
536 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
538 /* 0x50 - 2560x1600@120Hz RB */
539 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
540 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
542 /* 0x57 - 4096x2160@60Hz RB */
543 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
544 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
546 /* 0x58 - 4096x2160@59.94Hz RB */
547 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
548 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
553 * These more or less come from the DMT spec. The 720x400 modes are
554 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
555 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
556 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
559 * The DMT modes have been fact-checked; the rest are mild guesses.
561 static const struct drm_display_mode edid_est_modes[] = {
562 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
563 968, 1056, 0, 600, 601, 605, 628, 0,
564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
565 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
566 896, 1024, 0, 600, 601, 603, 625, 0,
567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
568 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
569 720, 840, 0, 480, 481, 484, 500, 0,
570 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
571 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
572 704, 832, 0, 480, 489, 492, 520, 0,
573 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
574 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
575 768, 864, 0, 480, 483, 486, 525, 0,
576 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
577 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
578 752, 800, 0, 480, 490, 492, 525, 0,
579 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
580 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
581 846, 900, 0, 400, 421, 423, 449, 0,
582 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
583 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
584 846, 900, 0, 400, 412, 414, 449, 0,
585 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
586 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
587 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
589 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
590 1136, 1312, 0, 768, 769, 772, 800, 0,
591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
592 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
593 1184, 1328, 0, 768, 771, 777, 806, 0,
594 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
595 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
596 1184, 1344, 0, 768, 771, 777, 806, 0,
597 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
598 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
599 1208, 1264, 0, 768, 768, 776, 817, 0,
600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
601 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
602 928, 1152, 0, 624, 625, 628, 667, 0,
603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
604 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
605 896, 1056, 0, 600, 601, 604, 625, 0,
606 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
607 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
608 976, 1040, 0, 600, 637, 643, 666, 0,
609 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
610 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
611 1344, 1600, 0, 864, 865, 868, 900, 0,
612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
622 static const struct minimode est3_modes[] = {
630 { 1024, 768, 85, 0 },
631 { 1152, 864, 75, 0 },
633 { 1280, 768, 60, 1 },
634 { 1280, 768, 60, 0 },
635 { 1280, 768, 75, 0 },
636 { 1280, 768, 85, 0 },
637 { 1280, 960, 60, 0 },
638 { 1280, 960, 85, 0 },
639 { 1280, 1024, 60, 0 },
640 { 1280, 1024, 85, 0 },
642 { 1360, 768, 60, 0 },
643 { 1440, 900, 60, 1 },
644 { 1440, 900, 60, 0 },
645 { 1440, 900, 75, 0 },
646 { 1440, 900, 85, 0 },
647 { 1400, 1050, 60, 1 },
648 { 1400, 1050, 60, 0 },
649 { 1400, 1050, 75, 0 },
651 { 1400, 1050, 85, 0 },
652 { 1680, 1050, 60, 1 },
653 { 1680, 1050, 60, 0 },
654 { 1680, 1050, 75, 0 },
655 { 1680, 1050, 85, 0 },
656 { 1600, 1200, 60, 0 },
657 { 1600, 1200, 65, 0 },
658 { 1600, 1200, 70, 0 },
660 { 1600, 1200, 75, 0 },
661 { 1600, 1200, 85, 0 },
662 { 1792, 1344, 60, 0 },
663 { 1792, 1344, 75, 0 },
664 { 1856, 1392, 60, 0 },
665 { 1856, 1392, 75, 0 },
666 { 1920, 1200, 60, 1 },
667 { 1920, 1200, 60, 0 },
669 { 1920, 1200, 75, 0 },
670 { 1920, 1200, 85, 0 },
671 { 1920, 1440, 60, 0 },
672 { 1920, 1440, 75, 0 },
675 static const struct minimode extra_modes[] = {
676 { 1024, 576, 60, 0 },
677 { 1366, 768, 60, 0 },
678 { 1600, 900, 60, 0 },
679 { 1680, 945, 60, 0 },
680 { 1920, 1080, 60, 0 },
681 { 2048, 1152, 60, 0 },
682 { 2048, 1536, 60, 0 },
686 * Probably taken from CEA-861 spec.
687 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
689 * Index using the VIC.
691 static const struct drm_display_mode edid_cea_modes[] = {
692 /* 0 - dummy, VICs start at 1 */
694 /* 1 - 640x480@60Hz 4:3 */
695 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
696 752, 800, 0, 480, 490, 492, 525, 0,
697 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
698 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
699 /* 2 - 720x480@60Hz 4:3 */
700 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
701 798, 858, 0, 480, 489, 495, 525, 0,
702 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
703 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
704 /* 3 - 720x480@60Hz 16:9 */
705 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
706 798, 858, 0, 480, 489, 495, 525, 0,
707 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
708 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
709 /* 4 - 1280x720@60Hz 16:9 */
710 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
711 1430, 1650, 0, 720, 725, 730, 750, 0,
712 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
713 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
714 /* 5 - 1920x1080i@60Hz 16:9 */
715 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
716 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
717 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
718 DRM_MODE_FLAG_INTERLACE),
719 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
720 /* 6 - 720(1440)x480i@60Hz 4:3 */
721 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
722 801, 858, 0, 480, 488, 494, 525, 0,
723 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
724 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
725 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
726 /* 7 - 720(1440)x480i@60Hz 16:9 */
727 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
728 801, 858, 0, 480, 488, 494, 525, 0,
729 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
730 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
731 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
732 /* 8 - 720(1440)x240@60Hz 4:3 */
733 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
734 801, 858, 0, 240, 244, 247, 262, 0,
735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
736 DRM_MODE_FLAG_DBLCLK),
737 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
738 /* 9 - 720(1440)x240@60Hz 16:9 */
739 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
740 801, 858, 0, 240, 244, 247, 262, 0,
741 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
742 DRM_MODE_FLAG_DBLCLK),
743 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
744 /* 10 - 2880x480i@60Hz 4:3 */
745 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
746 3204, 3432, 0, 480, 488, 494, 525, 0,
747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
748 DRM_MODE_FLAG_INTERLACE),
749 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
750 /* 11 - 2880x480i@60Hz 16:9 */
751 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
752 3204, 3432, 0, 480, 488, 494, 525, 0,
753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
754 DRM_MODE_FLAG_INTERLACE),
755 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
756 /* 12 - 2880x240@60Hz 4:3 */
757 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
758 3204, 3432, 0, 240, 244, 247, 262, 0,
759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
760 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
761 /* 13 - 2880x240@60Hz 16:9 */
762 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
763 3204, 3432, 0, 240, 244, 247, 262, 0,
764 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
765 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
766 /* 14 - 1440x480@60Hz 4:3 */
767 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
768 1596, 1716, 0, 480, 489, 495, 525, 0,
769 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
770 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
771 /* 15 - 1440x480@60Hz 16:9 */
772 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
773 1596, 1716, 0, 480, 489, 495, 525, 0,
774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
775 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
776 /* 16 - 1920x1080@60Hz 16:9 */
777 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
778 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
779 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
780 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
781 /* 17 - 720x576@50Hz 4:3 */
782 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
783 796, 864, 0, 576, 581, 586, 625, 0,
784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
785 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
786 /* 18 - 720x576@50Hz 16:9 */
787 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
788 796, 864, 0, 576, 581, 586, 625, 0,
789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
790 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
791 /* 19 - 1280x720@50Hz 16:9 */
792 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
793 1760, 1980, 0, 720, 725, 730, 750, 0,
794 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
795 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
796 /* 20 - 1920x1080i@50Hz 16:9 */
797 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
798 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
799 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
800 DRM_MODE_FLAG_INTERLACE),
801 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
802 /* 21 - 720(1440)x576i@50Hz 4:3 */
803 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
804 795, 864, 0, 576, 580, 586, 625, 0,
805 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
806 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
807 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
808 /* 22 - 720(1440)x576i@50Hz 16:9 */
809 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
810 795, 864, 0, 576, 580, 586, 625, 0,
811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
812 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
813 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
814 /* 23 - 720(1440)x288@50Hz 4:3 */
815 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
816 795, 864, 0, 288, 290, 293, 312, 0,
817 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
818 DRM_MODE_FLAG_DBLCLK),
819 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
820 /* 24 - 720(1440)x288@50Hz 16:9 */
821 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
822 795, 864, 0, 288, 290, 293, 312, 0,
823 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
824 DRM_MODE_FLAG_DBLCLK),
825 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
826 /* 25 - 2880x576i@50Hz 4:3 */
827 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
828 3180, 3456, 0, 576, 580, 586, 625, 0,
829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
830 DRM_MODE_FLAG_INTERLACE),
831 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
832 /* 26 - 2880x576i@50Hz 16:9 */
833 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
834 3180, 3456, 0, 576, 580, 586, 625, 0,
835 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
836 DRM_MODE_FLAG_INTERLACE),
837 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
838 /* 27 - 2880x288@50Hz 4:3 */
839 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
840 3180, 3456, 0, 288, 290, 293, 312, 0,
841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
842 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
843 /* 28 - 2880x288@50Hz 16:9 */
844 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
845 3180, 3456, 0, 288, 290, 293, 312, 0,
846 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
847 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
848 /* 29 - 1440x576@50Hz 4:3 */
849 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
850 1592, 1728, 0, 576, 581, 586, 625, 0,
851 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
852 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
853 /* 30 - 1440x576@50Hz 16:9 */
854 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
855 1592, 1728, 0, 576, 581, 586, 625, 0,
856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
857 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
858 /* 31 - 1920x1080@50Hz 16:9 */
859 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
860 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
861 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
862 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
863 /* 32 - 1920x1080@24Hz 16:9 */
864 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
865 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
866 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
867 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
868 /* 33 - 1920x1080@25Hz 16:9 */
869 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
870 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
871 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
872 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
873 /* 34 - 1920x1080@30Hz 16:9 */
874 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
875 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
876 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
877 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
878 /* 35 - 2880x480@60Hz 4:3 */
879 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
880 3192, 3432, 0, 480, 489, 495, 525, 0,
881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
882 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
883 /* 36 - 2880x480@60Hz 16:9 */
884 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
885 3192, 3432, 0, 480, 489, 495, 525, 0,
886 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
887 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
888 /* 37 - 2880x576@50Hz 4:3 */
889 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
890 3184, 3456, 0, 576, 581, 586, 625, 0,
891 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
892 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
893 /* 38 - 2880x576@50Hz 16:9 */
894 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
895 3184, 3456, 0, 576, 581, 586, 625, 0,
896 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
897 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
898 /* 39 - 1920x1080i@50Hz 16:9 */
899 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
900 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
902 DRM_MODE_FLAG_INTERLACE),
903 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
904 /* 40 - 1920x1080i@100Hz 16:9 */
905 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
906 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
907 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
908 DRM_MODE_FLAG_INTERLACE),
909 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
910 /* 41 - 1280x720@100Hz 16:9 */
911 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
912 1760, 1980, 0, 720, 725, 730, 750, 0,
913 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
914 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
915 /* 42 - 720x576@100Hz 4:3 */
916 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
917 796, 864, 0, 576, 581, 586, 625, 0,
918 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
919 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
920 /* 43 - 720x576@100Hz 16:9 */
921 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
922 796, 864, 0, 576, 581, 586, 625, 0,
923 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
924 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
925 /* 44 - 720(1440)x576i@100Hz 4:3 */
926 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
927 795, 864, 0, 576, 580, 586, 625, 0,
928 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
929 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
930 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
931 /* 45 - 720(1440)x576i@100Hz 16:9 */
932 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
933 795, 864, 0, 576, 580, 586, 625, 0,
934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
935 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
936 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
937 /* 46 - 1920x1080i@120Hz 16:9 */
938 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
939 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
940 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
941 DRM_MODE_FLAG_INTERLACE),
942 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
943 /* 47 - 1280x720@120Hz 16:9 */
944 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
945 1430, 1650, 0, 720, 725, 730, 750, 0,
946 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
947 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
948 /* 48 - 720x480@120Hz 4:3 */
949 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
950 798, 858, 0, 480, 489, 495, 525, 0,
951 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
952 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
953 /* 49 - 720x480@120Hz 16:9 */
954 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
955 798, 858, 0, 480, 489, 495, 525, 0,
956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
957 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
958 /* 50 - 720(1440)x480i@120Hz 4:3 */
959 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
960 801, 858, 0, 480, 488, 494, 525, 0,
961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
962 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
963 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
964 /* 51 - 720(1440)x480i@120Hz 16:9 */
965 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
966 801, 858, 0, 480, 488, 494, 525, 0,
967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
968 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
969 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
970 /* 52 - 720x576@200Hz 4:3 */
971 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
972 796, 864, 0, 576, 581, 586, 625, 0,
973 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
974 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
975 /* 53 - 720x576@200Hz 16:9 */
976 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
977 796, 864, 0, 576, 581, 586, 625, 0,
978 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
979 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
980 /* 54 - 720(1440)x576i@200Hz 4:3 */
981 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
982 795, 864, 0, 576, 580, 586, 625, 0,
983 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
984 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
986 /* 55 - 720(1440)x576i@200Hz 16:9 */
987 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
988 795, 864, 0, 576, 580, 586, 625, 0,
989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
990 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
991 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
992 /* 56 - 720x480@240Hz 4:3 */
993 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
994 798, 858, 0, 480, 489, 495, 525, 0,
995 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
996 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
997 /* 57 - 720x480@240Hz 16:9 */
998 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
999 798, 858, 0, 480, 489, 495, 525, 0,
1000 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1001 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1002 /* 58 - 720(1440)x480i@240Hz 4:3 */
1003 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1004 801, 858, 0, 480, 488, 494, 525, 0,
1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1006 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1007 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1008 /* 59 - 720(1440)x480i@240Hz 16:9 */
1009 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1010 801, 858, 0, 480, 488, 494, 525, 0,
1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1012 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1013 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1014 /* 60 - 1280x720@24Hz 16:9 */
1015 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1016 3080, 3300, 0, 720, 725, 730, 750, 0,
1017 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1018 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1019 /* 61 - 1280x720@25Hz 16:9 */
1020 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1021 3740, 3960, 0, 720, 725, 730, 750, 0,
1022 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1023 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1024 /* 62 - 1280x720@30Hz 16:9 */
1025 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1026 3080, 3300, 0, 720, 725, 730, 750, 0,
1027 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1028 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1029 /* 63 - 1920x1080@120Hz 16:9 */
1030 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1031 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1032 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1033 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1034 /* 64 - 1920x1080@100Hz 16:9 */
1035 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1036 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1037 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1038 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1039 /* 65 - 1280x720@24Hz 64:27 */
1040 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1041 3080, 3300, 0, 720, 725, 730, 750, 0,
1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1043 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1044 /* 66 - 1280x720@25Hz 64:27 */
1045 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1046 3740, 3960, 0, 720, 725, 730, 750, 0,
1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1048 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1049 /* 67 - 1280x720@30Hz 64:27 */
1050 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1051 3080, 3300, 0, 720, 725, 730, 750, 0,
1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1053 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1054 /* 68 - 1280x720@50Hz 64:27 */
1055 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1056 1760, 1980, 0, 720, 725, 730, 750, 0,
1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1058 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1059 /* 69 - 1280x720@60Hz 64:27 */
1060 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1061 1430, 1650, 0, 720, 725, 730, 750, 0,
1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1063 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1064 /* 70 - 1280x720@100Hz 64:27 */
1065 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1066 1760, 1980, 0, 720, 725, 730, 750, 0,
1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1068 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1069 /* 71 - 1280x720@120Hz 64:27 */
1070 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1071 1430, 1650, 0, 720, 725, 730, 750, 0,
1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1073 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1074 /* 72 - 1920x1080@24Hz 64:27 */
1075 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1076 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1078 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1079 /* 73 - 1920x1080@25Hz 64:27 */
1080 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1081 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1083 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1084 /* 74 - 1920x1080@30Hz 64:27 */
1085 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1086 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1088 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1089 /* 75 - 1920x1080@50Hz 64:27 */
1090 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1091 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1093 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1094 /* 76 - 1920x1080@60Hz 64:27 */
1095 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1096 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1098 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1099 /* 77 - 1920x1080@100Hz 64:27 */
1100 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1101 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1103 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1104 /* 78 - 1920x1080@120Hz 64:27 */
1105 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1106 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1108 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1109 /* 79 - 1680x720@24Hz 64:27 */
1110 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1111 3080, 3300, 0, 720, 725, 730, 750, 0,
1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1113 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1114 /* 80 - 1680x720@25Hz 64:27 */
1115 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1116 2948, 3168, 0, 720, 725, 730, 750, 0,
1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1118 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1119 /* 81 - 1680x720@30Hz 64:27 */
1120 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1121 2420, 2640, 0, 720, 725, 730, 750, 0,
1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1123 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1124 /* 82 - 1680x720@50Hz 64:27 */
1125 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1126 1980, 2200, 0, 720, 725, 730, 750, 0,
1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1128 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1129 /* 83 - 1680x720@60Hz 64:27 */
1130 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1131 1980, 2200, 0, 720, 725, 730, 750, 0,
1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1133 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1134 /* 84 - 1680x720@100Hz 64:27 */
1135 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1136 1780, 2000, 0, 720, 725, 730, 825, 0,
1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1138 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1139 /* 85 - 1680x720@120Hz 64:27 */
1140 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1141 1780, 2000, 0, 720, 725, 730, 825, 0,
1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1143 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1144 /* 86 - 2560x1080@24Hz 64:27 */
1145 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1146 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1148 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1149 /* 87 - 2560x1080@25Hz 64:27 */
1150 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1151 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1153 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1154 /* 88 - 2560x1080@30Hz 64:27 */
1155 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1156 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1158 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1159 /* 89 - 2560x1080@50Hz 64:27 */
1160 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1161 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1163 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1164 /* 90 - 2560x1080@60Hz 64:27 */
1165 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1166 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1168 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1169 /* 91 - 2560x1080@100Hz 64:27 */
1170 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1171 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1173 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1174 /* 92 - 2560x1080@120Hz 64:27 */
1175 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1176 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1178 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1179 /* 93 - 3840x2160@24Hz 16:9 */
1180 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1181 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1183 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1184 /* 94 - 3840x2160@25Hz 16:9 */
1185 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1186 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1188 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1189 /* 95 - 3840x2160@30Hz 16:9 */
1190 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1191 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1193 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1194 /* 96 - 3840x2160@50Hz 16:9 */
1195 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1196 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1198 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1199 /* 97 - 3840x2160@60Hz 16:9 */
1200 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1201 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1203 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1204 /* 98 - 4096x2160@24Hz 256:135 */
1205 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1206 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1208 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1209 /* 99 - 4096x2160@25Hz 256:135 */
1210 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1211 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1213 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1214 /* 100 - 4096x2160@30Hz 256:135 */
1215 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1216 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1218 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1219 /* 101 - 4096x2160@50Hz 256:135 */
1220 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1221 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1223 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1224 /* 102 - 4096x2160@60Hz 256:135 */
1225 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1226 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1228 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1229 /* 103 - 3840x2160@24Hz 64:27 */
1230 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1231 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1233 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1234 /* 104 - 3840x2160@25Hz 64:27 */
1235 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1236 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1238 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1239 /* 105 - 3840x2160@30Hz 64:27 */
1240 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1241 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1243 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1244 /* 106 - 3840x2160@50Hz 64:27 */
1245 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1246 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1248 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1249 /* 107 - 3840x2160@60Hz 64:27 */
1250 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1251 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1253 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1257 * HDMI 1.4 4k modes. Index using the VIC.
1259 static const struct drm_display_mode edid_4k_modes[] = {
1260 /* 0 - dummy, VICs start at 1 */
1262 /* 1 - 3840x2160@30Hz */
1263 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1264 3840, 4016, 4104, 4400, 0,
1265 2160, 2168, 2178, 2250, 0,
1266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1268 /* 2 - 3840x2160@25Hz */
1269 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1270 3840, 4896, 4984, 5280, 0,
1271 2160, 2168, 2178, 2250, 0,
1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1274 /* 3 - 3840x2160@24Hz */
1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1276 3840, 5116, 5204, 5500, 0,
1277 2160, 2168, 2178, 2250, 0,
1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1280 /* 4 - 4096x2160@24Hz (SMPTE) */
1281 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1282 4096, 5116, 5204, 5500, 0,
1283 2160, 2168, 2178, 2250, 0,
1284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1288 /*** DDC fetch and block validation ***/
1290 static const u8 edid_header[] = {
1291 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1295 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1296 * @raw_edid: pointer to raw base EDID block
1298 * Sanity check the header of the base EDID block.
1300 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1302 int drm_edid_header_is_valid(const u8 *raw_edid)
1306 for (i = 0; i < sizeof(edid_header); i++)
1307 if (raw_edid[i] == edid_header[i])
1312 EXPORT_SYMBOL(drm_edid_header_is_valid);
1314 static int edid_fixup __read_mostly = 6;
1315 module_param_named(edid_fixup, edid_fixup, int, 0400);
1316 MODULE_PARM_DESC(edid_fixup,
1317 "Minimum number of valid EDID header bytes (0-8, default 6)");
1319 static void drm_get_displayid(struct drm_connector *connector,
1322 static int drm_edid_block_checksum(const u8 *raw_edid)
1326 for (i = 0; i < EDID_LENGTH; i++)
1327 csum += raw_edid[i];
1332 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1334 if (memchr_inv(in_edid, 0, length))
1341 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1342 * @raw_edid: pointer to raw EDID block
1343 * @block: type of block to validate (0 for base, extension otherwise)
1344 * @print_bad_edid: if true, dump bad EDID blocks to the console
1345 * @edid_corrupt: if true, the header or checksum is invalid
1347 * Validate a base or extension EDID block and optionally dump bad blocks to
1350 * Return: True if the block is valid, false otherwise.
1352 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1356 struct edid *edid = (struct edid *)raw_edid;
1358 if (WARN_ON(!raw_edid))
1361 if (edid_fixup > 8 || edid_fixup < 0)
1365 int score = drm_edid_header_is_valid(raw_edid);
1368 *edid_corrupt = false;
1369 } else if (score >= edid_fixup) {
1370 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1371 * The corrupt flag needs to be set here otherwise, the
1372 * fix-up code here will correct the problem, the
1373 * checksum is correct and the test fails
1376 *edid_corrupt = true;
1377 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1378 memcpy(raw_edid, edid_header, sizeof(edid_header));
1381 *edid_corrupt = true;
1386 csum = drm_edid_block_checksum(raw_edid);
1389 *edid_corrupt = true;
1391 /* allow CEA to slide through, switches mangle this */
1392 if (raw_edid[0] == CEA_EXT) {
1393 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1394 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1397 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1403 /* per-block-type checks */
1404 switch (raw_edid[0]) {
1406 if (edid->version != 1) {
1407 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1411 if (edid->revision > 4)
1412 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1422 if (print_bad_edid) {
1423 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1424 pr_notice("EDID block is all zeroes\n");
1426 pr_notice("Raw EDID:\n");
1427 print_hex_dump(KERN_NOTICE,
1428 " \t", DUMP_PREFIX_NONE, 16, 1,
1429 raw_edid, EDID_LENGTH, false);
1434 EXPORT_SYMBOL(drm_edid_block_valid);
1437 * drm_edid_is_valid - sanity check EDID data
1440 * Sanity-check an entire EDID record (including extensions)
1442 * Return: True if the EDID data is valid, false otherwise.
1444 bool drm_edid_is_valid(struct edid *edid)
1447 u8 *raw = (u8 *)edid;
1452 for (i = 0; i <= edid->extensions; i++)
1453 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1458 EXPORT_SYMBOL(drm_edid_is_valid);
1460 #define DDC_SEGMENT_ADDR 0x30
1462 * drm_do_probe_ddc_edid() - get EDID information via I2C
1463 * @data: I2C device adapter
1464 * @buf: EDID data buffer to be filled
1465 * @block: 128 byte EDID block to start fetching from
1466 * @len: EDID data buffer length to fetch
1468 * Try to fetch EDID information by calling I2C driver functions.
1470 * Return: 0 on success or -1 on failure.
1473 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1475 struct i2c_adapter *adapter = data;
1476 unsigned char start = block * EDID_LENGTH;
1477 unsigned char segment = block >> 1;
1478 unsigned char xfers = segment ? 3 : 2;
1479 int ret, retries = 5;
1482 * The core I2C driver will automatically retry the transfer if the
1483 * adapter reports EAGAIN. However, we find that bit-banging transfers
1484 * are susceptible to errors under a heavily loaded machine and
1485 * generate spurious NAKs and timeouts. Retrying the transfer
1486 * of the individual block a few times seems to overcome this.
1489 struct i2c_msg msgs[] = {
1491 .addr = DDC_SEGMENT_ADDR,
1509 * Avoid sending the segment addr to not upset non-compliant
1512 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1514 if (ret == -ENXIO) {
1515 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1519 } while (ret != xfers && --retries);
1521 return ret == xfers ? 0 : -1;
1524 static void connector_bad_edid(struct drm_connector *connector,
1525 u8 *edid, int num_blocks)
1529 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1532 dev_warn(connector->dev->dev,
1533 "%s: EDID is invalid:\n",
1535 for (i = 0; i < num_blocks; i++) {
1536 u8 *block = edid + i * EDID_LENGTH;
1539 if (drm_edid_is_zero(block, EDID_LENGTH))
1540 sprintf(prefix, "\t[%02x] ZERO ", i);
1541 else if (!drm_edid_block_valid(block, i, false, NULL))
1542 sprintf(prefix, "\t[%02x] BAD ", i);
1544 sprintf(prefix, "\t[%02x] GOOD ", i);
1546 print_hex_dump(KERN_WARNING,
1547 prefix, DUMP_PREFIX_NONE, 16, 1,
1548 block, EDID_LENGTH, false);
1553 * drm_do_get_edid - get EDID data using a custom EDID block read function
1554 * @connector: connector we're probing
1555 * @get_edid_block: EDID block read function
1556 * @data: private data passed to the block read function
1558 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1559 * exposes a different interface to read EDID blocks this function can be used
1560 * to get EDID data using a custom block read function.
1562 * As in the general case the DDC bus is accessible by the kernel at the I2C
1563 * level, drivers must make all reasonable efforts to expose it as an I2C
1564 * adapter and use drm_get_edid() instead of abusing this function.
1566 * The EDID may be overridden using debugfs override_edid or firmare EDID
1567 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1568 * order. Having either of them bypasses actual EDID reads.
1570 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1572 struct edid *drm_do_get_edid(struct drm_connector *connector,
1573 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1577 int i, j = 0, valid_extensions = 0;
1579 struct edid *override = NULL;
1581 if (connector->override_edid)
1582 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1585 override = drm_load_edid_firmware(connector);
1587 if (!IS_ERR_OR_NULL(override))
1590 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1593 /* base block fetch */
1594 for (i = 0; i < 4; i++) {
1595 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1597 if (drm_edid_block_valid(edid, 0, false,
1598 &connector->edid_corrupt))
1600 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1601 connector->null_edid_counter++;
1608 /* if there's no extensions, we're done */
1609 valid_extensions = edid[0x7e];
1610 if (valid_extensions == 0)
1611 return (struct edid *)edid;
1613 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1618 for (j = 1; j <= edid[0x7e]; j++) {
1619 u8 *block = edid + j * EDID_LENGTH;
1621 for (i = 0; i < 4; i++) {
1622 if (get_edid_block(data, block, j, EDID_LENGTH))
1624 if (drm_edid_block_valid(block, j, false, NULL))
1632 if (valid_extensions != edid[0x7e]) {
1635 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1637 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1638 edid[0x7e] = valid_extensions;
1640 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1646 for (i = 0; i <= edid[0x7e]; i++) {
1647 u8 *block = edid + i * EDID_LENGTH;
1649 if (!drm_edid_block_valid(block, i, false, NULL))
1652 memcpy(base, block, EDID_LENGTH);
1653 base += EDID_LENGTH;
1660 return (struct edid *)edid;
1663 connector_bad_edid(connector, edid, 1);
1668 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1671 * drm_probe_ddc() - probe DDC presence
1672 * @adapter: I2C adapter to probe
1674 * Return: True on success, false on failure.
1677 drm_probe_ddc(struct i2c_adapter *adapter)
1681 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1683 EXPORT_SYMBOL(drm_probe_ddc);
1686 * drm_get_edid - get EDID data, if available
1687 * @connector: connector we're probing
1688 * @adapter: I2C adapter to use for DDC
1690 * Poke the given I2C channel to grab EDID data if possible. If found,
1691 * attach it to the connector.
1693 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1695 struct edid *drm_get_edid(struct drm_connector *connector,
1696 struct i2c_adapter *adapter)
1700 if (connector->force == DRM_FORCE_OFF)
1703 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1706 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1708 drm_get_displayid(connector, edid);
1711 EXPORT_SYMBOL(drm_get_edid);
1714 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1715 * @connector: connector we're probing
1716 * @adapter: I2C adapter to use for DDC
1718 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1719 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1720 * switch DDC to the GPU which is retrieving EDID.
1722 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1724 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1725 struct i2c_adapter *adapter)
1727 struct pci_dev *pdev = connector->dev->pdev;
1730 vga_switcheroo_lock_ddc(pdev);
1731 edid = drm_get_edid(connector, adapter);
1732 vga_switcheroo_unlock_ddc(pdev);
1736 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1739 * drm_edid_duplicate - duplicate an EDID and the extensions
1740 * @edid: EDID to duplicate
1742 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1744 struct edid *drm_edid_duplicate(const struct edid *edid)
1746 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1748 EXPORT_SYMBOL(drm_edid_duplicate);
1750 /*** EDID parsing ***/
1753 * edid_vendor - match a string against EDID's obfuscated vendor field
1754 * @edid: EDID to match
1755 * @vendor: vendor string
1757 * Returns true if @vendor is in @edid, false otherwise
1759 static bool edid_vendor(const struct edid *edid, const char *vendor)
1761 char edid_vendor[3];
1763 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1764 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1765 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1766 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1768 return !strncmp(edid_vendor, vendor, 3);
1772 * edid_get_quirks - return quirk flags for a given EDID
1773 * @edid: EDID to process
1775 * This tells subsequent routines what fixes they need to apply.
1777 static u32 edid_get_quirks(const struct edid *edid)
1779 const struct edid_quirk *quirk;
1782 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1783 quirk = &edid_quirk_list[i];
1785 if (edid_vendor(edid, quirk->vendor) &&
1786 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1787 return quirk->quirks;
1793 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1794 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1797 * edid_fixup_preferred - set preferred modes based on quirk list
1798 * @connector: has mode list to fix up
1799 * @quirks: quirks list
1801 * Walk the mode list for @connector, clearing the preferred status
1802 * on existing modes and setting it anew for the right mode ala @quirks.
1804 static void edid_fixup_preferred(struct drm_connector *connector,
1807 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1808 int target_refresh = 0;
1809 int cur_vrefresh, preferred_vrefresh;
1811 if (list_empty(&connector->probed_modes))
1814 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1815 target_refresh = 60;
1816 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1817 target_refresh = 75;
1819 preferred_mode = list_first_entry(&connector->probed_modes,
1820 struct drm_display_mode, head);
1822 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1823 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1825 if (cur_mode == preferred_mode)
1828 /* Largest mode is preferred */
1829 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1830 preferred_mode = cur_mode;
1832 cur_vrefresh = cur_mode->vrefresh ?
1833 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1834 preferred_vrefresh = preferred_mode->vrefresh ?
1835 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1836 /* At a given size, try to get closest to target refresh */
1837 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1838 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1839 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1840 preferred_mode = cur_mode;
1844 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1848 mode_is_rb(const struct drm_display_mode *mode)
1850 return (mode->htotal - mode->hdisplay == 160) &&
1851 (mode->hsync_end - mode->hdisplay == 80) &&
1852 (mode->hsync_end - mode->hsync_start == 32) &&
1853 (mode->vsync_start - mode->vdisplay == 3);
1857 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1858 * @dev: Device to duplicate against
1859 * @hsize: Mode width
1860 * @vsize: Mode height
1861 * @fresh: Mode refresh rate
1862 * @rb: Mode reduced-blanking-ness
1864 * Walk the DMT mode list looking for a match for the given parameters.
1866 * Return: A newly allocated copy of the mode, or NULL if not found.
1868 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1869 int hsize, int vsize, int fresh,
1874 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1875 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1876 if (hsize != ptr->hdisplay)
1878 if (vsize != ptr->vdisplay)
1880 if (fresh != drm_mode_vrefresh(ptr))
1882 if (rb != mode_is_rb(ptr))
1885 return drm_mode_duplicate(dev, ptr);
1890 EXPORT_SYMBOL(drm_mode_find_dmt);
1892 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1895 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1899 u8 *det_base = ext + d;
1902 for (i = 0; i < n; i++)
1903 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1907 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1909 unsigned int i, n = min((int)ext[0x02], 6);
1910 u8 *det_base = ext + 5;
1913 return; /* unknown version */
1915 for (i = 0; i < n; i++)
1916 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1920 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1923 struct edid *edid = (struct edid *)raw_edid;
1928 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1929 cb(&(edid->detailed_timings[i]), closure);
1931 for (i = 1; i <= raw_edid[0x7e]; i++) {
1932 u8 *ext = raw_edid + (i * EDID_LENGTH);
1935 cea_for_each_detailed_block(ext, cb, closure);
1938 vtb_for_each_detailed_block(ext, cb, closure);
1947 is_rb(struct detailed_timing *t, void *data)
1950 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1952 *(bool *)data = true;
1955 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1957 drm_monitor_supports_rb(struct edid *edid)
1959 if (edid->revision >= 4) {
1961 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1965 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1969 find_gtf2(struct detailed_timing *t, void *data)
1972 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1976 /* Secondary GTF curve kicks in above some break frequency */
1978 drm_gtf2_hbreak(struct edid *edid)
1981 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1982 return r ? (r[12] * 2) : 0;
1986 drm_gtf2_2c(struct edid *edid)
1989 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1990 return r ? r[13] : 0;
1994 drm_gtf2_m(struct edid *edid)
1997 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1998 return r ? (r[15] << 8) + r[14] : 0;
2002 drm_gtf2_k(struct edid *edid)
2005 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2006 return r ? r[16] : 0;
2010 drm_gtf2_2j(struct edid *edid)
2013 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2014 return r ? r[17] : 0;
2018 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2019 * @edid: EDID block to scan
2021 static int standard_timing_level(struct edid *edid)
2023 if (edid->revision >= 2) {
2024 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2026 if (drm_gtf2_hbreak(edid))
2034 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2035 * monitors fill with ascii space (0x20) instead.
2038 bad_std_timing(u8 a, u8 b)
2040 return (a == 0x00 && b == 0x00) ||
2041 (a == 0x01 && b == 0x01) ||
2042 (a == 0x20 && b == 0x20);
2046 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2047 * @connector: connector of for the EDID block
2048 * @edid: EDID block to scan
2049 * @t: standard timing params
2051 * Take the standard timing params (in this case width, aspect, and refresh)
2052 * and convert them into a real mode using CVT/GTF/DMT.
2054 static struct drm_display_mode *
2055 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2056 struct std_timing *t)
2058 struct drm_device *dev = connector->dev;
2059 struct drm_display_mode *m, *mode = NULL;
2062 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2063 >> EDID_TIMING_ASPECT_SHIFT;
2064 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2065 >> EDID_TIMING_VFREQ_SHIFT;
2066 int timing_level = standard_timing_level(edid);
2068 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2071 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2072 hsize = t->hsize * 8 + 248;
2073 /* vrefresh_rate = vfreq + 60 */
2074 vrefresh_rate = vfreq + 60;
2075 /* the vdisplay is calculated based on the aspect ratio */
2076 if (aspect_ratio == 0) {
2077 if (edid->revision < 3)
2080 vsize = (hsize * 10) / 16;
2081 } else if (aspect_ratio == 1)
2082 vsize = (hsize * 3) / 4;
2083 else if (aspect_ratio == 2)
2084 vsize = (hsize * 4) / 5;
2086 vsize = (hsize * 9) / 16;
2088 /* HDTV hack, part 1 */
2089 if (vrefresh_rate == 60 &&
2090 ((hsize == 1360 && vsize == 765) ||
2091 (hsize == 1368 && vsize == 769))) {
2097 * If this connector already has a mode for this size and refresh
2098 * rate (because it came from detailed or CVT info), use that
2099 * instead. This way we don't have to guess at interlace or
2102 list_for_each_entry(m, &connector->probed_modes, head)
2103 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2104 drm_mode_vrefresh(m) == vrefresh_rate)
2107 /* HDTV hack, part 2 */
2108 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2109 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2113 mode->hdisplay = 1366;
2114 mode->hsync_start = mode->hsync_start - 1;
2115 mode->hsync_end = mode->hsync_end - 1;
2119 /* check whether it can be found in default mode table */
2120 if (drm_monitor_supports_rb(edid)) {
2121 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2126 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2130 /* okay, generate it */
2131 switch (timing_level) {
2135 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2139 * This is potentially wrong if there's ever a monitor with
2140 * more than one ranges section, each claiming a different
2141 * secondary GTF curve. Please don't do that.
2143 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2146 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2147 drm_mode_destroy(dev, mode);
2148 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2149 vrefresh_rate, 0, 0,
2157 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2165 * EDID is delightfully ambiguous about how interlaced modes are to be
2166 * encoded. Our internal representation is of frame height, but some
2167 * HDTV detailed timings are encoded as field height.
2169 * The format list here is from CEA, in frame size. Technically we
2170 * should be checking refresh rate too. Whatever.
2173 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2174 struct detailed_pixel_timing *pt)
2177 static const struct {
2179 } cea_interlaced[] = {
2189 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2192 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2193 if ((mode->hdisplay == cea_interlaced[i].w) &&
2194 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2195 mode->vdisplay *= 2;
2196 mode->vsync_start *= 2;
2197 mode->vsync_end *= 2;
2203 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2207 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2208 * @dev: DRM device (needed to create new mode)
2210 * @timing: EDID detailed timing info
2211 * @quirks: quirks to apply
2213 * An EDID detailed timing block contains enough info for us to create and
2214 * return a new struct drm_display_mode.
2216 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2218 struct detailed_timing *timing,
2221 struct drm_display_mode *mode;
2222 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2223 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2224 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2225 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2226 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2227 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2228 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2229 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2230 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2232 /* ignore tiny modes */
2233 if (hactive < 64 || vactive < 64)
2236 if (pt->misc & DRM_EDID_PT_STEREO) {
2237 DRM_DEBUG_KMS("stereo mode not supported\n");
2240 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2241 DRM_DEBUG_KMS("composite sync not supported\n");
2244 /* it is incorrect if hsync/vsync width is zero */
2245 if (!hsync_pulse_width || !vsync_pulse_width) {
2246 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2247 "Wrong Hsync/Vsync pulse width\n");
2251 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2252 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2259 mode = drm_mode_create(dev);
2263 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2264 timing->pixel_clock = cpu_to_le16(1088);
2266 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2268 mode->hdisplay = hactive;
2269 mode->hsync_start = mode->hdisplay + hsync_offset;
2270 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2271 mode->htotal = mode->hdisplay + hblank;
2273 mode->vdisplay = vactive;
2274 mode->vsync_start = mode->vdisplay + vsync_offset;
2275 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2276 mode->vtotal = mode->vdisplay + vblank;
2278 /* Some EDIDs have bogus h/vtotal values */
2279 if (mode->hsync_end > mode->htotal)
2280 mode->htotal = mode->hsync_end + 1;
2281 if (mode->vsync_end > mode->vtotal)
2282 mode->vtotal = mode->vsync_end + 1;
2284 drm_mode_do_interlace_quirk(mode, pt);
2286 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2287 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2290 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2291 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2292 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2293 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2296 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2297 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2299 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2300 mode->width_mm *= 10;
2301 mode->height_mm *= 10;
2304 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2305 mode->width_mm = edid->width_cm * 10;
2306 mode->height_mm = edid->height_cm * 10;
2309 mode->type = DRM_MODE_TYPE_DRIVER;
2310 mode->vrefresh = drm_mode_vrefresh(mode);
2311 drm_mode_set_name(mode);
2317 mode_in_hsync_range(const struct drm_display_mode *mode,
2318 struct edid *edid, u8 *t)
2320 int hsync, hmin, hmax;
2323 if (edid->revision >= 4)
2324 hmin += ((t[4] & 0x04) ? 255 : 0);
2326 if (edid->revision >= 4)
2327 hmax += ((t[4] & 0x08) ? 255 : 0);
2328 hsync = drm_mode_hsync(mode);
2330 return (hsync <= hmax && hsync >= hmin);
2334 mode_in_vsync_range(const struct drm_display_mode *mode,
2335 struct edid *edid, u8 *t)
2337 int vsync, vmin, vmax;
2340 if (edid->revision >= 4)
2341 vmin += ((t[4] & 0x01) ? 255 : 0);
2343 if (edid->revision >= 4)
2344 vmax += ((t[4] & 0x02) ? 255 : 0);
2345 vsync = drm_mode_vrefresh(mode);
2347 return (vsync <= vmax && vsync >= vmin);
2351 range_pixel_clock(struct edid *edid, u8 *t)
2354 if (t[9] == 0 || t[9] == 255)
2357 /* 1.4 with CVT support gives us real precision, yay */
2358 if (edid->revision >= 4 && t[10] == 0x04)
2359 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2361 /* 1.3 is pathetic, so fuzz up a bit */
2362 return t[9] * 10000 + 5001;
2366 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2367 struct detailed_timing *timing)
2370 u8 *t = (u8 *)timing;
2372 if (!mode_in_hsync_range(mode, edid, t))
2375 if (!mode_in_vsync_range(mode, edid, t))
2378 if ((max_clock = range_pixel_clock(edid, t)))
2379 if (mode->clock > max_clock)
2382 /* 1.4 max horizontal check */
2383 if (edid->revision >= 4 && t[10] == 0x04)
2384 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2387 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2393 static bool valid_inferred_mode(const struct drm_connector *connector,
2394 const struct drm_display_mode *mode)
2396 const struct drm_display_mode *m;
2399 list_for_each_entry(m, &connector->probed_modes, head) {
2400 if (mode->hdisplay == m->hdisplay &&
2401 mode->vdisplay == m->vdisplay &&
2402 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2403 return false; /* duplicated */
2404 if (mode->hdisplay <= m->hdisplay &&
2405 mode->vdisplay <= m->vdisplay)
2412 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2413 struct detailed_timing *timing)
2416 struct drm_display_mode *newmode;
2417 struct drm_device *dev = connector->dev;
2419 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2420 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2421 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2422 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2424 drm_mode_probed_add(connector, newmode);
2433 /* fix up 1366x768 mode from 1368x768;
2434 * GFT/CVT can't express 1366 width which isn't dividable by 8
2436 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2438 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2439 mode->hdisplay = 1366;
2440 mode->hsync_start--;
2442 drm_mode_set_name(mode);
2447 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2448 struct detailed_timing *timing)
2451 struct drm_display_mode *newmode;
2452 struct drm_device *dev = connector->dev;
2454 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2455 const struct minimode *m = &extra_modes[i];
2456 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2460 drm_mode_fixup_1366x768(newmode);
2461 if (!mode_in_range(newmode, edid, timing) ||
2462 !valid_inferred_mode(connector, newmode)) {
2463 drm_mode_destroy(dev, newmode);
2467 drm_mode_probed_add(connector, newmode);
2475 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2476 struct detailed_timing *timing)
2479 struct drm_display_mode *newmode;
2480 struct drm_device *dev = connector->dev;
2481 bool rb = drm_monitor_supports_rb(edid);
2483 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2484 const struct minimode *m = &extra_modes[i];
2485 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2489 drm_mode_fixup_1366x768(newmode);
2490 if (!mode_in_range(newmode, edid, timing) ||
2491 !valid_inferred_mode(connector, newmode)) {
2492 drm_mode_destroy(dev, newmode);
2496 drm_mode_probed_add(connector, newmode);
2504 do_inferred_modes(struct detailed_timing *timing, void *c)
2506 struct detailed_mode_closure *closure = c;
2507 struct detailed_non_pixel *data = &timing->data.other_data;
2508 struct detailed_data_monitor_range *range = &data->data.range;
2510 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2513 closure->modes += drm_dmt_modes_for_range(closure->connector,
2517 if (!version_greater(closure->edid, 1, 1))
2518 return; /* GTF not defined yet */
2520 switch (range->flags) {
2521 case 0x02: /* secondary gtf, XXX could do more */
2522 case 0x00: /* default gtf */
2523 closure->modes += drm_gtf_modes_for_range(closure->connector,
2527 case 0x04: /* cvt, only in 1.4+ */
2528 if (!version_greater(closure->edid, 1, 3))
2531 closure->modes += drm_cvt_modes_for_range(closure->connector,
2535 case 0x01: /* just the ranges, no formula */
2542 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2544 struct detailed_mode_closure closure = {
2545 .connector = connector,
2549 if (version_greater(edid, 1, 0))
2550 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2553 return closure.modes;
2557 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2559 int i, j, m, modes = 0;
2560 struct drm_display_mode *mode;
2561 u8 *est = ((u8 *)timing) + 6;
2563 for (i = 0; i < 6; i++) {
2564 for (j = 7; j >= 0; j--) {
2565 m = (i * 8) + (7 - j);
2566 if (m >= ARRAY_SIZE(est3_modes))
2568 if (est[i] & (1 << j)) {
2569 mode = drm_mode_find_dmt(connector->dev,
2575 drm_mode_probed_add(connector, mode);
2586 do_established_modes(struct detailed_timing *timing, void *c)
2588 struct detailed_mode_closure *closure = c;
2589 struct detailed_non_pixel *data = &timing->data.other_data;
2591 if (data->type == EDID_DETAIL_EST_TIMINGS)
2592 closure->modes += drm_est3_modes(closure->connector, timing);
2596 * add_established_modes - get est. modes from EDID and add them
2597 * @connector: connector to add mode(s) to
2598 * @edid: EDID block to scan
2600 * Each EDID block contains a bitmap of the supported "established modes" list
2601 * (defined above). Tease them out and add them to the global modes list.
2604 add_established_modes(struct drm_connector *connector, struct edid *edid)
2606 struct drm_device *dev = connector->dev;
2607 unsigned long est_bits = edid->established_timings.t1 |
2608 (edid->established_timings.t2 << 8) |
2609 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2611 struct detailed_mode_closure closure = {
2612 .connector = connector,
2616 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2617 if (est_bits & (1<<i)) {
2618 struct drm_display_mode *newmode;
2619 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2621 drm_mode_probed_add(connector, newmode);
2627 if (version_greater(edid, 1, 0))
2628 drm_for_each_detailed_block((u8 *)edid,
2629 do_established_modes, &closure);
2631 return modes + closure.modes;
2635 do_standard_modes(struct detailed_timing *timing, void *c)
2637 struct detailed_mode_closure *closure = c;
2638 struct detailed_non_pixel *data = &timing->data.other_data;
2639 struct drm_connector *connector = closure->connector;
2640 struct edid *edid = closure->edid;
2642 if (data->type == EDID_DETAIL_STD_MODES) {
2644 for (i = 0; i < 6; i++) {
2645 struct std_timing *std;
2646 struct drm_display_mode *newmode;
2648 std = &data->data.timings[i];
2649 newmode = drm_mode_std(connector, edid, std);
2651 drm_mode_probed_add(connector, newmode);
2659 * add_standard_modes - get std. modes from EDID and add them
2660 * @connector: connector to add mode(s) to
2661 * @edid: EDID block to scan
2663 * Standard modes can be calculated using the appropriate standard (DMT,
2664 * GTF or CVT. Grab them from @edid and add them to the list.
2667 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2670 struct detailed_mode_closure closure = {
2671 .connector = connector,
2675 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2676 struct drm_display_mode *newmode;
2678 newmode = drm_mode_std(connector, edid,
2679 &edid->standard_timings[i]);
2681 drm_mode_probed_add(connector, newmode);
2686 if (version_greater(edid, 1, 0))
2687 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2690 /* XXX should also look for standard codes in VTB blocks */
2692 return modes + closure.modes;
2695 static int drm_cvt_modes(struct drm_connector *connector,
2696 struct detailed_timing *timing)
2698 int i, j, modes = 0;
2699 struct drm_display_mode *newmode;
2700 struct drm_device *dev = connector->dev;
2701 struct cvt_timing *cvt;
2702 const int rates[] = { 60, 85, 75, 60, 50 };
2703 const u8 empty[3] = { 0, 0, 0 };
2705 for (i = 0; i < 4; i++) {
2706 int uninitialized_var(width), height;
2707 cvt = &(timing->data.other_data.data.cvt[i]);
2709 if (!memcmp(cvt->code, empty, 3))
2712 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2713 switch (cvt->code[1] & 0x0c) {
2715 width = height * 4 / 3;
2718 width = height * 16 / 9;
2721 width = height * 16 / 10;
2724 width = height * 15 / 9;
2728 for (j = 1; j < 5; j++) {
2729 if (cvt->code[2] & (1 << j)) {
2730 newmode = drm_cvt_mode(dev, width, height,
2734 drm_mode_probed_add(connector, newmode);
2745 do_cvt_mode(struct detailed_timing *timing, void *c)
2747 struct detailed_mode_closure *closure = c;
2748 struct detailed_non_pixel *data = &timing->data.other_data;
2750 if (data->type == EDID_DETAIL_CVT_3BYTE)
2751 closure->modes += drm_cvt_modes(closure->connector, timing);
2755 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2757 struct detailed_mode_closure closure = {
2758 .connector = connector,
2762 if (version_greater(edid, 1, 2))
2763 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2765 /* XXX should also look for CVT codes in VTB blocks */
2767 return closure.modes;
2770 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2773 do_detailed_mode(struct detailed_timing *timing, void *c)
2775 struct detailed_mode_closure *closure = c;
2776 struct drm_display_mode *newmode;
2778 if (timing->pixel_clock) {
2779 newmode = drm_mode_detailed(closure->connector->dev,
2780 closure->edid, timing,
2785 if (closure->preferred)
2786 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2789 * Detailed modes are limited to 10kHz pixel clock resolution,
2790 * so fix up anything that looks like CEA/HDMI mode, but the clock
2791 * is just slightly off.
2793 fixup_detailed_cea_mode_clock(newmode);
2795 drm_mode_probed_add(closure->connector, newmode);
2797 closure->preferred = false;
2802 * add_detailed_modes - Add modes from detailed timings
2803 * @connector: attached connector
2804 * @edid: EDID block to scan
2805 * @quirks: quirks to apply
2808 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2811 struct detailed_mode_closure closure = {
2812 .connector = connector,
2818 if (closure.preferred && !version_greater(edid, 1, 3))
2820 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2822 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2824 return closure.modes;
2827 #define AUDIO_BLOCK 0x01
2828 #define VIDEO_BLOCK 0x02
2829 #define VENDOR_BLOCK 0x03
2830 #define SPEAKER_BLOCK 0x04
2831 #define USE_EXTENDED_TAG 0x07
2832 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
2833 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
2834 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
2835 #define EDID_BASIC_AUDIO (1 << 6)
2836 #define EDID_CEA_YCRCB444 (1 << 5)
2837 #define EDID_CEA_YCRCB422 (1 << 4)
2838 #define EDID_CEA_VCDB_QS (1 << 6)
2841 * Search EDID for CEA extension block.
2843 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
2845 u8 *edid_ext = NULL;
2848 /* No EDID or EDID extensions */
2849 if (edid == NULL || edid->extensions == 0)
2852 /* Find CEA extension */
2853 for (i = 0; i < edid->extensions; i++) {
2854 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2855 if (edid_ext[0] == ext_id)
2859 if (i == edid->extensions)
2865 static u8 *drm_find_cea_extension(const struct edid *edid)
2867 return drm_find_edid_extension(edid, CEA_EXT);
2870 static u8 *drm_find_displayid_extension(const struct edid *edid)
2872 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2876 * Calculate the alternate clock for the CEA mode
2877 * (60Hz vs. 59.94Hz etc.)
2880 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2882 unsigned int clock = cea_mode->clock;
2884 if (cea_mode->vrefresh % 6 != 0)
2888 * edid_cea_modes contains the 59.94Hz
2889 * variant for 240 and 480 line modes,
2890 * and the 60Hz variant otherwise.
2892 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2893 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2895 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2901 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2904 * For certain VICs the spec allows the vertical
2905 * front porch to vary by one or two lines.
2907 * cea_modes[] stores the variant with the shortest
2908 * vertical front porch. We can adjust the mode to
2909 * get the other variants by simply increasing the
2910 * vertical front porch length.
2912 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2913 edid_cea_modes[9].vtotal != 262 ||
2914 edid_cea_modes[12].vtotal != 262 ||
2915 edid_cea_modes[13].vtotal != 262 ||
2916 edid_cea_modes[23].vtotal != 312 ||
2917 edid_cea_modes[24].vtotal != 312 ||
2918 edid_cea_modes[27].vtotal != 312 ||
2919 edid_cea_modes[28].vtotal != 312);
2921 if (((vic == 8 || vic == 9 ||
2922 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2923 ((vic == 23 || vic == 24 ||
2924 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2925 mode->vsync_start++;
2935 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2936 unsigned int clock_tolerance)
2938 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
2941 if (!to_match->clock)
2944 if (to_match->picture_aspect_ratio)
2945 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
2947 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2948 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2949 unsigned int clock1, clock2;
2951 /* Check both 60Hz and 59.94Hz */
2952 clock1 = cea_mode.clock;
2953 clock2 = cea_mode_alternate_clock(&cea_mode);
2955 if (abs(to_match->clock - clock1) > clock_tolerance &&
2956 abs(to_match->clock - clock2) > clock_tolerance)
2960 if (drm_mode_match(to_match, &cea_mode, match_flags))
2962 } while (cea_mode_alternate_timings(vic, &cea_mode));
2969 * drm_match_cea_mode - look for a CEA mode matching given mode
2970 * @to_match: display mode
2972 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2975 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2977 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
2980 if (!to_match->clock)
2983 if (to_match->picture_aspect_ratio)
2984 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
2986 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2987 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2988 unsigned int clock1, clock2;
2990 /* Check both 60Hz and 59.94Hz */
2991 clock1 = cea_mode.clock;
2992 clock2 = cea_mode_alternate_clock(&cea_mode);
2994 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
2995 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
2999 if (drm_mode_match(to_match, &cea_mode, match_flags))
3001 } while (cea_mode_alternate_timings(vic, &cea_mode));
3006 EXPORT_SYMBOL(drm_match_cea_mode);
3008 static bool drm_valid_cea_vic(u8 vic)
3010 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
3014 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
3015 * the input VIC from the CEA mode list
3016 * @video_code: ID given to each of the CEA modes
3018 * Returns picture aspect ratio
3020 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3022 return edid_cea_modes[video_code].picture_aspect_ratio;
3024 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
3027 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3030 * It's almost like cea_mode_alternate_clock(), we just need to add an
3031 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
3035 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3037 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
3038 return hdmi_mode->clock;
3040 return cea_mode_alternate_clock(hdmi_mode);
3043 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3044 unsigned int clock_tolerance)
3046 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3049 if (!to_match->clock)
3052 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3053 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3054 unsigned int clock1, clock2;
3056 /* Make sure to also match alternate clocks */
3057 clock1 = hdmi_mode->clock;
3058 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3060 if (abs(to_match->clock - clock1) > clock_tolerance &&
3061 abs(to_match->clock - clock2) > clock_tolerance)
3064 if (drm_mode_match(to_match, hdmi_mode, match_flags))
3072 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3073 * @to_match: display mode
3075 * An HDMI mode is one defined in the HDMI vendor specific block.
3077 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3079 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3081 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3084 if (!to_match->clock)
3087 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3088 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3089 unsigned int clock1, clock2;
3091 /* Make sure to also match alternate clocks */
3092 clock1 = hdmi_mode->clock;
3093 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3095 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3096 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3097 drm_mode_match(to_match, hdmi_mode, match_flags))
3103 static bool drm_valid_hdmi_vic(u8 vic)
3105 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3109 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3111 struct drm_device *dev = connector->dev;
3112 struct drm_display_mode *mode, *tmp;
3116 /* Don't add CEA modes if the CEA extension block is missing */
3117 if (!drm_find_cea_extension(edid))
3121 * Go through all probed modes and create a new mode
3122 * with the alternate clock for certain CEA modes.
3124 list_for_each_entry(mode, &connector->probed_modes, head) {
3125 const struct drm_display_mode *cea_mode = NULL;
3126 struct drm_display_mode *newmode;
3127 u8 vic = drm_match_cea_mode(mode);
3128 unsigned int clock1, clock2;
3130 if (drm_valid_cea_vic(vic)) {
3131 cea_mode = &edid_cea_modes[vic];
3132 clock2 = cea_mode_alternate_clock(cea_mode);
3134 vic = drm_match_hdmi_mode(mode);
3135 if (drm_valid_hdmi_vic(vic)) {
3136 cea_mode = &edid_4k_modes[vic];
3137 clock2 = hdmi_mode_alternate_clock(cea_mode);
3144 clock1 = cea_mode->clock;
3146 if (clock1 == clock2)
3149 if (mode->clock != clock1 && mode->clock != clock2)
3152 newmode = drm_mode_duplicate(dev, cea_mode);
3156 /* Carry over the stereo flags */
3157 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3160 * The current mode could be either variant. Make
3161 * sure to pick the "other" clock for the new mode.
3163 if (mode->clock != clock1)
3164 newmode->clock = clock1;
3166 newmode->clock = clock2;
3168 list_add_tail(&newmode->head, &list);
3171 list_for_each_entry_safe(mode, tmp, &list, head) {
3172 list_del(&mode->head);
3173 drm_mode_probed_add(connector, mode);
3180 static u8 svd_to_vic(u8 svd)
3182 /* 0-6 bit vic, 7th bit native mode indicator */
3183 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3189 static struct drm_display_mode *
3190 drm_display_mode_from_vic_index(struct drm_connector *connector,
3191 const u8 *video_db, u8 video_len,
3194 struct drm_device *dev = connector->dev;
3195 struct drm_display_mode *newmode;
3198 if (video_db == NULL || video_index >= video_len)
3201 /* CEA modes are numbered 1..127 */
3202 vic = svd_to_vic(video_db[video_index]);
3203 if (!drm_valid_cea_vic(vic))
3206 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3210 newmode->vrefresh = 0;
3216 * do_y420vdb_modes - Parse YCBCR 420 only modes
3217 * @connector: connector corresponding to the HDMI sink
3218 * @svds: start of the data block of CEA YCBCR 420 VDB
3219 * @len: length of the CEA YCBCR 420 VDB
3221 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3222 * which contains modes which can be supported in YCBCR 420
3223 * output format only.
3225 static int do_y420vdb_modes(struct drm_connector *connector,
3226 const u8 *svds, u8 svds_len)
3229 struct drm_device *dev = connector->dev;
3230 struct drm_display_info *info = &connector->display_info;
3231 struct drm_hdmi_info *hdmi = &info->hdmi;
3233 for (i = 0; i < svds_len; i++) {
3234 u8 vic = svd_to_vic(svds[i]);
3235 struct drm_display_mode *newmode;
3237 if (!drm_valid_cea_vic(vic))
3240 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3243 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3244 drm_mode_probed_add(connector, newmode);
3249 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3254 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3255 * @connector: connector corresponding to the HDMI sink
3256 * @vic: CEA vic for the video mode to be added in the map
3258 * Makes an entry for a videomode in the YCBCR 420 bitmap
3261 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3263 u8 vic = svd_to_vic(svd);
3264 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3266 if (!drm_valid_cea_vic(vic))
3269 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3273 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3276 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3278 for (i = 0; i < len; i++) {
3279 struct drm_display_mode *mode;
3280 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3283 * YCBCR420 capability block contains a bitmap which
3284 * gives the index of CEA modes from CEA VDB, which
3285 * can support YCBCR 420 sampling output also (apart
3286 * from RGB/YCBCR444 etc).
3287 * For example, if the bit 0 in bitmap is set,
3288 * first mode in VDB can support YCBCR420 output too.
3289 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3291 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3292 drm_add_cmdb_modes(connector, db[i]);
3294 drm_mode_probed_add(connector, mode);
3302 struct stereo_mandatory_mode {
3303 int width, height, vrefresh;
3307 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3308 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3309 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3311 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3313 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3314 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3315 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3316 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3317 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3321 stereo_match_mandatory(const struct drm_display_mode *mode,
3322 const struct stereo_mandatory_mode *stereo_mode)
3324 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3326 return mode->hdisplay == stereo_mode->width &&
3327 mode->vdisplay == stereo_mode->height &&
3328 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3329 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3332 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3334 struct drm_device *dev = connector->dev;
3335 const struct drm_display_mode *mode;
3336 struct list_head stereo_modes;
3339 INIT_LIST_HEAD(&stereo_modes);
3341 list_for_each_entry(mode, &connector->probed_modes, head) {
3342 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3343 const struct stereo_mandatory_mode *mandatory;
3344 struct drm_display_mode *new_mode;
3346 if (!stereo_match_mandatory(mode,
3347 &stereo_mandatory_modes[i]))
3350 mandatory = &stereo_mandatory_modes[i];
3351 new_mode = drm_mode_duplicate(dev, mode);
3355 new_mode->flags |= mandatory->flags;
3356 list_add_tail(&new_mode->head, &stereo_modes);
3361 list_splice_tail(&stereo_modes, &connector->probed_modes);
3366 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3368 struct drm_device *dev = connector->dev;
3369 struct drm_display_mode *newmode;
3371 if (!drm_valid_hdmi_vic(vic)) {
3372 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3376 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3380 drm_mode_probed_add(connector, newmode);
3385 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3386 const u8 *video_db, u8 video_len, u8 video_index)
3388 struct drm_display_mode *newmode;
3391 if (structure & (1 << 0)) {
3392 newmode = drm_display_mode_from_vic_index(connector, video_db,
3396 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3397 drm_mode_probed_add(connector, newmode);
3401 if (structure & (1 << 6)) {
3402 newmode = drm_display_mode_from_vic_index(connector, video_db,
3406 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3407 drm_mode_probed_add(connector, newmode);
3411 if (structure & (1 << 8)) {
3412 newmode = drm_display_mode_from_vic_index(connector, video_db,
3416 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3417 drm_mode_probed_add(connector, newmode);
3426 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3427 * @connector: connector corresponding to the HDMI sink
3428 * @db: start of the CEA vendor specific block
3429 * @len: length of the CEA block payload, ie. one can access up to db[len]
3431 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3432 * also adds the stereo 3d modes when applicable.
3435 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3436 const u8 *video_db, u8 video_len)
3438 struct drm_display_info *info = &connector->display_info;
3439 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3440 u8 vic_len, hdmi_3d_len = 0;
3447 /* no HDMI_Video_Present */
3448 if (!(db[8] & (1 << 5)))
3451 /* Latency_Fields_Present */
3452 if (db[8] & (1 << 7))
3455 /* I_Latency_Fields_Present */
3456 if (db[8] & (1 << 6))
3459 /* the declared length is not long enough for the 2 first bytes
3460 * of additional video format capabilities */
3461 if (len < (8 + offset + 2))
3466 if (db[8 + offset] & (1 << 7)) {
3467 modes += add_hdmi_mandatory_stereo_modes(connector);
3469 /* 3D_Multi_present */
3470 multi_present = (db[8 + offset] & 0x60) >> 5;
3474 vic_len = db[8 + offset] >> 5;
3475 hdmi_3d_len = db[8 + offset] & 0x1f;
3477 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3480 vic = db[9 + offset + i];
3481 modes += add_hdmi_mode(connector, vic);
3483 offset += 1 + vic_len;
3485 if (multi_present == 1)
3487 else if (multi_present == 2)
3492 if (len < (8 + offset + hdmi_3d_len - 1))
3495 if (hdmi_3d_len < multi_len)
3498 if (multi_present == 1 || multi_present == 2) {
3499 /* 3D_Structure_ALL */
3500 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3502 /* check if 3D_MASK is present */
3503 if (multi_present == 2)
3504 mask = (db[10 + offset] << 8) | db[11 + offset];
3508 for (i = 0; i < 16; i++) {
3509 if (mask & (1 << i))
3510 modes += add_3d_struct_modes(connector,
3517 offset += multi_len;
3519 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3521 struct drm_display_mode *newmode = NULL;
3522 unsigned int newflag = 0;
3523 bool detail_present;
3525 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3527 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3530 /* 2D_VIC_order_X */
3531 vic_index = db[8 + offset + i] >> 4;
3533 /* 3D_Structure_X */
3534 switch (db[8 + offset + i] & 0x0f) {
3536 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3539 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3543 if ((db[9 + offset + i] >> 4) == 1)
3544 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3549 newmode = drm_display_mode_from_vic_index(connector,
3555 newmode->flags |= newflag;
3556 drm_mode_probed_add(connector, newmode);
3567 info->has_hdmi_infoframe = true;
3572 cea_db_payload_len(const u8 *db)
3574 return db[0] & 0x1f;
3578 cea_db_extended_tag(const u8 *db)
3584 cea_db_tag(const u8 *db)
3590 cea_revision(const u8 *cea)
3596 cea_db_offsets(const u8 *cea, int *start, int *end)
3598 /* Data block offset in CEA extension block */
3603 if (*end < 4 || *end > 127)
3608 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3612 if (cea_db_tag(db) != VENDOR_BLOCK)
3615 if (cea_db_payload_len(db) < 5)
3618 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3620 return hdmi_id == HDMI_IEEE_OUI;
3623 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3627 if (cea_db_tag(db) != VENDOR_BLOCK)
3630 if (cea_db_payload_len(db) < 7)
3633 oui = db[3] << 16 | db[2] << 8 | db[1];
3635 return oui == HDMI_FORUM_IEEE_OUI;
3638 static bool cea_db_is_y420cmdb(const u8 *db)
3640 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3643 if (!cea_db_payload_len(db))
3646 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3652 static bool cea_db_is_y420vdb(const u8 *db)
3654 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3657 if (!cea_db_payload_len(db))
3660 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3666 #define for_each_cea_db(cea, i, start, end) \
3667 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3669 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3672 struct drm_display_info *info = &connector->display_info;
3673 struct drm_hdmi_info *hdmi = &info->hdmi;
3674 u8 map_len = cea_db_payload_len(db) - 1;
3679 /* All CEA modes support ycbcr420 sampling also.*/
3680 hdmi->y420_cmdb_map = U64_MAX;
3681 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3686 * This map indicates which of the existing CEA block modes
3687 * from VDB can support YCBCR420 output too. So if bit=0 is
3688 * set, first mode from VDB can support YCBCR420 output too.
3689 * We will parse and keep this map, before parsing VDB itself
3690 * to avoid going through the same block again and again.
3692 * Spec is not clear about max possible size of this block.
3693 * Clamping max bitmap block size at 8 bytes. Every byte can
3694 * address 8 CEA modes, in this way this map can address
3695 * 8*8 = first 64 SVDs.
3697 if (WARN_ON_ONCE(map_len > 8))
3700 for (count = 0; count < map_len; count++)
3701 map |= (u64)db[2 + count] << (8 * count);
3704 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3706 hdmi->y420_cmdb_map = map;
3710 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3712 const u8 *cea = drm_find_cea_extension(edid);
3713 const u8 *db, *hdmi = NULL, *video = NULL;
3714 u8 dbl, hdmi_len, video_len = 0;
3717 if (cea && cea_revision(cea) >= 3) {
3720 if (cea_db_offsets(cea, &start, &end))
3723 for_each_cea_db(cea, i, start, end) {
3725 dbl = cea_db_payload_len(db);
3727 if (cea_db_tag(db) == VIDEO_BLOCK) {
3730 modes += do_cea_modes(connector, video, dbl);
3731 } else if (cea_db_is_hdmi_vsdb(db)) {
3734 } else if (cea_db_is_y420vdb(db)) {
3735 const u8 *vdb420 = &db[2];
3737 /* Add 4:2:0(only) modes present in EDID */
3738 modes += do_y420vdb_modes(connector,
3746 * We parse the HDMI VSDB after having added the cea modes as we will
3747 * be patching their flags when the sink supports stereo 3D.
3750 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3756 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3758 const struct drm_display_mode *cea_mode;
3759 int clock1, clock2, clock;
3764 * allow 5kHz clock difference either way to account for
3765 * the 10kHz clock resolution limit of detailed timings.
3767 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3768 if (drm_valid_cea_vic(vic)) {
3770 cea_mode = &edid_cea_modes[vic];
3771 clock1 = cea_mode->clock;
3772 clock2 = cea_mode_alternate_clock(cea_mode);
3774 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3775 if (drm_valid_hdmi_vic(vic)) {
3777 cea_mode = &edid_4k_modes[vic];
3778 clock1 = cea_mode->clock;
3779 clock2 = hdmi_mode_alternate_clock(cea_mode);
3785 /* pick whichever is closest */
3786 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3791 if (mode->clock == clock)
3794 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3795 type, vic, mode->clock, clock);
3796 mode->clock = clock;
3800 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3802 u8 len = cea_db_payload_len(db);
3804 if (len >= 6 && (db[6] & (1 << 7)))
3805 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
3807 connector->latency_present[0] = db[8] >> 7;
3808 connector->latency_present[1] = (db[8] >> 6) & 1;
3811 connector->video_latency[0] = db[9];
3813 connector->audio_latency[0] = db[10];
3815 connector->video_latency[1] = db[11];
3817 connector->audio_latency[1] = db[12];
3819 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3820 "video latency %d %d, "
3821 "audio latency %d %d\n",
3822 connector->latency_present[0],
3823 connector->latency_present[1],
3824 connector->video_latency[0],
3825 connector->video_latency[1],
3826 connector->audio_latency[0],
3827 connector->audio_latency[1]);
3831 monitor_name(struct detailed_timing *t, void *data)
3833 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3834 *(u8 **)data = t->data.other_data.data.str.str;
3837 static int get_monitor_name(struct edid *edid, char name[13])
3839 char *edid_name = NULL;
3845 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3846 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3847 if (edid_name[mnl] == 0x0a)
3850 name[mnl] = edid_name[mnl];
3857 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3858 * @edid: monitor EDID information
3859 * @name: pointer to a character array to hold the name of the monitor
3860 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3863 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3871 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3872 memcpy(name, buf, name_length);
3873 name[name_length] = '\0';
3875 EXPORT_SYMBOL(drm_edid_get_monitor_name);
3877 static void clear_eld(struct drm_connector *connector)
3879 memset(connector->eld, 0, sizeof(connector->eld));
3881 connector->latency_present[0] = false;
3882 connector->latency_present[1] = false;
3883 connector->video_latency[0] = 0;
3884 connector->audio_latency[0] = 0;
3885 connector->video_latency[1] = 0;
3886 connector->audio_latency[1] = 0;
3890 * drm_edid_to_eld - build ELD from EDID
3891 * @connector: connector corresponding to the HDMI/DP sink
3892 * @edid: EDID to parse
3894 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3895 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
3897 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3899 uint8_t *eld = connector->eld;
3902 int total_sad_count = 0;
3906 clear_eld(connector);
3911 cea = drm_find_cea_extension(edid);
3913 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3917 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
3918 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
3920 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
3921 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
3923 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
3925 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
3926 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
3927 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
3928 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
3930 if (cea_revision(cea) >= 3) {
3933 if (cea_db_offsets(cea, &start, &end)) {
3938 for_each_cea_db(cea, i, start, end) {
3940 dbl = cea_db_payload_len(db);
3942 switch (cea_db_tag(db)) {
3946 /* Audio Data Block, contains SADs */
3947 sad_count = min(dbl / 3, 15 - total_sad_count);
3949 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
3950 &db[1], sad_count * 3);
3951 total_sad_count += sad_count;
3954 /* Speaker Allocation Data Block */
3956 eld[DRM_ELD_SPEAKER] = db[1];
3959 /* HDMI Vendor-Specific Data Block */
3960 if (cea_db_is_hdmi_vsdb(db))
3961 drm_parse_hdmi_vsdb_audio(connector, db);
3968 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
3970 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3971 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3972 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
3974 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
3976 eld[DRM_ELD_BASELINE_ELD_LEN] =
3977 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3979 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3980 drm_eld_size(eld), total_sad_count);
3984 * drm_edid_to_sad - extracts SADs from EDID
3985 * @edid: EDID to parse
3986 * @sads: pointer that will be set to the extracted SADs
3988 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3990 * Note: The returned pointer needs to be freed using kfree().
3992 * Return: The number of found SADs or negative number on error.
3994 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3997 int i, start, end, dbl;
4000 cea = drm_find_cea_extension(edid);
4002 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4006 if (cea_revision(cea) < 3) {
4007 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4011 if (cea_db_offsets(cea, &start, &end)) {
4012 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4016 for_each_cea_db(cea, i, start, end) {
4019 if (cea_db_tag(db) == AUDIO_BLOCK) {
4021 dbl = cea_db_payload_len(db);
4023 count = dbl / 3; /* SAD is 3B */
4024 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4027 for (j = 0; j < count; j++) {
4028 u8 *sad = &db[1 + j * 3];
4030 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4031 (*sads)[j].channels = sad[0] & 0x7;
4032 (*sads)[j].freq = sad[1] & 0x7F;
4033 (*sads)[j].byte2 = sad[2];
4041 EXPORT_SYMBOL(drm_edid_to_sad);
4044 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4045 * @edid: EDID to parse
4046 * @sadb: pointer to the speaker block
4048 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4050 * Note: The returned pointer needs to be freed using kfree().
4052 * Return: The number of found Speaker Allocation Blocks or negative number on
4055 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4058 int i, start, end, dbl;
4061 cea = drm_find_cea_extension(edid);
4063 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4067 if (cea_revision(cea) < 3) {
4068 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4072 if (cea_db_offsets(cea, &start, &end)) {
4073 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4077 for_each_cea_db(cea, i, start, end) {
4078 const u8 *db = &cea[i];
4080 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4081 dbl = cea_db_payload_len(db);
4083 /* Speaker Allocation Data Block */
4085 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4096 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4099 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4100 * @connector: connector associated with the HDMI/DP sink
4101 * @mode: the display mode
4103 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4104 * the sink doesn't support audio or video.
4106 int drm_av_sync_delay(struct drm_connector *connector,
4107 const struct drm_display_mode *mode)
4109 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4112 if (!connector->latency_present[0])
4114 if (!connector->latency_present[1])
4117 a = connector->audio_latency[i];
4118 v = connector->video_latency[i];
4121 * HDMI/DP sink doesn't support audio or video?
4123 if (a == 255 || v == 255)
4127 * Convert raw EDID values to millisecond.
4128 * Treat unknown latency as 0ms.
4131 a = min(2 * (a - 1), 500);
4133 v = min(2 * (v - 1), 500);
4135 return max(v - a, 0);
4137 EXPORT_SYMBOL(drm_av_sync_delay);
4140 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4141 * @edid: monitor EDID information
4143 * Parse the CEA extension according to CEA-861-B.
4145 * Return: True if the monitor is HDMI, false if not or unknown.
4147 bool drm_detect_hdmi_monitor(struct edid *edid)
4151 int start_offset, end_offset;
4153 edid_ext = drm_find_cea_extension(edid);
4157 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4161 * Because HDMI identifier is in Vendor Specific Block,
4162 * search it from all data blocks of CEA extension.
4164 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4165 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4171 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4174 * drm_detect_monitor_audio - check monitor audio capability
4175 * @edid: EDID block to scan
4177 * Monitor should have CEA extension block.
4178 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4179 * audio' only. If there is any audio extension block and supported
4180 * audio format, assume at least 'basic audio' support, even if 'basic
4181 * audio' is not defined in EDID.
4183 * Return: True if the monitor supports audio, false otherwise.
4185 bool drm_detect_monitor_audio(struct edid *edid)
4189 bool has_audio = false;
4190 int start_offset, end_offset;
4192 edid_ext = drm_find_cea_extension(edid);
4196 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4199 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4203 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4206 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4207 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4209 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4210 DRM_DEBUG_KMS("CEA audio format %d\n",
4211 (edid_ext[i + j] >> 3) & 0xf);
4218 EXPORT_SYMBOL(drm_detect_monitor_audio);
4221 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
4222 * @edid: EDID block to scan
4224 * Check whether the monitor reports the RGB quantization range selection
4225 * as supported. The AVI infoframe can then be used to inform the monitor
4226 * which quantization range (full or limited) is used.
4228 * Return: True if the RGB quantization range is selectable, false otherwise.
4230 bool drm_rgb_quant_range_selectable(struct edid *edid)
4235 edid_ext = drm_find_cea_extension(edid);
4239 if (cea_db_offsets(edid_ext, &start, &end))
4242 for_each_cea_db(edid_ext, i, start, end) {
4243 if (cea_db_tag(&edid_ext[i]) == USE_EXTENDED_TAG &&
4244 cea_db_payload_len(&edid_ext[i]) == 2 &&
4245 cea_db_extended_tag(&edid_ext[i]) ==
4246 EXT_VIDEO_CAPABILITY_BLOCK) {
4247 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
4248 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
4254 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
4257 * drm_default_rgb_quant_range - default RGB quantization range
4258 * @mode: display mode
4260 * Determine the default RGB quantization range for the mode,
4261 * as specified in CEA-861.
4263 * Return: The default RGB quantization range for the mode
4265 enum hdmi_quantization_range
4266 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4268 /* All CEA modes other than VIC 1 use limited quantization range. */
4269 return drm_match_cea_mode(mode) > 1 ?
4270 HDMI_QUANTIZATION_RANGE_LIMITED :
4271 HDMI_QUANTIZATION_RANGE_FULL;
4273 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4275 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4279 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4281 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4282 hdmi->y420_dc_modes |= dc_mask;
4285 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4288 struct drm_display_info *display = &connector->display_info;
4289 struct drm_hdmi_info *hdmi = &display->hdmi;
4291 display->has_hdmi_infoframe = true;
4293 if (hf_vsdb[6] & 0x80) {
4294 hdmi->scdc.supported = true;
4295 if (hf_vsdb[6] & 0x40)
4296 hdmi->scdc.read_request = true;
4300 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4301 * And as per the spec, three factors confirm this:
4302 * * Availability of a HF-VSDB block in EDID (check)
4303 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4304 * * SCDC support available (let's check)
4305 * Lets check it out.
4309 /* max clock is 5000 KHz times block value */
4310 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4311 struct drm_scdc *scdc = &hdmi->scdc;
4313 if (max_tmds_clock > 340000) {
4314 display->max_tmds_clock = max_tmds_clock;
4315 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4316 display->max_tmds_clock);
4319 if (scdc->supported) {
4320 scdc->scrambling.supported = true;
4322 /* Few sinks support scrambling for cloks < 340M */
4323 if ((hf_vsdb[6] & 0x8))
4324 scdc->scrambling.low_rates = true;
4328 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4331 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4334 struct drm_display_info *info = &connector->display_info;
4335 unsigned int dc_bpc = 0;
4337 /* HDMI supports at least 8 bpc */
4340 if (cea_db_payload_len(hdmi) < 6)
4343 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4345 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4346 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4350 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4352 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4353 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4357 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4359 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4360 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4365 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4370 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4371 connector->name, dc_bpc);
4375 * Deep color support mandates RGB444 support for all video
4376 * modes and forbids YCRCB422 support for all video modes per
4379 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4381 /* YCRCB444 is optional according to spec. */
4382 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4383 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4384 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4389 * Spec says that if any deep color mode is supported at all,
4390 * then deep color 36 bit must be supported.
4392 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4393 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4399 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4401 struct drm_display_info *info = &connector->display_info;
4402 u8 len = cea_db_payload_len(db);
4405 info->dvi_dual = db[6] & 1;
4407 info->max_tmds_clock = db[7] * 5000;
4409 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4410 "max TMDS clock %d kHz\n",
4412 info->max_tmds_clock);
4414 drm_parse_hdmi_deep_color_info(connector, db);
4417 static void drm_parse_cea_ext(struct drm_connector *connector,
4418 const struct edid *edid)
4420 struct drm_display_info *info = &connector->display_info;
4424 edid_ext = drm_find_cea_extension(edid);
4428 info->cea_rev = edid_ext[1];
4430 /* The existence of a CEA block should imply RGB support */
4431 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4432 if (edid_ext[3] & EDID_CEA_YCRCB444)
4433 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4434 if (edid_ext[3] & EDID_CEA_YCRCB422)
4435 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4437 if (cea_db_offsets(edid_ext, &start, &end))
4440 for_each_cea_db(edid_ext, i, start, end) {
4441 const u8 *db = &edid_ext[i];
4443 if (cea_db_is_hdmi_vsdb(db))
4444 drm_parse_hdmi_vsdb_video(connector, db);
4445 if (cea_db_is_hdmi_forum_vsdb(db))
4446 drm_parse_hdmi_forum_vsdb(connector, db);
4447 if (cea_db_is_y420cmdb(db))
4448 drm_parse_y420cmdb_bitmap(connector, db);
4452 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4453 * all of the values which would have been set from EDID
4456 drm_reset_display_info(struct drm_connector *connector)
4458 struct drm_display_info *info = &connector->display_info;
4461 info->height_mm = 0;
4464 info->color_formats = 0;
4466 info->max_tmds_clock = 0;
4467 info->dvi_dual = false;
4468 info->has_hdmi_infoframe = false;
4469 memset(&info->hdmi, 0, sizeof(info->hdmi));
4471 info->non_desktop = 0;
4474 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
4476 struct drm_display_info *info = &connector->display_info;
4478 u32 quirks = edid_get_quirks(edid);
4480 drm_reset_display_info(connector);
4482 info->width_mm = edid->width_cm * 10;
4483 info->height_mm = edid->height_cm * 10;
4485 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4487 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4489 if (edid->revision < 3)
4492 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4495 drm_parse_cea_ext(connector, edid);
4498 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4500 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4501 * tells us to assume 8 bpc color depth if the EDID doesn't have
4502 * extensions which tell otherwise.
4504 if ((info->bpc == 0) && (edid->revision < 4) &&
4505 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
4507 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4508 connector->name, info->bpc);
4511 /* Only defined for 1.4 with digital displays */
4512 if (edid->revision < 4)
4515 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4516 case DRM_EDID_DIGITAL_DEPTH_6:
4519 case DRM_EDID_DIGITAL_DEPTH_8:
4522 case DRM_EDID_DIGITAL_DEPTH_10:
4525 case DRM_EDID_DIGITAL_DEPTH_12:
4528 case DRM_EDID_DIGITAL_DEPTH_14:
4531 case DRM_EDID_DIGITAL_DEPTH_16:
4534 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4540 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4541 connector->name, info->bpc);
4543 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4544 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4545 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4546 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4547 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4551 static int validate_displayid(u8 *displayid, int length, int idx)
4555 struct displayid_hdr *base;
4557 base = (struct displayid_hdr *)&displayid[idx];
4559 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4560 base->rev, base->bytes, base->prod_id, base->ext_count);
4562 if (base->bytes + 5 > length - idx)
4564 for (i = idx; i <= base->bytes + 5; i++) {
4565 csum += displayid[i];
4568 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4574 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4575 struct displayid_detailed_timings_1 *timings)
4577 struct drm_display_mode *mode;
4578 unsigned pixel_clock = (timings->pixel_clock[0] |
4579 (timings->pixel_clock[1] << 8) |
4580 (timings->pixel_clock[2] << 16));
4581 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4582 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4583 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4584 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4585 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4586 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4587 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4588 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4589 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4590 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4591 mode = drm_mode_create(dev);
4595 mode->clock = pixel_clock * 10;
4596 mode->hdisplay = hactive;
4597 mode->hsync_start = mode->hdisplay + hsync;
4598 mode->hsync_end = mode->hsync_start + hsync_width;
4599 mode->htotal = mode->hdisplay + hblank;
4601 mode->vdisplay = vactive;
4602 mode->vsync_start = mode->vdisplay + vsync;
4603 mode->vsync_end = mode->vsync_start + vsync_width;
4604 mode->vtotal = mode->vdisplay + vblank;
4607 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4608 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4609 mode->type = DRM_MODE_TYPE_DRIVER;
4611 if (timings->flags & 0x80)
4612 mode->type |= DRM_MODE_TYPE_PREFERRED;
4613 mode->vrefresh = drm_mode_vrefresh(mode);
4614 drm_mode_set_name(mode);
4619 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4620 struct displayid_block *block)
4622 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4625 struct drm_display_mode *newmode;
4627 /* blocks must be multiple of 20 bytes length */
4628 if (block->num_bytes % 20)
4631 num_timings = block->num_bytes / 20;
4632 for (i = 0; i < num_timings; i++) {
4633 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4635 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4639 drm_mode_probed_add(connector, newmode);
4645 static int add_displayid_detailed_modes(struct drm_connector *connector,
4651 int length = EDID_LENGTH;
4652 struct displayid_block *block;
4655 displayid = drm_find_displayid_extension(edid);
4659 ret = validate_displayid(displayid, length, idx);
4663 idx += sizeof(struct displayid_hdr);
4664 while (block = (struct displayid_block *)&displayid[idx],
4665 idx + sizeof(struct displayid_block) <= length &&
4666 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4667 block->num_bytes > 0) {
4668 idx += block->num_bytes + sizeof(struct displayid_block);
4669 switch (block->tag) {
4670 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4671 num_modes += add_displayid_detailed_1_modes(connector, block);
4679 * drm_add_edid_modes - add modes from EDID data, if available
4680 * @connector: connector we're probing
4683 * Add the specified modes to the connector's mode list. Also fills out the
4684 * &drm_display_info structure and ELD in @connector with any information which
4685 * can be derived from the edid.
4687 * Return: The number of modes added or 0 if we couldn't find any.
4689 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4695 clear_eld(connector);
4698 if (!drm_edid_is_valid(edid)) {
4699 clear_eld(connector);
4700 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4705 drm_edid_to_eld(connector, edid);
4708 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4709 * To avoid multiple parsing of same block, lets parse that map
4710 * from sink info, before parsing CEA modes.
4712 quirks = drm_add_display_info(connector, edid);
4715 * EDID spec says modes should be preferred in this order:
4716 * - preferred detailed mode
4717 * - other detailed modes from base block
4718 * - detailed modes from extension blocks
4719 * - CVT 3-byte code modes
4720 * - standard timing codes
4721 * - established timing codes
4722 * - modes inferred from GTF or CVT range information
4724 * We get this pretty much right.
4726 * XXX order for additional mode types in extension blocks?
4728 num_modes += add_detailed_modes(connector, edid, quirks);
4729 num_modes += add_cvt_modes(connector, edid);
4730 num_modes += add_standard_modes(connector, edid);
4731 num_modes += add_established_modes(connector, edid);
4732 num_modes += add_cea_modes(connector, edid);
4733 num_modes += add_alternate_cea_modes(connector, edid);
4734 num_modes += add_displayid_detailed_modes(connector, edid);
4735 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4736 num_modes += add_inferred_modes(connector, edid);
4738 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4739 edid_fixup_preferred(connector, quirks);
4741 if (quirks & EDID_QUIRK_FORCE_6BPC)
4742 connector->display_info.bpc = 6;
4744 if (quirks & EDID_QUIRK_FORCE_8BPC)
4745 connector->display_info.bpc = 8;
4747 if (quirks & EDID_QUIRK_FORCE_10BPC)
4748 connector->display_info.bpc = 10;
4750 if (quirks & EDID_QUIRK_FORCE_12BPC)
4751 connector->display_info.bpc = 12;
4755 EXPORT_SYMBOL(drm_add_edid_modes);
4758 * drm_add_modes_noedid - add modes for the connectors without EDID
4759 * @connector: connector we're probing
4760 * @hdisplay: the horizontal display limit
4761 * @vdisplay: the vertical display limit
4763 * Add the specified modes to the connector's mode list. Only when the
4764 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4766 * Return: The number of modes added or 0 if we couldn't find any.
4768 int drm_add_modes_noedid(struct drm_connector *connector,
4769 int hdisplay, int vdisplay)
4771 int i, count, num_modes = 0;
4772 struct drm_display_mode *mode;
4773 struct drm_device *dev = connector->dev;
4775 count = ARRAY_SIZE(drm_dmt_modes);
4781 for (i = 0; i < count; i++) {
4782 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4783 if (hdisplay && vdisplay) {
4785 * Only when two are valid, they will be used to check
4786 * whether the mode should be added to the mode list of
4789 if (ptr->hdisplay > hdisplay ||
4790 ptr->vdisplay > vdisplay)
4793 if (drm_mode_vrefresh(ptr) > 61)
4795 mode = drm_mode_duplicate(dev, ptr);
4797 drm_mode_probed_add(connector, mode);
4803 EXPORT_SYMBOL(drm_add_modes_noedid);
4806 * drm_set_preferred_mode - Sets the preferred mode of a connector
4807 * @connector: connector whose mode list should be processed
4808 * @hpref: horizontal resolution of preferred mode
4809 * @vpref: vertical resolution of preferred mode
4811 * Marks a mode as preferred if it matches the resolution specified by @hpref
4814 void drm_set_preferred_mode(struct drm_connector *connector,
4815 int hpref, int vpref)
4817 struct drm_display_mode *mode;
4819 list_for_each_entry(mode, &connector->probed_modes, head) {
4820 if (mode->hdisplay == hpref &&
4821 mode->vdisplay == vpref)
4822 mode->type |= DRM_MODE_TYPE_PREFERRED;
4825 EXPORT_SYMBOL(drm_set_preferred_mode);
4828 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4829 * data from a DRM display mode
4830 * @frame: HDMI AVI infoframe
4831 * @mode: DRM display mode
4832 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant
4834 * Return: 0 on success or a negative error code on failure.
4837 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4838 const struct drm_display_mode *mode,
4841 enum hdmi_picture_aspect picture_aspect;
4844 if (!frame || !mode)
4847 err = hdmi_avi_infoframe_init(frame);
4851 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4852 frame->pixel_repeat = 1;
4854 frame->video_code = drm_match_cea_mode(mode);
4857 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4858 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4859 * have to make sure we dont break HDMI 1.4 sinks.
4861 if (!is_hdmi2_sink && frame->video_code > 64)
4862 frame->video_code = 0;
4865 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
4866 * we should send its VIC in vendor infoframes, else send the
4867 * VIC in AVI infoframes. Lets check if this mode is present in
4868 * HDMI 1.4b 4K modes
4870 if (frame->video_code) {
4871 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
4872 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
4874 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
4875 frame->video_code = 0;
4878 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4881 * As some drivers don't support atomic, we can't use connector state.
4882 * So just initialize the frame with default values, just the same way
4883 * as it's done with other properties here.
4885 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
4889 * Populate picture aspect ratio from either
4890 * user input (if specified) or from the CEA mode list.
4892 picture_aspect = mode->picture_aspect_ratio;
4893 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE)
4894 picture_aspect = drm_get_cea_aspect_ratio(frame->video_code);
4897 * The infoframe can't convey anything but none, 4:3
4898 * and 16:9, so if the user has asked for anything else
4899 * we can only satisfy it by specifying the right VIC.
4901 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
4902 if (picture_aspect !=
4903 drm_get_cea_aspect_ratio(frame->video_code))
4905 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4908 frame->picture_aspect = picture_aspect;
4909 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4910 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4914 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4917 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
4918 * quantization range information
4919 * @frame: HDMI AVI infoframe
4920 * @mode: DRM display mode
4921 * @rgb_quant_range: RGB quantization range (Q)
4922 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
4923 * @is_hdmi2_sink: HDMI 2.0 sink, which has different default recommendations
4925 * Note that @is_hdmi2_sink can be derived by looking at the
4926 * &drm_scdc.supported flag stored in &drm_hdmi_info.scdc,
4927 * &drm_display_info.hdmi, which can be found in &drm_connector.display_info.
4930 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
4931 const struct drm_display_mode *mode,
4932 enum hdmi_quantization_range rgb_quant_range,
4933 bool rgb_quant_range_selectable,
4938 * "A Source shall not send a non-zero Q value that does not correspond
4939 * to the default RGB Quantization Range for the transmitted Picture
4940 * unless the Sink indicates support for the Q bit in a Video
4941 * Capabilities Data Block."
4943 * HDMI 2.0 recommends sending non-zero Q when it does match the
4944 * default RGB quantization range for the mode, even when QS=0.
4946 if (rgb_quant_range_selectable ||
4947 rgb_quant_range == drm_default_rgb_quant_range(mode))
4948 frame->quantization_range = rgb_quant_range;
4950 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
4954 * "When transmitting any RGB colorimetry, the Source should set the
4955 * YQ-field to match the RGB Quantization Range being transmitted
4956 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
4957 * set YQ=1) and the Sink shall ignore the YQ-field."
4959 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
4960 * by non-zero YQ when receiving RGB. There doesn't seem to be any
4961 * good way to tell which version of CEA-861 the sink supports, so
4962 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
4965 if (!is_hdmi2_sink ||
4966 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
4967 frame->ycc_quantization_range =
4968 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
4970 frame->ycc_quantization_range =
4971 HDMI_YCC_QUANTIZATION_RANGE_FULL;
4973 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
4975 static enum hdmi_3d_structure
4976 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4978 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4981 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4982 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4983 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4984 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4985 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4986 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4987 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4988 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4989 case DRM_MODE_FLAG_3D_L_DEPTH:
4990 return HDMI_3D_STRUCTURE_L_DEPTH;
4991 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4992 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4993 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4994 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4995 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4996 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4998 return HDMI_3D_STRUCTURE_INVALID;
5003 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5004 * data from a DRM display mode
5005 * @frame: HDMI vendor infoframe
5006 * @connector: the connector
5007 * @mode: DRM display mode
5009 * Note that there's is a need to send HDMI vendor infoframes only when using a
5010 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5011 * function will return -EINVAL, error that can be safely ignored.
5013 * Return: 0 on success or a negative error code on failure.
5016 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
5017 struct drm_connector *connector,
5018 const struct drm_display_mode *mode)
5021 * FIXME: sil-sii8620 doesn't have a connector around when
5022 * we need one, so we have to be prepared for a NULL connector.
5024 bool has_hdmi_infoframe = connector ?
5025 connector->display_info.has_hdmi_infoframe : false;
5030 if (!frame || !mode)
5033 if (!has_hdmi_infoframe)
5036 vic = drm_match_hdmi_mode(mode);
5037 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
5040 * Even if it's not absolutely necessary to send the infoframe
5041 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5042 * know that the sink can handle it. This is based on a
5043 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5044 * have trouble realizing that they shuld switch from 3D to 2D
5045 * mode if the source simply stops sending the infoframe when
5046 * it wants to switch from 3D to 2D.
5049 if (vic && s3d_flags)
5052 err = hdmi_vendor_infoframe_init(frame);
5057 frame->s3d_struct = s3d_structure_from_display_mode(mode);
5061 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
5063 static int drm_parse_tiled_block(struct drm_connector *connector,
5064 struct displayid_block *block)
5066 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5068 u8 tile_v_loc, tile_h_loc;
5069 u8 num_v_tile, num_h_tile;
5070 struct drm_tile_group *tg;
5072 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5073 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5075 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5076 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5077 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5078 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5080 connector->has_tile = true;
5081 if (tile->tile_cap & 0x80)
5082 connector->tile_is_single_monitor = true;
5084 connector->num_h_tile = num_h_tile + 1;
5085 connector->num_v_tile = num_v_tile + 1;
5086 connector->tile_h_loc = tile_h_loc;
5087 connector->tile_v_loc = tile_v_loc;
5088 connector->tile_h_size = w + 1;
5089 connector->tile_v_size = h + 1;
5091 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5092 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5093 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5094 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5095 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5097 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5099 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5104 if (connector->tile_group != tg) {
5105 /* if we haven't got a pointer,
5106 take the reference, drop ref to old tile group */
5107 if (connector->tile_group) {
5108 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5110 connector->tile_group = tg;
5112 /* if same tile group, then release the ref we just took. */
5113 drm_mode_put_tile_group(connector->dev, tg);
5117 static int drm_parse_display_id(struct drm_connector *connector,
5118 u8 *displayid, int length,
5119 bool is_edid_extension)
5121 /* if this is an EDID extension the first byte will be 0x70 */
5123 struct displayid_block *block;
5126 if (is_edid_extension)
5129 ret = validate_displayid(displayid, length, idx);
5133 idx += sizeof(struct displayid_hdr);
5134 while (block = (struct displayid_block *)&displayid[idx],
5135 idx + sizeof(struct displayid_block) <= length &&
5136 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
5137 block->num_bytes > 0) {
5138 idx += block->num_bytes + sizeof(struct displayid_block);
5139 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5140 block->tag, block->rev, block->num_bytes);
5142 switch (block->tag) {
5143 case DATA_BLOCK_TILED_DISPLAY:
5144 ret = drm_parse_tiled_block(connector, block);
5148 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5149 /* handled in mode gathering code. */
5152 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5159 static void drm_get_displayid(struct drm_connector *connector,
5162 void *displayid = NULL;
5164 connector->has_tile = false;
5165 displayid = drm_find_displayid_extension(edid);
5167 /* drop reference to any tile group we had */
5171 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5174 if (!connector->has_tile)
5178 if (connector->tile_group) {
5179 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5180 connector->tile_group = NULL;
projects / linux-2.6-microblaze.git / blob