2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
35 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_displayid.h>
40 #include <drm/drm_scdc_helper.h>
42 #include "drm_crtc_internal.h"
44 #define version_greater(edid, maj, min) \
45 (((edid)->version > (maj)) || \
46 ((edid)->version == (maj) && (edid)->revision > (min)))
48 #define EDID_EST_TIMINGS 16
49 #define EDID_STD_TIMINGS 8
50 #define EDID_DETAILED_TIMINGS 4
53 * EDID blocks out in the wild have a variety of bugs, try to collect
54 * them here (note that userspace may work around broken monitors first,
55 * but fixes should make their way here so that the kernel "just works"
56 * on as many displays as possible).
59 /* First detailed mode wrong, use largest 60Hz mode */
60 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
61 /* Reported 135MHz pixel clock is too high, needs adjustment */
62 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
63 /* Prefer the largest mode at 75 Hz */
64 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
65 /* Detail timing is in cm not mm */
66 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
67 /* Detailed timing descriptors have bogus size values, so just take the
68 * maximum size and use that.
70 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
71 /* Monitor forgot to set the first detailed is preferred bit. */
72 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
73 /* use +hsync +vsync for detailed mode */
74 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
75 /* Force reduced-blanking timings for detailed modes */
76 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
78 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
80 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
82 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
84 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
85 /* Non desktop display (i.e. HMD) */
86 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
88 struct detailed_mode_closure {
89 struct drm_connector *connector;
101 static const struct edid_quirk {
105 } edid_quirk_list[] = {
107 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
109 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
111 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
113 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
114 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
116 /* Belinea 10 15 55 */
117 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
118 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
120 /* Envision Peripherals, Inc. EN-7100e */
121 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
122 /* Envision EN2028 */
123 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
125 /* Funai Electronics PM36B */
126 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
127 EDID_QUIRK_DETAILED_IN_CM },
129 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
130 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
132 /* LG Philips LCD LP154W01-A5 */
133 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
134 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
136 /* Philips 107p5 CRT */
137 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
140 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
142 /* Samsung SyncMaster 205BW. Note: irony */
143 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
144 /* Samsung SyncMaster 22[5-6]BW */
145 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
146 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
148 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
149 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
151 /* ViewSonic VA2026w */
152 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
154 /* Medion MD 30217 PG */
155 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
157 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
158 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
160 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
161 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
165 * Autogenerated from the DMT spec.
166 * This table is copied from xfree86/modes/xf86EdidModes.c.
168 static const struct drm_display_mode drm_dmt_modes[] = {
169 /* 0x01 - 640x350@85Hz */
170 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
171 736, 832, 0, 350, 382, 385, 445, 0,
172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
173 /* 0x02 - 640x400@85Hz */
174 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
175 736, 832, 0, 400, 401, 404, 445, 0,
176 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
177 /* 0x03 - 720x400@85Hz */
178 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
179 828, 936, 0, 400, 401, 404, 446, 0,
180 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
181 /* 0x04 - 640x480@60Hz */
182 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
183 752, 800, 0, 480, 490, 492, 525, 0,
184 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
185 /* 0x05 - 640x480@72Hz */
186 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
187 704, 832, 0, 480, 489, 492, 520, 0,
188 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
189 /* 0x06 - 640x480@75Hz */
190 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
191 720, 840, 0, 480, 481, 484, 500, 0,
192 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
193 /* 0x07 - 640x480@85Hz */
194 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
195 752, 832, 0, 480, 481, 484, 509, 0,
196 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
197 /* 0x08 - 800x600@56Hz */
198 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
199 896, 1024, 0, 600, 601, 603, 625, 0,
200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
201 /* 0x09 - 800x600@60Hz */
202 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
203 968, 1056, 0, 600, 601, 605, 628, 0,
204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
205 /* 0x0a - 800x600@72Hz */
206 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
207 976, 1040, 0, 600, 637, 643, 666, 0,
208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
209 /* 0x0b - 800x600@75Hz */
210 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
211 896, 1056, 0, 600, 601, 604, 625, 0,
212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
213 /* 0x0c - 800x600@85Hz */
214 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
215 896, 1048, 0, 600, 601, 604, 631, 0,
216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
217 /* 0x0d - 800x600@120Hz RB */
218 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
219 880, 960, 0, 600, 603, 607, 636, 0,
220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
221 /* 0x0e - 848x480@60Hz */
222 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
223 976, 1088, 0, 480, 486, 494, 517, 0,
224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
225 /* 0x0f - 1024x768@43Hz, interlace */
226 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
227 1208, 1264, 0, 768, 768, 776, 817, 0,
228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
229 DRM_MODE_FLAG_INTERLACE) },
230 /* 0x10 - 1024x768@60Hz */
231 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
232 1184, 1344, 0, 768, 771, 777, 806, 0,
233 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
234 /* 0x11 - 1024x768@70Hz */
235 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
236 1184, 1328, 0, 768, 771, 777, 806, 0,
237 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
238 /* 0x12 - 1024x768@75Hz */
239 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
240 1136, 1312, 0, 768, 769, 772, 800, 0,
241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
242 /* 0x13 - 1024x768@85Hz */
243 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
244 1168, 1376, 0, 768, 769, 772, 808, 0,
245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
246 /* 0x14 - 1024x768@120Hz RB */
247 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
248 1104, 1184, 0, 768, 771, 775, 813, 0,
249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
250 /* 0x15 - 1152x864@75Hz */
251 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
252 1344, 1600, 0, 864, 865, 868, 900, 0,
253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
254 /* 0x55 - 1280x720@60Hz */
255 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
256 1430, 1650, 0, 720, 725, 730, 750, 0,
257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
258 /* 0x16 - 1280x768@60Hz RB */
259 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
260 1360, 1440, 0, 768, 771, 778, 790, 0,
261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
262 /* 0x17 - 1280x768@60Hz */
263 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
264 1472, 1664, 0, 768, 771, 778, 798, 0,
265 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
266 /* 0x18 - 1280x768@75Hz */
267 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
268 1488, 1696, 0, 768, 771, 778, 805, 0,
269 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
270 /* 0x19 - 1280x768@85Hz */
271 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
272 1496, 1712, 0, 768, 771, 778, 809, 0,
273 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
274 /* 0x1a - 1280x768@120Hz RB */
275 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
276 1360, 1440, 0, 768, 771, 778, 813, 0,
277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
278 /* 0x1b - 1280x800@60Hz RB */
279 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
280 1360, 1440, 0, 800, 803, 809, 823, 0,
281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
282 /* 0x1c - 1280x800@60Hz */
283 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
284 1480, 1680, 0, 800, 803, 809, 831, 0,
285 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
286 /* 0x1d - 1280x800@75Hz */
287 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
288 1488, 1696, 0, 800, 803, 809, 838, 0,
289 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
290 /* 0x1e - 1280x800@85Hz */
291 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
292 1496, 1712, 0, 800, 803, 809, 843, 0,
293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
294 /* 0x1f - 1280x800@120Hz RB */
295 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
296 1360, 1440, 0, 800, 803, 809, 847, 0,
297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
298 /* 0x20 - 1280x960@60Hz */
299 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
300 1488, 1800, 0, 960, 961, 964, 1000, 0,
301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
302 /* 0x21 - 1280x960@85Hz */
303 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
304 1504, 1728, 0, 960, 961, 964, 1011, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
306 /* 0x22 - 1280x960@120Hz RB */
307 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
308 1360, 1440, 0, 960, 963, 967, 1017, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
310 /* 0x23 - 1280x1024@60Hz */
311 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
312 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
314 /* 0x24 - 1280x1024@75Hz */
315 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
316 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
318 /* 0x25 - 1280x1024@85Hz */
319 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
320 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
322 /* 0x26 - 1280x1024@120Hz RB */
323 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
324 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
326 /* 0x27 - 1360x768@60Hz */
327 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
328 1536, 1792, 0, 768, 771, 777, 795, 0,
329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
330 /* 0x28 - 1360x768@120Hz RB */
331 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
332 1440, 1520, 0, 768, 771, 776, 813, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
334 /* 0x51 - 1366x768@60Hz */
335 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
336 1579, 1792, 0, 768, 771, 774, 798, 0,
337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
338 /* 0x56 - 1366x768@60Hz */
339 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
340 1436, 1500, 0, 768, 769, 772, 800, 0,
341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
342 /* 0x29 - 1400x1050@60Hz RB */
343 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
344 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
346 /* 0x2a - 1400x1050@60Hz */
347 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
348 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
350 /* 0x2b - 1400x1050@75Hz */
351 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
352 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
353 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
354 /* 0x2c - 1400x1050@85Hz */
355 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
356 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
358 /* 0x2d - 1400x1050@120Hz RB */
359 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
360 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
362 /* 0x2e - 1440x900@60Hz RB */
363 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
364 1520, 1600, 0, 900, 903, 909, 926, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
366 /* 0x2f - 1440x900@60Hz */
367 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
368 1672, 1904, 0, 900, 903, 909, 934, 0,
369 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
370 /* 0x30 - 1440x900@75Hz */
371 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
372 1688, 1936, 0, 900, 903, 909, 942, 0,
373 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
374 /* 0x31 - 1440x900@85Hz */
375 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
376 1696, 1952, 0, 900, 903, 909, 948, 0,
377 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
378 /* 0x32 - 1440x900@120Hz RB */
379 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
380 1520, 1600, 0, 900, 903, 909, 953, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
382 /* 0x53 - 1600x900@60Hz */
383 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
384 1704, 1800, 0, 900, 901, 904, 1000, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
386 /* 0x33 - 1600x1200@60Hz */
387 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
388 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
390 /* 0x34 - 1600x1200@65Hz */
391 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
392 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 0x35 - 1600x1200@70Hz */
395 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
396 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
398 /* 0x36 - 1600x1200@75Hz */
399 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
400 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
402 /* 0x37 - 1600x1200@85Hz */
403 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
404 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
406 /* 0x38 - 1600x1200@120Hz RB */
407 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
408 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
410 /* 0x39 - 1680x1050@60Hz RB */
411 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
412 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
414 /* 0x3a - 1680x1050@60Hz */
415 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
416 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
417 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
418 /* 0x3b - 1680x1050@75Hz */
419 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
420 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
422 /* 0x3c - 1680x1050@85Hz */
423 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
424 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
426 /* 0x3d - 1680x1050@120Hz RB */
427 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
428 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
430 /* 0x3e - 1792x1344@60Hz */
431 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
432 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
434 /* 0x3f - 1792x1344@75Hz */
435 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
436 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
438 /* 0x40 - 1792x1344@120Hz RB */
439 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
440 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
442 /* 0x41 - 1856x1392@60Hz */
443 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
444 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
446 /* 0x42 - 1856x1392@75Hz */
447 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
448 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
449 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
450 /* 0x43 - 1856x1392@120Hz RB */
451 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
452 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
454 /* 0x52 - 1920x1080@60Hz */
455 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
456 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
457 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
458 /* 0x44 - 1920x1200@60Hz RB */
459 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
460 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
462 /* 0x45 - 1920x1200@60Hz */
463 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
464 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
465 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
466 /* 0x46 - 1920x1200@75Hz */
467 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
468 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
469 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
470 /* 0x47 - 1920x1200@85Hz */
471 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
472 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
474 /* 0x48 - 1920x1200@120Hz RB */
475 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
476 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
478 /* 0x49 - 1920x1440@60Hz */
479 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
480 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
482 /* 0x4a - 1920x1440@75Hz */
483 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
484 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
485 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
486 /* 0x4b - 1920x1440@120Hz RB */
487 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
488 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
490 /* 0x54 - 2048x1152@60Hz */
491 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
492 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
494 /* 0x4c - 2560x1600@60Hz RB */
495 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
496 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
498 /* 0x4d - 2560x1600@60Hz */
499 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
500 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
502 /* 0x4e - 2560x1600@75Hz */
503 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
504 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
506 /* 0x4f - 2560x1600@85Hz */
507 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
508 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
510 /* 0x50 - 2560x1600@120Hz RB */
511 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
512 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
514 /* 0x57 - 4096x2160@60Hz RB */
515 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
516 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
518 /* 0x58 - 4096x2160@59.94Hz RB */
519 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
520 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
525 * These more or less come from the DMT spec. The 720x400 modes are
526 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
527 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
528 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
531 * The DMT modes have been fact-checked; the rest are mild guesses.
533 static const struct drm_display_mode edid_est_modes[] = {
534 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
535 968, 1056, 0, 600, 601, 605, 628, 0,
536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
537 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
538 896, 1024, 0, 600, 601, 603, 625, 0,
539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
540 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
541 720, 840, 0, 480, 481, 484, 500, 0,
542 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
543 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
544 704, 832, 0, 480, 489, 492, 520, 0,
545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
546 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
547 768, 864, 0, 480, 483, 486, 525, 0,
548 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
549 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
550 752, 800, 0, 480, 490, 492, 525, 0,
551 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
552 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
553 846, 900, 0, 400, 421, 423, 449, 0,
554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
555 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
556 846, 900, 0, 400, 412, 414, 449, 0,
557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
558 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
559 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
561 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
562 1136, 1312, 0, 768, 769, 772, 800, 0,
563 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
564 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
565 1184, 1328, 0, 768, 771, 777, 806, 0,
566 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
567 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
568 1184, 1344, 0, 768, 771, 777, 806, 0,
569 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
570 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
571 1208, 1264, 0, 768, 768, 776, 817, 0,
572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
573 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
574 928, 1152, 0, 624, 625, 628, 667, 0,
575 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
576 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
577 896, 1056, 0, 600, 601, 604, 625, 0,
578 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
579 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
580 976, 1040, 0, 600, 637, 643, 666, 0,
581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
582 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
583 1344, 1600, 0, 864, 865, 868, 900, 0,
584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
594 static const struct minimode est3_modes[] = {
602 { 1024, 768, 85, 0 },
603 { 1152, 864, 75, 0 },
605 { 1280, 768, 60, 1 },
606 { 1280, 768, 60, 0 },
607 { 1280, 768, 75, 0 },
608 { 1280, 768, 85, 0 },
609 { 1280, 960, 60, 0 },
610 { 1280, 960, 85, 0 },
611 { 1280, 1024, 60, 0 },
612 { 1280, 1024, 85, 0 },
614 { 1360, 768, 60, 0 },
615 { 1440, 900, 60, 1 },
616 { 1440, 900, 60, 0 },
617 { 1440, 900, 75, 0 },
618 { 1440, 900, 85, 0 },
619 { 1400, 1050, 60, 1 },
620 { 1400, 1050, 60, 0 },
621 { 1400, 1050, 75, 0 },
623 { 1400, 1050, 85, 0 },
624 { 1680, 1050, 60, 1 },
625 { 1680, 1050, 60, 0 },
626 { 1680, 1050, 75, 0 },
627 { 1680, 1050, 85, 0 },
628 { 1600, 1200, 60, 0 },
629 { 1600, 1200, 65, 0 },
630 { 1600, 1200, 70, 0 },
632 { 1600, 1200, 75, 0 },
633 { 1600, 1200, 85, 0 },
634 { 1792, 1344, 60, 0 },
635 { 1792, 1344, 75, 0 },
636 { 1856, 1392, 60, 0 },
637 { 1856, 1392, 75, 0 },
638 { 1920, 1200, 60, 1 },
639 { 1920, 1200, 60, 0 },
641 { 1920, 1200, 75, 0 },
642 { 1920, 1200, 85, 0 },
643 { 1920, 1440, 60, 0 },
644 { 1920, 1440, 75, 0 },
647 static const struct minimode extra_modes[] = {
648 { 1024, 576, 60, 0 },
649 { 1366, 768, 60, 0 },
650 { 1600, 900, 60, 0 },
651 { 1680, 945, 60, 0 },
652 { 1920, 1080, 60, 0 },
653 { 2048, 1152, 60, 0 },
654 { 2048, 1536, 60, 0 },
658 * Probably taken from CEA-861 spec.
659 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
661 * Index using the VIC.
663 static const struct drm_display_mode edid_cea_modes[] = {
664 /* 0 - dummy, VICs start at 1 */
666 /* 1 - 640x480@60Hz */
667 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
668 752, 800, 0, 480, 490, 492, 525, 0,
669 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
670 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
671 /* 2 - 720x480@60Hz */
672 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
673 798, 858, 0, 480, 489, 495, 525, 0,
674 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
675 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
676 /* 3 - 720x480@60Hz */
677 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
678 798, 858, 0, 480, 489, 495, 525, 0,
679 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
680 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
681 /* 4 - 1280x720@60Hz */
682 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
683 1430, 1650, 0, 720, 725, 730, 750, 0,
684 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
685 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
686 /* 5 - 1920x1080i@60Hz */
687 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
688 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
689 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
690 DRM_MODE_FLAG_INTERLACE),
691 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
692 /* 6 - 720(1440)x480i@60Hz */
693 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
694 801, 858, 0, 480, 488, 494, 525, 0,
695 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
696 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
697 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
698 /* 7 - 720(1440)x480i@60Hz */
699 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
700 801, 858, 0, 480, 488, 494, 525, 0,
701 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
702 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
703 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
704 /* 8 - 720(1440)x240@60Hz */
705 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
706 801, 858, 0, 240, 244, 247, 262, 0,
707 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
708 DRM_MODE_FLAG_DBLCLK),
709 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
710 /* 9 - 720(1440)x240@60Hz */
711 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
712 801, 858, 0, 240, 244, 247, 262, 0,
713 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
714 DRM_MODE_FLAG_DBLCLK),
715 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
716 /* 10 - 2880x480i@60Hz */
717 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
718 3204, 3432, 0, 480, 488, 494, 525, 0,
719 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
720 DRM_MODE_FLAG_INTERLACE),
721 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
722 /* 11 - 2880x480i@60Hz */
723 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
724 3204, 3432, 0, 480, 488, 494, 525, 0,
725 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
726 DRM_MODE_FLAG_INTERLACE),
727 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
728 /* 12 - 2880x240@60Hz */
729 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
730 3204, 3432, 0, 240, 244, 247, 262, 0,
731 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
732 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
733 /* 13 - 2880x240@60Hz */
734 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
735 3204, 3432, 0, 240, 244, 247, 262, 0,
736 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
737 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
738 /* 14 - 1440x480@60Hz */
739 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
740 1596, 1716, 0, 480, 489, 495, 525, 0,
741 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
742 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
743 /* 15 - 1440x480@60Hz */
744 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
745 1596, 1716, 0, 480, 489, 495, 525, 0,
746 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
747 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
748 /* 16 - 1920x1080@60Hz */
749 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
750 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
751 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
752 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
753 /* 17 - 720x576@50Hz */
754 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
755 796, 864, 0, 576, 581, 586, 625, 0,
756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
757 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
758 /* 18 - 720x576@50Hz */
759 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
760 796, 864, 0, 576, 581, 586, 625, 0,
761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
762 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
763 /* 19 - 1280x720@50Hz */
764 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
765 1760, 1980, 0, 720, 725, 730, 750, 0,
766 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
767 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
768 /* 20 - 1920x1080i@50Hz */
769 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
770 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
771 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
772 DRM_MODE_FLAG_INTERLACE),
773 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
774 /* 21 - 720(1440)x576i@50Hz */
775 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
776 795, 864, 0, 576, 580, 586, 625, 0,
777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
778 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
779 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
780 /* 22 - 720(1440)x576i@50Hz */
781 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
782 795, 864, 0, 576, 580, 586, 625, 0,
783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
784 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
785 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
786 /* 23 - 720(1440)x288@50Hz */
787 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
788 795, 864, 0, 288, 290, 293, 312, 0,
789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
790 DRM_MODE_FLAG_DBLCLK),
791 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
792 /* 24 - 720(1440)x288@50Hz */
793 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
794 795, 864, 0, 288, 290, 293, 312, 0,
795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
796 DRM_MODE_FLAG_DBLCLK),
797 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
798 /* 25 - 2880x576i@50Hz */
799 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
800 3180, 3456, 0, 576, 580, 586, 625, 0,
801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
802 DRM_MODE_FLAG_INTERLACE),
803 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
804 /* 26 - 2880x576i@50Hz */
805 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
806 3180, 3456, 0, 576, 580, 586, 625, 0,
807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
808 DRM_MODE_FLAG_INTERLACE),
809 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
810 /* 27 - 2880x288@50Hz */
811 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
812 3180, 3456, 0, 288, 290, 293, 312, 0,
813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
814 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
815 /* 28 - 2880x288@50Hz */
816 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
817 3180, 3456, 0, 288, 290, 293, 312, 0,
818 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
819 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
820 /* 29 - 1440x576@50Hz */
821 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
822 1592, 1728, 0, 576, 581, 586, 625, 0,
823 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
824 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
825 /* 30 - 1440x576@50Hz */
826 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
827 1592, 1728, 0, 576, 581, 586, 625, 0,
828 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
829 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
830 /* 31 - 1920x1080@50Hz */
831 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
832 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
833 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
834 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
835 /* 32 - 1920x1080@24Hz */
836 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
837 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
838 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
839 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
840 /* 33 - 1920x1080@25Hz */
841 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
842 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
843 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
844 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
845 /* 34 - 1920x1080@30Hz */
846 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
847 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
848 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
849 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
850 /* 35 - 2880x480@60Hz */
851 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
852 3192, 3432, 0, 480, 489, 495, 525, 0,
853 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
854 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
855 /* 36 - 2880x480@60Hz */
856 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
857 3192, 3432, 0, 480, 489, 495, 525, 0,
858 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
859 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
860 /* 37 - 2880x576@50Hz */
861 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
862 3184, 3456, 0, 576, 581, 586, 625, 0,
863 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
864 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
865 /* 38 - 2880x576@50Hz */
866 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
867 3184, 3456, 0, 576, 581, 586, 625, 0,
868 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
869 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
870 /* 39 - 1920x1080i@50Hz */
871 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
872 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
873 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
874 DRM_MODE_FLAG_INTERLACE),
875 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
876 /* 40 - 1920x1080i@100Hz */
877 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
878 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
879 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
880 DRM_MODE_FLAG_INTERLACE),
881 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
882 /* 41 - 1280x720@100Hz */
883 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
884 1760, 1980, 0, 720, 725, 730, 750, 0,
885 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
886 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
887 /* 42 - 720x576@100Hz */
888 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
889 796, 864, 0, 576, 581, 586, 625, 0,
890 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
891 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
892 /* 43 - 720x576@100Hz */
893 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
894 796, 864, 0, 576, 581, 586, 625, 0,
895 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
896 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
897 /* 44 - 720(1440)x576i@100Hz */
898 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
899 795, 864, 0, 576, 580, 586, 625, 0,
900 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
901 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
902 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
903 /* 45 - 720(1440)x576i@100Hz */
904 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
905 795, 864, 0, 576, 580, 586, 625, 0,
906 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
907 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
908 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
909 /* 46 - 1920x1080i@120Hz */
910 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
911 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
912 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
913 DRM_MODE_FLAG_INTERLACE),
914 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
915 /* 47 - 1280x720@120Hz */
916 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
917 1430, 1650, 0, 720, 725, 730, 750, 0,
918 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
919 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
920 /* 48 - 720x480@120Hz */
921 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
922 798, 858, 0, 480, 489, 495, 525, 0,
923 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
924 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
925 /* 49 - 720x480@120Hz */
926 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
927 798, 858, 0, 480, 489, 495, 525, 0,
928 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
929 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
930 /* 50 - 720(1440)x480i@120Hz */
931 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
932 801, 858, 0, 480, 488, 494, 525, 0,
933 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
934 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
935 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
936 /* 51 - 720(1440)x480i@120Hz */
937 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
938 801, 858, 0, 480, 488, 494, 525, 0,
939 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
940 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
941 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
942 /* 52 - 720x576@200Hz */
943 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
944 796, 864, 0, 576, 581, 586, 625, 0,
945 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
946 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
947 /* 53 - 720x576@200Hz */
948 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
949 796, 864, 0, 576, 581, 586, 625, 0,
950 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
951 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
952 /* 54 - 720(1440)x576i@200Hz */
953 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
954 795, 864, 0, 576, 580, 586, 625, 0,
955 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
956 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
957 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
958 /* 55 - 720(1440)x576i@200Hz */
959 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
960 795, 864, 0, 576, 580, 586, 625, 0,
961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
962 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
963 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
964 /* 56 - 720x480@240Hz */
965 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
966 798, 858, 0, 480, 489, 495, 525, 0,
967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
968 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
969 /* 57 - 720x480@240Hz */
970 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
971 798, 858, 0, 480, 489, 495, 525, 0,
972 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
973 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
974 /* 58 - 720(1440)x480i@240Hz */
975 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
976 801, 858, 0, 480, 488, 494, 525, 0,
977 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
978 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
979 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
980 /* 59 - 720(1440)x480i@240Hz */
981 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
982 801, 858, 0, 480, 488, 494, 525, 0,
983 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
984 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
986 /* 60 - 1280x720@24Hz */
987 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
988 3080, 3300, 0, 720, 725, 730, 750, 0,
989 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
990 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
991 /* 61 - 1280x720@25Hz */
992 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
993 3740, 3960, 0, 720, 725, 730, 750, 0,
994 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
995 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
996 /* 62 - 1280x720@30Hz */
997 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
998 3080, 3300, 0, 720, 725, 730, 750, 0,
999 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1000 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1001 /* 63 - 1920x1080@120Hz */
1002 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1003 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1004 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1005 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1006 /* 64 - 1920x1080@100Hz */
1007 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1008 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1009 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1010 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1011 /* 65 - 1280x720@24Hz */
1012 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1013 3080, 3300, 0, 720, 725, 730, 750, 0,
1014 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1015 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1016 /* 66 - 1280x720@25Hz */
1017 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1018 3740, 3960, 0, 720, 725, 730, 750, 0,
1019 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1020 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1021 /* 67 - 1280x720@30Hz */
1022 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1023 3080, 3300, 0, 720, 725, 730, 750, 0,
1024 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1025 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1026 /* 68 - 1280x720@50Hz */
1027 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1028 1760, 1980, 0, 720, 725, 730, 750, 0,
1029 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1030 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1031 /* 69 - 1280x720@60Hz */
1032 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1033 1430, 1650, 0, 720, 725, 730, 750, 0,
1034 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1035 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1036 /* 70 - 1280x720@100Hz */
1037 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1038 1760, 1980, 0, 720, 725, 730, 750, 0,
1039 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1040 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1041 /* 71 - 1280x720@120Hz */
1042 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1043 1430, 1650, 0, 720, 725, 730, 750, 0,
1044 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1045 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1046 /* 72 - 1920x1080@24Hz */
1047 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1048 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1049 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1050 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1051 /* 73 - 1920x1080@25Hz */
1052 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1053 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1054 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1055 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1056 /* 74 - 1920x1080@30Hz */
1057 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1058 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1059 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1060 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1061 /* 75 - 1920x1080@50Hz */
1062 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1063 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1064 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1065 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1066 /* 76 - 1920x1080@60Hz */
1067 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1068 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1069 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1070 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1071 /* 77 - 1920x1080@100Hz */
1072 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1073 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1075 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1076 /* 78 - 1920x1080@120Hz */
1077 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1078 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1079 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1080 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1081 /* 79 - 1680x720@24Hz */
1082 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1083 3080, 3300, 0, 720, 725, 730, 750, 0,
1084 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1085 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1086 /* 80 - 1680x720@25Hz */
1087 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1088 2948, 3168, 0, 720, 725, 730, 750, 0,
1089 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1090 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1091 /* 81 - 1680x720@30Hz */
1092 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1093 2420, 2640, 0, 720, 725, 730, 750, 0,
1094 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1095 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1096 /* 82 - 1680x720@50Hz */
1097 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1098 1980, 2200, 0, 720, 725, 730, 750, 0,
1099 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1100 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1101 /* 83 - 1680x720@60Hz */
1102 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1103 1980, 2200, 0, 720, 725, 730, 750, 0,
1104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1105 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1106 /* 84 - 1680x720@100Hz */
1107 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1108 1780, 2000, 0, 720, 725, 730, 825, 0,
1109 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1110 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1111 /* 85 - 1680x720@120Hz */
1112 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1113 1780, 2000, 0, 720, 725, 730, 825, 0,
1114 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1115 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1116 /* 86 - 2560x1080@24Hz */
1117 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1118 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1119 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1120 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1121 /* 87 - 2560x1080@25Hz */
1122 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1123 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1124 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1125 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1126 /* 88 - 2560x1080@30Hz */
1127 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1128 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1129 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1130 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1131 /* 89 - 2560x1080@50Hz */
1132 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1133 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1135 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1136 /* 90 - 2560x1080@60Hz */
1137 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1138 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1139 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1140 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1141 /* 91 - 2560x1080@100Hz */
1142 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1143 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1145 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1146 /* 92 - 2560x1080@120Hz */
1147 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1148 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1149 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1150 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1151 /* 93 - 3840x2160p@24Hz 16:9 */
1152 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1153 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1155 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1156 /* 94 - 3840x2160p@25Hz 16:9 */
1157 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1158 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1159 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1160 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1161 /* 95 - 3840x2160p@30Hz 16:9 */
1162 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1163 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1165 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1166 /* 96 - 3840x2160p@50Hz 16:9 */
1167 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1168 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1170 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1171 /* 97 - 3840x2160p@60Hz 16:9 */
1172 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1173 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1175 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1176 /* 98 - 4096x2160p@24Hz 256:135 */
1177 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1178 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1180 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1181 /* 99 - 4096x2160p@25Hz 256:135 */
1182 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1183 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1185 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1186 /* 100 - 4096x2160p@30Hz 256:135 */
1187 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1188 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1190 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1191 /* 101 - 4096x2160p@50Hz 256:135 */
1192 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1193 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1195 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1196 /* 102 - 4096x2160p@60Hz 256:135 */
1197 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1198 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1200 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1201 /* 103 - 3840x2160p@24Hz 64:27 */
1202 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1203 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1205 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1206 /* 104 - 3840x2160p@25Hz 64:27 */
1207 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1208 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1210 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1211 /* 105 - 3840x2160p@30Hz 64:27 */
1212 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1213 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1215 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1216 /* 106 - 3840x2160p@50Hz 64:27 */
1217 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1218 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1220 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1221 /* 107 - 3840x2160p@60Hz 64:27 */
1222 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1223 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1225 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1229 * HDMI 1.4 4k modes. Index using the VIC.
1231 static const struct drm_display_mode edid_4k_modes[] = {
1232 /* 0 - dummy, VICs start at 1 */
1234 /* 1 - 3840x2160@30Hz */
1235 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1236 3840, 4016, 4104, 4400, 0,
1237 2160, 2168, 2178, 2250, 0,
1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1240 /* 2 - 3840x2160@25Hz */
1241 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1242 3840, 4896, 4984, 5280, 0,
1243 2160, 2168, 2178, 2250, 0,
1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1246 /* 3 - 3840x2160@24Hz */
1247 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1248 3840, 5116, 5204, 5500, 0,
1249 2160, 2168, 2178, 2250, 0,
1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1252 /* 4 - 4096x2160@24Hz (SMPTE) */
1253 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1254 4096, 5116, 5204, 5500, 0,
1255 2160, 2168, 2178, 2250, 0,
1256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1260 /*** DDC fetch and block validation ***/
1262 static const u8 edid_header[] = {
1263 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1267 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1268 * @raw_edid: pointer to raw base EDID block
1270 * Sanity check the header of the base EDID block.
1272 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1274 int drm_edid_header_is_valid(const u8 *raw_edid)
1278 for (i = 0; i < sizeof(edid_header); i++)
1279 if (raw_edid[i] == edid_header[i])
1284 EXPORT_SYMBOL(drm_edid_header_is_valid);
1286 static int edid_fixup __read_mostly = 6;
1287 module_param_named(edid_fixup, edid_fixup, int, 0400);
1288 MODULE_PARM_DESC(edid_fixup,
1289 "Minimum number of valid EDID header bytes (0-8, default 6)");
1291 static void drm_get_displayid(struct drm_connector *connector,
1294 static int drm_edid_block_checksum(const u8 *raw_edid)
1298 for (i = 0; i < EDID_LENGTH; i++)
1299 csum += raw_edid[i];
1304 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1306 if (memchr_inv(in_edid, 0, length))
1313 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1314 * @raw_edid: pointer to raw EDID block
1315 * @block: type of block to validate (0 for base, extension otherwise)
1316 * @print_bad_edid: if true, dump bad EDID blocks to the console
1317 * @edid_corrupt: if true, the header or checksum is invalid
1319 * Validate a base or extension EDID block and optionally dump bad blocks to
1322 * Return: True if the block is valid, false otherwise.
1324 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1328 struct edid *edid = (struct edid *)raw_edid;
1330 if (WARN_ON(!raw_edid))
1333 if (edid_fixup > 8 || edid_fixup < 0)
1337 int score = drm_edid_header_is_valid(raw_edid);
1340 *edid_corrupt = false;
1341 } else if (score >= edid_fixup) {
1342 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1343 * The corrupt flag needs to be set here otherwise, the
1344 * fix-up code here will correct the problem, the
1345 * checksum is correct and the test fails
1348 *edid_corrupt = true;
1349 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1350 memcpy(raw_edid, edid_header, sizeof(edid_header));
1353 *edid_corrupt = true;
1358 csum = drm_edid_block_checksum(raw_edid);
1361 *edid_corrupt = true;
1363 /* allow CEA to slide through, switches mangle this */
1364 if (raw_edid[0] == CEA_EXT) {
1365 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1366 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1369 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1375 /* per-block-type checks */
1376 switch (raw_edid[0]) {
1378 if (edid->version != 1) {
1379 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1383 if (edid->revision > 4)
1384 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1394 if (print_bad_edid) {
1395 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1396 pr_notice("EDID block is all zeroes\n");
1398 pr_notice("Raw EDID:\n");
1399 print_hex_dump(KERN_NOTICE,
1400 " \t", DUMP_PREFIX_NONE, 16, 1,
1401 raw_edid, EDID_LENGTH, false);
1406 EXPORT_SYMBOL(drm_edid_block_valid);
1409 * drm_edid_is_valid - sanity check EDID data
1412 * Sanity-check an entire EDID record (including extensions)
1414 * Return: True if the EDID data is valid, false otherwise.
1416 bool drm_edid_is_valid(struct edid *edid)
1419 u8 *raw = (u8 *)edid;
1424 for (i = 0; i <= edid->extensions; i++)
1425 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1430 EXPORT_SYMBOL(drm_edid_is_valid);
1432 #define DDC_SEGMENT_ADDR 0x30
1434 * drm_do_probe_ddc_edid() - get EDID information via I2C
1435 * @data: I2C device adapter
1436 * @buf: EDID data buffer to be filled
1437 * @block: 128 byte EDID block to start fetching from
1438 * @len: EDID data buffer length to fetch
1440 * Try to fetch EDID information by calling I2C driver functions.
1442 * Return: 0 on success or -1 on failure.
1445 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1447 struct i2c_adapter *adapter = data;
1448 unsigned char start = block * EDID_LENGTH;
1449 unsigned char segment = block >> 1;
1450 unsigned char xfers = segment ? 3 : 2;
1451 int ret, retries = 5;
1454 * The core I2C driver will automatically retry the transfer if the
1455 * adapter reports EAGAIN. However, we find that bit-banging transfers
1456 * are susceptible to errors under a heavily loaded machine and
1457 * generate spurious NAKs and timeouts. Retrying the transfer
1458 * of the individual block a few times seems to overcome this.
1461 struct i2c_msg msgs[] = {
1463 .addr = DDC_SEGMENT_ADDR,
1481 * Avoid sending the segment addr to not upset non-compliant
1484 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1486 if (ret == -ENXIO) {
1487 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1491 } while (ret != xfers && --retries);
1493 return ret == xfers ? 0 : -1;
1496 static void connector_bad_edid(struct drm_connector *connector,
1497 u8 *edid, int num_blocks)
1501 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1504 dev_warn(connector->dev->dev,
1505 "%s: EDID is invalid:\n",
1507 for (i = 0; i < num_blocks; i++) {
1508 u8 *block = edid + i * EDID_LENGTH;
1511 if (drm_edid_is_zero(block, EDID_LENGTH))
1512 sprintf(prefix, "\t[%02x] ZERO ", i);
1513 else if (!drm_edid_block_valid(block, i, false, NULL))
1514 sprintf(prefix, "\t[%02x] BAD ", i);
1516 sprintf(prefix, "\t[%02x] GOOD ", i);
1518 print_hex_dump(KERN_WARNING,
1519 prefix, DUMP_PREFIX_NONE, 16, 1,
1520 block, EDID_LENGTH, false);
1525 * drm_do_get_edid - get EDID data using a custom EDID block read function
1526 * @connector: connector we're probing
1527 * @get_edid_block: EDID block read function
1528 * @data: private data passed to the block read function
1530 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1531 * exposes a different interface to read EDID blocks this function can be used
1532 * to get EDID data using a custom block read function.
1534 * As in the general case the DDC bus is accessible by the kernel at the I2C
1535 * level, drivers must make all reasonable efforts to expose it as an I2C
1536 * adapter and use drm_get_edid() instead of abusing this function.
1538 * The EDID may be overridden using debugfs override_edid or firmare EDID
1539 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1540 * order. Having either of them bypasses actual EDID reads.
1542 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1544 struct edid *drm_do_get_edid(struct drm_connector *connector,
1545 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1549 int i, j = 0, valid_extensions = 0;
1551 struct edid *override = NULL;
1553 if (connector->override_edid)
1554 override = drm_edid_duplicate((const struct edid *)
1555 connector->edid_blob_ptr->data);
1558 override = drm_load_edid_firmware(connector);
1560 if (!IS_ERR_OR_NULL(override))
1563 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1566 /* base block fetch */
1567 for (i = 0; i < 4; i++) {
1568 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1570 if (drm_edid_block_valid(edid, 0, false,
1571 &connector->edid_corrupt))
1573 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1574 connector->null_edid_counter++;
1581 /* if there's no extensions, we're done */
1582 valid_extensions = edid[0x7e];
1583 if (valid_extensions == 0)
1584 return (struct edid *)edid;
1586 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1591 for (j = 1; j <= edid[0x7e]; j++) {
1592 u8 *block = edid + j * EDID_LENGTH;
1594 for (i = 0; i < 4; i++) {
1595 if (get_edid_block(data, block, j, EDID_LENGTH))
1597 if (drm_edid_block_valid(block, j, false, NULL))
1605 if (valid_extensions != edid[0x7e]) {
1608 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1610 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1611 edid[0x7e] = valid_extensions;
1613 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1618 for (i = 0; i <= edid[0x7e]; i++) {
1619 u8 *block = edid + i * EDID_LENGTH;
1621 if (!drm_edid_block_valid(block, i, false, NULL))
1624 memcpy(base, block, EDID_LENGTH);
1625 base += EDID_LENGTH;
1632 return (struct edid *)edid;
1635 connector_bad_edid(connector, edid, 1);
1640 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1643 * drm_probe_ddc() - probe DDC presence
1644 * @adapter: I2C adapter to probe
1646 * Return: True on success, false on failure.
1649 drm_probe_ddc(struct i2c_adapter *adapter)
1653 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1655 EXPORT_SYMBOL(drm_probe_ddc);
1658 * drm_get_edid - get EDID data, if available
1659 * @connector: connector we're probing
1660 * @adapter: I2C adapter to use for DDC
1662 * Poke the given I2C channel to grab EDID data if possible. If found,
1663 * attach it to the connector.
1665 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1667 struct edid *drm_get_edid(struct drm_connector *connector,
1668 struct i2c_adapter *adapter)
1672 if (connector->force == DRM_FORCE_OFF)
1675 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1678 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1680 drm_get_displayid(connector, edid);
1683 EXPORT_SYMBOL(drm_get_edid);
1686 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1687 * @connector: connector we're probing
1688 * @adapter: I2C adapter to use for DDC
1690 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1691 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1692 * switch DDC to the GPU which is retrieving EDID.
1694 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1696 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1697 struct i2c_adapter *adapter)
1699 struct pci_dev *pdev = connector->dev->pdev;
1702 vga_switcheroo_lock_ddc(pdev);
1703 edid = drm_get_edid(connector, adapter);
1704 vga_switcheroo_unlock_ddc(pdev);
1708 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1711 * drm_edid_duplicate - duplicate an EDID and the extensions
1712 * @edid: EDID to duplicate
1714 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1716 struct edid *drm_edid_duplicate(const struct edid *edid)
1718 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1720 EXPORT_SYMBOL(drm_edid_duplicate);
1722 /*** EDID parsing ***/
1725 * edid_vendor - match a string against EDID's obfuscated vendor field
1726 * @edid: EDID to match
1727 * @vendor: vendor string
1729 * Returns true if @vendor is in @edid, false otherwise
1731 static bool edid_vendor(struct edid *edid, const char *vendor)
1733 char edid_vendor[3];
1735 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1736 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1737 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1738 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1740 return !strncmp(edid_vendor, vendor, 3);
1744 * edid_get_quirks - return quirk flags for a given EDID
1745 * @edid: EDID to process
1747 * This tells subsequent routines what fixes they need to apply.
1749 static u32 edid_get_quirks(struct edid *edid)
1751 const struct edid_quirk *quirk;
1754 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1755 quirk = &edid_quirk_list[i];
1757 if (edid_vendor(edid, quirk->vendor) &&
1758 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1759 return quirk->quirks;
1765 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1766 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1769 * edid_fixup_preferred - set preferred modes based on quirk list
1770 * @connector: has mode list to fix up
1771 * @quirks: quirks list
1773 * Walk the mode list for @connector, clearing the preferred status
1774 * on existing modes and setting it anew for the right mode ala @quirks.
1776 static void edid_fixup_preferred(struct drm_connector *connector,
1779 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1780 int target_refresh = 0;
1781 int cur_vrefresh, preferred_vrefresh;
1783 if (list_empty(&connector->probed_modes))
1786 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1787 target_refresh = 60;
1788 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1789 target_refresh = 75;
1791 preferred_mode = list_first_entry(&connector->probed_modes,
1792 struct drm_display_mode, head);
1794 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1795 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1797 if (cur_mode == preferred_mode)
1800 /* Largest mode is preferred */
1801 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1802 preferred_mode = cur_mode;
1804 cur_vrefresh = cur_mode->vrefresh ?
1805 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1806 preferred_vrefresh = preferred_mode->vrefresh ?
1807 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1808 /* At a given size, try to get closest to target refresh */
1809 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1810 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1811 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1812 preferred_mode = cur_mode;
1816 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1820 mode_is_rb(const struct drm_display_mode *mode)
1822 return (mode->htotal - mode->hdisplay == 160) &&
1823 (mode->hsync_end - mode->hdisplay == 80) &&
1824 (mode->hsync_end - mode->hsync_start == 32) &&
1825 (mode->vsync_start - mode->vdisplay == 3);
1829 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1830 * @dev: Device to duplicate against
1831 * @hsize: Mode width
1832 * @vsize: Mode height
1833 * @fresh: Mode refresh rate
1834 * @rb: Mode reduced-blanking-ness
1836 * Walk the DMT mode list looking for a match for the given parameters.
1838 * Return: A newly allocated copy of the mode, or NULL if not found.
1840 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1841 int hsize, int vsize, int fresh,
1846 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1847 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1848 if (hsize != ptr->hdisplay)
1850 if (vsize != ptr->vdisplay)
1852 if (fresh != drm_mode_vrefresh(ptr))
1854 if (rb != mode_is_rb(ptr))
1857 return drm_mode_duplicate(dev, ptr);
1862 EXPORT_SYMBOL(drm_mode_find_dmt);
1864 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1867 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1871 u8 *det_base = ext + d;
1874 for (i = 0; i < n; i++)
1875 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1879 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1881 unsigned int i, n = min((int)ext[0x02], 6);
1882 u8 *det_base = ext + 5;
1885 return; /* unknown version */
1887 for (i = 0; i < n; i++)
1888 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1892 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1895 struct edid *edid = (struct edid *)raw_edid;
1900 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1901 cb(&(edid->detailed_timings[i]), closure);
1903 for (i = 1; i <= raw_edid[0x7e]; i++) {
1904 u8 *ext = raw_edid + (i * EDID_LENGTH);
1907 cea_for_each_detailed_block(ext, cb, closure);
1910 vtb_for_each_detailed_block(ext, cb, closure);
1919 is_rb(struct detailed_timing *t, void *data)
1922 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1924 *(bool *)data = true;
1927 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1929 drm_monitor_supports_rb(struct edid *edid)
1931 if (edid->revision >= 4) {
1933 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1937 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1941 find_gtf2(struct detailed_timing *t, void *data)
1944 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1948 /* Secondary GTF curve kicks in above some break frequency */
1950 drm_gtf2_hbreak(struct edid *edid)
1953 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1954 return r ? (r[12] * 2) : 0;
1958 drm_gtf2_2c(struct edid *edid)
1961 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1962 return r ? r[13] : 0;
1966 drm_gtf2_m(struct edid *edid)
1969 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1970 return r ? (r[15] << 8) + r[14] : 0;
1974 drm_gtf2_k(struct edid *edid)
1977 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1978 return r ? r[16] : 0;
1982 drm_gtf2_2j(struct edid *edid)
1985 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1986 return r ? r[17] : 0;
1990 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1991 * @edid: EDID block to scan
1993 static int standard_timing_level(struct edid *edid)
1995 if (edid->revision >= 2) {
1996 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1998 if (drm_gtf2_hbreak(edid))
2006 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2007 * monitors fill with ascii space (0x20) instead.
2010 bad_std_timing(u8 a, u8 b)
2012 return (a == 0x00 && b == 0x00) ||
2013 (a == 0x01 && b == 0x01) ||
2014 (a == 0x20 && b == 0x20);
2018 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2019 * @connector: connector of for the EDID block
2020 * @edid: EDID block to scan
2021 * @t: standard timing params
2023 * Take the standard timing params (in this case width, aspect, and refresh)
2024 * and convert them into a real mode using CVT/GTF/DMT.
2026 static struct drm_display_mode *
2027 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2028 struct std_timing *t)
2030 struct drm_device *dev = connector->dev;
2031 struct drm_display_mode *m, *mode = NULL;
2034 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2035 >> EDID_TIMING_ASPECT_SHIFT;
2036 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2037 >> EDID_TIMING_VFREQ_SHIFT;
2038 int timing_level = standard_timing_level(edid);
2040 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2043 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2044 hsize = t->hsize * 8 + 248;
2045 /* vrefresh_rate = vfreq + 60 */
2046 vrefresh_rate = vfreq + 60;
2047 /* the vdisplay is calculated based on the aspect ratio */
2048 if (aspect_ratio == 0) {
2049 if (edid->revision < 3)
2052 vsize = (hsize * 10) / 16;
2053 } else if (aspect_ratio == 1)
2054 vsize = (hsize * 3) / 4;
2055 else if (aspect_ratio == 2)
2056 vsize = (hsize * 4) / 5;
2058 vsize = (hsize * 9) / 16;
2060 /* HDTV hack, part 1 */
2061 if (vrefresh_rate == 60 &&
2062 ((hsize == 1360 && vsize == 765) ||
2063 (hsize == 1368 && vsize == 769))) {
2069 * If this connector already has a mode for this size and refresh
2070 * rate (because it came from detailed or CVT info), use that
2071 * instead. This way we don't have to guess at interlace or
2074 list_for_each_entry(m, &connector->probed_modes, head)
2075 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2076 drm_mode_vrefresh(m) == vrefresh_rate)
2079 /* HDTV hack, part 2 */
2080 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2081 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2083 mode->hdisplay = 1366;
2084 mode->hsync_start = mode->hsync_start - 1;
2085 mode->hsync_end = mode->hsync_end - 1;
2089 /* check whether it can be found in default mode table */
2090 if (drm_monitor_supports_rb(edid)) {
2091 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2096 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2100 /* okay, generate it */
2101 switch (timing_level) {
2105 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2109 * This is potentially wrong if there's ever a monitor with
2110 * more than one ranges section, each claiming a different
2111 * secondary GTF curve. Please don't do that.
2113 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2116 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2117 drm_mode_destroy(dev, mode);
2118 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2119 vrefresh_rate, 0, 0,
2127 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2135 * EDID is delightfully ambiguous about how interlaced modes are to be
2136 * encoded. Our internal representation is of frame height, but some
2137 * HDTV detailed timings are encoded as field height.
2139 * The format list here is from CEA, in frame size. Technically we
2140 * should be checking refresh rate too. Whatever.
2143 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2144 struct detailed_pixel_timing *pt)
2147 static const struct {
2149 } cea_interlaced[] = {
2159 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2162 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2163 if ((mode->hdisplay == cea_interlaced[i].w) &&
2164 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2165 mode->vdisplay *= 2;
2166 mode->vsync_start *= 2;
2167 mode->vsync_end *= 2;
2173 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2177 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2178 * @dev: DRM device (needed to create new mode)
2180 * @timing: EDID detailed timing info
2181 * @quirks: quirks to apply
2183 * An EDID detailed timing block contains enough info for us to create and
2184 * return a new struct drm_display_mode.
2186 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2188 struct detailed_timing *timing,
2191 struct drm_display_mode *mode;
2192 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2193 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2194 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2195 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2196 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2197 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2198 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2199 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2200 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2202 /* ignore tiny modes */
2203 if (hactive < 64 || vactive < 64)
2206 if (pt->misc & DRM_EDID_PT_STEREO) {
2207 DRM_DEBUG_KMS("stereo mode not supported\n");
2210 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2211 DRM_DEBUG_KMS("composite sync not supported\n");
2214 /* it is incorrect if hsync/vsync width is zero */
2215 if (!hsync_pulse_width || !vsync_pulse_width) {
2216 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2217 "Wrong Hsync/Vsync pulse width\n");
2221 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2222 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2229 mode = drm_mode_create(dev);
2233 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2234 timing->pixel_clock = cpu_to_le16(1088);
2236 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2238 mode->hdisplay = hactive;
2239 mode->hsync_start = mode->hdisplay + hsync_offset;
2240 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2241 mode->htotal = mode->hdisplay + hblank;
2243 mode->vdisplay = vactive;
2244 mode->vsync_start = mode->vdisplay + vsync_offset;
2245 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2246 mode->vtotal = mode->vdisplay + vblank;
2248 /* Some EDIDs have bogus h/vtotal values */
2249 if (mode->hsync_end > mode->htotal)
2250 mode->htotal = mode->hsync_end + 1;
2251 if (mode->vsync_end > mode->vtotal)
2252 mode->vtotal = mode->vsync_end + 1;
2254 drm_mode_do_interlace_quirk(mode, pt);
2256 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2257 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2260 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2261 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2262 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2263 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2266 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2267 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2269 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2270 mode->width_mm *= 10;
2271 mode->height_mm *= 10;
2274 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2275 mode->width_mm = edid->width_cm * 10;
2276 mode->height_mm = edid->height_cm * 10;
2279 mode->type = DRM_MODE_TYPE_DRIVER;
2280 mode->vrefresh = drm_mode_vrefresh(mode);
2281 drm_mode_set_name(mode);
2287 mode_in_hsync_range(const struct drm_display_mode *mode,
2288 struct edid *edid, u8 *t)
2290 int hsync, hmin, hmax;
2293 if (edid->revision >= 4)
2294 hmin += ((t[4] & 0x04) ? 255 : 0);
2296 if (edid->revision >= 4)
2297 hmax += ((t[4] & 0x08) ? 255 : 0);
2298 hsync = drm_mode_hsync(mode);
2300 return (hsync <= hmax && hsync >= hmin);
2304 mode_in_vsync_range(const struct drm_display_mode *mode,
2305 struct edid *edid, u8 *t)
2307 int vsync, vmin, vmax;
2310 if (edid->revision >= 4)
2311 vmin += ((t[4] & 0x01) ? 255 : 0);
2313 if (edid->revision >= 4)
2314 vmax += ((t[4] & 0x02) ? 255 : 0);
2315 vsync = drm_mode_vrefresh(mode);
2317 return (vsync <= vmax && vsync >= vmin);
2321 range_pixel_clock(struct edid *edid, u8 *t)
2324 if (t[9] == 0 || t[9] == 255)
2327 /* 1.4 with CVT support gives us real precision, yay */
2328 if (edid->revision >= 4 && t[10] == 0x04)
2329 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2331 /* 1.3 is pathetic, so fuzz up a bit */
2332 return t[9] * 10000 + 5001;
2336 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2337 struct detailed_timing *timing)
2340 u8 *t = (u8 *)timing;
2342 if (!mode_in_hsync_range(mode, edid, t))
2345 if (!mode_in_vsync_range(mode, edid, t))
2348 if ((max_clock = range_pixel_clock(edid, t)))
2349 if (mode->clock > max_clock)
2352 /* 1.4 max horizontal check */
2353 if (edid->revision >= 4 && t[10] == 0x04)
2354 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2357 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2363 static bool valid_inferred_mode(const struct drm_connector *connector,
2364 const struct drm_display_mode *mode)
2366 const struct drm_display_mode *m;
2369 list_for_each_entry(m, &connector->probed_modes, head) {
2370 if (mode->hdisplay == m->hdisplay &&
2371 mode->vdisplay == m->vdisplay &&
2372 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2373 return false; /* duplicated */
2374 if (mode->hdisplay <= m->hdisplay &&
2375 mode->vdisplay <= m->vdisplay)
2382 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2383 struct detailed_timing *timing)
2386 struct drm_display_mode *newmode;
2387 struct drm_device *dev = connector->dev;
2389 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2390 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2391 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2392 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2394 drm_mode_probed_add(connector, newmode);
2403 /* fix up 1366x768 mode from 1368x768;
2404 * GFT/CVT can't express 1366 width which isn't dividable by 8
2406 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2408 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2409 mode->hdisplay = 1366;
2410 mode->hsync_start--;
2412 drm_mode_set_name(mode);
2417 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2418 struct detailed_timing *timing)
2421 struct drm_display_mode *newmode;
2422 struct drm_device *dev = connector->dev;
2424 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2425 const struct minimode *m = &extra_modes[i];
2426 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2430 drm_mode_fixup_1366x768(newmode);
2431 if (!mode_in_range(newmode, edid, timing) ||
2432 !valid_inferred_mode(connector, newmode)) {
2433 drm_mode_destroy(dev, newmode);
2437 drm_mode_probed_add(connector, newmode);
2445 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2446 struct detailed_timing *timing)
2449 struct drm_display_mode *newmode;
2450 struct drm_device *dev = connector->dev;
2451 bool rb = drm_monitor_supports_rb(edid);
2453 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2454 const struct minimode *m = &extra_modes[i];
2455 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2459 drm_mode_fixup_1366x768(newmode);
2460 if (!mode_in_range(newmode, edid, timing) ||
2461 !valid_inferred_mode(connector, newmode)) {
2462 drm_mode_destroy(dev, newmode);
2466 drm_mode_probed_add(connector, newmode);
2474 do_inferred_modes(struct detailed_timing *timing, void *c)
2476 struct detailed_mode_closure *closure = c;
2477 struct detailed_non_pixel *data = &timing->data.other_data;
2478 struct detailed_data_monitor_range *range = &data->data.range;
2480 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2483 closure->modes += drm_dmt_modes_for_range(closure->connector,
2487 if (!version_greater(closure->edid, 1, 1))
2488 return; /* GTF not defined yet */
2490 switch (range->flags) {
2491 case 0x02: /* secondary gtf, XXX could do more */
2492 case 0x00: /* default gtf */
2493 closure->modes += drm_gtf_modes_for_range(closure->connector,
2497 case 0x04: /* cvt, only in 1.4+ */
2498 if (!version_greater(closure->edid, 1, 3))
2501 closure->modes += drm_cvt_modes_for_range(closure->connector,
2505 case 0x01: /* just the ranges, no formula */
2512 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2514 struct detailed_mode_closure closure = {
2515 .connector = connector,
2519 if (version_greater(edid, 1, 0))
2520 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2523 return closure.modes;
2527 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2529 int i, j, m, modes = 0;
2530 struct drm_display_mode *mode;
2531 u8 *est = ((u8 *)timing) + 6;
2533 for (i = 0; i < 6; i++) {
2534 for (j = 7; j >= 0; j--) {
2535 m = (i * 8) + (7 - j);
2536 if (m >= ARRAY_SIZE(est3_modes))
2538 if (est[i] & (1 << j)) {
2539 mode = drm_mode_find_dmt(connector->dev,
2545 drm_mode_probed_add(connector, mode);
2556 do_established_modes(struct detailed_timing *timing, void *c)
2558 struct detailed_mode_closure *closure = c;
2559 struct detailed_non_pixel *data = &timing->data.other_data;
2561 if (data->type == EDID_DETAIL_EST_TIMINGS)
2562 closure->modes += drm_est3_modes(closure->connector, timing);
2566 * add_established_modes - get est. modes from EDID and add them
2567 * @connector: connector to add mode(s) to
2568 * @edid: EDID block to scan
2570 * Each EDID block contains a bitmap of the supported "established modes" list
2571 * (defined above). Tease them out and add them to the global modes list.
2574 add_established_modes(struct drm_connector *connector, struct edid *edid)
2576 struct drm_device *dev = connector->dev;
2577 unsigned long est_bits = edid->established_timings.t1 |
2578 (edid->established_timings.t2 << 8) |
2579 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2581 struct detailed_mode_closure closure = {
2582 .connector = connector,
2586 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2587 if (est_bits & (1<<i)) {
2588 struct drm_display_mode *newmode;
2589 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2591 drm_mode_probed_add(connector, newmode);
2597 if (version_greater(edid, 1, 0))
2598 drm_for_each_detailed_block((u8 *)edid,
2599 do_established_modes, &closure);
2601 return modes + closure.modes;
2605 do_standard_modes(struct detailed_timing *timing, void *c)
2607 struct detailed_mode_closure *closure = c;
2608 struct detailed_non_pixel *data = &timing->data.other_data;
2609 struct drm_connector *connector = closure->connector;
2610 struct edid *edid = closure->edid;
2612 if (data->type == EDID_DETAIL_STD_MODES) {
2614 for (i = 0; i < 6; i++) {
2615 struct std_timing *std;
2616 struct drm_display_mode *newmode;
2618 std = &data->data.timings[i];
2619 newmode = drm_mode_std(connector, edid, std);
2621 drm_mode_probed_add(connector, newmode);
2629 * add_standard_modes - get std. modes from EDID and add them
2630 * @connector: connector to add mode(s) to
2631 * @edid: EDID block to scan
2633 * Standard modes can be calculated using the appropriate standard (DMT,
2634 * GTF or CVT. Grab them from @edid and add them to the list.
2637 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2640 struct detailed_mode_closure closure = {
2641 .connector = connector,
2645 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2646 struct drm_display_mode *newmode;
2648 newmode = drm_mode_std(connector, edid,
2649 &edid->standard_timings[i]);
2651 drm_mode_probed_add(connector, newmode);
2656 if (version_greater(edid, 1, 0))
2657 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2660 /* XXX should also look for standard codes in VTB blocks */
2662 return modes + closure.modes;
2665 static int drm_cvt_modes(struct drm_connector *connector,
2666 struct detailed_timing *timing)
2668 int i, j, modes = 0;
2669 struct drm_display_mode *newmode;
2670 struct drm_device *dev = connector->dev;
2671 struct cvt_timing *cvt;
2672 const int rates[] = { 60, 85, 75, 60, 50 };
2673 const u8 empty[3] = { 0, 0, 0 };
2675 for (i = 0; i < 4; i++) {
2676 int uninitialized_var(width), height;
2677 cvt = &(timing->data.other_data.data.cvt[i]);
2679 if (!memcmp(cvt->code, empty, 3))
2682 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2683 switch (cvt->code[1] & 0x0c) {
2685 width = height * 4 / 3;
2688 width = height * 16 / 9;
2691 width = height * 16 / 10;
2694 width = height * 15 / 9;
2698 for (j = 1; j < 5; j++) {
2699 if (cvt->code[2] & (1 << j)) {
2700 newmode = drm_cvt_mode(dev, width, height,
2704 drm_mode_probed_add(connector, newmode);
2715 do_cvt_mode(struct detailed_timing *timing, void *c)
2717 struct detailed_mode_closure *closure = c;
2718 struct detailed_non_pixel *data = &timing->data.other_data;
2720 if (data->type == EDID_DETAIL_CVT_3BYTE)
2721 closure->modes += drm_cvt_modes(closure->connector, timing);
2725 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2727 struct detailed_mode_closure closure = {
2728 .connector = connector,
2732 if (version_greater(edid, 1, 2))
2733 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2735 /* XXX should also look for CVT codes in VTB blocks */
2737 return closure.modes;
2740 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2743 do_detailed_mode(struct detailed_timing *timing, void *c)
2745 struct detailed_mode_closure *closure = c;
2746 struct drm_display_mode *newmode;
2748 if (timing->pixel_clock) {
2749 newmode = drm_mode_detailed(closure->connector->dev,
2750 closure->edid, timing,
2755 if (closure->preferred)
2756 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2759 * Detailed modes are limited to 10kHz pixel clock resolution,
2760 * so fix up anything that looks like CEA/HDMI mode, but the clock
2761 * is just slightly off.
2763 fixup_detailed_cea_mode_clock(newmode);
2765 drm_mode_probed_add(closure->connector, newmode);
2767 closure->preferred = 0;
2772 * add_detailed_modes - Add modes from detailed timings
2773 * @connector: attached connector
2774 * @edid: EDID block to scan
2775 * @quirks: quirks to apply
2778 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2781 struct detailed_mode_closure closure = {
2782 .connector = connector,
2788 if (closure.preferred && !version_greater(edid, 1, 3))
2790 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2792 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2794 return closure.modes;
2797 #define AUDIO_BLOCK 0x01
2798 #define VIDEO_BLOCK 0x02
2799 #define VENDOR_BLOCK 0x03
2800 #define SPEAKER_BLOCK 0x04
2801 #define USE_EXTENDED_TAG 0x07
2802 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
2803 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
2804 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
2805 #define EDID_BASIC_AUDIO (1 << 6)
2806 #define EDID_CEA_YCRCB444 (1 << 5)
2807 #define EDID_CEA_YCRCB422 (1 << 4)
2808 #define EDID_CEA_VCDB_QS (1 << 6)
2811 * Search EDID for CEA extension block.
2813 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id)
2815 u8 *edid_ext = NULL;
2818 /* No EDID or EDID extensions */
2819 if (edid == NULL || edid->extensions == 0)
2822 /* Find CEA extension */
2823 for (i = 0; i < edid->extensions; i++) {
2824 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2825 if (edid_ext[0] == ext_id)
2829 if (i == edid->extensions)
2835 static u8 *drm_find_cea_extension(struct edid *edid)
2837 return drm_find_edid_extension(edid, CEA_EXT);
2840 static u8 *drm_find_displayid_extension(struct edid *edid)
2842 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2846 * Calculate the alternate clock for the CEA mode
2847 * (60Hz vs. 59.94Hz etc.)
2850 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2852 unsigned int clock = cea_mode->clock;
2854 if (cea_mode->vrefresh % 6 != 0)
2858 * edid_cea_modes contains the 59.94Hz
2859 * variant for 240 and 480 line modes,
2860 * and the 60Hz variant otherwise.
2862 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2863 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2865 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2871 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2874 * For certain VICs the spec allows the vertical
2875 * front porch to vary by one or two lines.
2877 * cea_modes[] stores the variant with the shortest
2878 * vertical front porch. We can adjust the mode to
2879 * get the other variants by simply increasing the
2880 * vertical front porch length.
2882 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2883 edid_cea_modes[9].vtotal != 262 ||
2884 edid_cea_modes[12].vtotal != 262 ||
2885 edid_cea_modes[13].vtotal != 262 ||
2886 edid_cea_modes[23].vtotal != 312 ||
2887 edid_cea_modes[24].vtotal != 312 ||
2888 edid_cea_modes[27].vtotal != 312 ||
2889 edid_cea_modes[28].vtotal != 312);
2891 if (((vic == 8 || vic == 9 ||
2892 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2893 ((vic == 23 || vic == 24 ||
2894 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2895 mode->vsync_start++;
2905 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2906 unsigned int clock_tolerance)
2910 if (!to_match->clock)
2913 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2914 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2915 unsigned int clock1, clock2;
2917 /* Check both 60Hz and 59.94Hz */
2918 clock1 = cea_mode.clock;
2919 clock2 = cea_mode_alternate_clock(&cea_mode);
2921 if (abs(to_match->clock - clock1) > clock_tolerance &&
2922 abs(to_match->clock - clock2) > clock_tolerance)
2926 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2928 } while (cea_mode_alternate_timings(vic, &cea_mode));
2935 * drm_match_cea_mode - look for a CEA mode matching given mode
2936 * @to_match: display mode
2938 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2941 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2945 if (!to_match->clock)
2948 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2949 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2950 unsigned int clock1, clock2;
2952 /* Check both 60Hz and 59.94Hz */
2953 clock1 = cea_mode.clock;
2954 clock2 = cea_mode_alternate_clock(&cea_mode);
2956 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
2957 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
2961 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2963 } while (cea_mode_alternate_timings(vic, &cea_mode));
2968 EXPORT_SYMBOL(drm_match_cea_mode);
2970 static bool drm_valid_cea_vic(u8 vic)
2972 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2976 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2977 * the input VIC from the CEA mode list
2978 * @video_code: ID given to each of the CEA modes
2980 * Returns picture aspect ratio
2982 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2984 return edid_cea_modes[video_code].picture_aspect_ratio;
2986 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2989 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2992 * It's almost like cea_mode_alternate_clock(), we just need to add an
2993 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2997 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2999 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
3000 return hdmi_mode->clock;
3002 return cea_mode_alternate_clock(hdmi_mode);
3005 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3006 unsigned int clock_tolerance)
3010 if (!to_match->clock)
3013 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3014 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3015 unsigned int clock1, clock2;
3017 /* Make sure to also match alternate clocks */
3018 clock1 = hdmi_mode->clock;
3019 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3021 if (abs(to_match->clock - clock1) > clock_tolerance &&
3022 abs(to_match->clock - clock2) > clock_tolerance)
3025 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
3033 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3034 * @to_match: display mode
3036 * An HDMI mode is one defined in the HDMI vendor specific block.
3038 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3040 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3044 if (!to_match->clock)
3047 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3048 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3049 unsigned int clock1, clock2;
3051 /* Make sure to also match alternate clocks */
3052 clock1 = hdmi_mode->clock;
3053 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3055 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3056 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3057 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
3063 static bool drm_valid_hdmi_vic(u8 vic)
3065 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3069 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3071 struct drm_device *dev = connector->dev;
3072 struct drm_display_mode *mode, *tmp;
3076 /* Don't add CEA modes if the CEA extension block is missing */
3077 if (!drm_find_cea_extension(edid))
3081 * Go through all probed modes and create a new mode
3082 * with the alternate clock for certain CEA modes.
3084 list_for_each_entry(mode, &connector->probed_modes, head) {
3085 const struct drm_display_mode *cea_mode = NULL;
3086 struct drm_display_mode *newmode;
3087 u8 vic = drm_match_cea_mode(mode);
3088 unsigned int clock1, clock2;
3090 if (drm_valid_cea_vic(vic)) {
3091 cea_mode = &edid_cea_modes[vic];
3092 clock2 = cea_mode_alternate_clock(cea_mode);
3094 vic = drm_match_hdmi_mode(mode);
3095 if (drm_valid_hdmi_vic(vic)) {
3096 cea_mode = &edid_4k_modes[vic];
3097 clock2 = hdmi_mode_alternate_clock(cea_mode);
3104 clock1 = cea_mode->clock;
3106 if (clock1 == clock2)
3109 if (mode->clock != clock1 && mode->clock != clock2)
3112 newmode = drm_mode_duplicate(dev, cea_mode);
3116 /* Carry over the stereo flags */
3117 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3120 * The current mode could be either variant. Make
3121 * sure to pick the "other" clock for the new mode.
3123 if (mode->clock != clock1)
3124 newmode->clock = clock1;
3126 newmode->clock = clock2;
3128 list_add_tail(&newmode->head, &list);
3131 list_for_each_entry_safe(mode, tmp, &list, head) {
3132 list_del(&mode->head);
3133 drm_mode_probed_add(connector, mode);
3140 static u8 svd_to_vic(u8 svd)
3142 /* 0-6 bit vic, 7th bit native mode indicator */
3143 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3149 static struct drm_display_mode *
3150 drm_display_mode_from_vic_index(struct drm_connector *connector,
3151 const u8 *video_db, u8 video_len,
3154 struct drm_device *dev = connector->dev;
3155 struct drm_display_mode *newmode;
3158 if (video_db == NULL || video_index >= video_len)
3161 /* CEA modes are numbered 1..127 */
3162 vic = svd_to_vic(video_db[video_index]);
3163 if (!drm_valid_cea_vic(vic))
3166 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3170 newmode->vrefresh = 0;
3176 * do_y420vdb_modes - Parse YCBCR 420 only modes
3177 * @connector: connector corresponding to the HDMI sink
3178 * @svds: start of the data block of CEA YCBCR 420 VDB
3179 * @len: length of the CEA YCBCR 420 VDB
3181 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3182 * which contains modes which can be supported in YCBCR 420
3183 * output format only.
3185 static int do_y420vdb_modes(struct drm_connector *connector,
3186 const u8 *svds, u8 svds_len)
3189 struct drm_device *dev = connector->dev;
3190 struct drm_display_info *info = &connector->display_info;
3191 struct drm_hdmi_info *hdmi = &info->hdmi;
3193 for (i = 0; i < svds_len; i++) {
3194 u8 vic = svd_to_vic(svds[i]);
3195 struct drm_display_mode *newmode;
3197 if (!drm_valid_cea_vic(vic))
3200 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3203 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3204 drm_mode_probed_add(connector, newmode);
3209 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3214 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3215 * @connector: connector corresponding to the HDMI sink
3216 * @vic: CEA vic for the video mode to be added in the map
3218 * Makes an entry for a videomode in the YCBCR 420 bitmap
3221 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3223 u8 vic = svd_to_vic(svd);
3224 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3226 if (!drm_valid_cea_vic(vic))
3229 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3233 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3236 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3238 for (i = 0; i < len; i++) {
3239 struct drm_display_mode *mode;
3240 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3243 * YCBCR420 capability block contains a bitmap which
3244 * gives the index of CEA modes from CEA VDB, which
3245 * can support YCBCR 420 sampling output also (apart
3246 * from RGB/YCBCR444 etc).
3247 * For example, if the bit 0 in bitmap is set,
3248 * first mode in VDB can support YCBCR420 output too.
3249 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3251 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3252 drm_add_cmdb_modes(connector, db[i]);
3254 drm_mode_probed_add(connector, mode);
3262 struct stereo_mandatory_mode {
3263 int width, height, vrefresh;
3267 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3268 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3269 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3271 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3273 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3274 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3275 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3276 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3277 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3281 stereo_match_mandatory(const struct drm_display_mode *mode,
3282 const struct stereo_mandatory_mode *stereo_mode)
3284 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3286 return mode->hdisplay == stereo_mode->width &&
3287 mode->vdisplay == stereo_mode->height &&
3288 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3289 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3292 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3294 struct drm_device *dev = connector->dev;
3295 const struct drm_display_mode *mode;
3296 struct list_head stereo_modes;
3299 INIT_LIST_HEAD(&stereo_modes);
3301 list_for_each_entry(mode, &connector->probed_modes, head) {
3302 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3303 const struct stereo_mandatory_mode *mandatory;
3304 struct drm_display_mode *new_mode;
3306 if (!stereo_match_mandatory(mode,
3307 &stereo_mandatory_modes[i]))
3310 mandatory = &stereo_mandatory_modes[i];
3311 new_mode = drm_mode_duplicate(dev, mode);
3315 new_mode->flags |= mandatory->flags;
3316 list_add_tail(&new_mode->head, &stereo_modes);
3321 list_splice_tail(&stereo_modes, &connector->probed_modes);
3326 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3328 struct drm_device *dev = connector->dev;
3329 struct drm_display_mode *newmode;
3331 if (!drm_valid_hdmi_vic(vic)) {
3332 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3336 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3340 drm_mode_probed_add(connector, newmode);
3345 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3346 const u8 *video_db, u8 video_len, u8 video_index)
3348 struct drm_display_mode *newmode;
3351 if (structure & (1 << 0)) {
3352 newmode = drm_display_mode_from_vic_index(connector, video_db,
3356 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3357 drm_mode_probed_add(connector, newmode);
3361 if (structure & (1 << 6)) {
3362 newmode = drm_display_mode_from_vic_index(connector, video_db,
3366 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3367 drm_mode_probed_add(connector, newmode);
3371 if (structure & (1 << 8)) {
3372 newmode = drm_display_mode_from_vic_index(connector, video_db,
3376 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3377 drm_mode_probed_add(connector, newmode);
3386 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3387 * @connector: connector corresponding to the HDMI sink
3388 * @db: start of the CEA vendor specific block
3389 * @len: length of the CEA block payload, ie. one can access up to db[len]
3391 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3392 * also adds the stereo 3d modes when applicable.
3395 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3396 const u8 *video_db, u8 video_len)
3398 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3399 u8 vic_len, hdmi_3d_len = 0;
3406 /* no HDMI_Video_Present */
3407 if (!(db[8] & (1 << 5)))
3410 /* Latency_Fields_Present */
3411 if (db[8] & (1 << 7))
3414 /* I_Latency_Fields_Present */
3415 if (db[8] & (1 << 6))
3418 /* the declared length is not long enough for the 2 first bytes
3419 * of additional video format capabilities */
3420 if (len < (8 + offset + 2))
3425 if (db[8 + offset] & (1 << 7)) {
3426 modes += add_hdmi_mandatory_stereo_modes(connector);
3428 /* 3D_Multi_present */
3429 multi_present = (db[8 + offset] & 0x60) >> 5;
3433 vic_len = db[8 + offset] >> 5;
3434 hdmi_3d_len = db[8 + offset] & 0x1f;
3436 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3439 vic = db[9 + offset + i];
3440 modes += add_hdmi_mode(connector, vic);
3442 offset += 1 + vic_len;
3444 if (multi_present == 1)
3446 else if (multi_present == 2)
3451 if (len < (8 + offset + hdmi_3d_len - 1))
3454 if (hdmi_3d_len < multi_len)
3457 if (multi_present == 1 || multi_present == 2) {
3458 /* 3D_Structure_ALL */
3459 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3461 /* check if 3D_MASK is present */
3462 if (multi_present == 2)
3463 mask = (db[10 + offset] << 8) | db[11 + offset];
3467 for (i = 0; i < 16; i++) {
3468 if (mask & (1 << i))
3469 modes += add_3d_struct_modes(connector,
3476 offset += multi_len;
3478 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3480 struct drm_display_mode *newmode = NULL;
3481 unsigned int newflag = 0;
3482 bool detail_present;
3484 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3486 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3489 /* 2D_VIC_order_X */
3490 vic_index = db[8 + offset + i] >> 4;
3492 /* 3D_Structure_X */
3493 switch (db[8 + offset + i] & 0x0f) {
3495 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3498 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3502 if ((db[9 + offset + i] >> 4) == 1)
3503 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3508 newmode = drm_display_mode_from_vic_index(connector,
3514 newmode->flags |= newflag;
3515 drm_mode_probed_add(connector, newmode);
3529 cea_db_payload_len(const u8 *db)
3531 return db[0] & 0x1f;
3535 cea_db_extended_tag(const u8 *db)
3541 cea_db_tag(const u8 *db)
3547 cea_revision(const u8 *cea)
3553 cea_db_offsets(const u8 *cea, int *start, int *end)
3555 /* Data block offset in CEA extension block */
3560 if (*end < 4 || *end > 127)
3565 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3569 if (cea_db_tag(db) != VENDOR_BLOCK)
3572 if (cea_db_payload_len(db) < 5)
3575 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3577 return hdmi_id == HDMI_IEEE_OUI;
3580 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3584 if (cea_db_tag(db) != VENDOR_BLOCK)
3587 if (cea_db_payload_len(db) < 7)
3590 oui = db[3] << 16 | db[2] << 8 | db[1];
3592 return oui == HDMI_FORUM_IEEE_OUI;
3595 static bool cea_db_is_y420cmdb(const u8 *db)
3597 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3600 if (!cea_db_payload_len(db))
3603 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3609 static bool cea_db_is_y420vdb(const u8 *db)
3611 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3614 if (!cea_db_payload_len(db))
3617 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3623 #define for_each_cea_db(cea, i, start, end) \
3624 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3626 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3629 struct drm_display_info *info = &connector->display_info;
3630 struct drm_hdmi_info *hdmi = &info->hdmi;
3631 u8 map_len = cea_db_payload_len(db) - 1;
3636 /* All CEA modes support ycbcr420 sampling also.*/
3637 hdmi->y420_cmdb_map = U64_MAX;
3638 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3643 * This map indicates which of the existing CEA block modes
3644 * from VDB can support YCBCR420 output too. So if bit=0 is
3645 * set, first mode from VDB can support YCBCR420 output too.
3646 * We will parse and keep this map, before parsing VDB itself
3647 * to avoid going through the same block again and again.
3649 * Spec is not clear about max possible size of this block.
3650 * Clamping max bitmap block size at 8 bytes. Every byte can
3651 * address 8 CEA modes, in this way this map can address
3652 * 8*8 = first 64 SVDs.
3654 if (WARN_ON_ONCE(map_len > 8))
3657 for (count = 0; count < map_len; count++)
3658 map |= (u64)db[2 + count] << (8 * count);
3661 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3663 hdmi->y420_cmdb_map = map;
3667 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3669 const u8 *cea = drm_find_cea_extension(edid);
3670 const u8 *db, *hdmi = NULL, *video = NULL;
3671 u8 dbl, hdmi_len, video_len = 0;
3674 if (cea && cea_revision(cea) >= 3) {
3677 if (cea_db_offsets(cea, &start, &end))
3680 for_each_cea_db(cea, i, start, end) {
3682 dbl = cea_db_payload_len(db);
3684 if (cea_db_tag(db) == VIDEO_BLOCK) {
3687 modes += do_cea_modes(connector, video, dbl);
3688 } else if (cea_db_is_hdmi_vsdb(db)) {
3691 } else if (cea_db_is_y420vdb(db)) {
3692 const u8 *vdb420 = &db[2];
3694 /* Add 4:2:0(only) modes present in EDID */
3695 modes += do_y420vdb_modes(connector,
3703 * We parse the HDMI VSDB after having added the cea modes as we will
3704 * be patching their flags when the sink supports stereo 3D.
3707 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3713 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3715 const struct drm_display_mode *cea_mode;
3716 int clock1, clock2, clock;
3721 * allow 5kHz clock difference either way to account for
3722 * the 10kHz clock resolution limit of detailed timings.
3724 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3725 if (drm_valid_cea_vic(vic)) {
3727 cea_mode = &edid_cea_modes[vic];
3728 clock1 = cea_mode->clock;
3729 clock2 = cea_mode_alternate_clock(cea_mode);
3731 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3732 if (drm_valid_hdmi_vic(vic)) {
3734 cea_mode = &edid_4k_modes[vic];
3735 clock1 = cea_mode->clock;
3736 clock2 = hdmi_mode_alternate_clock(cea_mode);
3742 /* pick whichever is closest */
3743 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3748 if (mode->clock == clock)
3751 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3752 type, vic, mode->clock, clock);
3753 mode->clock = clock;
3757 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3759 u8 len = cea_db_payload_len(db);
3762 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
3764 connector->latency_present[0] = db[8] >> 7;
3765 connector->latency_present[1] = (db[8] >> 6) & 1;
3768 connector->video_latency[0] = db[9];
3770 connector->audio_latency[0] = db[10];
3772 connector->video_latency[1] = db[11];
3774 connector->audio_latency[1] = db[12];
3776 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3777 "video latency %d %d, "
3778 "audio latency %d %d\n",
3779 connector->latency_present[0],
3780 connector->latency_present[1],
3781 connector->video_latency[0],
3782 connector->video_latency[1],
3783 connector->audio_latency[0],
3784 connector->audio_latency[1]);
3788 monitor_name(struct detailed_timing *t, void *data)
3790 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3791 *(u8 **)data = t->data.other_data.data.str.str;
3794 static int get_monitor_name(struct edid *edid, char name[13])
3796 char *edid_name = NULL;
3802 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3803 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3804 if (edid_name[mnl] == 0x0a)
3807 name[mnl] = edid_name[mnl];
3814 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3815 * @edid: monitor EDID information
3816 * @name: pointer to a character array to hold the name of the monitor
3817 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3820 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3828 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3829 memcpy(name, buf, name_length);
3830 name[name_length] = '\0';
3832 EXPORT_SYMBOL(drm_edid_get_monitor_name);
3835 * drm_edid_to_eld - build ELD from EDID
3836 * @connector: connector corresponding to the HDMI/DP sink
3837 * @edid: EDID to parse
3839 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3840 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3843 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3845 uint8_t *eld = connector->eld;
3848 int total_sad_count = 0;
3852 memset(eld, 0, sizeof(connector->eld));
3854 connector->latency_present[0] = false;
3855 connector->latency_present[1] = false;
3856 connector->video_latency[0] = 0;
3857 connector->audio_latency[0] = 0;
3858 connector->video_latency[1] = 0;
3859 connector->audio_latency[1] = 0;
3864 cea = drm_find_cea_extension(edid);
3866 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3870 mnl = get_monitor_name(edid, eld + 20);
3872 eld[4] = (cea[1] << 5) | mnl;
3873 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3875 eld[0] = 2 << 3; /* ELD version: 2 */
3877 eld[16] = edid->mfg_id[0];
3878 eld[17] = edid->mfg_id[1];
3879 eld[18] = edid->prod_code[0];
3880 eld[19] = edid->prod_code[1];
3882 if (cea_revision(cea) >= 3) {
3885 if (cea_db_offsets(cea, &start, &end)) {
3890 for_each_cea_db(cea, i, start, end) {
3892 dbl = cea_db_payload_len(db);
3894 switch (cea_db_tag(db)) {
3898 /* Audio Data Block, contains SADs */
3899 sad_count = min(dbl / 3, 15 - total_sad_count);
3901 memcpy(eld + 20 + mnl + total_sad_count * 3,
3902 &db[1], sad_count * 3);
3903 total_sad_count += sad_count;
3906 /* Speaker Allocation Data Block */
3911 /* HDMI Vendor-Specific Data Block */
3912 if (cea_db_is_hdmi_vsdb(db))
3913 drm_parse_hdmi_vsdb_audio(connector, db);
3920 eld[5] |= total_sad_count << 4;
3922 eld[DRM_ELD_BASELINE_ELD_LEN] =
3923 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3925 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3926 drm_eld_size(eld), total_sad_count);
3928 EXPORT_SYMBOL(drm_edid_to_eld);
3931 * drm_edid_to_sad - extracts SADs from EDID
3932 * @edid: EDID to parse
3933 * @sads: pointer that will be set to the extracted SADs
3935 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3937 * Note: The returned pointer needs to be freed using kfree().
3939 * Return: The number of found SADs or negative number on error.
3941 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3944 int i, start, end, dbl;
3947 cea = drm_find_cea_extension(edid);
3949 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3953 if (cea_revision(cea) < 3) {
3954 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3958 if (cea_db_offsets(cea, &start, &end)) {
3959 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3963 for_each_cea_db(cea, i, start, end) {
3966 if (cea_db_tag(db) == AUDIO_BLOCK) {
3968 dbl = cea_db_payload_len(db);
3970 count = dbl / 3; /* SAD is 3B */
3971 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3974 for (j = 0; j < count; j++) {
3975 u8 *sad = &db[1 + j * 3];
3977 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3978 (*sads)[j].channels = sad[0] & 0x7;
3979 (*sads)[j].freq = sad[1] & 0x7F;
3980 (*sads)[j].byte2 = sad[2];
3988 EXPORT_SYMBOL(drm_edid_to_sad);
3991 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3992 * @edid: EDID to parse
3993 * @sadb: pointer to the speaker block
3995 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
3997 * Note: The returned pointer needs to be freed using kfree().
3999 * Return: The number of found Speaker Allocation Blocks or negative number on
4002 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4005 int i, start, end, dbl;
4008 cea = drm_find_cea_extension(edid);
4010 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4014 if (cea_revision(cea) < 3) {
4015 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4019 if (cea_db_offsets(cea, &start, &end)) {
4020 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4024 for_each_cea_db(cea, i, start, end) {
4025 const u8 *db = &cea[i];
4027 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4028 dbl = cea_db_payload_len(db);
4030 /* Speaker Allocation Data Block */
4032 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4043 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4046 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4047 * @connector: connector associated with the HDMI/DP sink
4048 * @mode: the display mode
4050 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4051 * the sink doesn't support audio or video.
4053 int drm_av_sync_delay(struct drm_connector *connector,
4054 const struct drm_display_mode *mode)
4056 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4059 if (!connector->latency_present[0])
4061 if (!connector->latency_present[1])
4064 a = connector->audio_latency[i];
4065 v = connector->video_latency[i];
4068 * HDMI/DP sink doesn't support audio or video?
4070 if (a == 255 || v == 255)
4074 * Convert raw EDID values to millisecond.
4075 * Treat unknown latency as 0ms.
4078 a = min(2 * (a - 1), 500);
4080 v = min(2 * (v - 1), 500);
4082 return max(v - a, 0);
4084 EXPORT_SYMBOL(drm_av_sync_delay);
4087 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4088 * @edid: monitor EDID information
4090 * Parse the CEA extension according to CEA-861-B.
4092 * Return: True if the monitor is HDMI, false if not or unknown.
4094 bool drm_detect_hdmi_monitor(struct edid *edid)
4098 int start_offset, end_offset;
4100 edid_ext = drm_find_cea_extension(edid);
4104 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4108 * Because HDMI identifier is in Vendor Specific Block,
4109 * search it from all data blocks of CEA extension.
4111 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4112 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4118 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4121 * drm_detect_monitor_audio - check monitor audio capability
4122 * @edid: EDID block to scan
4124 * Monitor should have CEA extension block.
4125 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4126 * audio' only. If there is any audio extension block and supported
4127 * audio format, assume at least 'basic audio' support, even if 'basic
4128 * audio' is not defined in EDID.
4130 * Return: True if the monitor supports audio, false otherwise.
4132 bool drm_detect_monitor_audio(struct edid *edid)
4136 bool has_audio = false;
4137 int start_offset, end_offset;
4139 edid_ext = drm_find_cea_extension(edid);
4143 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4146 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4150 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4153 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4154 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4156 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4157 DRM_DEBUG_KMS("CEA audio format %d\n",
4158 (edid_ext[i + j] >> 3) & 0xf);
4165 EXPORT_SYMBOL(drm_detect_monitor_audio);
4168 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
4169 * @edid: EDID block to scan
4171 * Check whether the monitor reports the RGB quantization range selection
4172 * as supported. The AVI infoframe can then be used to inform the monitor
4173 * which quantization range (full or limited) is used.
4175 * Return: True if the RGB quantization range is selectable, false otherwise.
4177 bool drm_rgb_quant_range_selectable(struct edid *edid)
4182 edid_ext = drm_find_cea_extension(edid);
4186 if (cea_db_offsets(edid_ext, &start, &end))
4189 for_each_cea_db(edid_ext, i, start, end) {
4190 if (cea_db_tag(&edid_ext[i]) == USE_EXTENDED_TAG &&
4191 cea_db_payload_len(&edid_ext[i]) == 2 &&
4192 cea_db_extended_tag(&edid_ext[i]) ==
4193 EXT_VIDEO_CAPABILITY_BLOCK) {
4194 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
4195 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
4201 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
4204 * drm_default_rgb_quant_range - default RGB quantization range
4205 * @mode: display mode
4207 * Determine the default RGB quantization range for the mode,
4208 * as specified in CEA-861.
4210 * Return: The default RGB quantization range for the mode
4212 enum hdmi_quantization_range
4213 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4215 /* All CEA modes other than VIC 1 use limited quantization range. */
4216 return drm_match_cea_mode(mode) > 1 ?
4217 HDMI_QUANTIZATION_RANGE_LIMITED :
4218 HDMI_QUANTIZATION_RANGE_FULL;
4220 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4222 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4226 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4228 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4229 hdmi->y420_dc_modes |= dc_mask;
4232 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4235 struct drm_display_info *display = &connector->display_info;
4236 struct drm_hdmi_info *hdmi = &display->hdmi;
4238 if (hf_vsdb[6] & 0x80) {
4239 hdmi->scdc.supported = true;
4240 if (hf_vsdb[6] & 0x40)
4241 hdmi->scdc.read_request = true;
4245 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4246 * And as per the spec, three factors confirm this:
4247 * * Availability of a HF-VSDB block in EDID (check)
4248 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4249 * * SCDC support available (let's check)
4250 * Lets check it out.
4254 /* max clock is 5000 KHz times block value */
4255 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4256 struct drm_scdc *scdc = &hdmi->scdc;
4258 if (max_tmds_clock > 340000) {
4259 display->max_tmds_clock = max_tmds_clock;
4260 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4261 display->max_tmds_clock);
4264 if (scdc->supported) {
4265 scdc->scrambling.supported = true;
4267 /* Few sinks support scrambling for cloks < 340M */
4268 if ((hf_vsdb[6] & 0x8))
4269 scdc->scrambling.low_rates = true;
4273 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4276 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4279 struct drm_display_info *info = &connector->display_info;
4280 unsigned int dc_bpc = 0;
4282 /* HDMI supports at least 8 bpc */
4285 if (cea_db_payload_len(hdmi) < 6)
4288 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4290 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4291 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4295 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4297 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4298 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4302 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4304 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4305 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4310 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4315 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4316 connector->name, dc_bpc);
4320 * Deep color support mandates RGB444 support for all video
4321 * modes and forbids YCRCB422 support for all video modes per
4324 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4326 /* YCRCB444 is optional according to spec. */
4327 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4328 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4329 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4334 * Spec says that if any deep color mode is supported at all,
4335 * then deep color 36 bit must be supported.
4337 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4338 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4344 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4346 struct drm_display_info *info = &connector->display_info;
4347 u8 len = cea_db_payload_len(db);
4350 info->dvi_dual = db[6] & 1;
4352 info->max_tmds_clock = db[7] * 5000;
4354 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4355 "max TMDS clock %d kHz\n",
4357 info->max_tmds_clock);
4359 drm_parse_hdmi_deep_color_info(connector, db);
4362 static void drm_parse_cea_ext(struct drm_connector *connector,
4365 struct drm_display_info *info = &connector->display_info;
4369 edid_ext = drm_find_cea_extension(edid);
4373 info->cea_rev = edid_ext[1];
4375 /* The existence of a CEA block should imply RGB support */
4376 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4377 if (edid_ext[3] & EDID_CEA_YCRCB444)
4378 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4379 if (edid_ext[3] & EDID_CEA_YCRCB422)
4380 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4382 if (cea_db_offsets(edid_ext, &start, &end))
4385 for_each_cea_db(edid_ext, i, start, end) {
4386 const u8 *db = &edid_ext[i];
4388 if (cea_db_is_hdmi_vsdb(db))
4389 drm_parse_hdmi_vsdb_video(connector, db);
4390 if (cea_db_is_hdmi_forum_vsdb(db))
4391 drm_parse_hdmi_forum_vsdb(connector, db);
4392 if (cea_db_is_y420cmdb(db))
4393 drm_parse_y420cmdb_bitmap(connector, db);
4397 static void drm_add_display_info(struct drm_connector *connector,
4398 struct edid *edid, u32 quirks)
4400 struct drm_display_info *info = &connector->display_info;
4402 info->width_mm = edid->width_cm * 10;
4403 info->height_mm = edid->height_cm * 10;
4405 /* driver figures it out in this case */
4407 info->color_formats = 0;
4409 info->max_tmds_clock = 0;
4410 info->dvi_dual = false;
4412 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4414 if (edid->revision < 3)
4417 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4420 drm_parse_cea_ext(connector, edid);
4423 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4425 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4426 * tells us to assume 8 bpc color depth if the EDID doesn't have
4427 * extensions which tell otherwise.
4429 if ((info->bpc == 0) && (edid->revision < 4) &&
4430 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
4432 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4433 connector->name, info->bpc);
4436 /* Only defined for 1.4 with digital displays */
4437 if (edid->revision < 4)
4440 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4441 case DRM_EDID_DIGITAL_DEPTH_6:
4444 case DRM_EDID_DIGITAL_DEPTH_8:
4447 case DRM_EDID_DIGITAL_DEPTH_10:
4450 case DRM_EDID_DIGITAL_DEPTH_12:
4453 case DRM_EDID_DIGITAL_DEPTH_14:
4456 case DRM_EDID_DIGITAL_DEPTH_16:
4459 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4465 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4466 connector->name, info->bpc);
4468 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4469 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4470 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4471 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4472 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4475 static int validate_displayid(u8 *displayid, int length, int idx)
4479 struct displayid_hdr *base;
4481 base = (struct displayid_hdr *)&displayid[idx];
4483 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4484 base->rev, base->bytes, base->prod_id, base->ext_count);
4486 if (base->bytes + 5 > length - idx)
4488 for (i = idx; i <= base->bytes + 5; i++) {
4489 csum += displayid[i];
4492 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4498 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4499 struct displayid_detailed_timings_1 *timings)
4501 struct drm_display_mode *mode;
4502 unsigned pixel_clock = (timings->pixel_clock[0] |
4503 (timings->pixel_clock[1] << 8) |
4504 (timings->pixel_clock[2] << 16));
4505 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4506 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4507 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4508 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4509 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4510 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4511 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4512 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4513 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4514 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4515 mode = drm_mode_create(dev);
4519 mode->clock = pixel_clock * 10;
4520 mode->hdisplay = hactive;
4521 mode->hsync_start = mode->hdisplay + hsync;
4522 mode->hsync_end = mode->hsync_start + hsync_width;
4523 mode->htotal = mode->hdisplay + hblank;
4525 mode->vdisplay = vactive;
4526 mode->vsync_start = mode->vdisplay + vsync;
4527 mode->vsync_end = mode->vsync_start + vsync_width;
4528 mode->vtotal = mode->vdisplay + vblank;
4531 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4532 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4533 mode->type = DRM_MODE_TYPE_DRIVER;
4535 if (timings->flags & 0x80)
4536 mode->type |= DRM_MODE_TYPE_PREFERRED;
4537 mode->vrefresh = drm_mode_vrefresh(mode);
4538 drm_mode_set_name(mode);
4543 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4544 struct displayid_block *block)
4546 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4549 struct drm_display_mode *newmode;
4551 /* blocks must be multiple of 20 bytes length */
4552 if (block->num_bytes % 20)
4555 num_timings = block->num_bytes / 20;
4556 for (i = 0; i < num_timings; i++) {
4557 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4559 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4563 drm_mode_probed_add(connector, newmode);
4569 static int add_displayid_detailed_modes(struct drm_connector *connector,
4575 int length = EDID_LENGTH;
4576 struct displayid_block *block;
4579 displayid = drm_find_displayid_extension(edid);
4583 ret = validate_displayid(displayid, length, idx);
4587 idx += sizeof(struct displayid_hdr);
4588 while (block = (struct displayid_block *)&displayid[idx],
4589 idx + sizeof(struct displayid_block) <= length &&
4590 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4591 block->num_bytes > 0) {
4592 idx += block->num_bytes + sizeof(struct displayid_block);
4593 switch (block->tag) {
4594 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4595 num_modes += add_displayid_detailed_1_modes(connector, block);
4603 * drm_add_edid_modes - add modes from EDID data, if available
4604 * @connector: connector we're probing
4607 * Add the specified modes to the connector's mode list. Also fills out the
4608 * &drm_display_info structure in @connector with any information which can be
4609 * derived from the edid.
4611 * Return: The number of modes added or 0 if we couldn't find any.
4613 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4621 if (!drm_edid_is_valid(edid)) {
4622 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4627 quirks = edid_get_quirks(edid);
4630 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4631 * To avoid multiple parsing of same block, lets parse that map
4632 * from sink info, before parsing CEA modes.
4634 drm_add_display_info(connector, edid, quirks);
4637 * EDID spec says modes should be preferred in this order:
4638 * - preferred detailed mode
4639 * - other detailed modes from base block
4640 * - detailed modes from extension blocks
4641 * - CVT 3-byte code modes
4642 * - standard timing codes
4643 * - established timing codes
4644 * - modes inferred from GTF or CVT range information
4646 * We get this pretty much right.
4648 * XXX order for additional mode types in extension blocks?
4650 num_modes += add_detailed_modes(connector, edid, quirks);
4651 num_modes += add_cvt_modes(connector, edid);
4652 num_modes += add_standard_modes(connector, edid);
4653 num_modes += add_established_modes(connector, edid);
4654 num_modes += add_cea_modes(connector, edid);
4655 num_modes += add_alternate_cea_modes(connector, edid);
4656 num_modes += add_displayid_detailed_modes(connector, edid);
4657 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4658 num_modes += add_inferred_modes(connector, edid);
4660 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4661 edid_fixup_preferred(connector, quirks);
4663 if (quirks & EDID_QUIRK_FORCE_6BPC)
4664 connector->display_info.bpc = 6;
4666 if (quirks & EDID_QUIRK_FORCE_8BPC)
4667 connector->display_info.bpc = 8;
4669 if (quirks & EDID_QUIRK_FORCE_10BPC)
4670 connector->display_info.bpc = 10;
4672 if (quirks & EDID_QUIRK_FORCE_12BPC)
4673 connector->display_info.bpc = 12;
4677 EXPORT_SYMBOL(drm_add_edid_modes);
4680 * drm_add_modes_noedid - add modes for the connectors without EDID
4681 * @connector: connector we're probing
4682 * @hdisplay: the horizontal display limit
4683 * @vdisplay: the vertical display limit
4685 * Add the specified modes to the connector's mode list. Only when the
4686 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4688 * Return: The number of modes added or 0 if we couldn't find any.
4690 int drm_add_modes_noedid(struct drm_connector *connector,
4691 int hdisplay, int vdisplay)
4693 int i, count, num_modes = 0;
4694 struct drm_display_mode *mode;
4695 struct drm_device *dev = connector->dev;
4697 count = ARRAY_SIZE(drm_dmt_modes);
4703 for (i = 0; i < count; i++) {
4704 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4705 if (hdisplay && vdisplay) {
4707 * Only when two are valid, they will be used to check
4708 * whether the mode should be added to the mode list of
4711 if (ptr->hdisplay > hdisplay ||
4712 ptr->vdisplay > vdisplay)
4715 if (drm_mode_vrefresh(ptr) > 61)
4717 mode = drm_mode_duplicate(dev, ptr);
4719 drm_mode_probed_add(connector, mode);
4725 EXPORT_SYMBOL(drm_add_modes_noedid);
4728 * drm_set_preferred_mode - Sets the preferred mode of a connector
4729 * @connector: connector whose mode list should be processed
4730 * @hpref: horizontal resolution of preferred mode
4731 * @vpref: vertical resolution of preferred mode
4733 * Marks a mode as preferred if it matches the resolution specified by @hpref
4736 void drm_set_preferred_mode(struct drm_connector *connector,
4737 int hpref, int vpref)
4739 struct drm_display_mode *mode;
4741 list_for_each_entry(mode, &connector->probed_modes, head) {
4742 if (mode->hdisplay == hpref &&
4743 mode->vdisplay == vpref)
4744 mode->type |= DRM_MODE_TYPE_PREFERRED;
4747 EXPORT_SYMBOL(drm_set_preferred_mode);
4750 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4751 * data from a DRM display mode
4752 * @frame: HDMI AVI infoframe
4753 * @mode: DRM display mode
4754 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant
4756 * Return: 0 on success or a negative error code on failure.
4759 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4760 const struct drm_display_mode *mode,
4765 if (!frame || !mode)
4768 err = hdmi_avi_infoframe_init(frame);
4772 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4773 frame->pixel_repeat = 1;
4775 frame->video_code = drm_match_cea_mode(mode);
4778 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4779 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4780 * have to make sure we dont break HDMI 1.4 sinks.
4782 if (!is_hdmi2_sink && frame->video_code > 64)
4783 frame->video_code = 0;
4786 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
4787 * we should send its VIC in vendor infoframes, else send the
4788 * VIC in AVI infoframes. Lets check if this mode is present in
4789 * HDMI 1.4b 4K modes
4791 if (frame->video_code) {
4792 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
4793 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
4795 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
4796 frame->video_code = 0;
4799 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4802 * Populate picture aspect ratio from either
4803 * user input (if specified) or from the CEA mode list.
4805 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4806 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4807 frame->picture_aspect = mode->picture_aspect_ratio;
4808 else if (frame->video_code > 0)
4809 frame->picture_aspect = drm_get_cea_aspect_ratio(
4812 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4813 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4817 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4820 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
4821 * quantization range information
4822 * @frame: HDMI AVI infoframe
4823 * @mode: DRM display mode
4824 * @rgb_quant_range: RGB quantization range (Q)
4825 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
4828 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
4829 const struct drm_display_mode *mode,
4830 enum hdmi_quantization_range rgb_quant_range,
4831 bool rgb_quant_range_selectable)
4835 * "A Source shall not send a non-zero Q value that does not correspond
4836 * to the default RGB Quantization Range for the transmitted Picture
4837 * unless the Sink indicates support for the Q bit in a Video
4838 * Capabilities Data Block."
4840 * HDMI 2.0 recommends sending non-zero Q when it does match the
4841 * default RGB quantization range for the mode, even when QS=0.
4843 if (rgb_quant_range_selectable ||
4844 rgb_quant_range == drm_default_rgb_quant_range(mode))
4845 frame->quantization_range = rgb_quant_range;
4847 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
4851 * "When transmitting any RGB colorimetry, the Source should set the
4852 * YQ-field to match the RGB Quantization Range being transmitted
4853 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
4854 * set YQ=1) and the Sink shall ignore the YQ-field."
4856 if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
4857 frame->ycc_quantization_range =
4858 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
4860 frame->ycc_quantization_range =
4861 HDMI_YCC_QUANTIZATION_RANGE_FULL;
4863 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
4865 static enum hdmi_3d_structure
4866 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4868 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4871 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4872 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4873 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4874 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4875 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4876 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4877 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4878 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4879 case DRM_MODE_FLAG_3D_L_DEPTH:
4880 return HDMI_3D_STRUCTURE_L_DEPTH;
4881 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4882 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4883 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4884 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4885 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4886 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4888 return HDMI_3D_STRUCTURE_INVALID;
4893 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4894 * data from a DRM display mode
4895 * @frame: HDMI vendor infoframe
4896 * @mode: DRM display mode
4898 * Note that there's is a need to send HDMI vendor infoframes only when using a
4899 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4900 * function will return -EINVAL, error that can be safely ignored.
4902 * Return: 0 on success or a negative error code on failure.
4905 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4906 const struct drm_display_mode *mode)
4912 if (!frame || !mode)
4915 vic = drm_match_hdmi_mode(mode);
4916 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4918 if (!vic && !s3d_flags)
4921 if (vic && s3d_flags)
4924 err = hdmi_vendor_infoframe_init(frame);
4931 frame->s3d_struct = s3d_structure_from_display_mode(mode);
4935 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
4937 static int drm_parse_tiled_block(struct drm_connector *connector,
4938 struct displayid_block *block)
4940 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
4942 u8 tile_v_loc, tile_h_loc;
4943 u8 num_v_tile, num_h_tile;
4944 struct drm_tile_group *tg;
4946 w = tile->tile_size[0] | tile->tile_size[1] << 8;
4947 h = tile->tile_size[2] | tile->tile_size[3] << 8;
4949 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
4950 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
4951 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
4952 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
4954 connector->has_tile = true;
4955 if (tile->tile_cap & 0x80)
4956 connector->tile_is_single_monitor = true;
4958 connector->num_h_tile = num_h_tile + 1;
4959 connector->num_v_tile = num_v_tile + 1;
4960 connector->tile_h_loc = tile_h_loc;
4961 connector->tile_v_loc = tile_v_loc;
4962 connector->tile_h_size = w + 1;
4963 connector->tile_v_size = h + 1;
4965 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
4966 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
4967 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
4968 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
4969 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
4971 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
4973 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
4978 if (connector->tile_group != tg) {
4979 /* if we haven't got a pointer,
4980 take the reference, drop ref to old tile group */
4981 if (connector->tile_group) {
4982 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4984 connector->tile_group = tg;
4986 /* if same tile group, then release the ref we just took. */
4987 drm_mode_put_tile_group(connector->dev, tg);
4991 static int drm_parse_display_id(struct drm_connector *connector,
4992 u8 *displayid, int length,
4993 bool is_edid_extension)
4995 /* if this is an EDID extension the first byte will be 0x70 */
4997 struct displayid_block *block;
5000 if (is_edid_extension)
5003 ret = validate_displayid(displayid, length, idx);
5007 idx += sizeof(struct displayid_hdr);
5008 while (block = (struct displayid_block *)&displayid[idx],
5009 idx + sizeof(struct displayid_block) <= length &&
5010 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
5011 block->num_bytes > 0) {
5012 idx += block->num_bytes + sizeof(struct displayid_block);
5013 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5014 block->tag, block->rev, block->num_bytes);
5016 switch (block->tag) {
5017 case DATA_BLOCK_TILED_DISPLAY:
5018 ret = drm_parse_tiled_block(connector, block);
5022 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5023 /* handled in mode gathering code. */
5026 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5033 static void drm_get_displayid(struct drm_connector *connector,
5036 void *displayid = NULL;
5038 connector->has_tile = false;
5039 displayid = drm_find_displayid_extension(edid);
5041 /* drop reference to any tile group we had */
5045 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5048 if (!connector->has_tile)
5052 if (connector->tile_group) {
5053 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5054 connector->tile_group = NULL;
projects / linux-2.6-microblaze.git / blob