drivers/gpu/drm/drm_dp_helper.c

   1 /*
   2  * Copyright © 2009 Keith Packard
   3  *
   4  * Permission to use, copy, modify, distribute, and sell this software and its
   5  * documentation for any purpose is hereby granted without fee, provided that
   6  * the above copyright notice appear in all copies and that both that copyright
   7  * notice and this permission notice appear in supporting documentation, and
   8  * that the name of the copyright holders not be used in advertising or
   9  * publicity pertaining to distribution of the software without specific,
  10  * written prior permission.  The copyright holders make no representations
  11  * about the suitability of this software for any purpose.  It is provided "as
  12  * is" without express or implied warranty.
  13  *
  14  * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
  15  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
  16  * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
  17  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
  18  * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  19  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
  20  * OF THIS SOFTWARE.
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/errno.h>
  25 #include <linux/i2c.h>
  26 #include <linux/init.h>
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/sched.h>
  30 #include <linux/seq_file.h>
  31
  32 #include <drm/drm_dp_helper.h>
  33 #include <drm/drm_print.h>
  34 #include <drm/drm_vblank.h>
  35 #include <drm/drm_dp_mst_helper.h>
  36
  37 #include "drm_crtc_helper_internal.h"
  38
  39 /**
  40  * DOC: dp helpers
  41  *
  42  * These functions contain some common logic and helpers at various abstraction
  43  * levels to deal with Display Port sink devices and related things like DP aux
  44  * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
  45  * blocks, ...
  46  */
  47
  48 /* Helpers for DP link training */
  49 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
  50 {
  51         return link_status[r - DP_LANE0_1_STATUS];
  52 }
  53
  54 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
  55                              int lane)
  56 {
  57         int i = DP_LANE0_1_STATUS + (lane >> 1);
  58         int s = (lane & 1) * 4;
  59         u8 l = dp_link_status(link_status, i);
  60
  61         return (l >> s) & 0xf;
  62 }
  63
  64 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
  65                           int lane_count)
  66 {
  67         u8 lane_align;
  68         u8 lane_status;
  69         int lane;
  70
  71         lane_align = dp_link_status(link_status,
  72                                     DP_LANE_ALIGN_STATUS_UPDATED);
  73         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
  74                 return false;
  75         for (lane = 0; lane < lane_count; lane++) {
  76                 lane_status = dp_get_lane_status(link_status, lane);
  77                 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
  78                         return false;
  79         }
  80         return true;
  81 }
  82 EXPORT_SYMBOL(drm_dp_channel_eq_ok);
  83
  84 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
  85                               int lane_count)
  86 {
  87         int lane;
  88         u8 lane_status;
  89
  90         for (lane = 0; lane < lane_count; lane++) {
  91                 lane_status = dp_get_lane_status(link_status, lane);
  92                 if ((lane_status & DP_LANE_CR_DONE) == 0)
  93                         return false;
  94         }
  95         return true;
  96 }
  97 EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
  98
  99 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
 100                                      int lane)
 101 {
 102         int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 103         int s = ((lane & 1) ?
 104                  DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
 105                  DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
 106         u8 l = dp_link_status(link_status, i);
 107
 108         return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
 109 }
 110 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
 111
 112 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
 113                                           int lane)
 114 {
 115         int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 116         int s = ((lane & 1) ?
 117                  DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
 118                  DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
 119         u8 l = dp_link_status(link_status, i);
 120
 121         return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
 122 }
 123 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
 124
 125 u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
 126                                          unsigned int lane)
 127 {
 128         unsigned int offset = DP_ADJUST_REQUEST_POST_CURSOR2;
 129         u8 value = dp_link_status(link_status, offset);
 130
 131         return (value >> (lane << 1)) & 0x3;
 132 }
 133 EXPORT_SYMBOL(drm_dp_get_adjust_request_post_cursor);
 134
 135 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 136 {
 137         unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
 138                                          DP_TRAINING_AUX_RD_MASK;
 139
 140         if (rd_interval > 4)
 141                 DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",
 142                               rd_interval);
 143
 144         if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
 145                 rd_interval = 100;
 146         else
 147                 rd_interval *= 4 * USEC_PER_MSEC;
 148
 149         usleep_range(rd_interval, rd_interval * 2);
 150 }
 151 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
 152
 153 static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval)
 154 {
 155         if (rd_interval > 4)
 156                 DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",
 157                               rd_interval);
 158
 159         if (rd_interval == 0)
 160                 rd_interval = 400;
 161         else
 162                 rd_interval *= 4 * USEC_PER_MSEC;
 163
 164         usleep_range(rd_interval, rd_interval * 2);
 165 }
 166
 167 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 168 {
 169         __drm_dp_link_train_channel_eq_delay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
 170                                              DP_TRAINING_AUX_RD_MASK);
 171 }
 172 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
 173
 174 void drm_dp_lttpr_link_train_clock_recovery_delay(void)
 175 {
 176         usleep_range(100, 200);
 177 }
 178 EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay);
 179
 180 static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r)
 181 {
 182         return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1];
 183 }
 184
 185 void drm_dp_lttpr_link_train_channel_eq_delay(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE])
 186 {
 187         u8 interval = dp_lttpr_phy_cap(phy_cap,
 188                                        DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) &
 189                       DP_TRAINING_AUX_RD_MASK;
 190
 191         __drm_dp_link_train_channel_eq_delay(interval);
 192 }
 193 EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);
 194
 195 u8 drm_dp_link_rate_to_bw_code(int link_rate)
 196 {
 197         /* Spec says link_bw = link_rate / 0.27Gbps */
 198         return link_rate / 27000;
 199 }
 200 EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
 201
 202 int drm_dp_bw_code_to_link_rate(u8 link_bw)
 203 {
 204         /* Spec says link_rate = link_bw * 0.27Gbps */
 205         return link_bw * 27000;
 206 }
 207 EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
 208
 209 #define AUX_RETRY_INTERVAL 500 /* us */
 210
 211 static inline void
 212 drm_dp_dump_access(const struct drm_dp_aux *aux,
 213                    u8 request, uint offset, void *buffer, int ret)
 214 {
 215         const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-";
 216
 217         if (ret > 0)
 218                 DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
 219                              aux->name, offset, arrow, ret, min(ret, 20), buffer);
 220         else
 221                 DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d)\n",
 222                              aux->name, offset, arrow, ret);
 223 }
 224
 225 /**
 226  * DOC: dp helpers
 227  *
 228  * The DisplayPort AUX channel is an abstraction to allow generic, driver-
 229  * independent access to AUX functionality. Drivers can take advantage of
 230  * this by filling in the fields of the drm_dp_aux structure.
 231  *
 232  * Transactions are described using a hardware-independent drm_dp_aux_msg
 233  * structure, which is passed into a driver's .transfer() implementation.
 234  * Both native and I2C-over-AUX transactions are supported.
 235  */
 236
 237 static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
 238                               unsigned int offset, void *buffer, size_t size)
 239 {
 240         struct drm_dp_aux_msg msg;
 241         unsigned int retry, native_reply;
 242         int err = 0, ret = 0;
 243
 244         memset(&msg, 0, sizeof(msg));
 245         msg.address = offset;
 246         msg.request = request;
 247         msg.buffer = buffer;
 248         msg.size = size;
 249
 250         mutex_lock(&aux->hw_mutex);
 251
 252         /*
 253          * The specification doesn't give any recommendation on how often to
 254          * retry native transactions. We used to retry 7 times like for
 255          * aux i2c transactions but real world devices this wasn't
 256          * sufficient, bump to 32 which makes Dell 4k monitors happier.
 257          */
 258         for (retry = 0; retry < 32; retry++) {
 259                 if (ret != 0 && ret != -ETIMEDOUT) {
 260                         usleep_range(AUX_RETRY_INTERVAL,
 261                                      AUX_RETRY_INTERVAL + 100);
 262                 }
 263
 264                 ret = aux->transfer(aux, &msg);
 265                 if (ret >= 0) {
 266                         native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK;
 267                         if (native_reply == DP_AUX_NATIVE_REPLY_ACK) {
 268                                 if (ret == size)
 269                                         goto unlock;
 270
 271                                 ret = -EPROTO;
 272                         } else
 273                                 ret = -EIO;
 274                 }
 275
 276                 /*
 277                  * We want the error we return to be the error we received on
 278                  * the first transaction, since we may get a different error the
 279                  * next time we retry
 280                  */
 281                 if (!err)
 282                         err = ret;
 283         }
 284
 285         DRM_DEBUG_KMS("%s: Too many retries, giving up. First error: %d\n",
 286                       aux->name, err);
 287         ret = err;
 288
 289 unlock:
 290         mutex_unlock(&aux->hw_mutex);
 291         return ret;
 292 }
 293
 294 /**
 295  * drm_dp_dpcd_read() - read a series of bytes from the DPCD
 296  * @aux: DisplayPort AUX channel (SST or MST)
 297  * @offset: address of the (first) register to read
 298  * @buffer: buffer to store the register values
 299  * @size: number of bytes in @buffer
 300  *
 301  * Returns the number of bytes transferred on success, or a negative error
 302  * code on failure. -EIO is returned if the request was NAKed by the sink or
 303  * if the retry count was exceeded. If not all bytes were transferred, this
 304  * function returns -EPROTO. Errors from the underlying AUX channel transfer
 305  * function, with the exception of -EBUSY (which causes the transaction to
 306  * be retried), are propagated to the caller.
 307  */
 308 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
 309                          void *buffer, size_t size)
 310 {
 311         int ret;
 312
 313         /*
 314          * HP ZR24w corrupts the first DPCD access after entering power save
 315          * mode. Eg. on a read, the entire buffer will be filled with the same
 316          * byte. Do a throw away read to avoid corrupting anything we care
 317          * about. Afterwards things will work correctly until the monitor
 318          * gets woken up and subsequently re-enters power save mode.
 319          *
 320          * The user pressing any button on the monitor is enough to wake it
 321          * up, so there is no particularly good place to do the workaround.
 322          * We just have to do it before any DPCD access and hope that the
 323          * monitor doesn't power down exactly after the throw away read.
 324          */
 325         if (!aux->is_remote) {
 326                 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV,
 327                                          buffer, 1);
 328                 if (ret != 1)
 329                         goto out;
 330         }
 331
 332         if (aux->is_remote)
 333                 ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size);
 334         else
 335                 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset,
 336                                          buffer, size);
 337
 338 out:
 339         drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret);
 340         return ret;
 341 }
 342 EXPORT_SYMBOL(drm_dp_dpcd_read);
 343
 344 /**
 345  * drm_dp_dpcd_write() - write a series of bytes to the DPCD
 346  * @aux: DisplayPort AUX channel (SST or MST)
 347  * @offset: address of the (first) register to write
 348  * @buffer: buffer containing the values to write
 349  * @size: number of bytes in @buffer
 350  *
 351  * Returns the number of bytes transferred on success, or a negative error
 352  * code on failure. -EIO is returned if the request was NAKed by the sink or
 353  * if the retry count was exceeded. If not all bytes were transferred, this
 354  * function returns -EPROTO. Errors from the underlying AUX channel transfer
 355  * function, with the exception of -EBUSY (which causes the transaction to
 356  * be retried), are propagated to the caller.
 357  */
 358 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
 359                           void *buffer, size_t size)
 360 {
 361         int ret;
 362
 363         if (aux->is_remote)
 364                 ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size);
 365         else
 366                 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset,
 367                                          buffer, size);
 368
 369         drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
 370         return ret;
 371 }
 372 EXPORT_SYMBOL(drm_dp_dpcd_write);
 373
 374 /**
 375  * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
 376  * @aux: DisplayPort AUX channel
 377  * @status: buffer to store the link status in (must be at least 6 bytes)
 378  *
 379  * Returns the number of bytes transferred on success or a negative error
 380  * code on failure.
 381  */
 382 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
 383                                  u8 status[DP_LINK_STATUS_SIZE])
 384 {
 385         return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
 386                                 DP_LINK_STATUS_SIZE);
 387 }
 388 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
 389
 390 /**
 391  * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY
 392  * @aux: DisplayPort AUX channel
 393  * @dp_phy: the DP PHY to get the link status for
 394  * @link_status: buffer to return the status in
 395  *
 396  * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The
 397  * layout of the returned @link_status matches the DPCD register layout of the
 398  * DPRX PHY link status.
 399  *
 400  * Returns 0 if the information was read successfully or a negative error code
 401  * on failure.
 402  */
 403 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
 404                                      enum drm_dp_phy dp_phy,
 405                                      u8 link_status[DP_LINK_STATUS_SIZE])
 406 {
 407         int ret;
 408
 409         if (dp_phy == DP_PHY_DPRX) {
 410                 ret = drm_dp_dpcd_read(aux,
 411                                        DP_LANE0_1_STATUS,
 412                                        link_status,
 413                                        DP_LINK_STATUS_SIZE);
 414
 415                 if (ret < 0)
 416                         return ret;
 417
 418                 WARN_ON(ret != DP_LINK_STATUS_SIZE);
 419
 420                 return 0;
 421         }
 422
 423         ret = drm_dp_dpcd_read(aux,
 424                                DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy),
 425                                link_status,
 426                                DP_LINK_STATUS_SIZE - 1);
 427
 428         if (ret < 0)
 429                 return ret;
 430
 431         WARN_ON(ret != DP_LINK_STATUS_SIZE - 1);
 432
 433         /* Convert the LTTPR to the sink PHY link status layout */
 434         memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1],
 435                 &link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS],
 436                 DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1);
 437         link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0;
 438
 439         return 0;
 440 }
 441 EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status);
 442
 443 static bool is_edid_digital_input_dp(const struct edid *edid)
 444 {
 445         return edid && edid->revision >= 4 &&
 446                 edid->input & DRM_EDID_INPUT_DIGITAL &&
 447                 (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP;
 448 }
 449
 450 /**
 451  * drm_dp_downstream_is_type() - is the downstream facing port of certain type?
 452  * @dpcd: DisplayPort configuration data
 453  * @port_cap: port capabilities
 454  * @type: port type to be checked. Can be:
 455  *        %DP_DS_PORT_TYPE_DP, %DP_DS_PORT_TYPE_VGA, %DP_DS_PORT_TYPE_DVI,
 456  *        %DP_DS_PORT_TYPE_HDMI, %DP_DS_PORT_TYPE_NON_EDID,
 457  *        %DP_DS_PORT_TYPE_DP_DUALMODE or %DP_DS_PORT_TYPE_WIRELESS.
 458  *
 459  * Caveat: Only works with DPCD 1.1+ port caps.
 460  *
 461  * Returns: whether the downstream facing port matches the type.
 462  */
 463 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 464                                const u8 port_cap[4], u8 type)
 465 {
 466         return drm_dp_is_branch(dpcd) &&
 467                 dpcd[DP_DPCD_REV] >= 0x11 &&
 468                 (port_cap[0] & DP_DS_PORT_TYPE_MASK) == type;
 469 }
 470 EXPORT_SYMBOL(drm_dp_downstream_is_type);
 471
 472 /**
 473  * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS?
 474  * @dpcd: DisplayPort configuration data
 475  * @port_cap: port capabilities
 476  * @edid: EDID
 477  *
 478  * Returns: whether the downstream facing port is TMDS (HDMI/DVI).
 479  */
 480 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 481                                const u8 port_cap[4],
 482                                const struct edid *edid)
 483 {
 484         if (dpcd[DP_DPCD_REV] < 0x11) {
 485                 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
 486                 case DP_DWN_STRM_PORT_TYPE_TMDS:
 487                         return true;
 488                 default:
 489                         return false;
 490                 }
 491         }
 492
 493         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
 494         case DP_DS_PORT_TYPE_DP_DUALMODE:
 495                 if (is_edid_digital_input_dp(edid))
 496                         return false;
 497                 fallthrough;
 498         case DP_DS_PORT_TYPE_DVI:
 499         case DP_DS_PORT_TYPE_HDMI:
 500                 return true;
 501         default:
 502                 return false;
 503         }
 504 }
 505 EXPORT_SYMBOL(drm_dp_downstream_is_tmds);
 506
 507 /**
 508  * drm_dp_send_real_edid_checksum() - send back real edid checksum value
 509  * @aux: DisplayPort AUX channel
 510  * @real_edid_checksum: real edid checksum for the last block
 511  *
 512  * Returns:
 513  * True on success
 514  */
 515 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
 516                                     u8 real_edid_checksum)
 517 {
 518         u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;
 519
 520         if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
 521                              &auto_test_req, 1) < 1) {
 522                 DRM_ERROR("%s: DPCD failed read at register 0x%x\n",
 523                           aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
 524                 return false;
 525         }
 526         auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
 527
 528         if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1) < 1) {
 529                 DRM_ERROR("%s: DPCD failed read at register 0x%x\n",
 530                           aux->name, DP_TEST_REQUEST);
 531                 return false;
 532         }
 533         link_edid_read &= DP_TEST_LINK_EDID_READ;
 534
 535         if (!auto_test_req || !link_edid_read) {
 536                 DRM_DEBUG_KMS("%s: Source DUT does not support TEST_EDID_READ\n",
 537                               aux->name);
 538                 return false;
 539         }
 540
 541         if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
 542                               &auto_test_req, 1) < 1) {
 543                 DRM_ERROR("%s: DPCD failed write at register 0x%x\n",
 544                           aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
 545                 return false;
 546         }
 547
 548         /* send back checksum for the last edid extension block data */
 549         if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM,
 550                               &real_edid_checksum, 1) < 1) {
 551                 DRM_ERROR("%s: DPCD failed write at register 0x%x\n",
 552                           aux->name, DP_TEST_EDID_CHECKSUM);
 553                 return false;
 554         }
 555
 556         test_resp |= DP_TEST_EDID_CHECKSUM_WRITE;
 557         if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) {
 558                 DRM_ERROR("%s: DPCD failed write at register 0x%x\n",
 559                           aux->name, DP_TEST_RESPONSE);
 560                 return false;
 561         }
 562
 563         return true;
 564 }
 565 EXPORT_SYMBOL(drm_dp_send_real_edid_checksum);
 566
 567 static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 568 {
 569         u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK;
 570
 571         if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4)
 572                 port_count = 4;
 573
 574         return port_count;
 575 }
 576
 577 static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux,
 578                                           u8 dpcd[DP_RECEIVER_CAP_SIZE])
 579 {
 580         u8 dpcd_ext[6];
 581         int ret;
 582
 583         /*
 584          * Prior to DP1.3 the bit represented by
 585          * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
 586          * If it is set DP_DPCD_REV at 0000h could be at a value less than
 587          * the true capability of the panel. The only way to check is to
 588          * then compare 0000h and 2200h.
 589          */
 590         if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
 591               DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
 592                 return 0;
 593
 594         ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext,
 595                                sizeof(dpcd_ext));
 596         if (ret < 0)
 597                 return ret;
 598         if (ret != sizeof(dpcd_ext))
 599                 return -EIO;
 600
 601         if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
 602                 DRM_DEBUG_KMS("%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n",
 603                               aux->name, dpcd[DP_DPCD_REV],
 604                               dpcd_ext[DP_DPCD_REV]);
 605                 return 0;
 606         }
 607
 608         if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext)))
 609                 return 0;
 610
 611         DRM_DEBUG_KMS("%s: Base DPCD: %*ph\n",
 612                       aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
 613
 614         memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext));
 615
 616         return 0;
 617 }
 618
 619 /**
 620  * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if
 621  * available
 622  * @aux: DisplayPort AUX channel
 623  * @dpcd: Buffer to store the resulting DPCD in
 624  *
 625  * Attempts to read the base DPCD caps for @aux. Additionally, this function
 626  * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if
 627  * present.
 628  *
 629  * Returns: %0 if the DPCD was read successfully, negative error code
 630  * otherwise.
 631  */
 632 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
 633                           u8 dpcd[DP_RECEIVER_CAP_SIZE])
 634 {
 635         int ret;
 636
 637         ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE);
 638         if (ret < 0)
 639                 return ret;
 640         if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0)
 641                 return -EIO;
 642
 643         ret = drm_dp_read_extended_dpcd_caps(aux, dpcd);
 644         if (ret < 0)
 645                 return ret;
 646
 647         DRM_DEBUG_KMS("%s: DPCD: %*ph\n",
 648                       aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
 649
 650         return ret;
 651 }
 652 EXPORT_SYMBOL(drm_dp_read_dpcd_caps);
 653
 654 /**
 655  * drm_dp_read_downstream_info() - read DPCD downstream port info if available
 656  * @aux: DisplayPort AUX channel
 657  * @dpcd: A cached copy of the port's DPCD
 658  * @downstream_ports: buffer to store the downstream port info in
 659  *
 660  * See also:
 661  * drm_dp_downstream_max_clock()
 662  * drm_dp_downstream_max_bpc()
 663  *
 664  * Returns: 0 if either the downstream port info was read successfully or
 665  * there was no downstream info to read, or a negative error code otherwise.
 666  */
 667 int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
 668                                 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 669                                 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS])
 670 {
 671         int ret;
 672         u8 len;
 673
 674         memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS);
 675
 676         /* No downstream info to read */
 677         if (!drm_dp_is_branch(dpcd) ||
 678             dpcd[DP_DPCD_REV] < DP_DPCD_REV_10 ||
 679             !(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
 680                 return 0;
 681
 682         len = drm_dp_downstream_port_count(dpcd);
 683         if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE)
 684                 len *= 4;
 685
 686         ret = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, downstream_ports, len);
 687         if (ret < 0)
 688                 return ret;
 689         if (ret != len)
 690                 return -EIO;
 691
 692         DRM_DEBUG_KMS("%s: DPCD DFP: %*ph\n",
 693                       aux->name, len, downstream_ports);
 694
 695         return 0;
 696 }
 697 EXPORT_SYMBOL(drm_dp_read_downstream_info);
 698
 699 /**
 700  * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock
 701  * @dpcd: DisplayPort configuration data
 702  * @port_cap: port capabilities
 703  *
 704  * Returns: Downstream facing port max dot clock in kHz on success,
 705  * or 0 if max clock not defined
 706  */
 707 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 708                                    const u8 port_cap[4])
 709 {
 710         if (!drm_dp_is_branch(dpcd))
 711                 return 0;
 712
 713         if (dpcd[DP_DPCD_REV] < 0x11)
 714                 return 0;
 715
 716         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
 717         case DP_DS_PORT_TYPE_VGA:
 718                 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
 719                         return 0;
 720                 return port_cap[1] * 8000;
 721         default:
 722                 return 0;
 723         }
 724 }
 725 EXPORT_SYMBOL(drm_dp_downstream_max_dotclock);
 726
 727 /**
 728  * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock
 729  * @dpcd: DisplayPort configuration data
 730  * @port_cap: port capabilities
 731  * @edid: EDID
 732  *
 733  * Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success,
 734  * or 0 if max TMDS clock not defined
 735  */
 736 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 737                                      const u8 port_cap[4],
 738                                      const struct edid *edid)
 739 {
 740         if (!drm_dp_is_branch(dpcd))
 741                 return 0;
 742
 743         if (dpcd[DP_DPCD_REV] < 0x11) {
 744                 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
 745                 case DP_DWN_STRM_PORT_TYPE_TMDS:
 746                         return 165000;
 747                 default:
 748                         return 0;
 749                 }
 750         }
 751
 752         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
 753         case DP_DS_PORT_TYPE_DP_DUALMODE:
 754                 if (is_edid_digital_input_dp(edid))
 755                         return 0;
 756                 /*
 757                  * It's left up to the driver to check the
 758                  * DP dual mode adapter's max TMDS clock.
 759                  *
 760                  * Unfortunatley it looks like branch devices
 761                  * may not fordward that the DP dual mode i2c
 762                  * access so we just usually get i2c nak :(
 763                  */
 764                 fallthrough;
 765         case DP_DS_PORT_TYPE_HDMI:
 766                  /*
 767                   * We should perhaps assume 165 MHz when detailed cap
 768                   * info is not available. But looks like many typical
 769                   * branch devices fall into that category and so we'd
 770                   * probably end up with users complaining that they can't
 771                   * get high resolution modes with their favorite dongle.
 772                   *
 773                   * So let's limit to 300 MHz instead since DPCD 1.4
 774                   * HDMI 2.0 DFPs are required to have the detailed cap
 775                   * info. So it's more likely we're dealing with a HDMI 1.4
 776                   * compatible* device here.
 777                   */
 778                 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
 779                         return 300000;
 780                 return port_cap[1] * 2500;
 781         case DP_DS_PORT_TYPE_DVI:
 782                 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
 783                         return 165000;
 784                 /* FIXME what to do about DVI dual link? */
 785                 return port_cap[1] * 2500;
 786         default:
 787                 return 0;
 788         }
 789 }
 790 EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock);
 791
 792 /**
 793  * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock
 794  * @dpcd: DisplayPort configuration data
 795  * @port_cap: port capabilities
 796  * @edid: EDID
 797  *
 798  * Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success,
 799  * or 0 if max TMDS clock not defined
 800  */
 801 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 802                                      const u8 port_cap[4],
 803                                      const struct edid *edid)
 804 {
 805         if (!drm_dp_is_branch(dpcd))
 806                 return 0;
 807
 808         if (dpcd[DP_DPCD_REV] < 0x11) {
 809                 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
 810                 case DP_DWN_STRM_PORT_TYPE_TMDS:
 811                         return 25000;
 812                 default:
 813                         return 0;
 814                 }
 815         }
 816
 817         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
 818         case DP_DS_PORT_TYPE_DP_DUALMODE:
 819                 if (is_edid_digital_input_dp(edid))
 820                         return 0;
 821                 fallthrough;
 822         case DP_DS_PORT_TYPE_DVI:
 823         case DP_DS_PORT_TYPE_HDMI:
 824                 /*
 825                  * Unclear whether the protocol converter could
 826                  * utilize pixel replication. Assume it won't.
 827                  */
 828                 return 25000;
 829         default:
 830                 return 0;
 831         }
 832 }
 833 EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock);
 834
 835 /**
 836  * drm_dp_downstream_max_bpc() - extract downstream facing port max
 837  *                               bits per component
 838  * @dpcd: DisplayPort configuration data
 839  * @port_cap: downstream facing port capabilities
 840  * @edid: EDID
 841  *
 842  * Returns: Max bpc on success or 0 if max bpc not defined
 843  */
 844 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 845                               const u8 port_cap[4],
 846                               const struct edid *edid)
 847 {
 848         if (!drm_dp_is_branch(dpcd))
 849                 return 0;
 850
 851         if (dpcd[DP_DPCD_REV] < 0x11) {
 852                 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
 853                 case DP_DWN_STRM_PORT_TYPE_DP:
 854                         return 0;
 855                 default:
 856                         return 8;
 857                 }
 858         }
 859
 860         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
 861         case DP_DS_PORT_TYPE_DP:
 862                 return 0;
 863         case DP_DS_PORT_TYPE_DP_DUALMODE:
 864                 if (is_edid_digital_input_dp(edid))
 865                         return 0;
 866                 fallthrough;
 867         case DP_DS_PORT_TYPE_HDMI:
 868         case DP_DS_PORT_TYPE_DVI:
 869         case DP_DS_PORT_TYPE_VGA:
 870                 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
 871                         return 8;
 872
 873                 switch (port_cap[2] & DP_DS_MAX_BPC_MASK) {
 874                 case DP_DS_8BPC:
 875                         return 8;
 876                 case DP_DS_10BPC:
 877                         return 10;
 878                 case DP_DS_12BPC:
 879                         return 12;
 880                 case DP_DS_16BPC:
 881                         return 16;
 882                 default:
 883                         return 8;
 884                 }
 885                 break;
 886         default:
 887                 return 8;
 888         }
 889 }
 890 EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
 891
 892 /**
 893  * drm_dp_downstream_420_passthrough() - determine downstream facing port
 894  *                                       YCbCr 4:2:0 pass-through capability
 895  * @dpcd: DisplayPort configuration data
 896  * @port_cap: downstream facing port capabilities
 897  *
 898  * Returns: whether the downstream facing port can pass through YCbCr 4:2:0
 899  */
 900 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 901                                        const u8 port_cap[4])
 902 {
 903         if (!drm_dp_is_branch(dpcd))
 904                 return false;
 905
 906         if (dpcd[DP_DPCD_REV] < 0x13)
 907                 return false;
 908
 909         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
 910         case DP_DS_PORT_TYPE_DP:
 911                 return true;
 912         case DP_DS_PORT_TYPE_HDMI:
 913                 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
 914                         return false;
 915
 916                 return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH;
 917         default:
 918                 return false;
 919         }
 920 }
 921 EXPORT_SYMBOL(drm_dp_downstream_420_passthrough);
 922
 923 /**
 924  * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port
 925  *                                             YCbCr 4:4:4->4:2:0 conversion capability
 926  * @dpcd: DisplayPort configuration data
 927  * @port_cap: downstream facing port capabilities
 928  *
 929  * Returns: whether the downstream facing port can convert YCbCr 4:4:4 to 4:2:0
 930  */
 931 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 932                                              const u8 port_cap[4])
 933 {
 934         if (!drm_dp_is_branch(dpcd))
 935                 return false;
 936
 937         if (dpcd[DP_DPCD_REV] < 0x13)
 938                 return false;
 939
 940         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
 941         case DP_DS_PORT_TYPE_HDMI:
 942                 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
 943                         return false;
 944
 945                 return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV;
 946         default:
 947                 return false;
 948         }
 949 }
 950 EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion);
 951
 952 /**
 953  * drm_dp_downstream_rgb_to_ycbcr_conversion() - determine downstream facing port
 954  *                                               RGB->YCbCr conversion capability
 955  * @dpcd: DisplayPort configuration data
 956  * @port_cap: downstream facing port capabilities
 957  * @color_spc: Colorspace for which conversion cap is sought
 958  *
 959  * Returns: whether the downstream facing port can convert RGB->YCbCr for a given
 960  * colorspace.
 961  */
 962 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 963                                                const u8 port_cap[4],
 964                                                u8 color_spc)
 965 {
 966         if (!drm_dp_is_branch(dpcd))
 967                 return false;
 968
 969         if (dpcd[DP_DPCD_REV] < 0x13)
 970                 return false;
 971
 972         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
 973         case DP_DS_PORT_TYPE_HDMI:
 974                 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
 975                         return false;
 976
 977                 return port_cap[3] & color_spc;
 978         default:
 979                 return false;
 980         }
 981 }
 982 EXPORT_SYMBOL(drm_dp_downstream_rgb_to_ycbcr_conversion);
 983
 984 /**
 985  * drm_dp_downstream_mode() - return a mode for downstream facing port
 986  * @dev: DRM device
 987  * @dpcd: DisplayPort configuration data
 988  * @port_cap: port capabilities
 989  *
 990  * Provides a suitable mode for downstream facing ports without EDID.
 991  *
 992  * Returns: A new drm_display_mode on success or NULL on failure
 993  */
 994 struct drm_display_mode *
 995 drm_dp_downstream_mode(struct drm_device *dev,
 996                        const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 997                        const u8 port_cap[4])
 998
 999 {
1000         u8 vic;
1001
1002         if (!drm_dp_is_branch(dpcd))
1003                 return NULL;
1004
1005         if (dpcd[DP_DPCD_REV] < 0x11)
1006                 return NULL;
1007
1008         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1009         case DP_DS_PORT_TYPE_NON_EDID:
1010                 switch (port_cap[0] & DP_DS_NON_EDID_MASK) {
1011                 case DP_DS_NON_EDID_720x480i_60:
1012                         vic = 6;
1013                         break;
1014                 case DP_DS_NON_EDID_720x480i_50:
1015                         vic = 21;
1016                         break;
1017                 case DP_DS_NON_EDID_1920x1080i_60:
1018                         vic = 5;
1019                         break;
1020                 case DP_DS_NON_EDID_1920x1080i_50:
1021                         vic = 20;
1022                         break;
1023                 case DP_DS_NON_EDID_1280x720_60:
1024                         vic = 4;
1025                         break;
1026                 case DP_DS_NON_EDID_1280x720_50:
1027                         vic = 19;
1028                         break;
1029                 default:
1030                         return NULL;
1031                 }
1032                 return drm_display_mode_from_cea_vic(dev, vic);
1033         default:
1034                 return NULL;
1035         }
1036 }
1037 EXPORT_SYMBOL(drm_dp_downstream_mode);
1038
1039 /**
1040  * drm_dp_downstream_id() - identify branch device
1041  * @aux: DisplayPort AUX channel
1042  * @id: DisplayPort branch device id
1043  *
1044  * Returns branch device id on success or NULL on failure
1045  */
1046 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
1047 {
1048         return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);
1049 }
1050 EXPORT_SYMBOL(drm_dp_downstream_id);
1051
1052 /**
1053  * drm_dp_downstream_debug() - debug DP branch devices
1054  * @m: pointer for debugfs file
1055  * @dpcd: DisplayPort configuration data
1056  * @port_cap: port capabilities
1057  * @edid: EDID
1058  * @aux: DisplayPort AUX channel
1059  *
1060  */
1061 void drm_dp_downstream_debug(struct seq_file *m,
1062                              const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1063                              const u8 port_cap[4],
1064                              const struct edid *edid,
1065                              struct drm_dp_aux *aux)
1066 {
1067         bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1068                                  DP_DETAILED_CAP_INFO_AVAILABLE;
1069         int clk;
1070         int bpc;
1071         char id[7];
1072         int len;
1073         uint8_t rev[2];
1074         int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1075         bool branch_device = drm_dp_is_branch(dpcd);
1076
1077         seq_printf(m, "\tDP branch device present: %s\n",
1078                    branch_device ? "yes" : "no");
1079
1080         if (!branch_device)
1081                 return;
1082
1083         switch (type) {
1084         case DP_DS_PORT_TYPE_DP:
1085                 seq_puts(m, "\t\tType: DisplayPort\n");
1086                 break;
1087         case DP_DS_PORT_TYPE_VGA:
1088                 seq_puts(m, "\t\tType: VGA\n");
1089                 break;
1090         case DP_DS_PORT_TYPE_DVI:
1091                 seq_puts(m, "\t\tType: DVI\n");
1092                 break;
1093         case DP_DS_PORT_TYPE_HDMI:
1094                 seq_puts(m, "\t\tType: HDMI\n");
1095                 break;
1096         case DP_DS_PORT_TYPE_NON_EDID:
1097                 seq_puts(m, "\t\tType: others without EDID support\n");
1098                 break;
1099         case DP_DS_PORT_TYPE_DP_DUALMODE:
1100                 seq_puts(m, "\t\tType: DP++\n");
1101                 break;
1102         case DP_DS_PORT_TYPE_WIRELESS:
1103                 seq_puts(m, "\t\tType: Wireless\n");
1104                 break;
1105         default:
1106                 seq_puts(m, "\t\tType: N/A\n");
1107         }
1108
1109         memset(id, 0, sizeof(id));
1110         drm_dp_downstream_id(aux, id);
1111         seq_printf(m, "\t\tID: %s\n", id);
1112
1113         len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1);
1114         if (len > 0)
1115                 seq_printf(m, "\t\tHW: %d.%d\n",
1116                            (rev[0] & 0xf0) >> 4, rev[0] & 0xf);
1117
1118         len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2);
1119         if (len > 0)
1120                 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
1121
1122         if (detailed_cap_info) {
1123                 clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);
1124                 if (clk > 0)
1125                         seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
1126
1127                 clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, edid);
1128                 if (clk > 0)
1129                         seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);
1130
1131                 clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, edid);
1132                 if (clk > 0)
1133                         seq_printf(m, "\t\tMin TMDS clock: %d kHz\n", clk);
1134
1135                 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid);
1136
1137                 if (bpc > 0)
1138                         seq_printf(m, "\t\tMax bpc: %d\n", bpc);
1139         }
1140 }
1141 EXPORT_SYMBOL(drm_dp_downstream_debug);
1142
1143 /**
1144  * drm_dp_subconnector_type() - get DP branch device type
1145  * @dpcd: DisplayPort configuration data
1146  * @port_cap: port capabilities
1147  */
1148 enum drm_mode_subconnector
1149 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1150                          const u8 port_cap[4])
1151 {
1152         int type;
1153         if (!drm_dp_is_branch(dpcd))
1154                 return DRM_MODE_SUBCONNECTOR_Native;
1155         /* DP 1.0 approach */
1156         if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) {
1157                 type = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1158                        DP_DWN_STRM_PORT_TYPE_MASK;
1159
1160                 switch (type) {
1161                 case DP_DWN_STRM_PORT_TYPE_TMDS:
1162                         /* Can be HDMI or DVI-D, DVI-D is a safer option */
1163                         return DRM_MODE_SUBCONNECTOR_DVID;
1164                 case DP_DWN_STRM_PORT_TYPE_ANALOG:
1165                         /* Can be VGA or DVI-A, VGA is more popular */
1166                         return DRM_MODE_SUBCONNECTOR_VGA;
1167                 case DP_DWN_STRM_PORT_TYPE_DP:
1168                         return DRM_MODE_SUBCONNECTOR_DisplayPort;
1169                 case DP_DWN_STRM_PORT_TYPE_OTHER:
1170                 default:
1171                         return DRM_MODE_SUBCONNECTOR_Unknown;
1172                 }
1173         }
1174         type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1175
1176         switch (type) {
1177         case DP_DS_PORT_TYPE_DP:
1178         case DP_DS_PORT_TYPE_DP_DUALMODE:
1179                 return DRM_MODE_SUBCONNECTOR_DisplayPort;
1180         case DP_DS_PORT_TYPE_VGA:
1181                 return DRM_MODE_SUBCONNECTOR_VGA;
1182         case DP_DS_PORT_TYPE_DVI:
1183                 return DRM_MODE_SUBCONNECTOR_DVID;
1184         case DP_DS_PORT_TYPE_HDMI:
1185                 return DRM_MODE_SUBCONNECTOR_HDMIA;
1186         case DP_DS_PORT_TYPE_WIRELESS:
1187                 return DRM_MODE_SUBCONNECTOR_Wireless;
1188         case DP_DS_PORT_TYPE_NON_EDID:
1189         default:
1190                 return DRM_MODE_SUBCONNECTOR_Unknown;
1191         }
1192 }
1193 EXPORT_SYMBOL(drm_dp_subconnector_type);
1194
1195 /**
1196  * drm_dp_set_subconnector_property - set subconnector for DP connector
1197  * @connector: connector to set property on
1198  * @status: connector status
1199  * @dpcd: DisplayPort configuration data
1200  * @port_cap: port capabilities
1201  *
1202  * Called by a driver on every detect event.
1203  */
1204 void drm_dp_set_subconnector_property(struct drm_connector *connector,
1205                                       enum drm_connector_status status,
1206                                       const u8 *dpcd,
1207                                       const u8 port_cap[4])
1208 {
1209         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
1210
1211         if (status == connector_status_connected)
1212                 subconnector = drm_dp_subconnector_type(dpcd, port_cap);
1213         drm_object_property_set_value(&connector->base,
1214                         connector->dev->mode_config.dp_subconnector_property,
1215                         subconnector);
1216 }
1217 EXPORT_SYMBOL(drm_dp_set_subconnector_property);
1218
1219 /**
1220  * drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink
1221  * count
1222  * @connector: The DRM connector to check
1223  * @dpcd: A cached copy of the connector's DPCD RX capabilities
1224  * @desc: A cached copy of the connector's DP descriptor
1225  *
1226  * See also: drm_dp_read_sink_count()
1227  *
1228  * Returns: %True if the (e)DP connector has a valid sink count that should
1229  * be probed, %false otherwise.
1230  */
1231 bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
1232                                 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1233                                 const struct drm_dp_desc *desc)
1234 {
1235         /* Some eDP panels don't set a valid value for the sink count */
1236         return connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
1237                 dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 &&
1238                 dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
1239                 !drm_dp_has_quirk(desc, DP_DPCD_QUIRK_NO_SINK_COUNT);
1240 }
1241 EXPORT_SYMBOL(drm_dp_read_sink_count_cap);
1242
1243 /**
1244  * drm_dp_read_sink_count() - Retrieve the sink count for a given sink
1245  * @aux: The DP AUX channel to use
1246  *
1247  * See also: drm_dp_read_sink_count_cap()
1248  *
1249  * Returns: The current sink count reported by @aux, or a negative error code
1250  * otherwise.
1251  */
1252 int drm_dp_read_sink_count(struct drm_dp_aux *aux)
1253 {
1254         u8 count;
1255         int ret;
1256
1257         ret = drm_dp_dpcd_readb(aux, DP_SINK_COUNT, &count);
1258         if (ret < 0)
1259                 return ret;
1260         if (ret != 1)
1261                 return -EIO;
1262
1263         return DP_GET_SINK_COUNT(count);
1264 }
1265 EXPORT_SYMBOL(drm_dp_read_sink_count);
1266
1267 /*
1268  * I2C-over-AUX implementation
1269  */
1270
1271 static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
1272 {
1273         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1274                I2C_FUNC_SMBUS_READ_BLOCK_DATA |
1275                I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1276                I2C_FUNC_10BIT_ADDR;
1277 }
1278
1279 static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
1280 {
1281         /*
1282          * In case of i2c defer or short i2c ack reply to a write,
1283          * we need to switch to WRITE_STATUS_UPDATE to drain the
1284          * rest of the message
1285          */
1286         if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
1287                 msg->request &= DP_AUX_I2C_MOT;
1288                 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
1289         }
1290 }
1291
1292 #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */
1293 #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */
1294 #define AUX_STOP_LEN 4
1295 #define AUX_CMD_LEN 4
1296 #define AUX_ADDRESS_LEN 20
1297 #define AUX_REPLY_PAD_LEN 4
1298 #define AUX_LENGTH_LEN 8
1299
1300 /*
1301  * Calculate the duration of the AUX request/reply in usec. Gives the
1302  * "best" case estimate, ie. successful while as short as possible.
1303  */
1304 static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
1305 {
1306         int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1307                 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN;
1308
1309         if ((msg->request & DP_AUX_I2C_READ) == 0)
1310                 len += msg->size * 8;
1311
1312         return len;
1313 }
1314
1315 static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
1316 {
1317         int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1318                 AUX_CMD_LEN + AUX_REPLY_PAD_LEN;
1319
1320         /*
1321          * For read we expect what was asked. For writes there will
1322          * be 0 or 1 data bytes. Assume 0 for the "best" case.
1323          */
1324         if (msg->request & DP_AUX_I2C_READ)
1325                 len += msg->size * 8;
1326
1327         return len;
1328 }
1329
1330 #define I2C_START_LEN 1
1331 #define I2C_STOP_LEN 1
1332 #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */
1333 #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */
1334
1335 /*
1336  * Calculate the length of the i2c transfer in usec, assuming
1337  * the i2c bus speed is as specified. Gives the the "worst"
1338  * case estimate, ie. successful while as long as possible.
1339  * Doesn't account the the "MOT" bit, and instead assumes each
1340  * message includes a START, ADDRESS and STOP. Neither does it
1341  * account for additional random variables such as clock stretching.
1342  */
1343 static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
1344                                    int i2c_speed_khz)
1345 {
1346         /* AUX bitrate is 1MHz, i2c bitrate as specified */
1347         return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +
1348                              msg->size * I2C_DATA_LEN +
1349                              I2C_STOP_LEN) * 1000, i2c_speed_khz);
1350 }
1351
1352 /*
1353  * Deterine how many retries should be attempted to successfully transfer
1354  * the specified message, based on the estimated durations of the
1355  * i2c and AUX transfers.
1356  */
1357 static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
1358                               int i2c_speed_khz)
1359 {
1360         int aux_time_us = drm_dp_aux_req_duration(msg) +
1361                 drm_dp_aux_reply_duration(msg);
1362         int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);
1363
1364         return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);
1365 }
1366
1367 /*
1368  * FIXME currently assumes 10 kHz as some real world devices seem
1369  * to require it. We should query/set the speed via DPCD if supported.
1370  */
1371 static int dp_aux_i2c_speed_khz __read_mostly = 10;
1372 module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
1373 MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
1374                  "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
1375
1376 /*
1377  * Transfer a single I2C-over-AUX message and handle various error conditions,
1378  * retrying the transaction as appropriate.  It is assumed that the
1379  * &drm_dp_aux.transfer function does not modify anything in the msg other than the
1380  * reply field.
1381  *
1382  * Returns bytes transferred on success, or a negative error code on failure.
1383  */
1384 static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1385 {
1386         unsigned int retry, defer_i2c;
1387         int ret;
1388         /*
1389          * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
1390          * is required to retry at least seven times upon receiving AUX_DEFER
1391          * before giving up the AUX transaction.
1392          *
1393          * We also try to account for the i2c bus speed.
1394          */
1395         int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz));
1396
1397         for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
1398                 ret = aux->transfer(aux, msg);
1399                 if (ret < 0) {
1400                         if (ret == -EBUSY)
1401                                 continue;
1402
1403                         /*
1404                          * While timeouts can be errors, they're usually normal
1405                          * behavior (for instance, when a driver tries to
1406                          * communicate with a non-existant DisplayPort device).
1407                          * Avoid spamming the kernel log with timeout errors.
1408                          */
1409                         if (ret == -ETIMEDOUT)
1410                                 DRM_DEBUG_KMS_RATELIMITED("%s: transaction timed out\n",
1411                                                           aux->name);
1412                         else
1413                                 DRM_DEBUG_KMS("%s: transaction failed: %d\n",
1414                                               aux->name, ret);
1415                         return ret;
1416                 }
1417
1418
1419                 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
1420                 case DP_AUX_NATIVE_REPLY_ACK:
1421                         /*
1422                          * For I2C-over-AUX transactions this isn't enough, we
1423                          * need to check for the I2C ACK reply.
1424                          */
1425                         break;
1426
1427                 case DP_AUX_NATIVE_REPLY_NACK:
1428                         DRM_DEBUG_KMS("%s: native nack (result=%d, size=%zu)\n",
1429                                       aux->name, ret, msg->size);
1430                         return -EREMOTEIO;
1431
1432                 case DP_AUX_NATIVE_REPLY_DEFER:
1433                         DRM_DEBUG_KMS("%s: native defer\n", aux->name);
1434                         /*
1435                          * We could check for I2C bit rate capabilities and if
1436                          * available adjust this interval. We could also be
1437                          * more careful with DP-to-legacy adapters where a
1438                          * long legacy cable may force very low I2C bit rates.
1439                          *
1440                          * For now just defer for long enough to hopefully be
1441                          * safe for all use-cases.
1442                          */
1443                         usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
1444                         continue;
1445
1446                 default:
1447                         DRM_ERROR("%s: invalid native reply %#04x\n",
1448                                   aux->name, msg->reply);
1449                         return -EREMOTEIO;
1450                 }
1451
1452                 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
1453                 case DP_AUX_I2C_REPLY_ACK:
1454                         /*
1455                          * Both native ACK and I2C ACK replies received. We
1456                          * can assume the transfer was successful.
1457                          */
1458                         if (ret != msg->size)
1459                                 drm_dp_i2c_msg_write_status_update(msg);
1460                         return ret;
1461
1462                 case DP_AUX_I2C_REPLY_NACK:
1463                         DRM_DEBUG_KMS("%s: I2C nack (result=%d, size=%zu)\n",
1464                                       aux->name, ret, msg->size);
1465                         aux->i2c_nack_count++;
1466                         return -EREMOTEIO;
1467
1468                 case DP_AUX_I2C_REPLY_DEFER:
1469                         DRM_DEBUG_KMS("%s: I2C defer\n", aux->name);
1470                         /* DP Compliance Test 4.2.2.5 Requirement:
1471                          * Must have at least 7 retries for I2C defers on the
1472                          * transaction to pass this test
1473                          */
1474                         aux->i2c_defer_count++;
1475                         if (defer_i2c < 7)
1476                                 defer_i2c++;
1477                         usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
1478                         drm_dp_i2c_msg_write_status_update(msg);
1479
1480                         continue;
1481
1482                 default:
1483                         DRM_ERROR("%s: invalid I2C reply %#04x\n",
1484                                   aux->name, msg->reply);
1485                         return -EREMOTEIO;
1486                 }
1487         }
1488
1489         DRM_DEBUG_KMS("%s: Too many retries, giving up\n", aux->name);
1490         return -EREMOTEIO;
1491 }
1492
1493 static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
1494                                        const struct i2c_msg *i2c_msg)
1495 {
1496         msg->request = (i2c_msg->flags & I2C_M_RD) ?
1497                 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
1498         if (!(i2c_msg->flags & I2C_M_STOP))
1499                 msg->request |= DP_AUX_I2C_MOT;
1500 }
1501
1502 /*
1503  * Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
1504  *
1505  * Returns an error code on failure, or a recommended transfer size on success.
1506  */
1507 static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
1508 {
1509         int err, ret = orig_msg->size;
1510         struct drm_dp_aux_msg msg = *orig_msg;
1511
1512         while (msg.size > 0) {
1513                 err = drm_dp_i2c_do_msg(aux, &msg);
1514                 if (err <= 0)
1515                         return err == 0 ? -EPROTO : err;
1516
1517                 if (err < msg.size && err < ret) {
1518                         DRM_DEBUG_KMS("%s: Partial I2C reply: requested %zu bytes got %d bytes\n",
1519                                       aux->name, msg.size, err);
1520                         ret = err;
1521                 }
1522
1523                 msg.size -= err;
1524                 msg.buffer += err;
1525         }
1526
1527         return ret;
1528 }
1529
1530 /*
1531  * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
1532  * packets to be as large as possible. If not, the I2C transactions never
1533  * succeed. Hence the default is maximum.
1534  */
1535 static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES;
1536 module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
1537 MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
1538                  "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
1539
1540 static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
1541                            int num)
1542 {
1543         struct drm_dp_aux *aux = adapter->algo_data;
1544         unsigned int i, j;
1545         unsigned transfer_size;
1546         struct drm_dp_aux_msg msg;
1547         int err = 0;
1548
1549         dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
1550
1551         memset(&msg, 0, sizeof(msg));
1552
1553         for (i = 0; i < num; i++) {
1554                 msg.address = msgs[i].addr;
1555                 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1556                 /* Send a bare address packet to start the transaction.
1557                  * Zero sized messages specify an address only (bare
1558                  * address) transaction.
1559                  */
1560                 msg.buffer = NULL;
1561                 msg.size = 0;
1562                 err = drm_dp_i2c_do_msg(aux, &msg);
1563
1564                 /*
1565                  * Reset msg.request in case in case it got
1566                  * changed into a WRITE_STATUS_UPDATE.
1567                  */
1568                 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1569
1570                 if (err < 0)
1571                         break;
1572                 /* We want each transaction to be as large as possible, but
1573                  * we'll go to smaller sizes if the hardware gives us a
1574                  * short reply.
1575                  */
1576                 transfer_size = dp_aux_i2c_transfer_size;
1577                 for (j = 0; j < msgs[i].len; j += msg.size) {
1578                         msg.buffer = msgs[i].buf + j;
1579                         msg.size = min(transfer_size, msgs[i].len - j);
1580
1581                         err = drm_dp_i2c_drain_msg(aux, &msg);
1582
1583                         /*
1584                          * Reset msg.request in case in case it got
1585                          * changed into a WRITE_STATUS_UPDATE.
1586                          */
1587                         drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1588
1589                         if (err < 0)
1590                                 break;
1591                         transfer_size = err;
1592                 }
1593                 if (err < 0)
1594                         break;
1595         }
1596         if (err >= 0)
1597                 err = num;
1598         /* Send a bare address packet to close out the transaction.
1599          * Zero sized messages specify an address only (bare
1600          * address) transaction.
1601          */
1602         msg.request &= ~DP_AUX_I2C_MOT;
1603         msg.buffer = NULL;
1604         msg.size = 0;
1605         (void)drm_dp_i2c_do_msg(aux, &msg);
1606
1607         return err;
1608 }
1609
1610 static const struct i2c_algorithm drm_dp_i2c_algo = {
1611         .functionality = drm_dp_i2c_functionality,
1612         .master_xfer = drm_dp_i2c_xfer,
1613 };
1614
1615 static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c)
1616 {
1617         return container_of(i2c, struct drm_dp_aux, ddc);
1618 }
1619
1620 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
1621 {
1622         mutex_lock(&i2c_to_aux(i2c)->hw_mutex);
1623 }
1624
1625 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
1626 {
1627         return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex);
1628 }
1629
1630 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
1631 {
1632         mutex_unlock(&i2c_to_aux(i2c)->hw_mutex);
1633 }
1634
1635 static const struct i2c_lock_operations drm_dp_i2c_lock_ops = {
1636         .lock_bus = lock_bus,
1637         .trylock_bus = trylock_bus,
1638         .unlock_bus = unlock_bus,
1639 };
1640
1641 static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)
1642 {
1643         u8 buf, count;
1644         int ret;
1645
1646         ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1647         if (ret < 0)
1648                 return ret;
1649
1650         WARN_ON(!(buf & DP_TEST_SINK_START));
1651
1652         ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf);
1653         if (ret < 0)
1654                 return ret;
1655
1656         count = buf & DP_TEST_COUNT_MASK;
1657         if (count == aux->crc_count)
1658                 return -EAGAIN; /* No CRC yet */
1659
1660         aux->crc_count = count;
1661
1662         /*
1663          * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes
1664          * per component (RGB or CrYCb).
1665          */
1666         ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6);
1667         if (ret < 0)
1668                 return ret;
1669
1670         return 0;
1671 }
1672
1673 static void drm_dp_aux_crc_work(struct work_struct *work)
1674 {
1675         struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux,
1676                                               crc_work);
1677         struct drm_crtc *crtc;
1678         u8 crc_bytes[6];
1679         uint32_t crcs[3];
1680         int ret;
1681
1682         if (WARN_ON(!aux->crtc))
1683                 return;
1684
1685         crtc = aux->crtc;
1686         while (crtc->crc.opened) {
1687                 drm_crtc_wait_one_vblank(crtc);
1688                 if (!crtc->crc.opened)
1689                         break;
1690
1691                 ret = drm_dp_aux_get_crc(aux, crc_bytes);
1692                 if (ret == -EAGAIN) {
1693                         usleep_range(1000, 2000);
1694                         ret = drm_dp_aux_get_crc(aux, crc_bytes);
1695                 }
1696
1697                 if (ret == -EAGAIN) {
1698                         DRM_DEBUG_KMS("%s: Get CRC failed after retrying: %d\n",
1699                                       aux->name, ret);
1700                         continue;
1701                 } else if (ret) {
1702                         DRM_DEBUG_KMS("%s: Failed to get a CRC: %d\n",
1703                                       aux->name, ret);
1704                         continue;
1705                 }
1706
1707                 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8;
1708                 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8;
1709                 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8;
1710                 drm_crtc_add_crc_entry(crtc, false, 0, crcs);
1711         }
1712 }
1713
1714 /**
1715  * drm_dp_remote_aux_init() - minimally initialise a remote aux channel
1716  * @aux: DisplayPort AUX channel
1717  *
1718  * Used for remote aux channel in general. Merely initialize the crc work
1719  * struct.
1720  */
1721 void drm_dp_remote_aux_init(struct drm_dp_aux *aux)
1722 {
1723         INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
1724 }
1725 EXPORT_SYMBOL(drm_dp_remote_aux_init);
1726
1727 /**
1728  * drm_dp_aux_init() - minimally initialise an aux channel
1729  * @aux: DisplayPort AUX channel
1730  *
1731  * If you need to use the drm_dp_aux's i2c adapter prior to registering it
1732  * with the outside world, call drm_dp_aux_init() first. You must still
1733  * call drm_dp_aux_register() once the connector has been registered to
1734  * allow userspace access to the auxiliary DP channel.
1735  */
1736 void drm_dp_aux_init(struct drm_dp_aux *aux)
1737 {
1738         mutex_init(&aux->hw_mutex);
1739         mutex_init(&aux->cec.lock);
1740         INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
1741
1742         aux->ddc.algo = &drm_dp_i2c_algo;
1743         aux->ddc.algo_data = aux;
1744         aux->ddc.retries = 3;
1745
1746         aux->ddc.lock_ops = &drm_dp_i2c_lock_ops;
1747 }
1748 EXPORT_SYMBOL(drm_dp_aux_init);
1749
1750 /**
1751  * drm_dp_aux_register() - initialise and register aux channel
1752  * @aux: DisplayPort AUX channel
1753  *
1754  * Automatically calls drm_dp_aux_init() if this hasn't been done yet.
1755  * This should only be called when the underlying &struct drm_connector is
1756  * initialiazed already. Therefore the best place to call this is from
1757  * &drm_connector_funcs.late_register. Not that drivers which don't follow this
1758  * will Oops when CONFIG_DRM_DP_AUX_CHARDEV is enabled.
1759  *
1760  * Drivers which need to use the aux channel before that point (e.g. at driver
1761  * load time, before drm_dev_register() has been called) need to call
1762  * drm_dp_aux_init().
1763  *
1764  * Returns 0 on success or a negative error code on failure.
1765  */
1766 int drm_dp_aux_register(struct drm_dp_aux *aux)
1767 {
1768         int ret;
1769
1770         if (!aux->ddc.algo)
1771                 drm_dp_aux_init(aux);
1772
1773         aux->ddc.class = I2C_CLASS_DDC;
1774         aux->ddc.owner = THIS_MODULE;
1775         aux->ddc.dev.parent = aux->dev;
1776
1777         strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
1778                 sizeof(aux->ddc.name));
1779
1780         ret = drm_dp_aux_register_devnode(aux);
1781         if (ret)
1782                 return ret;
1783
1784         ret = i2c_add_adapter(&aux->ddc);
1785         if (ret) {
1786                 drm_dp_aux_unregister_devnode(aux);
1787                 return ret;
1788         }
1789
1790         return 0;
1791 }
1792 EXPORT_SYMBOL(drm_dp_aux_register);
1793
1794 /**
1795  * drm_dp_aux_unregister() - unregister an AUX adapter
1796  * @aux: DisplayPort AUX channel
1797  */
1798 void drm_dp_aux_unregister(struct drm_dp_aux *aux)
1799 {
1800         drm_dp_aux_unregister_devnode(aux);
1801         i2c_del_adapter(&aux->ddc);
1802 }
1803 EXPORT_SYMBOL(drm_dp_aux_unregister);
1804
1805 #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
1806
1807 /**
1808  * drm_dp_psr_setup_time() - PSR setup in time usec
1809  * @psr_cap: PSR capabilities from DPCD
1810  *
1811  * Returns:
1812  * PSR setup time for the panel in microseconds,  negative
1813  * error code on failure.
1814  */
1815 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
1816 {
1817         static const u16 psr_setup_time_us[] = {
1818                 PSR_SETUP_TIME(330),
1819                 PSR_SETUP_TIME(275),
1820                 PSR_SETUP_TIME(220),
1821                 PSR_SETUP_TIME(165),
1822                 PSR_SETUP_TIME(110),
1823                 PSR_SETUP_TIME(55),
1824                 PSR_SETUP_TIME(0),
1825         };
1826         int i;
1827
1828         i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
1829         if (i >= ARRAY_SIZE(psr_setup_time_us))
1830                 return -EINVAL;
1831
1832         return psr_setup_time_us[i];
1833 }
1834 EXPORT_SYMBOL(drm_dp_psr_setup_time);
1835
1836 #undef PSR_SETUP_TIME
1837
1838 /**
1839  * drm_dp_start_crc() - start capture of frame CRCs
1840  * @aux: DisplayPort AUX channel
1841  * @crtc: CRTC displaying the frames whose CRCs are to be captured
1842  *
1843  * Returns 0 on success or a negative error code on failure.
1844  */
1845 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
1846 {
1847         u8 buf;
1848         int ret;
1849
1850         ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1851         if (ret < 0)
1852                 return ret;
1853
1854         ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START);
1855         if (ret < 0)
1856                 return ret;
1857
1858         aux->crc_count = 0;
1859         aux->crtc = crtc;
1860         schedule_work(&aux->crc_work);
1861
1862         return 0;
1863 }
1864 EXPORT_SYMBOL(drm_dp_start_crc);
1865
1866 /**
1867  * drm_dp_stop_crc() - stop capture of frame CRCs
1868  * @aux: DisplayPort AUX channel
1869  *
1870  * Returns 0 on success or a negative error code on failure.
1871  */
1872 int drm_dp_stop_crc(struct drm_dp_aux *aux)
1873 {
1874         u8 buf;
1875         int ret;
1876
1877         ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1878         if (ret < 0)
1879                 return ret;
1880
1881         ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START);
1882         if (ret < 0)
1883                 return ret;
1884
1885         flush_work(&aux->crc_work);
1886         aux->crtc = NULL;
1887
1888         return 0;
1889 }
1890 EXPORT_SYMBOL(drm_dp_stop_crc);
1891
1892 struct dpcd_quirk {
1893         u8 oui[3];
1894         u8 device_id[6];
1895         bool is_branch;
1896         u32 quirks;
1897 };
1898
1899 #define OUI(first, second, third) { (first), (second), (third) }
1900 #define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
1901         { (first), (second), (third), (fourth), (fifth), (sixth) }
1902
1903 #define DEVICE_ID_ANY   DEVICE_ID(0, 0, 0, 0, 0, 0)
1904
1905 static const struct dpcd_quirk dpcd_quirk_list[] = {
1906         /* Analogix 7737 needs reduced M and N at HBR2 link rates */
1907         { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
1908         /* LG LP140WF6-SPM1 eDP panel */
1909         { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
1910         /* Apple panels need some additional handling to support PSR */
1911         { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
1912         /* CH7511 seems to leave SINK_COUNT zeroed */
1913         { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
1914         /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
1915         { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
1916         /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
1917         { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
1918 };
1919
1920 #undef OUI
1921
1922 /*
1923  * Get a bit mask of DPCD quirks for the sink/branch device identified by
1924  * ident. The quirk data is shared but it's up to the drivers to act on the
1925  * data.
1926  *
1927  * For now, only the OUI (first three bytes) is used, but this may be extended
1928  * to device identification string and hardware/firmware revisions later.
1929  */
1930 static u32
1931 drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
1932 {
1933         const struct dpcd_quirk *quirk;
1934         u32 quirks = 0;
1935         int i;
1936         u8 any_device[] = DEVICE_ID_ANY;
1937
1938         for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
1939                 quirk = &dpcd_quirk_list[i];
1940
1941                 if (quirk->is_branch != is_branch)
1942                         continue;
1943
1944                 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
1945                         continue;
1946
1947                 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 &&
1948                     memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0)
1949                         continue;
1950
1951                 quirks |= quirk->quirks;
1952         }
1953
1954         return quirks;
1955 }
1956
1957 #undef DEVICE_ID_ANY
1958 #undef DEVICE_ID
1959
1960 /**
1961  * drm_dp_read_desc - read sink/branch descriptor from DPCD
1962  * @aux: DisplayPort AUX channel
1963  * @desc: Device descriptor to fill from DPCD
1964  * @is_branch: true for branch devices, false for sink devices
1965  *
1966  * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
1967  * identification.
1968  *
1969  * Returns 0 on success or a negative error code on failure.
1970  */
1971 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
1972                      bool is_branch)
1973 {
1974         struct drm_dp_dpcd_ident *ident = &desc->ident;
1975         unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
1976         int ret, dev_id_len;
1977
1978         ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident));
1979         if (ret < 0)
1980                 return ret;
1981
1982         desc->quirks = drm_dp_get_quirks(ident, is_branch);
1983
1984         dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
1985
1986         DRM_DEBUG_KMS("%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",
1987                       aux->name, is_branch ? "branch" : "sink",
1988                       (int)sizeof(ident->oui), ident->oui,
1989                       dev_id_len, ident->device_id,
1990                       ident->hw_rev >> 4, ident->hw_rev & 0xf,
1991                       ident->sw_major_rev, ident->sw_minor_rev,
1992                       desc->quirks);
1993
1994         return 0;
1995 }
1996 EXPORT_SYMBOL(drm_dp_read_desc);
1997
1998 /**
1999  * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
2000  * supported by the DSC sink.
2001  * @dsc_dpcd: DSC capabilities from DPCD
2002  * @is_edp: true if its eDP, false for DP
2003  *
2004  * Read the slice capabilities DPCD register from DSC sink to get
2005  * the maximum slice count supported. This is used to populate
2006  * the DSC parameters in the &struct drm_dsc_config by the driver.
2007  * Driver creates an infoframe using these parameters to populate
2008  * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2009  * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2010  *
2011  * Returns:
2012  * Maximum slice count supported by DSC sink or 0 its invalid
2013  */
2014 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2015                                    bool is_edp)
2016 {
2017         u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
2018
2019         if (is_edp) {
2020                 /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */
2021                 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2022                         return 4;
2023                 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2024                         return 2;
2025                 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2026                         return 1;
2027         } else {
2028                 /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
2029                 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
2030
2031                 if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
2032                         return 24;
2033                 if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
2034                         return 20;
2035                 if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
2036                         return 16;
2037                 if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
2038                         return 12;
2039                 if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
2040                         return 10;
2041                 if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
2042                         return 8;
2043                 if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
2044                         return 6;
2045                 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2046                         return 4;
2047                 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2048                         return 2;
2049                 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2050                         return 1;
2051         }
2052
2053         return 0;
2054 }
2055 EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
2056
2057 /**
2058  * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
2059  * @dsc_dpcd: DSC capabilities from DPCD
2060  *
2061  * Read the DSC DPCD register to parse the line buffer depth in bits which is
2062  * number of bits of precision within the decoder line buffer supported by
2063  * the DSC sink. This is used to populate the DSC parameters in the
2064  * &struct drm_dsc_config by the driver.
2065  * Driver creates an infoframe using these parameters to populate
2066  * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2067  * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2068  *
2069  * Returns:
2070  * Line buffer depth supported by DSC panel or 0 its invalid
2071  */
2072 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
2073 {
2074         u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT];
2075
2076         switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
2077         case DP_DSC_LINE_BUF_BIT_DEPTH_9:
2078                 return 9;
2079         case DP_DSC_LINE_BUF_BIT_DEPTH_10:
2080                 return 10;
2081         case DP_DSC_LINE_BUF_BIT_DEPTH_11:
2082                 return 11;
2083         case DP_DSC_LINE_BUF_BIT_DEPTH_12:
2084                 return 12;
2085         case DP_DSC_LINE_BUF_BIT_DEPTH_13:
2086                 return 13;
2087         case DP_DSC_LINE_BUF_BIT_DEPTH_14:
2088                 return 14;
2089         case DP_DSC_LINE_BUF_BIT_DEPTH_15:
2090                 return 15;
2091         case DP_DSC_LINE_BUF_BIT_DEPTH_16:
2092                 return 16;
2093         case DP_DSC_LINE_BUF_BIT_DEPTH_8:
2094                 return 8;
2095         }
2096
2097         return 0;
2098 }
2099 EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
2100
2101 /**
2102  * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
2103  * values supported by the DSC sink.
2104  * @dsc_dpcd: DSC capabilities from DPCD
2105  * @dsc_bpc: An array to be filled by this helper with supported
2106  *           input bpcs.
2107  *
2108  * Read the DSC DPCD from the sink device to parse the supported bits per
2109  * component values. This is used to populate the DSC parameters
2110  * in the &struct drm_dsc_config by the driver.
2111  * Driver creates an infoframe using these parameters to populate
2112  * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2113  * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2114  *
2115  * Returns:
2116  * Number of input BPC values parsed from the DPCD
2117  */
2118 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2119                                          u8 dsc_bpc[3])
2120 {
2121         int num_bpc = 0;
2122         u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
2123
2124         if (color_depth & DP_DSC_12_BPC)
2125                 dsc_bpc[num_bpc++] = 12;
2126         if (color_depth & DP_DSC_10_BPC)
2127                 dsc_bpc[num_bpc++] = 10;
2128         if (color_depth & DP_DSC_8_BPC)
2129                 dsc_bpc[num_bpc++] = 8;
2130
2131         return num_bpc;
2132 }
2133 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
2134
2135 /**
2136  * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
2137  * @aux: DisplayPort AUX channel
2138  * @caps: buffer to return the capability info in
2139  *
2140  * Read capabilities common to all LTTPRs.
2141  *
2142  * Returns 0 on success or a negative error code on failure.
2143  */
2144 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
2145                                   u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2146 {
2147         int ret;
2148
2149         ret = drm_dp_dpcd_read(aux,
2150                                DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
2151                                caps, DP_LTTPR_COMMON_CAP_SIZE);
2152         if (ret < 0)
2153                 return ret;
2154
2155         WARN_ON(ret != DP_LTTPR_COMMON_CAP_SIZE);
2156
2157         return 0;
2158 }
2159 EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
2160
2161 /**
2162  * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
2163  * @aux: DisplayPort AUX channel
2164  * @dp_phy: LTTPR PHY to read the capabilities for
2165  * @caps: buffer to return the capability info in
2166  *
2167  * Read the capabilities for the given LTTPR PHY.
2168  *
2169  * Returns 0 on success or a negative error code on failure.
2170  */
2171 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
2172                                enum drm_dp_phy dp_phy,
2173                                u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2174 {
2175         int ret;
2176
2177         ret = drm_dp_dpcd_read(aux,
2178                                DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
2179                                caps, DP_LTTPR_PHY_CAP_SIZE);
2180         if (ret < 0)
2181                 return ret;
2182
2183         WARN_ON(ret != DP_LTTPR_PHY_CAP_SIZE);
2184
2185         return 0;
2186 }
2187 EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);
2188
2189 static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r)
2190 {
2191         return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
2192 }
2193
2194 /**
2195  * drm_dp_lttpr_count - get the number of detected LTTPRs
2196  * @caps: LTTPR common capabilities
2197  *
2198  * Get the number of detected LTTPRs from the LTTPR common capabilities info.
2199  *
2200  * Returns:
2201  *   -ERANGE if more than supported number (8) of LTTPRs are detected
2202  *   -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value
2203  *   otherwise the number of detected LTTPRs
2204  */
2205 int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2206 {
2207         u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT);
2208
2209         switch (hweight8(count)) {
2210         case 0:
2211                 return 0;
2212         case 1:
2213                 return 8 - ilog2(count);
2214         case 8:
2215                 return -ERANGE;
2216         default:
2217                 return -EINVAL;
2218         }
2219 }
2220 EXPORT_SYMBOL(drm_dp_lttpr_count);
2221
2222 /**
2223  * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs
2224  * @caps: LTTPR common capabilities
2225  *
2226  * Returns the maximum link rate supported by all detected LTTPRs.
2227  */
2228 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2229 {
2230         u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER);
2231
2232         return drm_dp_bw_code_to_link_rate(rate);
2233 }
2234 EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate);
2235
2236 /**
2237  * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs
2238  * @caps: LTTPR common capabilities
2239  *
2240  * Returns the maximum lane count supported by all detected LTTPRs.
2241  */
2242 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2243 {
2244         u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER);
2245
2246         return max_lanes & DP_MAX_LANE_COUNT_MASK;
2247 }
2248 EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count);
2249
2250 /**
2251  * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support
2252  * @caps: LTTPR PHY capabilities
2253  *
2254  * Returns true if the @caps for an LTTPR TX PHY indicate support for
2255  * voltage swing level 3.
2256  */
2257 bool
2258 drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2259 {
2260         u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
2261
2262         return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED;
2263 }
2264 EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported);
2265
2266 /**
2267  * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support
2268  * @caps: LTTPR PHY capabilities
2269  *
2270  * Returns true if the @caps for an LTTPR TX PHY indicate support for
2271  * pre-emphasis level 3.
2272  */
2273 bool
2274 drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2275 {
2276         u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
2277
2278         return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED;
2279 }
2280 EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported);
2281
2282 /**
2283  * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
2284  * @aux: DisplayPort AUX channel
2285  * @data: DP phy compliance test parameters.
2286  *
2287  * Returns 0 on success or a negative error code on failure.
2288  */
2289 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
2290                                 struct drm_dp_phy_test_params *data)
2291 {
2292         int err;
2293         u8 rate, lanes;
2294
2295         err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
2296         if (err < 0)
2297                 return err;
2298         data->link_rate = drm_dp_bw_code_to_link_rate(rate);
2299
2300         err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
2301         if (err < 0)
2302                 return err;
2303         data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
2304
2305         if (lanes & DP_ENHANCED_FRAME_CAP)
2306                 data->enhanced_frame_cap = true;
2307
2308         err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
2309         if (err < 0)
2310                 return err;
2311
2312         switch (data->phy_pattern) {
2313         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
2314                 err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2315                                        &data->custom80, sizeof(data->custom80));
2316                 if (err < 0)
2317                         return err;
2318
2319                 break;
2320         case DP_PHY_TEST_PATTERN_CP2520:
2321                 err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
2322                                        &data->hbr2_reset,
2323                                        sizeof(data->hbr2_reset));
2324                 if (err < 0)
2325                         return err;
2326         }
2327
2328         return 0;
2329 }
2330 EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
2331
2332 /**
2333  * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
2334  * @aux: DisplayPort AUX channel
2335  * @data: DP phy compliance test parameters.
2336  * @dp_rev: DP revision to use for compliance testing
2337  *
2338  * Returns 0 on success or a negative error code on failure.
2339  */
2340 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
2341                                 struct drm_dp_phy_test_params *data, u8 dp_rev)
2342 {
2343         int err, i;
2344         u8 link_config[2];
2345         u8 test_pattern;
2346
2347         link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
2348         link_config[1] = data->num_lanes;
2349         if (data->enhanced_frame_cap)
2350                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2351         err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
2352         if (err < 0)
2353                 return err;
2354
2355         test_pattern = data->phy_pattern;
2356         if (dp_rev < 0x12) {
2357                 test_pattern = (test_pattern << 2) &
2358                                DP_LINK_QUAL_PATTERN_11_MASK;
2359                 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
2360                                          test_pattern);
2361                 if (err < 0)
2362                         return err;
2363         } else {
2364                 for (i = 0; i < data->num_lanes; i++) {
2365                         err = drm_dp_dpcd_writeb(aux,
2366                                                  DP_LINK_QUAL_LANE0_SET + i,
2367                                                  test_pattern);
2368                         if (err < 0)
2369                                 return err;
2370                 }
2371         }
2372
2373         return 0;
2374 }
2375 EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
2376
2377 static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat)
2378 {
2379         if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
2380                 return "Invalid";
2381
2382         switch (pixelformat) {
2383         case DP_PIXELFORMAT_RGB:
2384                 return "RGB";
2385         case DP_PIXELFORMAT_YUV444:
2386                 return "YUV444";
2387         case DP_PIXELFORMAT_YUV422:
2388                 return "YUV422";
2389         case DP_PIXELFORMAT_YUV420:
2390                 return "YUV420";
2391         case DP_PIXELFORMAT_Y_ONLY:
2392                 return "Y_ONLY";
2393         case DP_PIXELFORMAT_RAW:
2394                 return "RAW";
2395         default:
2396                 return "Reserved";
2397         }
2398 }
2399
2400 static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat,
2401                                            enum dp_colorimetry colorimetry)
2402 {
2403         if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
2404                 return "Invalid";
2405
2406         switch (colorimetry) {
2407         case DP_COLORIMETRY_DEFAULT:
2408                 switch (pixelformat) {
2409                 case DP_PIXELFORMAT_RGB:
2410                         return "sRGB";
2411                 case DP_PIXELFORMAT_YUV444:
2412                 case DP_PIXELFORMAT_YUV422:
2413                 case DP_PIXELFORMAT_YUV420:
2414                         return "BT.601";
2415                 case DP_PIXELFORMAT_Y_ONLY:
2416                         return "DICOM PS3.14";
2417                 case DP_PIXELFORMAT_RAW:
2418                         return "Custom Color Profile";
2419                 default:
2420                         return "Reserved";
2421                 }
2422         case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
2423                 switch (pixelformat) {
2424                 case DP_PIXELFORMAT_RGB:
2425                         return "Wide Fixed";
2426                 case DP_PIXELFORMAT_YUV444:
2427                 case DP_PIXELFORMAT_YUV422:
2428                 case DP_PIXELFORMAT_YUV420:
2429                         return "BT.709";
2430                 default:
2431                         return "Reserved";
2432                 }
2433         case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
2434                 switch (pixelformat) {
2435                 case DP_PIXELFORMAT_RGB:
2436                         return "Wide Float";
2437                 case DP_PIXELFORMAT_YUV444:
2438                 case DP_PIXELFORMAT_YUV422:
2439                 case DP_PIXELFORMAT_YUV420:
2440                         return "xvYCC 601";
2441                 default:
2442                         return "Reserved";
2443                 }
2444         case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
2445                 switch (pixelformat) {
2446                 case DP_PIXELFORMAT_RGB:
2447                         return "OpRGB";
2448                 case DP_PIXELFORMAT_YUV444:
2449                 case DP_PIXELFORMAT_YUV422:
2450                 case DP_PIXELFORMAT_YUV420:
2451                         return "xvYCC 709";
2452                 default:
2453                         return "Reserved";
2454                 }
2455         case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
2456                 switch (pixelformat) {
2457                 case DP_PIXELFORMAT_RGB:
2458                         return "DCI-P3";
2459                 case DP_PIXELFORMAT_YUV444:
2460                 case DP_PIXELFORMAT_YUV422:
2461                 case DP_PIXELFORMAT_YUV420:
2462                         return "sYCC 601";
2463                 default:
2464                         return "Reserved";
2465                 }
2466         case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
2467                 switch (pixelformat) {
2468                 case DP_PIXELFORMAT_RGB:
2469                         return "Custom Profile";
2470                 case DP_PIXELFORMAT_YUV444:
2471                 case DP_PIXELFORMAT_YUV422:
2472                 case DP_PIXELFORMAT_YUV420:
2473                         return "OpYCC 601";
2474                 default:
2475                         return "Reserved";
2476                 }
2477         case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
2478                 switch (pixelformat) {
2479                 case DP_PIXELFORMAT_RGB:
2480                         return "BT.2020 RGB";
2481                 case DP_PIXELFORMAT_YUV444:
2482                 case DP_PIXELFORMAT_YUV422:
2483                 case DP_PIXELFORMAT_YUV420:
2484                         return "BT.2020 CYCC";
2485                 default:
2486                         return "Reserved";
2487                 }
2488         case DP_COLORIMETRY_BT2020_YCC:
2489                 switch (pixelformat) {
2490                 case DP_PIXELFORMAT_YUV444:
2491                 case DP_PIXELFORMAT_YUV422:
2492                 case DP_PIXELFORMAT_YUV420:
2493                         return "BT.2020 YCC";
2494                 default:
2495                         return "Reserved";
2496                 }
2497         default:
2498                 return "Invalid";
2499         }
2500 }
2501
2502 static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)
2503 {
2504         switch (dynamic_range) {
2505         case DP_DYNAMIC_RANGE_VESA:
2506                 return "VESA range";
2507         case DP_DYNAMIC_RANGE_CTA:
2508                 return "CTA range";
2509         default:
2510                 return "Invalid";
2511         }
2512 }
2513
2514 static const char *dp_content_type_get_name(enum dp_content_type content_type)
2515 {
2516         switch (content_type) {
2517         case DP_CONTENT_TYPE_NOT_DEFINED:
2518                 return "Not defined";
2519         case DP_CONTENT_TYPE_GRAPHICS:
2520                 return "Graphics";
2521         case DP_CONTENT_TYPE_PHOTO:
2522                 return "Photo";
2523         case DP_CONTENT_TYPE_VIDEO:
2524                 return "Video";
2525         case DP_CONTENT_TYPE_GAME:
2526                 return "Game";
2527         default:
2528                 return "Reserved";
2529         }
2530 }
2531
2532 void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
2533                         const struct drm_dp_vsc_sdp *vsc)
2534 {
2535 #define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__)
2536         DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
2537                    vsc->revision, vsc->length);
2538         DP_SDP_LOG("    pixelformat: %s\n",
2539                    dp_pixelformat_get_name(vsc->pixelformat));
2540         DP_SDP_LOG("    colorimetry: %s\n",
2541                    dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry));
2542         DP_SDP_LOG("    bpc: %u\n", vsc->bpc);
2543         DP_SDP_LOG("    dynamic range: %s\n",
2544                    dp_dynamic_range_get_name(vsc->dynamic_range));
2545         DP_SDP_LOG("    content type: %s\n",
2546                    dp_content_type_get_name(vsc->content_type));
2547 #undef DP_SDP_LOG
2548 }
2549 EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
2550
2551 /**
2552  * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON
2553  * @dpcd: DisplayPort configuration data
2554  * @port_cap: port capabilities
2555  *
2556  * Returns maximum frl bandwidth supported by PCON in GBPS,
2557  * returns 0 if not supported.
2558  */
2559 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2560                                const u8 port_cap[4])
2561 {
2562         int bw;
2563         u8 buf;
2564
2565         buf = port_cap[2];
2566         bw = buf & DP_PCON_MAX_FRL_BW;
2567
2568         switch (bw) {
2569         case DP_PCON_MAX_9GBPS:
2570                 return 9;
2571         case DP_PCON_MAX_18GBPS:
2572                 return 18;
2573         case DP_PCON_MAX_24GBPS:
2574                 return 24;
2575         case DP_PCON_MAX_32GBPS:
2576                 return 32;
2577         case DP_PCON_MAX_40GBPS:
2578                 return 40;
2579         case DP_PCON_MAX_48GBPS:
2580                 return 48;
2581         case DP_PCON_MAX_0GBPS:
2582         default:
2583                 return 0;
2584         }
2585
2586         return 0;
2587 }
2588 EXPORT_SYMBOL(drm_dp_get_pcon_max_frl_bw);
2589
2590 /**
2591  * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL.
2592  * @aux: DisplayPort AUX channel
2593  * @enable_frl_ready_hpd: Configure DP_PCON_ENABLE_HPD_READY.
2594  *
2595  * Returns 0 if success, else returns negative error code.
2596  */
2597 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd)
2598 {
2599         int ret;
2600         u8 buf = DP_PCON_ENABLE_SOURCE_CTL_MODE |
2601                  DP_PCON_ENABLE_LINK_FRL_MODE;
2602
2603         if (enable_frl_ready_hpd)
2604                 buf |= DP_PCON_ENABLE_HPD_READY;
2605
2606         ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2607
2608         return ret;
2609 }
2610 EXPORT_SYMBOL(drm_dp_pcon_frl_prepare);
2611
2612 /**
2613  * drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL
2614  * @aux: DisplayPort AUX channel
2615  *
2616  * Returns true if success, else returns false.
2617  */
2618 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux)
2619 {
2620         int ret;
2621         u8 buf;
2622
2623         ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
2624         if (ret < 0)
2625                 return false;
2626
2627         if (buf & DP_PCON_FRL_READY)
2628                 return true;
2629
2630         return false;
2631 }
2632 EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
2633
2634 /**
2635  * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
2636  * @aux: DisplayPort AUX channel
2637  * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink
2638  * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential.
2639  * In Concurrent Mode, the FRL link bring up can be done along with
2640  * DP Link training. In Sequential mode, the FRL link bring up is done prior to
2641  * the DP Link training.
2642  *
2643  * Returns 0 if success, else returns negative error code.
2644  */
2645
2646 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
2647                                 u8 frl_mode)
2648 {
2649         int ret;
2650         u8 buf;
2651
2652         ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
2653         if (ret < 0)
2654                 return ret;
2655
2656         if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK)
2657                 buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
2658         else
2659                 buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
2660
2661         switch (max_frl_gbps) {
2662         case 9:
2663                 buf |=  DP_PCON_ENABLE_MAX_BW_9GBPS;
2664                 break;
2665         case 18:
2666                 buf |=  DP_PCON_ENABLE_MAX_BW_18GBPS;
2667                 break;
2668         case 24:
2669                 buf |=  DP_PCON_ENABLE_MAX_BW_24GBPS;
2670                 break;
2671         case 32:
2672                 buf |=  DP_PCON_ENABLE_MAX_BW_32GBPS;
2673                 break;
2674         case 40:
2675                 buf |=  DP_PCON_ENABLE_MAX_BW_40GBPS;
2676                 break;
2677         case 48:
2678                 buf |=  DP_PCON_ENABLE_MAX_BW_48GBPS;
2679                 break;
2680         case 0:
2681                 buf |=  DP_PCON_ENABLE_MAX_BW_0GBPS;
2682                 break;
2683         default:
2684                 return -EINVAL;
2685         }
2686
2687         ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2688         if (ret < 0)
2689                 return ret;
2690
2691         return 0;
2692 }
2693 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
2694
2695 /**
2696  * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
2697  * @aux: DisplayPort AUX channel
2698  * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
2699  * @frl_type : FRL training type, can be Extended, or Normal.
2700  * In Normal FRL training, the PCON tries each frl bw from the max_frl_mask
2701  * starting from min, and stops when link training is successful. In Extended
2702  * FRL training, all frl bw selected in the mask are trained by the PCON.
2703  *
2704  * Returns 0 if success, else returns negative error code.
2705  */
2706 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
2707                                 u8 frl_type)
2708 {
2709         int ret;
2710         u8 buf = max_frl_mask;
2711
2712         if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED)
2713                 buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
2714         else
2715                 buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED;
2716
2717         ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
2718         if (ret < 0)
2719                 return ret;
2720
2721         return 0;
2722 }
2723 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_2);
2724
2725 /**
2726  * drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration.
2727  * @aux: DisplayPort AUX channel
2728  *
2729  * Returns 0 if success, else returns negative error code.
2730  */
2731 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux)
2732 {
2733         int ret;
2734
2735         ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, 0x0);
2736         if (ret < 0)
2737                 return ret;
2738
2739         return 0;
2740 }
2741 EXPORT_SYMBOL(drm_dp_pcon_reset_frl_config);
2742
2743 /**
2744  * drm_dp_pcon_frl_enable() - Enable HDMI link through FRL
2745  * @aux: DisplayPort AUX channel
2746  *
2747  * Returns 0 if success, else returns negative error code.
2748  */
2749 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux)
2750 {
2751         int ret;
2752         u8 buf = 0;
2753
2754         ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
2755         if (ret < 0)
2756                 return ret;
2757         if (!(buf & DP_PCON_ENABLE_SOURCE_CTL_MODE)) {
2758                 DRM_DEBUG_KMS("PCON in Autonomous mode, can't enable FRL\n");
2759                 return -EINVAL;
2760         }
2761         buf |= DP_PCON_ENABLE_HDMI_LINK;
2762         ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2763         if (ret < 0)
2764                 return ret;
2765
2766         return 0;
2767 }
2768 EXPORT_SYMBOL(drm_dp_pcon_frl_enable);
2769
2770 /**
2771  * drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is active.
2772  * @aux: DisplayPort AUX channel
2773  *
2774  * Returns true if link is active else returns false.
2775  */
2776 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux)
2777 {
2778         u8 buf;
2779         int ret;
2780
2781         ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
2782         if (ret < 0)
2783                 return false;
2784
2785         return buf & DP_PCON_HDMI_TX_LINK_ACTIVE;
2786 }
2787 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_active);
2788
2789 /**
2790  * drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE
2791  * @aux: DisplayPort AUX channel
2792  * @frl_trained_mask: pointer to store bitmask of the trained bw configuration.
2793  * Valid only if the MODE returned is FRL. For Normal Link training mode
2794  * only 1 of the bits will be set, but in case of Extended mode, more than
2795  * one bits can be set.
2796  *
2797  * Returns the link mode : TMDS or FRL on success, else returns negative error
2798  * code.
2799  */
2800 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask)
2801 {
2802         u8 buf;
2803         int mode;
2804         int ret;
2805
2806         ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_POST_FRL_STATUS, &buf);
2807         if (ret < 0)
2808                 return ret;
2809
2810         mode = buf & DP_PCON_HDMI_LINK_MODE;
2811
2812         if (frl_trained_mask && DP_PCON_HDMI_MODE_FRL == mode)
2813                 *frl_trained_mask = (buf & DP_PCON_HDMI_FRL_TRAINED_BW) >> 1;
2814
2815         return mode;
2816 }
2817 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode);
2818
2819 /**
2820  * drm_dp_pcon_hdmi_frl_link_error_count() - print the error count per lane
2821  * during link failure between PCON and HDMI sink
2822  * @aux: DisplayPort AUX channel
2823  * @connector: DRM connector
2824  * code.
2825  **/
2826
2827 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
2828                                            struct drm_connector *connector)
2829 {
2830         u8 buf, error_count;
2831         int i, num_error;
2832         struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
2833
2834         for (i = 0; i < hdmi->max_lanes; i++) {
2835                 if (drm_dp_dpcd_readb(aux, DP_PCON_HDMI_ERROR_STATUS_LN0 + i, &buf) < 0)
2836                         return;
2837
2838                 error_count = buf & DP_PCON_HDMI_ERROR_COUNT_MASK;
2839                 switch (error_count) {
2840                 case DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS:
2841                         num_error = 100;
2842                         break;
2843                 case DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS:
2844                         num_error = 10;
2845                         break;
2846                 case DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS:
2847                         num_error = 3;
2848                         break;
2849                 default:
2850                         num_error = 0;
2851                 }
2852
2853                 DRM_ERROR("More than %d errors since the last read for lane %d", num_error, i);
2854         }
2855 }
2856 EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count);
2857
2858 /*
2859  * drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2
2860  * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
2861  *
2862  * Returns true is PCON encoder is DSC 1.2 else returns false.
2863  */
2864 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
2865 {
2866         u8 buf;
2867         u8 major_v, minor_v;
2868
2869         buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION - DP_PCON_DSC_ENCODER];
2870         major_v = (buf & DP_PCON_DSC_MAJOR_MASK) >> DP_PCON_DSC_MAJOR_SHIFT;
2871         minor_v = (buf & DP_PCON_DSC_MINOR_MASK) >> DP_PCON_DSC_MINOR_SHIFT;
2872
2873         if (major_v == 1 && minor_v == 2)
2874                 return true;
2875
2876         return false;
2877 }
2878 EXPORT_SYMBOL(drm_dp_pcon_enc_is_dsc_1_2);
2879
2880 /*
2881  * drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC Encoder
2882  * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
2883  *
2884  * Returns maximum no. of slices supported by the PCON DSC Encoder.
2885  */
2886 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
2887 {
2888         u8 slice_cap1, slice_cap2;
2889
2890         slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_1 - DP_PCON_DSC_ENCODER];
2891         slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_2 - DP_PCON_DSC_ENCODER];
2892
2893         if (slice_cap2 & DP_PCON_DSC_24_PER_DSC_ENC)
2894                 return 24;
2895         if (slice_cap2 & DP_PCON_DSC_20_PER_DSC_ENC)
2896                 return 20;
2897         if (slice_cap2 & DP_PCON_DSC_16_PER_DSC_ENC)
2898                 return 16;
2899         if (slice_cap1 & DP_PCON_DSC_12_PER_DSC_ENC)
2900                 return 12;
2901         if (slice_cap1 & DP_PCON_DSC_10_PER_DSC_ENC)
2902                 return 10;
2903         if (slice_cap1 & DP_PCON_DSC_8_PER_DSC_ENC)
2904                 return 8;
2905         if (slice_cap1 & DP_PCON_DSC_6_PER_DSC_ENC)
2906                 return 6;
2907         if (slice_cap1 & DP_PCON_DSC_4_PER_DSC_ENC)
2908                 return 4;
2909         if (slice_cap1 & DP_PCON_DSC_2_PER_DSC_ENC)
2910                 return 2;
2911         if (slice_cap1 & DP_PCON_DSC_1_PER_DSC_ENC)
2912                 return 1;
2913
2914         return 0;
2915 }
2916 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slices);
2917
2918 /*
2919  * drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC encoder
2920  * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
2921  *
2922  * Returns maximum width of the slices in pixel width i.e. no. of pixels x 320.
2923  */
2924 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
2925 {
2926         u8 buf;
2927
2928         buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH - DP_PCON_DSC_ENCODER];
2929
2930         return buf * DP_DSC_SLICE_WIDTH_MULTIPLIER;
2931 }
2932 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slice_width);
2933
2934 /*
2935  * drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON DSC encoder
2936  * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
2937  *
2938  * Returns the bpp precision supported by the PCON encoder.
2939  */
2940 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
2941 {
2942         u8 buf;
2943
2944         buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR - DP_PCON_DSC_ENCODER];
2945
2946         switch (buf & DP_PCON_DSC_BPP_INCR_MASK) {
2947         case DP_PCON_DSC_ONE_16TH_BPP:
2948                 return 16;
2949         case DP_PCON_DSC_ONE_8TH_BPP:
2950                 return 8;
2951         case DP_PCON_DSC_ONE_4TH_BPP:
2952                 return 4;
2953         case DP_PCON_DSC_ONE_HALF_BPP:
2954                 return 2;
2955         case DP_PCON_DSC_ONE_BPP:
2956                 return 1;
2957         }
2958
2959         return 0;
2960 }
2961 EXPORT_SYMBOL(drm_dp_pcon_dsc_bpp_incr);
2962
2963 static
2964 int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config)
2965 {
2966         u8 buf;
2967         int ret;
2968
2969         ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf);
2970         if (ret < 0)
2971                 return ret;
2972
2973         buf |= DP_PCON_ENABLE_DSC_ENCODER;
2974
2975         if (pps_buf_config <= DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER) {
2976                 buf &= ~DP_PCON_ENCODER_PPS_OVERRIDE_MASK;
2977                 buf |= pps_buf_config << 2;
2978         }
2979
2980         ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf);
2981         if (ret < 0)
2982                 return ret;
2983
2984         return 0;
2985 }
2986
2987 /**
2988  * drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters
2989  * for DSC1.2 between PCON & HDMI2.1 sink
2990  * @aux: DisplayPort AUX channel
2991  *
2992  * Returns 0 on success, else returns negative error code.
2993  */
2994 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux)
2995 {
2996         int ret;
2997
2998         ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_DISABLED);
2999         if (ret < 0)
3000                 return ret;
3001
3002         return 0;
3003 }
3004 EXPORT_SYMBOL(drm_dp_pcon_pps_default);
3005
3006 /**
3007  * drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for
3008  * HDMI sink
3009  * @aux: DisplayPort AUX channel
3010  * @pps_buf: 128 bytes to be written into PPS buffer for HDMI sink by PCON.
3011  *
3012  * Returns 0 on success, else returns negative error code.
3013  */
3014 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128])
3015 {
3016         int ret;
3017
3018         ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE, &pps_buf, 128);
3019         if (ret < 0)
3020                 return ret;
3021
3022         ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
3023         if (ret < 0)
3024                 return ret;
3025
3026         return 0;
3027 }
3028 EXPORT_SYMBOL(drm_dp_pcon_pps_override_buf);
3029
3030 /*
3031  * drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder
3032  * override registers
3033  * @aux: DisplayPort AUX channel
3034  * @pps_param: 3 Parameters (2 Bytes each) : Slice Width, Slice Height,
3035  * bits_per_pixel.
3036  *
3037  * Returns 0 on success, else returns negative error code.
3038  */
3039 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6])
3040 {
3041         int ret;
3042
3043         ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, &pps_param[0], 2);
3044         if (ret < 0)
3045                 return ret;
3046         ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, &pps_param[2], 2);
3047         if (ret < 0)
3048                 return ret;
3049         ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_BPP, &pps_param[4], 2);
3050         if (ret < 0)
3051                 return ret;
3052
3053         ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
3054         if (ret < 0)
3055                 return ret;
3056
3057         return 0;
3058 }
3059 EXPORT_SYMBOL(drm_dp_pcon_pps_override_param);
3060
3061 /*
3062  * drm_dp_pcon_convert_rgb_to_ycbcr() - Configure the PCon to convert RGB to Ycbcr
3063  * @aux: displayPort AUX channel
3064  * @color_spc: Color-space/s for which conversion is to be enabled, 0 for disable.
3065  *
3066  * Returns 0 on success, else returns negative error code.
3067  */
3068 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc)
3069 {
3070         int ret;
3071         u8 buf;
3072
3073         ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf);
3074         if (ret < 0)
3075                 return ret;
3076
3077         if (color_spc & DP_CONVERSION_RGB_YCBCR_MASK)
3078                 buf |= (color_spc & DP_CONVERSION_RGB_YCBCR_MASK);
3079         else
3080                 buf &= ~DP_CONVERSION_RGB_YCBCR_MASK;
3081
3082         ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf);
3083         if (ret < 0)
3084                 return ret;
3085
3086         return 0;
3087 }
3088 EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);