2 * Copyright © 2009 Keith Packard
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
23 #include <linux/delay.h>
24 #include <linux/errno.h>
25 #include <linux/i2c.h>
26 #include <linux/init.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/sched.h>
30 #include <linux/seq_file.h>
32 #include <drm/drm_dp_helper.h>
33 #include <drm/drm_print.h>
34 #include <drm/drm_vblank.h>
35 #include <drm/drm_dp_mst_helper.h>
37 #include "drm_crtc_helper_internal.h"
42 * These functions contain some common logic and helpers at various abstraction
43 * levels to deal with Display Port sink devices and related things like DP aux
44 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
48 /* Helpers for DP link training */
49 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
51 return link_status[r - DP_LANE0_1_STATUS];
54 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
57 int i = DP_LANE0_1_STATUS + (lane >> 1);
58 int s = (lane & 1) * 4;
59 u8 l = dp_link_status(link_status, i);
61 return (l >> s) & 0xf;
64 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
71 lane_align = dp_link_status(link_status,
72 DP_LANE_ALIGN_STATUS_UPDATED);
73 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
75 for (lane = 0; lane < lane_count; lane++) {
76 lane_status = dp_get_lane_status(link_status, lane);
77 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
82 EXPORT_SYMBOL(drm_dp_channel_eq_ok);
84 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
90 for (lane = 0; lane < lane_count; lane++) {
91 lane_status = dp_get_lane_status(link_status, lane);
92 if ((lane_status & DP_LANE_CR_DONE) == 0)
97 EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
99 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
102 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
103 int s = ((lane & 1) ?
104 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
105 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
106 u8 l = dp_link_status(link_status, i);
108 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
110 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
112 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
115 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
116 int s = ((lane & 1) ?
117 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
118 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
119 u8 l = dp_link_status(link_status, i);
121 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
123 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
125 u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
128 unsigned int offset = DP_ADJUST_REQUEST_POST_CURSOR2;
129 u8 value = dp_link_status(link_status, offset);
131 return (value >> (lane << 1)) & 0x3;
133 EXPORT_SYMBOL(drm_dp_get_adjust_request_post_cursor);
135 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
137 unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
138 DP_TRAINING_AUX_RD_MASK;
141 DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",
144 if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
147 rd_interval *= 4 * USEC_PER_MSEC;
149 usleep_range(rd_interval, rd_interval * 2);
151 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
153 static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval)
156 DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",
159 if (rd_interval == 0)
162 rd_interval *= 4 * USEC_PER_MSEC;
164 usleep_range(rd_interval, rd_interval * 2);
167 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
169 __drm_dp_link_train_channel_eq_delay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
170 DP_TRAINING_AUX_RD_MASK);
172 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
174 void drm_dp_lttpr_link_train_clock_recovery_delay(void)
176 usleep_range(100, 200);
178 EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay);
180 static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r)
182 return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1];
185 void drm_dp_lttpr_link_train_channel_eq_delay(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE])
187 u8 interval = dp_lttpr_phy_cap(phy_cap,
188 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) &
189 DP_TRAINING_AUX_RD_MASK;
191 __drm_dp_link_train_channel_eq_delay(interval);
193 EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);
195 u8 drm_dp_link_rate_to_bw_code(int link_rate)
197 /* Spec says link_bw = link_rate / 0.27Gbps */
198 return link_rate / 27000;
200 EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
202 int drm_dp_bw_code_to_link_rate(u8 link_bw)
204 /* Spec says link_rate = link_bw * 0.27Gbps */
205 return link_bw * 27000;
207 EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
209 #define AUX_RETRY_INTERVAL 500 /* us */
212 drm_dp_dump_access(const struct drm_dp_aux *aux,
213 u8 request, uint offset, void *buffer, int ret)
215 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-";
218 DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
219 aux->name, offset, arrow, ret, min(ret, 20), buffer);
221 DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d)\n",
222 aux->name, offset, arrow, ret);
228 * The DisplayPort AUX channel is an abstraction to allow generic, driver-
229 * independent access to AUX functionality. Drivers can take advantage of
230 * this by filling in the fields of the drm_dp_aux structure.
232 * Transactions are described using a hardware-independent drm_dp_aux_msg
233 * structure, which is passed into a driver's .transfer() implementation.
234 * Both native and I2C-over-AUX transactions are supported.
237 static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
238 unsigned int offset, void *buffer, size_t size)
240 struct drm_dp_aux_msg msg;
241 unsigned int retry, native_reply;
242 int err = 0, ret = 0;
244 memset(&msg, 0, sizeof(msg));
245 msg.address = offset;
246 msg.request = request;
250 mutex_lock(&aux->hw_mutex);
253 * The specification doesn't give any recommendation on how often to
254 * retry native transactions. We used to retry 7 times like for
255 * aux i2c transactions but real world devices this wasn't
256 * sufficient, bump to 32 which makes Dell 4k monitors happier.
258 for (retry = 0; retry < 32; retry++) {
259 if (ret != 0 && ret != -ETIMEDOUT) {
260 usleep_range(AUX_RETRY_INTERVAL,
261 AUX_RETRY_INTERVAL + 100);
264 ret = aux->transfer(aux, &msg);
266 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK;
267 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) {
277 * We want the error we return to be the error we received on
278 * the first transaction, since we may get a different error the
285 DRM_DEBUG_KMS("%s: Too many retries, giving up. First error: %d\n",
290 mutex_unlock(&aux->hw_mutex);
295 * drm_dp_dpcd_read() - read a series of bytes from the DPCD
296 * @aux: DisplayPort AUX channel (SST or MST)
297 * @offset: address of the (first) register to read
298 * @buffer: buffer to store the register values
299 * @size: number of bytes in @buffer
301 * Returns the number of bytes transferred on success, or a negative error
302 * code on failure. -EIO is returned if the request was NAKed by the sink or
303 * if the retry count was exceeded. If not all bytes were transferred, this
304 * function returns -EPROTO. Errors from the underlying AUX channel transfer
305 * function, with the exception of -EBUSY (which causes the transaction to
306 * be retried), are propagated to the caller.
308 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
309 void *buffer, size_t size)
314 * HP ZR24w corrupts the first DPCD access after entering power save
315 * mode. Eg. on a read, the entire buffer will be filled with the same
316 * byte. Do a throw away read to avoid corrupting anything we care
317 * about. Afterwards things will work correctly until the monitor
318 * gets woken up and subsequently re-enters power save mode.
320 * The user pressing any button on the monitor is enough to wake it
321 * up, so there is no particularly good place to do the workaround.
322 * We just have to do it before any DPCD access and hope that the
323 * monitor doesn't power down exactly after the throw away read.
325 if (!aux->is_remote) {
326 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV,
333 ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size);
335 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset,
339 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret);
342 EXPORT_SYMBOL(drm_dp_dpcd_read);
345 * drm_dp_dpcd_write() - write a series of bytes to the DPCD
346 * @aux: DisplayPort AUX channel (SST or MST)
347 * @offset: address of the (first) register to write
348 * @buffer: buffer containing the values to write
349 * @size: number of bytes in @buffer
351 * Returns the number of bytes transferred on success, or a negative error
352 * code on failure. -EIO is returned if the request was NAKed by the sink or
353 * if the retry count was exceeded. If not all bytes were transferred, this
354 * function returns -EPROTO. Errors from the underlying AUX channel transfer
355 * function, with the exception of -EBUSY (which causes the transaction to
356 * be retried), are propagated to the caller.
358 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
359 void *buffer, size_t size)
364 ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size);
366 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset,
369 drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
372 EXPORT_SYMBOL(drm_dp_dpcd_write);
375 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
376 * @aux: DisplayPort AUX channel
377 * @status: buffer to store the link status in (must be at least 6 bytes)
379 * Returns the number of bytes transferred on success or a negative error
382 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
383 u8 status[DP_LINK_STATUS_SIZE])
385 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
386 DP_LINK_STATUS_SIZE);
388 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
391 * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY
392 * @aux: DisplayPort AUX channel
393 * @dp_phy: the DP PHY to get the link status for
394 * @link_status: buffer to return the status in
396 * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The
397 * layout of the returned @link_status matches the DPCD register layout of the
398 * DPRX PHY link status.
400 * Returns 0 if the information was read successfully or a negative error code
403 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
404 enum drm_dp_phy dp_phy,
405 u8 link_status[DP_LINK_STATUS_SIZE])
409 if (dp_phy == DP_PHY_DPRX) {
410 ret = drm_dp_dpcd_read(aux,
413 DP_LINK_STATUS_SIZE);
418 WARN_ON(ret != DP_LINK_STATUS_SIZE);
423 ret = drm_dp_dpcd_read(aux,
424 DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy),
426 DP_LINK_STATUS_SIZE - 1);
431 WARN_ON(ret != DP_LINK_STATUS_SIZE - 1);
433 /* Convert the LTTPR to the sink PHY link status layout */
434 memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1],
435 &link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS],
436 DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1);
437 link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0;
441 EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status);
443 static bool is_edid_digital_input_dp(const struct edid *edid)
445 return edid && edid->revision >= 4 &&
446 edid->input & DRM_EDID_INPUT_DIGITAL &&
447 (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP;
451 * drm_dp_downstream_is_type() - is the downstream facing port of certain type?
452 * @dpcd: DisplayPort configuration data
453 * @port_cap: port capabilities
454 * @type: port type to be checked. Can be:
455 * %DP_DS_PORT_TYPE_DP, %DP_DS_PORT_TYPE_VGA, %DP_DS_PORT_TYPE_DVI,
456 * %DP_DS_PORT_TYPE_HDMI, %DP_DS_PORT_TYPE_NON_EDID,
457 * %DP_DS_PORT_TYPE_DP_DUALMODE or %DP_DS_PORT_TYPE_WIRELESS.
459 * Caveat: Only works with DPCD 1.1+ port caps.
461 * Returns: whether the downstream facing port matches the type.
463 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
464 const u8 port_cap[4], u8 type)
466 return drm_dp_is_branch(dpcd) &&
467 dpcd[DP_DPCD_REV] >= 0x11 &&
468 (port_cap[0] & DP_DS_PORT_TYPE_MASK) == type;
470 EXPORT_SYMBOL(drm_dp_downstream_is_type);
473 * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS?
474 * @dpcd: DisplayPort configuration data
475 * @port_cap: port capabilities
478 * Returns: whether the downstream facing port is TMDS (HDMI/DVI).
480 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
481 const u8 port_cap[4],
482 const struct edid *edid)
484 if (dpcd[DP_DPCD_REV] < 0x11) {
485 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
486 case DP_DWN_STRM_PORT_TYPE_TMDS:
493 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
494 case DP_DS_PORT_TYPE_DP_DUALMODE:
495 if (is_edid_digital_input_dp(edid))
498 case DP_DS_PORT_TYPE_DVI:
499 case DP_DS_PORT_TYPE_HDMI:
505 EXPORT_SYMBOL(drm_dp_downstream_is_tmds);
508 * drm_dp_send_real_edid_checksum() - send back real edid checksum value
509 * @aux: DisplayPort AUX channel
510 * @real_edid_checksum: real edid checksum for the last block
515 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
516 u8 real_edid_checksum)
518 u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;
520 if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
521 &auto_test_req, 1) < 1) {
522 DRM_ERROR("%s: DPCD failed read at register 0x%x\n",
523 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
526 auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
528 if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1) < 1) {
529 DRM_ERROR("%s: DPCD failed read at register 0x%x\n",
530 aux->name, DP_TEST_REQUEST);
533 link_edid_read &= DP_TEST_LINK_EDID_READ;
535 if (!auto_test_req || !link_edid_read) {
536 DRM_DEBUG_KMS("%s: Source DUT does not support TEST_EDID_READ\n",
541 if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
542 &auto_test_req, 1) < 1) {
543 DRM_ERROR("%s: DPCD failed write at register 0x%x\n",
544 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
548 /* send back checksum for the last edid extension block data */
549 if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM,
550 &real_edid_checksum, 1) < 1) {
551 DRM_ERROR("%s: DPCD failed write at register 0x%x\n",
552 aux->name, DP_TEST_EDID_CHECKSUM);
556 test_resp |= DP_TEST_EDID_CHECKSUM_WRITE;
557 if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) {
558 DRM_ERROR("%s: DPCD failed write at register 0x%x\n",
559 aux->name, DP_TEST_RESPONSE);
565 EXPORT_SYMBOL(drm_dp_send_real_edid_checksum);
567 static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
569 u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK;
571 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4)
577 static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux,
578 u8 dpcd[DP_RECEIVER_CAP_SIZE])
584 * Prior to DP1.3 the bit represented by
585 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
586 * If it is set DP_DPCD_REV at 0000h could be at a value less than
587 * the true capability of the panel. The only way to check is to
588 * then compare 0000h and 2200h.
590 if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
591 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
594 ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext,
598 if (ret != sizeof(dpcd_ext))
601 if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
602 DRM_DEBUG_KMS("%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n",
603 aux->name, dpcd[DP_DPCD_REV],
604 dpcd_ext[DP_DPCD_REV]);
608 if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext)))
611 DRM_DEBUG_KMS("%s: Base DPCD: %*ph\n",
612 aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
614 memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext));
620 * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if
622 * @aux: DisplayPort AUX channel
623 * @dpcd: Buffer to store the resulting DPCD in
625 * Attempts to read the base DPCD caps for @aux. Additionally, this function
626 * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if
629 * Returns: %0 if the DPCD was read successfully, negative error code
632 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
633 u8 dpcd[DP_RECEIVER_CAP_SIZE])
637 ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE);
640 if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0)
643 ret = drm_dp_read_extended_dpcd_caps(aux, dpcd);
647 DRM_DEBUG_KMS("%s: DPCD: %*ph\n",
648 aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
652 EXPORT_SYMBOL(drm_dp_read_dpcd_caps);
655 * drm_dp_read_downstream_info() - read DPCD downstream port info if available
656 * @aux: DisplayPort AUX channel
657 * @dpcd: A cached copy of the port's DPCD
658 * @downstream_ports: buffer to store the downstream port info in
661 * drm_dp_downstream_max_clock()
662 * drm_dp_downstream_max_bpc()
664 * Returns: 0 if either the downstream port info was read successfully or
665 * there was no downstream info to read, or a negative error code otherwise.
667 int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
668 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
669 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS])
674 memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS);
676 /* No downstream info to read */
677 if (!drm_dp_is_branch(dpcd) ||
678 dpcd[DP_DPCD_REV] < DP_DPCD_REV_10 ||
679 !(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
682 len = drm_dp_downstream_port_count(dpcd);
683 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE)
686 ret = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, downstream_ports, len);
692 DRM_DEBUG_KMS("%s: DPCD DFP: %*ph\n",
693 aux->name, len, downstream_ports);
697 EXPORT_SYMBOL(drm_dp_read_downstream_info);
700 * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock
701 * @dpcd: DisplayPort configuration data
702 * @port_cap: port capabilities
704 * Returns: Downstream facing port max dot clock in kHz on success,
705 * or 0 if max clock not defined
707 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
708 const u8 port_cap[4])
710 if (!drm_dp_is_branch(dpcd))
713 if (dpcd[DP_DPCD_REV] < 0x11)
716 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
717 case DP_DS_PORT_TYPE_VGA:
718 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
720 return port_cap[1] * 8000;
725 EXPORT_SYMBOL(drm_dp_downstream_max_dotclock);
728 * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock
729 * @dpcd: DisplayPort configuration data
730 * @port_cap: port capabilities
733 * Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success,
734 * or 0 if max TMDS clock not defined
736 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
737 const u8 port_cap[4],
738 const struct edid *edid)
740 if (!drm_dp_is_branch(dpcd))
743 if (dpcd[DP_DPCD_REV] < 0x11) {
744 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
745 case DP_DWN_STRM_PORT_TYPE_TMDS:
752 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
753 case DP_DS_PORT_TYPE_DP_DUALMODE:
754 if (is_edid_digital_input_dp(edid))
757 * It's left up to the driver to check the
758 * DP dual mode adapter's max TMDS clock.
760 * Unfortunatley it looks like branch devices
761 * may not fordward that the DP dual mode i2c
762 * access so we just usually get i2c nak :(
765 case DP_DS_PORT_TYPE_HDMI:
767 * We should perhaps assume 165 MHz when detailed cap
768 * info is not available. But looks like many typical
769 * branch devices fall into that category and so we'd
770 * probably end up with users complaining that they can't
771 * get high resolution modes with their favorite dongle.
773 * So let's limit to 300 MHz instead since DPCD 1.4
774 * HDMI 2.0 DFPs are required to have the detailed cap
775 * info. So it's more likely we're dealing with a HDMI 1.4
776 * compatible* device here.
778 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
780 return port_cap[1] * 2500;
781 case DP_DS_PORT_TYPE_DVI:
782 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
784 /* FIXME what to do about DVI dual link? */
785 return port_cap[1] * 2500;
790 EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock);
793 * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock
794 * @dpcd: DisplayPort configuration data
795 * @port_cap: port capabilities
798 * Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success,
799 * or 0 if max TMDS clock not defined
801 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
802 const u8 port_cap[4],
803 const struct edid *edid)
805 if (!drm_dp_is_branch(dpcd))
808 if (dpcd[DP_DPCD_REV] < 0x11) {
809 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
810 case DP_DWN_STRM_PORT_TYPE_TMDS:
817 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
818 case DP_DS_PORT_TYPE_DP_DUALMODE:
819 if (is_edid_digital_input_dp(edid))
822 case DP_DS_PORT_TYPE_DVI:
823 case DP_DS_PORT_TYPE_HDMI:
825 * Unclear whether the protocol converter could
826 * utilize pixel replication. Assume it won't.
833 EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock);
836 * drm_dp_downstream_max_bpc() - extract downstream facing port max
838 * @dpcd: DisplayPort configuration data
839 * @port_cap: downstream facing port capabilities
842 * Returns: Max bpc on success or 0 if max bpc not defined
844 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
845 const u8 port_cap[4],
846 const struct edid *edid)
848 if (!drm_dp_is_branch(dpcd))
851 if (dpcd[DP_DPCD_REV] < 0x11) {
852 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
853 case DP_DWN_STRM_PORT_TYPE_DP:
860 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
861 case DP_DS_PORT_TYPE_DP:
863 case DP_DS_PORT_TYPE_DP_DUALMODE:
864 if (is_edid_digital_input_dp(edid))
867 case DP_DS_PORT_TYPE_HDMI:
868 case DP_DS_PORT_TYPE_DVI:
869 case DP_DS_PORT_TYPE_VGA:
870 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
873 switch (port_cap[2] & DP_DS_MAX_BPC_MASK) {
890 EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
893 * drm_dp_downstream_420_passthrough() - determine downstream facing port
894 * YCbCr 4:2:0 pass-through capability
895 * @dpcd: DisplayPort configuration data
896 * @port_cap: downstream facing port capabilities
898 * Returns: whether the downstream facing port can pass through YCbCr 4:2:0
900 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
901 const u8 port_cap[4])
903 if (!drm_dp_is_branch(dpcd))
906 if (dpcd[DP_DPCD_REV] < 0x13)
909 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
910 case DP_DS_PORT_TYPE_DP:
912 case DP_DS_PORT_TYPE_HDMI:
913 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
916 return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH;
921 EXPORT_SYMBOL(drm_dp_downstream_420_passthrough);
924 * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port
925 * YCbCr 4:4:4->4:2:0 conversion capability
926 * @dpcd: DisplayPort configuration data
927 * @port_cap: downstream facing port capabilities
929 * Returns: whether the downstream facing port can convert YCbCr 4:4:4 to 4:2:0
931 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
932 const u8 port_cap[4])
934 if (!drm_dp_is_branch(dpcd))
937 if (dpcd[DP_DPCD_REV] < 0x13)
940 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
941 case DP_DS_PORT_TYPE_HDMI:
942 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
945 return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV;
950 EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion);
953 * drm_dp_downstream_mode() - return a mode for downstream facing port
955 * @dpcd: DisplayPort configuration data
956 * @port_cap: port capabilities
958 * Provides a suitable mode for downstream facing ports without EDID.
960 * Returns: A new drm_display_mode on success or NULL on failure
962 struct drm_display_mode *
963 drm_dp_downstream_mode(struct drm_device *dev,
964 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
965 const u8 port_cap[4])
970 if (!drm_dp_is_branch(dpcd))
973 if (dpcd[DP_DPCD_REV] < 0x11)
976 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
977 case DP_DS_PORT_TYPE_NON_EDID:
978 switch (port_cap[0] & DP_DS_NON_EDID_MASK) {
979 case DP_DS_NON_EDID_720x480i_60:
982 case DP_DS_NON_EDID_720x480i_50:
985 case DP_DS_NON_EDID_1920x1080i_60:
988 case DP_DS_NON_EDID_1920x1080i_50:
991 case DP_DS_NON_EDID_1280x720_60:
994 case DP_DS_NON_EDID_1280x720_50:
1000 return drm_display_mode_from_cea_vic(dev, vic);
1005 EXPORT_SYMBOL(drm_dp_downstream_mode);
1008 * drm_dp_downstream_id() - identify branch device
1009 * @aux: DisplayPort AUX channel
1010 * @id: DisplayPort branch device id
1012 * Returns branch device id on success or NULL on failure
1014 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
1016 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);
1018 EXPORT_SYMBOL(drm_dp_downstream_id);
1021 * drm_dp_downstream_debug() - debug DP branch devices
1022 * @m: pointer for debugfs file
1023 * @dpcd: DisplayPort configuration data
1024 * @port_cap: port capabilities
1026 * @aux: DisplayPort AUX channel
1029 void drm_dp_downstream_debug(struct seq_file *m,
1030 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1031 const u8 port_cap[4],
1032 const struct edid *edid,
1033 struct drm_dp_aux *aux)
1035 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1036 DP_DETAILED_CAP_INFO_AVAILABLE;
1042 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1043 bool branch_device = drm_dp_is_branch(dpcd);
1045 seq_printf(m, "\tDP branch device present: %s\n",
1046 branch_device ? "yes" : "no");
1052 case DP_DS_PORT_TYPE_DP:
1053 seq_puts(m, "\t\tType: DisplayPort\n");
1055 case DP_DS_PORT_TYPE_VGA:
1056 seq_puts(m, "\t\tType: VGA\n");
1058 case DP_DS_PORT_TYPE_DVI:
1059 seq_puts(m, "\t\tType: DVI\n");
1061 case DP_DS_PORT_TYPE_HDMI:
1062 seq_puts(m, "\t\tType: HDMI\n");
1064 case DP_DS_PORT_TYPE_NON_EDID:
1065 seq_puts(m, "\t\tType: others without EDID support\n");
1067 case DP_DS_PORT_TYPE_DP_DUALMODE:
1068 seq_puts(m, "\t\tType: DP++\n");
1070 case DP_DS_PORT_TYPE_WIRELESS:
1071 seq_puts(m, "\t\tType: Wireless\n");
1074 seq_puts(m, "\t\tType: N/A\n");
1077 memset(id, 0, sizeof(id));
1078 drm_dp_downstream_id(aux, id);
1079 seq_printf(m, "\t\tID: %s\n", id);
1081 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1);
1083 seq_printf(m, "\t\tHW: %d.%d\n",
1084 (rev[0] & 0xf0) >> 4, rev[0] & 0xf);
1086 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2);
1088 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
1090 if (detailed_cap_info) {
1091 clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);
1093 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
1095 clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, edid);
1097 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);
1099 clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, edid);
1101 seq_printf(m, "\t\tMin TMDS clock: %d kHz\n", clk);
1103 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid);
1106 seq_printf(m, "\t\tMax bpc: %d\n", bpc);
1109 EXPORT_SYMBOL(drm_dp_downstream_debug);
1112 * drm_dp_subconnector_type() - get DP branch device type
1113 * @dpcd: DisplayPort configuration data
1114 * @port_cap: port capabilities
1116 enum drm_mode_subconnector
1117 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1118 const u8 port_cap[4])
1121 if (!drm_dp_is_branch(dpcd))
1122 return DRM_MODE_SUBCONNECTOR_Native;
1123 /* DP 1.0 approach */
1124 if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) {
1125 type = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1126 DP_DWN_STRM_PORT_TYPE_MASK;
1129 case DP_DWN_STRM_PORT_TYPE_TMDS:
1130 /* Can be HDMI or DVI-D, DVI-D is a safer option */
1131 return DRM_MODE_SUBCONNECTOR_DVID;
1132 case DP_DWN_STRM_PORT_TYPE_ANALOG:
1133 /* Can be VGA or DVI-A, VGA is more popular */
1134 return DRM_MODE_SUBCONNECTOR_VGA;
1135 case DP_DWN_STRM_PORT_TYPE_DP:
1136 return DRM_MODE_SUBCONNECTOR_DisplayPort;
1137 case DP_DWN_STRM_PORT_TYPE_OTHER:
1139 return DRM_MODE_SUBCONNECTOR_Unknown;
1142 type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1145 case DP_DS_PORT_TYPE_DP:
1146 case DP_DS_PORT_TYPE_DP_DUALMODE:
1147 return DRM_MODE_SUBCONNECTOR_DisplayPort;
1148 case DP_DS_PORT_TYPE_VGA:
1149 return DRM_MODE_SUBCONNECTOR_VGA;
1150 case DP_DS_PORT_TYPE_DVI:
1151 return DRM_MODE_SUBCONNECTOR_DVID;
1152 case DP_DS_PORT_TYPE_HDMI:
1153 return DRM_MODE_SUBCONNECTOR_HDMIA;
1154 case DP_DS_PORT_TYPE_WIRELESS:
1155 return DRM_MODE_SUBCONNECTOR_Wireless;
1156 case DP_DS_PORT_TYPE_NON_EDID:
1158 return DRM_MODE_SUBCONNECTOR_Unknown;
1161 EXPORT_SYMBOL(drm_dp_subconnector_type);
1164 * drm_dp_set_subconnector_property - set subconnector for DP connector
1165 * @connector: connector to set property on
1166 * @status: connector status
1167 * @dpcd: DisplayPort configuration data
1168 * @port_cap: port capabilities
1170 * Called by a driver on every detect event.
1172 void drm_dp_set_subconnector_property(struct drm_connector *connector,
1173 enum drm_connector_status status,
1175 const u8 port_cap[4])
1177 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
1179 if (status == connector_status_connected)
1180 subconnector = drm_dp_subconnector_type(dpcd, port_cap);
1181 drm_object_property_set_value(&connector->base,
1182 connector->dev->mode_config.dp_subconnector_property,
1185 EXPORT_SYMBOL(drm_dp_set_subconnector_property);
1188 * drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink
1190 * @connector: The DRM connector to check
1191 * @dpcd: A cached copy of the connector's DPCD RX capabilities
1192 * @desc: A cached copy of the connector's DP descriptor
1194 * See also: drm_dp_read_sink_count()
1196 * Returns: %True if the (e)DP connector has a valid sink count that should
1197 * be probed, %false otherwise.
1199 bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
1200 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1201 const struct drm_dp_desc *desc)
1203 /* Some eDP panels don't set a valid value for the sink count */
1204 return connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
1205 dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 &&
1206 dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
1207 !drm_dp_has_quirk(desc, 0, DP_DPCD_QUIRK_NO_SINK_COUNT);
1209 EXPORT_SYMBOL(drm_dp_read_sink_count_cap);
1212 * drm_dp_read_sink_count() - Retrieve the sink count for a given sink
1213 * @aux: The DP AUX channel to use
1215 * See also: drm_dp_read_sink_count_cap()
1217 * Returns: The current sink count reported by @aux, or a negative error code
1220 int drm_dp_read_sink_count(struct drm_dp_aux *aux)
1225 ret = drm_dp_dpcd_readb(aux, DP_SINK_COUNT, &count);
1231 return DP_GET_SINK_COUNT(count);
1233 EXPORT_SYMBOL(drm_dp_read_sink_count);
1236 * I2C-over-AUX implementation
1239 static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
1241 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1242 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
1243 I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1244 I2C_FUNC_10BIT_ADDR;
1247 static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
1250 * In case of i2c defer or short i2c ack reply to a write,
1251 * we need to switch to WRITE_STATUS_UPDATE to drain the
1252 * rest of the message
1254 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
1255 msg->request &= DP_AUX_I2C_MOT;
1256 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
1260 #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */
1261 #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */
1262 #define AUX_STOP_LEN 4
1263 #define AUX_CMD_LEN 4
1264 #define AUX_ADDRESS_LEN 20
1265 #define AUX_REPLY_PAD_LEN 4
1266 #define AUX_LENGTH_LEN 8
1269 * Calculate the duration of the AUX request/reply in usec. Gives the
1270 * "best" case estimate, ie. successful while as short as possible.
1272 static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
1274 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1275 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN;
1277 if ((msg->request & DP_AUX_I2C_READ) == 0)
1278 len += msg->size * 8;
1283 static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
1285 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1286 AUX_CMD_LEN + AUX_REPLY_PAD_LEN;
1289 * For read we expect what was asked. For writes there will
1290 * be 0 or 1 data bytes. Assume 0 for the "best" case.
1292 if (msg->request & DP_AUX_I2C_READ)
1293 len += msg->size * 8;
1298 #define I2C_START_LEN 1
1299 #define I2C_STOP_LEN 1
1300 #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */
1301 #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */
1304 * Calculate the length of the i2c transfer in usec, assuming
1305 * the i2c bus speed is as specified. Gives the the "worst"
1306 * case estimate, ie. successful while as long as possible.
1307 * Doesn't account the the "MOT" bit, and instead assumes each
1308 * message includes a START, ADDRESS and STOP. Neither does it
1309 * account for additional random variables such as clock stretching.
1311 static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
1314 /* AUX bitrate is 1MHz, i2c bitrate as specified */
1315 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +
1316 msg->size * I2C_DATA_LEN +
1317 I2C_STOP_LEN) * 1000, i2c_speed_khz);
1321 * Deterine how many retries should be attempted to successfully transfer
1322 * the specified message, based on the estimated durations of the
1323 * i2c and AUX transfers.
1325 static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
1328 int aux_time_us = drm_dp_aux_req_duration(msg) +
1329 drm_dp_aux_reply_duration(msg);
1330 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);
1332 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);
1336 * FIXME currently assumes 10 kHz as some real world devices seem
1337 * to require it. We should query/set the speed via DPCD if supported.
1339 static int dp_aux_i2c_speed_khz __read_mostly = 10;
1340 module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
1341 MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
1342 "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
1345 * Transfer a single I2C-over-AUX message and handle various error conditions,
1346 * retrying the transaction as appropriate. It is assumed that the
1347 * &drm_dp_aux.transfer function does not modify anything in the msg other than the
1350 * Returns bytes transferred on success, or a negative error code on failure.
1352 static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1354 unsigned int retry, defer_i2c;
1357 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
1358 * is required to retry at least seven times upon receiving AUX_DEFER
1359 * before giving up the AUX transaction.
1361 * We also try to account for the i2c bus speed.
1363 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz));
1365 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
1366 ret = aux->transfer(aux, msg);
1372 * While timeouts can be errors, they're usually normal
1373 * behavior (for instance, when a driver tries to
1374 * communicate with a non-existant DisplayPort device).
1375 * Avoid spamming the kernel log with timeout errors.
1377 if (ret == -ETIMEDOUT)
1378 DRM_DEBUG_KMS_RATELIMITED("%s: transaction timed out\n",
1381 DRM_DEBUG_KMS("%s: transaction failed: %d\n",
1387 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
1388 case DP_AUX_NATIVE_REPLY_ACK:
1390 * For I2C-over-AUX transactions this isn't enough, we
1391 * need to check for the I2C ACK reply.
1395 case DP_AUX_NATIVE_REPLY_NACK:
1396 DRM_DEBUG_KMS("%s: native nack (result=%d, size=%zu)\n",
1397 aux->name, ret, msg->size);
1400 case DP_AUX_NATIVE_REPLY_DEFER:
1401 DRM_DEBUG_KMS("%s: native defer\n", aux->name);
1403 * We could check for I2C bit rate capabilities and if
1404 * available adjust this interval. We could also be
1405 * more careful with DP-to-legacy adapters where a
1406 * long legacy cable may force very low I2C bit rates.
1408 * For now just defer for long enough to hopefully be
1409 * safe for all use-cases.
1411 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
1415 DRM_ERROR("%s: invalid native reply %#04x\n",
1416 aux->name, msg->reply);
1420 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
1421 case DP_AUX_I2C_REPLY_ACK:
1423 * Both native ACK and I2C ACK replies received. We
1424 * can assume the transfer was successful.
1426 if (ret != msg->size)
1427 drm_dp_i2c_msg_write_status_update(msg);
1430 case DP_AUX_I2C_REPLY_NACK:
1431 DRM_DEBUG_KMS("%s: I2C nack (result=%d, size=%zu)\n",
1432 aux->name, ret, msg->size);
1433 aux->i2c_nack_count++;
1436 case DP_AUX_I2C_REPLY_DEFER:
1437 DRM_DEBUG_KMS("%s: I2C defer\n", aux->name);
1438 /* DP Compliance Test 4.2.2.5 Requirement:
1439 * Must have at least 7 retries for I2C defers on the
1440 * transaction to pass this test
1442 aux->i2c_defer_count++;
1445 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
1446 drm_dp_i2c_msg_write_status_update(msg);
1451 DRM_ERROR("%s: invalid I2C reply %#04x\n",
1452 aux->name, msg->reply);
1457 DRM_DEBUG_KMS("%s: Too many retries, giving up\n", aux->name);
1461 static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
1462 const struct i2c_msg *i2c_msg)
1464 msg->request = (i2c_msg->flags & I2C_M_RD) ?
1465 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
1466 if (!(i2c_msg->flags & I2C_M_STOP))
1467 msg->request |= DP_AUX_I2C_MOT;
1471 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
1473 * Returns an error code on failure, or a recommended transfer size on success.
1475 static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
1477 int err, ret = orig_msg->size;
1478 struct drm_dp_aux_msg msg = *orig_msg;
1480 while (msg.size > 0) {
1481 err = drm_dp_i2c_do_msg(aux, &msg);
1483 return err == 0 ? -EPROTO : err;
1485 if (err < msg.size && err < ret) {
1486 DRM_DEBUG_KMS("%s: Partial I2C reply: requested %zu bytes got %d bytes\n",
1487 aux->name, msg.size, err);
1499 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
1500 * packets to be as large as possible. If not, the I2C transactions never
1501 * succeed. Hence the default is maximum.
1503 static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES;
1504 module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
1505 MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
1506 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
1508 static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
1511 struct drm_dp_aux *aux = adapter->algo_data;
1513 unsigned transfer_size;
1514 struct drm_dp_aux_msg msg;
1517 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
1519 memset(&msg, 0, sizeof(msg));
1521 for (i = 0; i < num; i++) {
1522 msg.address = msgs[i].addr;
1523 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1524 /* Send a bare address packet to start the transaction.
1525 * Zero sized messages specify an address only (bare
1526 * address) transaction.
1530 err = drm_dp_i2c_do_msg(aux, &msg);
1533 * Reset msg.request in case in case it got
1534 * changed into a WRITE_STATUS_UPDATE.
1536 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1540 /* We want each transaction to be as large as possible, but
1541 * we'll go to smaller sizes if the hardware gives us a
1544 transfer_size = dp_aux_i2c_transfer_size;
1545 for (j = 0; j < msgs[i].len; j += msg.size) {
1546 msg.buffer = msgs[i].buf + j;
1547 msg.size = min(transfer_size, msgs[i].len - j);
1549 err = drm_dp_i2c_drain_msg(aux, &msg);
1552 * Reset msg.request in case in case it got
1553 * changed into a WRITE_STATUS_UPDATE.
1555 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1559 transfer_size = err;
1566 /* Send a bare address packet to close out the transaction.
1567 * Zero sized messages specify an address only (bare
1568 * address) transaction.
1570 msg.request &= ~DP_AUX_I2C_MOT;
1573 (void)drm_dp_i2c_do_msg(aux, &msg);
1578 static const struct i2c_algorithm drm_dp_i2c_algo = {
1579 .functionality = drm_dp_i2c_functionality,
1580 .master_xfer = drm_dp_i2c_xfer,
1583 static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c)
1585 return container_of(i2c, struct drm_dp_aux, ddc);
1588 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
1590 mutex_lock(&i2c_to_aux(i2c)->hw_mutex);
1593 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
1595 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex);
1598 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
1600 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex);
1603 static const struct i2c_lock_operations drm_dp_i2c_lock_ops = {
1604 .lock_bus = lock_bus,
1605 .trylock_bus = trylock_bus,
1606 .unlock_bus = unlock_bus,
1609 static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)
1614 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1618 WARN_ON(!(buf & DP_TEST_SINK_START));
1620 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf);
1624 count = buf & DP_TEST_COUNT_MASK;
1625 if (count == aux->crc_count)
1626 return -EAGAIN; /* No CRC yet */
1628 aux->crc_count = count;
1631 * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes
1632 * per component (RGB or CrYCb).
1634 ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6);
1641 static void drm_dp_aux_crc_work(struct work_struct *work)
1643 struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux,
1645 struct drm_crtc *crtc;
1650 if (WARN_ON(!aux->crtc))
1654 while (crtc->crc.opened) {
1655 drm_crtc_wait_one_vblank(crtc);
1656 if (!crtc->crc.opened)
1659 ret = drm_dp_aux_get_crc(aux, crc_bytes);
1660 if (ret == -EAGAIN) {
1661 usleep_range(1000, 2000);
1662 ret = drm_dp_aux_get_crc(aux, crc_bytes);
1665 if (ret == -EAGAIN) {
1666 DRM_DEBUG_KMS("%s: Get CRC failed after retrying: %d\n",
1670 DRM_DEBUG_KMS("%s: Failed to get a CRC: %d\n",
1675 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8;
1676 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8;
1677 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8;
1678 drm_crtc_add_crc_entry(crtc, false, 0, crcs);
1683 * drm_dp_remote_aux_init() - minimally initialise a remote aux channel
1684 * @aux: DisplayPort AUX channel
1686 * Used for remote aux channel in general. Merely initialize the crc work
1689 void drm_dp_remote_aux_init(struct drm_dp_aux *aux)
1691 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
1693 EXPORT_SYMBOL(drm_dp_remote_aux_init);
1696 * drm_dp_aux_init() - minimally initialise an aux channel
1697 * @aux: DisplayPort AUX channel
1699 * If you need to use the drm_dp_aux's i2c adapter prior to registering it
1700 * with the outside world, call drm_dp_aux_init() first. You must still
1701 * call drm_dp_aux_register() once the connector has been registered to
1702 * allow userspace access to the auxiliary DP channel.
1704 void drm_dp_aux_init(struct drm_dp_aux *aux)
1706 mutex_init(&aux->hw_mutex);
1707 mutex_init(&aux->cec.lock);
1708 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
1710 aux->ddc.algo = &drm_dp_i2c_algo;
1711 aux->ddc.algo_data = aux;
1712 aux->ddc.retries = 3;
1714 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops;
1716 EXPORT_SYMBOL(drm_dp_aux_init);
1719 * drm_dp_aux_register() - initialise and register aux channel
1720 * @aux: DisplayPort AUX channel
1722 * Automatically calls drm_dp_aux_init() if this hasn't been done yet.
1723 * This should only be called when the underlying &struct drm_connector is
1724 * initialiazed already. Therefore the best place to call this is from
1725 * &drm_connector_funcs.late_register. Not that drivers which don't follow this
1726 * will Oops when CONFIG_DRM_DP_AUX_CHARDEV is enabled.
1728 * Drivers which need to use the aux channel before that point (e.g. at driver
1729 * load time, before drm_dev_register() has been called) need to call
1730 * drm_dp_aux_init().
1732 * Returns 0 on success or a negative error code on failure.
1734 int drm_dp_aux_register(struct drm_dp_aux *aux)
1739 drm_dp_aux_init(aux);
1741 aux->ddc.class = I2C_CLASS_DDC;
1742 aux->ddc.owner = THIS_MODULE;
1743 aux->ddc.dev.parent = aux->dev;
1745 strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
1746 sizeof(aux->ddc.name));
1748 ret = drm_dp_aux_register_devnode(aux);
1752 ret = i2c_add_adapter(&aux->ddc);
1754 drm_dp_aux_unregister_devnode(aux);
1760 EXPORT_SYMBOL(drm_dp_aux_register);
1763 * drm_dp_aux_unregister() - unregister an AUX adapter
1764 * @aux: DisplayPort AUX channel
1766 void drm_dp_aux_unregister(struct drm_dp_aux *aux)
1768 drm_dp_aux_unregister_devnode(aux);
1769 i2c_del_adapter(&aux->ddc);
1771 EXPORT_SYMBOL(drm_dp_aux_unregister);
1773 #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
1776 * drm_dp_psr_setup_time() - PSR setup in time usec
1777 * @psr_cap: PSR capabilities from DPCD
1780 * PSR setup time for the panel in microseconds, negative
1781 * error code on failure.
1783 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
1785 static const u16 psr_setup_time_us[] = {
1786 PSR_SETUP_TIME(330),
1787 PSR_SETUP_TIME(275),
1788 PSR_SETUP_TIME(220),
1789 PSR_SETUP_TIME(165),
1790 PSR_SETUP_TIME(110),
1796 i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
1797 if (i >= ARRAY_SIZE(psr_setup_time_us))
1800 return psr_setup_time_us[i];
1802 EXPORT_SYMBOL(drm_dp_psr_setup_time);
1804 #undef PSR_SETUP_TIME
1807 * drm_dp_start_crc() - start capture of frame CRCs
1808 * @aux: DisplayPort AUX channel
1809 * @crtc: CRTC displaying the frames whose CRCs are to be captured
1811 * Returns 0 on success or a negative error code on failure.
1813 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
1818 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1822 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START);
1828 schedule_work(&aux->crc_work);
1832 EXPORT_SYMBOL(drm_dp_start_crc);
1835 * drm_dp_stop_crc() - stop capture of frame CRCs
1836 * @aux: DisplayPort AUX channel
1838 * Returns 0 on success or a negative error code on failure.
1840 int drm_dp_stop_crc(struct drm_dp_aux *aux)
1845 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1849 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START);
1853 flush_work(&aux->crc_work);
1858 EXPORT_SYMBOL(drm_dp_stop_crc);
1867 #define OUI(first, second, third) { (first), (second), (third) }
1868 #define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
1869 { (first), (second), (third), (fourth), (fifth), (sixth) }
1871 #define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0)
1873 static const struct dpcd_quirk dpcd_quirk_list[] = {
1874 /* Analogix 7737 needs reduced M and N at HBR2 link rates */
1875 { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
1876 /* LG LP140WF6-SPM1 eDP panel */
1877 { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
1878 /* Apple panels need some additional handling to support PSR */
1879 { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
1880 /* CH7511 seems to leave SINK_COUNT zeroed */
1881 { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
1882 /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
1883 { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
1884 /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
1885 { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
1891 * Get a bit mask of DPCD quirks for the sink/branch device identified by
1892 * ident. The quirk data is shared but it's up to the drivers to act on the
1895 * For now, only the OUI (first three bytes) is used, but this may be extended
1896 * to device identification string and hardware/firmware revisions later.
1899 drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
1901 const struct dpcd_quirk *quirk;
1904 u8 any_device[] = DEVICE_ID_ANY;
1906 for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
1907 quirk = &dpcd_quirk_list[i];
1909 if (quirk->is_branch != is_branch)
1912 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
1915 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 &&
1916 memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0)
1919 quirks |= quirk->quirks;
1925 #undef DEVICE_ID_ANY
1934 #define MFG(first, second) { (first), (second) }
1935 #define PROD_ID(first, second) { (first), (second) }
1938 * Some devices have unreliable OUIDs where they don't set the device ID
1939 * correctly, and as a result we need to use the EDID for finding additional
1940 * DP quirks in such cases.
1942 static const struct edid_quirk edid_quirk_list[] = {
1943 /* Optional 4K AMOLED panel in the ThinkPad X1 Extreme 2nd Generation
1944 * only supports DPCD backlight controls
1946 { MFG(0x4c, 0x83), PROD_ID(0x41, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
1948 * Some Dell CML 2020 systems have panels support both AUX and PWM
1949 * backlight control, and some only support AUX backlight control. All
1950 * said panels start up in AUX mode by default, and we don't have any
1951 * support for disabling HDR mode on these panels which would be
1952 * required to switch to PWM backlight control mode (plus, I'm not
1953 * even sure we want PWM backlight controls over DPCD backlight
1954 * controls anyway...). Until we have a better way of detecting these,
1955 * force DPCD backlight mode on all of them.
1957 { MFG(0x06, 0xaf), PROD_ID(0x9b, 0x32), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
1958 { MFG(0x06, 0xaf), PROD_ID(0xeb, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
1959 { MFG(0x4d, 0x10), PROD_ID(0xc7, 0x14), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
1960 { MFG(0x4d, 0x10), PROD_ID(0xe6, 0x14), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
1961 { MFG(0x4c, 0x83), PROD_ID(0x47, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
1962 { MFG(0x09, 0xe5), PROD_ID(0xde, 0x08), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) },
1969 * drm_dp_get_edid_quirks() - Check the EDID of a DP device to find additional
1970 * DP-specific quirks
1971 * @edid: The EDID to check
1973 * While OUIDs are meant to be used to recognize a DisplayPort device, a lot
1974 * of manufacturers don't seem to like following standards and neglect to fill
1975 * the dev-ID in, making it impossible to only use OUIDs for determining
1976 * quirks in some cases. This function can be used to check the EDID and look
1977 * up any additional DP quirks. The bits returned by this function correspond
1978 * to the quirk bits in &drm_dp_quirk.
1980 * Returns: a bitmask of quirks, if any. The driver can check this using
1981 * drm_dp_has_quirk().
1983 u32 drm_dp_get_edid_quirks(const struct edid *edid)
1985 const struct edid_quirk *quirk;
1992 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1993 quirk = &edid_quirk_list[i];
1994 if (memcmp(quirk->mfg_id, edid->mfg_id,
1995 sizeof(edid->mfg_id)) == 0 &&
1996 memcmp(quirk->prod_id, edid->prod_code,
1997 sizeof(edid->prod_code)) == 0)
1998 quirks |= quirk->quirks;
2001 DRM_DEBUG_KMS("DP sink: EDID mfg %*phD prod-ID %*phD quirks: 0x%04x\n",
2002 (int)sizeof(edid->mfg_id), edid->mfg_id,
2003 (int)sizeof(edid->prod_code), edid->prod_code, quirks);
2007 EXPORT_SYMBOL(drm_dp_get_edid_quirks);
2010 * drm_dp_read_desc - read sink/branch descriptor from DPCD
2011 * @aux: DisplayPort AUX channel
2012 * @desc: Device descriptor to fill from DPCD
2013 * @is_branch: true for branch devices, false for sink devices
2015 * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
2018 * Returns 0 on success or a negative error code on failure.
2020 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
2023 struct drm_dp_dpcd_ident *ident = &desc->ident;
2024 unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
2025 int ret, dev_id_len;
2027 ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident));
2031 desc->quirks = drm_dp_get_quirks(ident, is_branch);
2033 dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
2035 DRM_DEBUG_KMS("%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",
2036 aux->name, is_branch ? "branch" : "sink",
2037 (int)sizeof(ident->oui), ident->oui,
2038 dev_id_len, ident->device_id,
2039 ident->hw_rev >> 4, ident->hw_rev & 0xf,
2040 ident->sw_major_rev, ident->sw_minor_rev,
2045 EXPORT_SYMBOL(drm_dp_read_desc);
2048 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
2049 * supported by the DSC sink.
2050 * @dsc_dpcd: DSC capabilities from DPCD
2051 * @is_edp: true if its eDP, false for DP
2053 * Read the slice capabilities DPCD register from DSC sink to get
2054 * the maximum slice count supported. This is used to populate
2055 * the DSC parameters in the &struct drm_dsc_config by the driver.
2056 * Driver creates an infoframe using these parameters to populate
2057 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2058 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2061 * Maximum slice count supported by DSC sink or 0 its invalid
2063 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2066 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
2069 /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */
2070 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2072 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2074 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2077 /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
2078 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
2080 if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
2082 if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
2084 if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
2086 if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
2088 if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
2090 if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
2092 if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
2094 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2096 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2098 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2104 EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
2107 * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
2108 * @dsc_dpcd: DSC capabilities from DPCD
2110 * Read the DSC DPCD register to parse the line buffer depth in bits which is
2111 * number of bits of precision within the decoder line buffer supported by
2112 * the DSC sink. This is used to populate the DSC parameters in the
2113 * &struct drm_dsc_config by the driver.
2114 * Driver creates an infoframe using these parameters to populate
2115 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2116 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2119 * Line buffer depth supported by DSC panel or 0 its invalid
2121 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
2123 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT];
2125 switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
2126 case DP_DSC_LINE_BUF_BIT_DEPTH_9:
2128 case DP_DSC_LINE_BUF_BIT_DEPTH_10:
2130 case DP_DSC_LINE_BUF_BIT_DEPTH_11:
2132 case DP_DSC_LINE_BUF_BIT_DEPTH_12:
2134 case DP_DSC_LINE_BUF_BIT_DEPTH_13:
2136 case DP_DSC_LINE_BUF_BIT_DEPTH_14:
2138 case DP_DSC_LINE_BUF_BIT_DEPTH_15:
2140 case DP_DSC_LINE_BUF_BIT_DEPTH_16:
2142 case DP_DSC_LINE_BUF_BIT_DEPTH_8:
2148 EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
2151 * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
2152 * values supported by the DSC sink.
2153 * @dsc_dpcd: DSC capabilities from DPCD
2154 * @dsc_bpc: An array to be filled by this helper with supported
2157 * Read the DSC DPCD from the sink device to parse the supported bits per
2158 * component values. This is used to populate the DSC parameters
2159 * in the &struct drm_dsc_config by the driver.
2160 * Driver creates an infoframe using these parameters to populate
2161 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2162 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2165 * Number of input BPC values parsed from the DPCD
2167 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2171 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
2173 if (color_depth & DP_DSC_12_BPC)
2174 dsc_bpc[num_bpc++] = 12;
2175 if (color_depth & DP_DSC_10_BPC)
2176 dsc_bpc[num_bpc++] = 10;
2177 if (color_depth & DP_DSC_8_BPC)
2178 dsc_bpc[num_bpc++] = 8;
2182 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
2185 * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
2186 * @aux: DisplayPort AUX channel
2187 * @caps: buffer to return the capability info in
2189 * Read capabilities common to all LTTPRs.
2191 * Returns 0 on success or a negative error code on failure.
2193 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
2194 u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2198 ret = drm_dp_dpcd_read(aux,
2199 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
2200 caps, DP_LTTPR_COMMON_CAP_SIZE);
2204 WARN_ON(ret != DP_LTTPR_COMMON_CAP_SIZE);
2208 EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
2211 * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
2212 * @aux: DisplayPort AUX channel
2213 * @dp_phy: LTTPR PHY to read the capabilities for
2214 * @caps: buffer to return the capability info in
2216 * Read the capabilities for the given LTTPR PHY.
2218 * Returns 0 on success or a negative error code on failure.
2220 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
2221 enum drm_dp_phy dp_phy,
2222 u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2226 ret = drm_dp_dpcd_read(aux,
2227 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
2228 caps, DP_LTTPR_PHY_CAP_SIZE);
2232 WARN_ON(ret != DP_LTTPR_PHY_CAP_SIZE);
2236 EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);
2238 static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r)
2240 return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
2244 * drm_dp_lttpr_count - get the number of detected LTTPRs
2245 * @caps: LTTPR common capabilities
2247 * Get the number of detected LTTPRs from the LTTPR common capabilities info.
2250 * -ERANGE if more than supported number (8) of LTTPRs are detected
2251 * -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value
2252 * otherwise the number of detected LTTPRs
2254 int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2256 u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT);
2258 switch (hweight8(count)) {
2262 return 8 - ilog2(count);
2269 EXPORT_SYMBOL(drm_dp_lttpr_count);
2272 * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs
2273 * @caps: LTTPR common capabilities
2275 * Returns the maximum link rate supported by all detected LTTPRs.
2277 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2279 u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER);
2281 return drm_dp_bw_code_to_link_rate(rate);
2283 EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate);
2286 * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs
2287 * @caps: LTTPR common capabilities
2289 * Returns the maximum lane count supported by all detected LTTPRs.
2291 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2293 u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER);
2295 return max_lanes & DP_MAX_LANE_COUNT_MASK;
2297 EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count);
2300 * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support
2301 * @caps: LTTPR PHY capabilities
2303 * Returns true if the @caps for an LTTPR TX PHY indicate support for
2304 * voltage swing level 3.
2307 drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2309 u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
2311 return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED;
2313 EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported);
2316 * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support
2317 * @caps: LTTPR PHY capabilities
2319 * Returns true if the @caps for an LTTPR TX PHY indicate support for
2320 * pre-emphasis level 3.
2323 drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2325 u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
2327 return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED;
2329 EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported);
2332 * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
2333 * @aux: DisplayPort AUX channel
2334 * @data: DP phy compliance test parameters.
2336 * Returns 0 on success or a negative error code on failure.
2338 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
2339 struct drm_dp_phy_test_params *data)
2344 err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
2347 data->link_rate = drm_dp_bw_code_to_link_rate(rate);
2349 err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
2352 data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
2354 if (lanes & DP_ENHANCED_FRAME_CAP)
2355 data->enhanced_frame_cap = true;
2357 err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
2361 switch (data->phy_pattern) {
2362 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
2363 err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2364 &data->custom80, sizeof(data->custom80));
2369 case DP_PHY_TEST_PATTERN_CP2520:
2370 err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
2372 sizeof(data->hbr2_reset));
2379 EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
2382 * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
2383 * @aux: DisplayPort AUX channel
2384 * @data: DP phy compliance test parameters.
2385 * @dp_rev: DP revision to use for compliance testing
2387 * Returns 0 on success or a negative error code on failure.
2389 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
2390 struct drm_dp_phy_test_params *data, u8 dp_rev)
2396 link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
2397 link_config[1] = data->num_lanes;
2398 if (data->enhanced_frame_cap)
2399 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2400 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
2404 test_pattern = data->phy_pattern;
2405 if (dp_rev < 0x12) {
2406 test_pattern = (test_pattern << 2) &
2407 DP_LINK_QUAL_PATTERN_11_MASK;
2408 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
2413 for (i = 0; i < data->num_lanes; i++) {
2414 err = drm_dp_dpcd_writeb(aux,
2415 DP_LINK_QUAL_LANE0_SET + i,
2424 EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
2426 static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat)
2428 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
2431 switch (pixelformat) {
2432 case DP_PIXELFORMAT_RGB:
2434 case DP_PIXELFORMAT_YUV444:
2436 case DP_PIXELFORMAT_YUV422:
2438 case DP_PIXELFORMAT_YUV420:
2440 case DP_PIXELFORMAT_Y_ONLY:
2442 case DP_PIXELFORMAT_RAW:
2449 static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat,
2450 enum dp_colorimetry colorimetry)
2452 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
2455 switch (colorimetry) {
2456 case DP_COLORIMETRY_DEFAULT:
2457 switch (pixelformat) {
2458 case DP_PIXELFORMAT_RGB:
2460 case DP_PIXELFORMAT_YUV444:
2461 case DP_PIXELFORMAT_YUV422:
2462 case DP_PIXELFORMAT_YUV420:
2464 case DP_PIXELFORMAT_Y_ONLY:
2465 return "DICOM PS3.14";
2466 case DP_PIXELFORMAT_RAW:
2467 return "Custom Color Profile";
2471 case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
2472 switch (pixelformat) {
2473 case DP_PIXELFORMAT_RGB:
2474 return "Wide Fixed";
2475 case DP_PIXELFORMAT_YUV444:
2476 case DP_PIXELFORMAT_YUV422:
2477 case DP_PIXELFORMAT_YUV420:
2482 case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
2483 switch (pixelformat) {
2484 case DP_PIXELFORMAT_RGB:
2485 return "Wide Float";
2486 case DP_PIXELFORMAT_YUV444:
2487 case DP_PIXELFORMAT_YUV422:
2488 case DP_PIXELFORMAT_YUV420:
2493 case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
2494 switch (pixelformat) {
2495 case DP_PIXELFORMAT_RGB:
2497 case DP_PIXELFORMAT_YUV444:
2498 case DP_PIXELFORMAT_YUV422:
2499 case DP_PIXELFORMAT_YUV420:
2504 case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
2505 switch (pixelformat) {
2506 case DP_PIXELFORMAT_RGB:
2508 case DP_PIXELFORMAT_YUV444:
2509 case DP_PIXELFORMAT_YUV422:
2510 case DP_PIXELFORMAT_YUV420:
2515 case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
2516 switch (pixelformat) {
2517 case DP_PIXELFORMAT_RGB:
2518 return "Custom Profile";
2519 case DP_PIXELFORMAT_YUV444:
2520 case DP_PIXELFORMAT_YUV422:
2521 case DP_PIXELFORMAT_YUV420:
2526 case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
2527 switch (pixelformat) {
2528 case DP_PIXELFORMAT_RGB:
2529 return "BT.2020 RGB";
2530 case DP_PIXELFORMAT_YUV444:
2531 case DP_PIXELFORMAT_YUV422:
2532 case DP_PIXELFORMAT_YUV420:
2533 return "BT.2020 CYCC";
2537 case DP_COLORIMETRY_BT2020_YCC:
2538 switch (pixelformat) {
2539 case DP_PIXELFORMAT_YUV444:
2540 case DP_PIXELFORMAT_YUV422:
2541 case DP_PIXELFORMAT_YUV420:
2542 return "BT.2020 YCC";
2551 static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)
2553 switch (dynamic_range) {
2554 case DP_DYNAMIC_RANGE_VESA:
2555 return "VESA range";
2556 case DP_DYNAMIC_RANGE_CTA:
2563 static const char *dp_content_type_get_name(enum dp_content_type content_type)
2565 switch (content_type) {
2566 case DP_CONTENT_TYPE_NOT_DEFINED:
2567 return "Not defined";
2568 case DP_CONTENT_TYPE_GRAPHICS:
2570 case DP_CONTENT_TYPE_PHOTO:
2572 case DP_CONTENT_TYPE_VIDEO:
2574 case DP_CONTENT_TYPE_GAME:
2581 void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
2582 const struct drm_dp_vsc_sdp *vsc)
2584 #define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__)
2585 DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
2586 vsc->revision, vsc->length);
2587 DP_SDP_LOG(" pixelformat: %s\n",
2588 dp_pixelformat_get_name(vsc->pixelformat));
2589 DP_SDP_LOG(" colorimetry: %s\n",
2590 dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry));
2591 DP_SDP_LOG(" bpc: %u\n", vsc->bpc);
2592 DP_SDP_LOG(" dynamic range: %s\n",
2593 dp_dynamic_range_get_name(vsc->dynamic_range));
2594 DP_SDP_LOG(" content type: %s\n",
2595 dp_content_type_get_name(vsc->content_type));
2598 EXPORT_SYMBOL(drm_dp_vsc_sdp_log);