2 * Copyright © 2009 Keith Packard
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
23 #include <linux/delay.h>
24 #include <linux/errno.h>
25 #include <linux/i2c.h>
26 #include <linux/init.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/sched.h>
30 #include <linux/seq_file.h>
32 #include <drm/drm_dp_helper.h>
33 #include <drm/drm_print.h>
34 #include <drm/drm_vblank.h>
36 #include "drm_crtc_helper_internal.h"
41 * These functions contain some common logic and helpers at various abstraction
42 * levels to deal with Display Port sink devices and related things like DP aux
43 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
47 /* Helpers for DP link training */
48 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
50 return link_status[r - DP_LANE0_1_STATUS];
53 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
56 int i = DP_LANE0_1_STATUS + (lane >> 1);
57 int s = (lane & 1) * 4;
58 u8 l = dp_link_status(link_status, i);
59 return (l >> s) & 0xf;
62 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
69 lane_align = dp_link_status(link_status,
70 DP_LANE_ALIGN_STATUS_UPDATED);
71 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
73 for (lane = 0; lane < lane_count; lane++) {
74 lane_status = dp_get_lane_status(link_status, lane);
75 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
80 EXPORT_SYMBOL(drm_dp_channel_eq_ok);
82 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
88 for (lane = 0; lane < lane_count; lane++) {
89 lane_status = dp_get_lane_status(link_status, lane);
90 if ((lane_status & DP_LANE_CR_DONE) == 0)
95 EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
97 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
100 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
101 int s = ((lane & 1) ?
102 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
103 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
104 u8 l = dp_link_status(link_status, i);
106 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
108 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
110 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
113 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
114 int s = ((lane & 1) ?
115 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
116 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
117 u8 l = dp_link_status(link_status, i);
119 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
121 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
123 u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
126 unsigned int offset = DP_ADJUST_REQUEST_POST_CURSOR2;
127 u8 value = dp_link_status(link_status, offset);
129 return (value >> (lane << 1)) & 0x3;
131 EXPORT_SYMBOL(drm_dp_get_adjust_request_post_cursor);
133 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
135 unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
136 DP_TRAINING_AUX_RD_MASK;
139 DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",
142 if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
145 rd_interval *= 4 * USEC_PER_MSEC;
147 usleep_range(rd_interval, rd_interval * 2);
149 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
151 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
153 unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
154 DP_TRAINING_AUX_RD_MASK;
157 DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",
160 if (rd_interval == 0)
163 rd_interval *= 4 * USEC_PER_MSEC;
165 usleep_range(rd_interval, rd_interval * 2);
167 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
169 u8 drm_dp_link_rate_to_bw_code(int link_rate)
171 /* Spec says link_bw = link_rate / 0.27Gbps */
172 return link_rate / 27000;
174 EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
176 int drm_dp_bw_code_to_link_rate(u8 link_bw)
178 /* Spec says link_rate = link_bw * 0.27Gbps */
179 return link_bw * 27000;
181 EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
183 #define AUX_RETRY_INTERVAL 500 /* us */
186 drm_dp_dump_access(const struct drm_dp_aux *aux,
187 u8 request, uint offset, void *buffer, int ret)
189 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-";
192 DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
193 aux->name, offset, arrow, ret, min(ret, 20), buffer);
195 DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d)\n",
196 aux->name, offset, arrow, ret);
202 * The DisplayPort AUX channel is an abstraction to allow generic, driver-
203 * independent access to AUX functionality. Drivers can take advantage of
204 * this by filling in the fields of the drm_dp_aux structure.
206 * Transactions are described using a hardware-independent drm_dp_aux_msg
207 * structure, which is passed into a driver's .transfer() implementation.
208 * Both native and I2C-over-AUX transactions are supported.
211 static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
212 unsigned int offset, void *buffer, size_t size)
214 struct drm_dp_aux_msg msg;
215 unsigned int retry, native_reply;
216 int err = 0, ret = 0;
218 memset(&msg, 0, sizeof(msg));
219 msg.address = offset;
220 msg.request = request;
224 mutex_lock(&aux->hw_mutex);
227 * The specification doesn't give any recommendation on how often to
228 * retry native transactions. We used to retry 7 times like for
229 * aux i2c transactions but real world devices this wasn't
230 * sufficient, bump to 32 which makes Dell 4k monitors happier.
232 for (retry = 0; retry < 32; retry++) {
233 if (ret != 0 && ret != -ETIMEDOUT) {
234 usleep_range(AUX_RETRY_INTERVAL,
235 AUX_RETRY_INTERVAL + 100);
238 ret = aux->transfer(aux, &msg);
240 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK;
241 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) {
251 * We want the error we return to be the error we received on
252 * the first transaction, since we may get a different error the
259 DRM_DEBUG_KMS("Too many retries, giving up. First error: %d\n", err);
263 mutex_unlock(&aux->hw_mutex);
268 * drm_dp_dpcd_read() - read a series of bytes from the DPCD
269 * @aux: DisplayPort AUX channel
270 * @offset: address of the (first) register to read
271 * @buffer: buffer to store the register values
272 * @size: number of bytes in @buffer
274 * Returns the number of bytes transferred on success, or a negative error
275 * code on failure. -EIO is returned if the request was NAKed by the sink or
276 * if the retry count was exceeded. If not all bytes were transferred, this
277 * function returns -EPROTO. Errors from the underlying AUX channel transfer
278 * function, with the exception of -EBUSY (which causes the transaction to
279 * be retried), are propagated to the caller.
281 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
282 void *buffer, size_t size)
287 * HP ZR24w corrupts the first DPCD access after entering power save
288 * mode. Eg. on a read, the entire buffer will be filled with the same
289 * byte. Do a throw away read to avoid corrupting anything we care
290 * about. Afterwards things will work correctly until the monitor
291 * gets woken up and subsequently re-enters power save mode.
293 * The user pressing any button on the monitor is enough to wake it
294 * up, so there is no particularly good place to do the workaround.
295 * We just have to do it before any DPCD access and hope that the
296 * monitor doesn't power down exactly after the throw away read.
298 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV, buffer,
303 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, buffer,
307 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret);
310 EXPORT_SYMBOL(drm_dp_dpcd_read);
313 * drm_dp_dpcd_write() - write a series of bytes to the DPCD
314 * @aux: DisplayPort AUX channel
315 * @offset: address of the (first) register to write
316 * @buffer: buffer containing the values to write
317 * @size: number of bytes in @buffer
319 * Returns the number of bytes transferred on success, or a negative error
320 * code on failure. -EIO is returned if the request was NAKed by the sink or
321 * if the retry count was exceeded. If not all bytes were transferred, this
322 * function returns -EPROTO. Errors from the underlying AUX channel transfer
323 * function, with the exception of -EBUSY (which causes the transaction to
324 * be retried), are propagated to the caller.
326 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
327 void *buffer, size_t size)
331 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer,
333 drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
336 EXPORT_SYMBOL(drm_dp_dpcd_write);
339 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
340 * @aux: DisplayPort AUX channel
341 * @status: buffer to store the link status in (must be at least 6 bytes)
343 * Returns the number of bytes transferred on success or a negative error
346 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
347 u8 status[DP_LINK_STATUS_SIZE])
349 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
350 DP_LINK_STATUS_SIZE);
352 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
355 * drm_dp_send_real_edid_checksum() - send back real edid checksum value
356 * @aux: DisplayPort AUX channel
357 * @real_edid_checksum: real edid checksum for the last block
362 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
363 u8 real_edid_checksum)
365 u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;
367 if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
368 &auto_test_req, 1) < 1) {
369 DRM_ERROR("DPCD failed read at register 0x%x\n",
370 DP_DEVICE_SERVICE_IRQ_VECTOR);
373 auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
375 if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1) < 1) {
376 DRM_ERROR("DPCD failed read at register 0x%x\n",
380 link_edid_read &= DP_TEST_LINK_EDID_READ;
382 if (!auto_test_req || !link_edid_read) {
383 DRM_DEBUG_KMS("Source DUT does not support TEST_EDID_READ\n");
387 if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
388 &auto_test_req, 1) < 1) {
389 DRM_ERROR("DPCD failed write at register 0x%x\n",
390 DP_DEVICE_SERVICE_IRQ_VECTOR);
394 /* send back checksum for the last edid extension block data */
395 if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM,
396 &real_edid_checksum, 1) < 1) {
397 DRM_ERROR("DPCD failed write at register 0x%x\n",
398 DP_TEST_EDID_CHECKSUM);
402 test_resp |= DP_TEST_EDID_CHECKSUM_WRITE;
403 if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) {
404 DRM_ERROR("DPCD failed write at register 0x%x\n",
411 EXPORT_SYMBOL(drm_dp_send_real_edid_checksum);
414 * drm_dp_downstream_max_clock() - extract branch device max
415 * pixel rate for legacy VGA
416 * converter or max TMDS clock
418 * @dpcd: DisplayPort configuration data
419 * @port_cap: port capabilities
421 * Returns max clock in kHz on success or 0 if max clock not defined
423 int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
424 const u8 port_cap[4])
426 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
427 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
428 DP_DETAILED_CAP_INFO_AVAILABLE;
430 if (!detailed_cap_info)
434 case DP_DS_PORT_TYPE_VGA:
435 return port_cap[1] * 8 * 1000;
436 case DP_DS_PORT_TYPE_DVI:
437 case DP_DS_PORT_TYPE_HDMI:
438 case DP_DS_PORT_TYPE_DP_DUALMODE:
439 return port_cap[1] * 2500;
444 EXPORT_SYMBOL(drm_dp_downstream_max_clock);
447 * drm_dp_downstream_max_bpc() - extract branch device max
449 * @dpcd: DisplayPort configuration data
450 * @port_cap: port capabilities
452 * Returns max bpc on success or 0 if max bpc not defined
454 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
455 const u8 port_cap[4])
457 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
458 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
459 DP_DETAILED_CAP_INFO_AVAILABLE;
462 if (!detailed_cap_info)
466 case DP_DS_PORT_TYPE_VGA:
467 case DP_DS_PORT_TYPE_DVI:
468 case DP_DS_PORT_TYPE_HDMI:
469 case DP_DS_PORT_TYPE_DP_DUALMODE:
470 bpc = port_cap[2] & DP_DS_MAX_BPC_MASK;
487 EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
490 * drm_dp_downstream_id() - identify branch device
491 * @aux: DisplayPort AUX channel
492 * @id: DisplayPort branch device id
494 * Returns branch device id on success or NULL on failure
496 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
498 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);
500 EXPORT_SYMBOL(drm_dp_downstream_id);
503 * drm_dp_downstream_debug() - debug DP branch devices
504 * @m: pointer for debugfs file
505 * @dpcd: DisplayPort configuration data
506 * @port_cap: port capabilities
507 * @aux: DisplayPort AUX channel
510 void drm_dp_downstream_debug(struct seq_file *m,
511 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
512 const u8 port_cap[4], struct drm_dp_aux *aux)
514 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
515 DP_DETAILED_CAP_INFO_AVAILABLE;
521 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
522 bool branch_device = drm_dp_is_branch(dpcd);
524 seq_printf(m, "\tDP branch device present: %s\n",
525 branch_device ? "yes" : "no");
531 case DP_DS_PORT_TYPE_DP:
532 seq_puts(m, "\t\tType: DisplayPort\n");
534 case DP_DS_PORT_TYPE_VGA:
535 seq_puts(m, "\t\tType: VGA\n");
537 case DP_DS_PORT_TYPE_DVI:
538 seq_puts(m, "\t\tType: DVI\n");
540 case DP_DS_PORT_TYPE_HDMI:
541 seq_puts(m, "\t\tType: HDMI\n");
543 case DP_DS_PORT_TYPE_NON_EDID:
544 seq_puts(m, "\t\tType: others without EDID support\n");
546 case DP_DS_PORT_TYPE_DP_DUALMODE:
547 seq_puts(m, "\t\tType: DP++\n");
549 case DP_DS_PORT_TYPE_WIRELESS:
550 seq_puts(m, "\t\tType: Wireless\n");
553 seq_puts(m, "\t\tType: N/A\n");
556 memset(id, 0, sizeof(id));
557 drm_dp_downstream_id(aux, id);
558 seq_printf(m, "\t\tID: %s\n", id);
560 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1);
562 seq_printf(m, "\t\tHW: %d.%d\n",
563 (rev[0] & 0xf0) >> 4, rev[0] & 0xf);
565 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2);
567 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
569 if (detailed_cap_info) {
570 clk = drm_dp_downstream_max_clock(dpcd, port_cap);
573 if (type == DP_DS_PORT_TYPE_VGA)
574 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
576 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);
579 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap);
582 seq_printf(m, "\t\tMax bpc: %d\n", bpc);
585 EXPORT_SYMBOL(drm_dp_downstream_debug);
588 * I2C-over-AUX implementation
591 static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
593 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
594 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
595 I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
599 static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
602 * In case of i2c defer or short i2c ack reply to a write,
603 * we need to switch to WRITE_STATUS_UPDATE to drain the
604 * rest of the message
606 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
607 msg->request &= DP_AUX_I2C_MOT;
608 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
612 #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */
613 #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */
614 #define AUX_STOP_LEN 4
615 #define AUX_CMD_LEN 4
616 #define AUX_ADDRESS_LEN 20
617 #define AUX_REPLY_PAD_LEN 4
618 #define AUX_LENGTH_LEN 8
621 * Calculate the duration of the AUX request/reply in usec. Gives the
622 * "best" case estimate, ie. successful while as short as possible.
624 static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
626 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
627 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN;
629 if ((msg->request & DP_AUX_I2C_READ) == 0)
630 len += msg->size * 8;
635 static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
637 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
638 AUX_CMD_LEN + AUX_REPLY_PAD_LEN;
641 * For read we expect what was asked. For writes there will
642 * be 0 or 1 data bytes. Assume 0 for the "best" case.
644 if (msg->request & DP_AUX_I2C_READ)
645 len += msg->size * 8;
650 #define I2C_START_LEN 1
651 #define I2C_STOP_LEN 1
652 #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */
653 #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */
656 * Calculate the length of the i2c transfer in usec, assuming
657 * the i2c bus speed is as specified. Gives the the "worst"
658 * case estimate, ie. successful while as long as possible.
659 * Doesn't account the the "MOT" bit, and instead assumes each
660 * message includes a START, ADDRESS and STOP. Neither does it
661 * account for additional random variables such as clock stretching.
663 static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
666 /* AUX bitrate is 1MHz, i2c bitrate as specified */
667 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +
668 msg->size * I2C_DATA_LEN +
669 I2C_STOP_LEN) * 1000, i2c_speed_khz);
673 * Deterine how many retries should be attempted to successfully transfer
674 * the specified message, based on the estimated durations of the
675 * i2c and AUX transfers.
677 static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
680 int aux_time_us = drm_dp_aux_req_duration(msg) +
681 drm_dp_aux_reply_duration(msg);
682 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);
684 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);
688 * FIXME currently assumes 10 kHz as some real world devices seem
689 * to require it. We should query/set the speed via DPCD if supported.
691 static int dp_aux_i2c_speed_khz __read_mostly = 10;
692 module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
693 MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
694 "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
697 * Transfer a single I2C-over-AUX message and handle various error conditions,
698 * retrying the transaction as appropriate. It is assumed that the
699 * &drm_dp_aux.transfer function does not modify anything in the msg other than the
702 * Returns bytes transferred on success, or a negative error code on failure.
704 static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
706 unsigned int retry, defer_i2c;
709 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
710 * is required to retry at least seven times upon receiving AUX_DEFER
711 * before giving up the AUX transaction.
713 * We also try to account for the i2c bus speed.
715 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz));
717 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
718 ret = aux->transfer(aux, msg);
724 * While timeouts can be errors, they're usually normal
725 * behavior (for instance, when a driver tries to
726 * communicate with a non-existant DisplayPort device).
727 * Avoid spamming the kernel log with timeout errors.
729 if (ret == -ETIMEDOUT)
730 DRM_DEBUG_KMS_RATELIMITED("transaction timed out\n");
732 DRM_DEBUG_KMS("transaction failed: %d\n", ret);
738 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
739 case DP_AUX_NATIVE_REPLY_ACK:
741 * For I2C-over-AUX transactions this isn't enough, we
742 * need to check for the I2C ACK reply.
746 case DP_AUX_NATIVE_REPLY_NACK:
747 DRM_DEBUG_KMS("native nack (result=%d, size=%zu)\n", ret, msg->size);
750 case DP_AUX_NATIVE_REPLY_DEFER:
751 DRM_DEBUG_KMS("native defer\n");
753 * We could check for I2C bit rate capabilities and if
754 * available adjust this interval. We could also be
755 * more careful with DP-to-legacy adapters where a
756 * long legacy cable may force very low I2C bit rates.
758 * For now just defer for long enough to hopefully be
759 * safe for all use-cases.
761 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
765 DRM_ERROR("invalid native reply %#04x\n", msg->reply);
769 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
770 case DP_AUX_I2C_REPLY_ACK:
772 * Both native ACK and I2C ACK replies received. We
773 * can assume the transfer was successful.
775 if (ret != msg->size)
776 drm_dp_i2c_msg_write_status_update(msg);
779 case DP_AUX_I2C_REPLY_NACK:
780 DRM_DEBUG_KMS("I2C nack (result=%d, size=%zu)\n",
782 aux->i2c_nack_count++;
785 case DP_AUX_I2C_REPLY_DEFER:
786 DRM_DEBUG_KMS("I2C defer\n");
787 /* DP Compliance Test 4.2.2.5 Requirement:
788 * Must have at least 7 retries for I2C defers on the
789 * transaction to pass this test
791 aux->i2c_defer_count++;
794 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
795 drm_dp_i2c_msg_write_status_update(msg);
800 DRM_ERROR("invalid I2C reply %#04x\n", msg->reply);
805 DRM_DEBUG_KMS("too many retries, giving up\n");
809 static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
810 const struct i2c_msg *i2c_msg)
812 msg->request = (i2c_msg->flags & I2C_M_RD) ?
813 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
814 if (!(i2c_msg->flags & I2C_M_STOP))
815 msg->request |= DP_AUX_I2C_MOT;
819 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
821 * Returns an error code on failure, or a recommended transfer size on success.
823 static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
825 int err, ret = orig_msg->size;
826 struct drm_dp_aux_msg msg = *orig_msg;
828 while (msg.size > 0) {
829 err = drm_dp_i2c_do_msg(aux, &msg);
831 return err == 0 ? -EPROTO : err;
833 if (err < msg.size && err < ret) {
834 DRM_DEBUG_KMS("Partial I2C reply: requested %zu bytes got %d bytes\n",
847 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
848 * packets to be as large as possible. If not, the I2C transactions never
849 * succeed. Hence the default is maximum.
851 static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES;
852 module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
853 MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
854 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
856 static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
859 struct drm_dp_aux *aux = adapter->algo_data;
861 unsigned transfer_size;
862 struct drm_dp_aux_msg msg;
865 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
867 memset(&msg, 0, sizeof(msg));
869 for (i = 0; i < num; i++) {
870 msg.address = msgs[i].addr;
871 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
872 /* Send a bare address packet to start the transaction.
873 * Zero sized messages specify an address only (bare
874 * address) transaction.
878 err = drm_dp_i2c_do_msg(aux, &msg);
881 * Reset msg.request in case in case it got
882 * changed into a WRITE_STATUS_UPDATE.
884 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
888 /* We want each transaction to be as large as possible, but
889 * we'll go to smaller sizes if the hardware gives us a
892 transfer_size = dp_aux_i2c_transfer_size;
893 for (j = 0; j < msgs[i].len; j += msg.size) {
894 msg.buffer = msgs[i].buf + j;
895 msg.size = min(transfer_size, msgs[i].len - j);
897 err = drm_dp_i2c_drain_msg(aux, &msg);
900 * Reset msg.request in case in case it got
901 * changed into a WRITE_STATUS_UPDATE.
903 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
914 /* Send a bare address packet to close out the transaction.
915 * Zero sized messages specify an address only (bare
916 * address) transaction.
918 msg.request &= ~DP_AUX_I2C_MOT;
921 (void)drm_dp_i2c_do_msg(aux, &msg);
926 static const struct i2c_algorithm drm_dp_i2c_algo = {
927 .functionality = drm_dp_i2c_functionality,
928 .master_xfer = drm_dp_i2c_xfer,
931 static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c)
933 return container_of(i2c, struct drm_dp_aux, ddc);
936 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
938 mutex_lock(&i2c_to_aux(i2c)->hw_mutex);
941 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
943 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex);
946 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
948 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex);
951 static const struct i2c_lock_operations drm_dp_i2c_lock_ops = {
952 .lock_bus = lock_bus,
953 .trylock_bus = trylock_bus,
954 .unlock_bus = unlock_bus,
957 static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)
962 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
966 WARN_ON(!(buf & DP_TEST_SINK_START));
968 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf);
972 count = buf & DP_TEST_COUNT_MASK;
973 if (count == aux->crc_count)
974 return -EAGAIN; /* No CRC yet */
976 aux->crc_count = count;
979 * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes
980 * per component (RGB or CrYCb).
982 ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6);
989 static void drm_dp_aux_crc_work(struct work_struct *work)
991 struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux,
993 struct drm_crtc *crtc;
998 if (WARN_ON(!aux->crtc))
1002 while (crtc->crc.opened) {
1003 drm_crtc_wait_one_vblank(crtc);
1004 if (!crtc->crc.opened)
1007 ret = drm_dp_aux_get_crc(aux, crc_bytes);
1008 if (ret == -EAGAIN) {
1009 usleep_range(1000, 2000);
1010 ret = drm_dp_aux_get_crc(aux, crc_bytes);
1013 if (ret == -EAGAIN) {
1014 DRM_DEBUG_KMS("Get CRC failed after retrying: %d\n",
1018 DRM_DEBUG_KMS("Failed to get a CRC: %d\n", ret);
1022 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8;
1023 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8;
1024 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8;
1025 drm_crtc_add_crc_entry(crtc, false, 0, crcs);
1030 * drm_dp_aux_init() - minimally initialise an aux channel
1031 * @aux: DisplayPort AUX channel
1033 * If you need to use the drm_dp_aux's i2c adapter prior to registering it
1034 * with the outside world, call drm_dp_aux_init() first. You must still
1035 * call drm_dp_aux_register() once the connector has been registered to
1036 * allow userspace access to the auxiliary DP channel.
1038 void drm_dp_aux_init(struct drm_dp_aux *aux)
1040 mutex_init(&aux->hw_mutex);
1041 mutex_init(&aux->cec.lock);
1042 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
1044 aux->ddc.algo = &drm_dp_i2c_algo;
1045 aux->ddc.algo_data = aux;
1046 aux->ddc.retries = 3;
1048 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops;
1050 EXPORT_SYMBOL(drm_dp_aux_init);
1053 * drm_dp_aux_register() - initialise and register aux channel
1054 * @aux: DisplayPort AUX channel
1056 * Automatically calls drm_dp_aux_init() if this hasn't been done yet.
1057 * This should only be called when the underlying &struct drm_connector is
1058 * initialiazed already. Therefore the best place to call this is from
1059 * &drm_connector_funcs.late_register. Not that drivers which don't follow this
1060 * will Oops when CONFIG_DRM_DP_AUX_CHARDEV is enabled.
1062 * Drivers which need to use the aux channel before that point (e.g. at driver
1063 * load time, before drm_dev_register() has been called) need to call
1064 * drm_dp_aux_init().
1066 * Returns 0 on success or a negative error code on failure.
1068 int drm_dp_aux_register(struct drm_dp_aux *aux)
1073 drm_dp_aux_init(aux);
1075 aux->ddc.class = I2C_CLASS_DDC;
1076 aux->ddc.owner = THIS_MODULE;
1077 aux->ddc.dev.parent = aux->dev;
1079 strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
1080 sizeof(aux->ddc.name));
1082 ret = drm_dp_aux_register_devnode(aux);
1086 ret = i2c_add_adapter(&aux->ddc);
1088 drm_dp_aux_unregister_devnode(aux);
1094 EXPORT_SYMBOL(drm_dp_aux_register);
1097 * drm_dp_aux_unregister() - unregister an AUX adapter
1098 * @aux: DisplayPort AUX channel
1100 void drm_dp_aux_unregister(struct drm_dp_aux *aux)
1102 drm_dp_aux_unregister_devnode(aux);
1103 i2c_del_adapter(&aux->ddc);
1105 EXPORT_SYMBOL(drm_dp_aux_unregister);
1107 #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
1110 * drm_dp_psr_setup_time() - PSR setup in time usec
1111 * @psr_cap: PSR capabilities from DPCD
1114 * PSR setup time for the panel in microseconds, negative
1115 * error code on failure.
1117 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
1119 static const u16 psr_setup_time_us[] = {
1120 PSR_SETUP_TIME(330),
1121 PSR_SETUP_TIME(275),
1122 PSR_SETUP_TIME(220),
1123 PSR_SETUP_TIME(165),
1124 PSR_SETUP_TIME(110),
1130 i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
1131 if (i >= ARRAY_SIZE(psr_setup_time_us))
1134 return psr_setup_time_us[i];
1136 EXPORT_SYMBOL(drm_dp_psr_setup_time);
1138 #undef PSR_SETUP_TIME
1141 * drm_dp_start_crc() - start capture of frame CRCs
1142 * @aux: DisplayPort AUX channel
1143 * @crtc: CRTC displaying the frames whose CRCs are to be captured
1145 * Returns 0 on success or a negative error code on failure.
1147 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
1152 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1156 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START);
1162 schedule_work(&aux->crc_work);
1166 EXPORT_SYMBOL(drm_dp_start_crc);
1169 * drm_dp_stop_crc() - stop capture of frame CRCs
1170 * @aux: DisplayPort AUX channel
1172 * Returns 0 on success or a negative error code on failure.
1174 int drm_dp_stop_crc(struct drm_dp_aux *aux)
1179 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1183 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START);
1187 flush_work(&aux->crc_work);
1192 EXPORT_SYMBOL(drm_dp_stop_crc);
1201 #define OUI(first, second, third) { (first), (second), (third) }
1202 #define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
1203 { (first), (second), (third), (fourth), (fifth), (sixth) }
1205 #define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0)
1207 static const struct dpcd_quirk dpcd_quirk_list[] = {
1208 /* Analogix 7737 needs reduced M and N at HBR2 link rates */
1209 { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
1210 /* LG LP140WF6-SPM1 eDP panel */
1211 { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
1212 /* Apple panels need some additional handling to support PSR */
1213 { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
1214 /* CH7511 seems to leave SINK_COUNT zeroed */
1215 { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
1221 * Get a bit mask of DPCD quirks for the sink/branch device identified by
1222 * ident. The quirk data is shared but it's up to the drivers to act on the
1225 * For now, only the OUI (first three bytes) is used, but this may be extended
1226 * to device identification string and hardware/firmware revisions later.
1229 drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
1231 const struct dpcd_quirk *quirk;
1234 u8 any_device[] = DEVICE_ID_ANY;
1236 for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
1237 quirk = &dpcd_quirk_list[i];
1239 if (quirk->is_branch != is_branch)
1242 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
1245 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 &&
1246 memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0)
1249 quirks |= quirk->quirks;
1255 #undef DEVICE_ID_ANY
1259 * drm_dp_read_desc - read sink/branch descriptor from DPCD
1260 * @aux: DisplayPort AUX channel
1261 * @desc: Device decriptor to fill from DPCD
1262 * @is_branch: true for branch devices, false for sink devices
1264 * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
1267 * Returns 0 on success or a negative error code on failure.
1269 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
1272 struct drm_dp_dpcd_ident *ident = &desc->ident;
1273 unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
1274 int ret, dev_id_len;
1276 ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident));
1280 desc->quirks = drm_dp_get_quirks(ident, is_branch);
1282 dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
1284 DRM_DEBUG_KMS("DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",
1285 is_branch ? "branch" : "sink",
1286 (int)sizeof(ident->oui), ident->oui,
1287 dev_id_len, ident->device_id,
1288 ident->hw_rev >> 4, ident->hw_rev & 0xf,
1289 ident->sw_major_rev, ident->sw_minor_rev,
1294 EXPORT_SYMBOL(drm_dp_read_desc);
1297 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
1298 * supported by the DSC sink.
1299 * @dsc_dpcd: DSC capabilities from DPCD
1300 * @is_edp: true if its eDP, false for DP
1302 * Read the slice capabilities DPCD register from DSC sink to get
1303 * the maximum slice count supported. This is used to populate
1304 * the DSC parameters in the &struct drm_dsc_config by the driver.
1305 * Driver creates an infoframe using these parameters to populate
1306 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
1307 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
1310 * Maximum slice count supported by DSC sink or 0 its invalid
1312 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
1315 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
1318 /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */
1319 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
1321 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
1323 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
1326 /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
1327 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
1329 if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
1331 if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
1333 if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
1335 if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
1337 if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
1339 if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
1341 if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
1343 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
1345 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
1347 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
1353 EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
1356 * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
1357 * @dsc_dpcd: DSC capabilities from DPCD
1359 * Read the DSC DPCD register to parse the line buffer depth in bits which is
1360 * number of bits of precision within the decoder line buffer supported by
1361 * the DSC sink. This is used to populate the DSC parameters in the
1362 * &struct drm_dsc_config by the driver.
1363 * Driver creates an infoframe using these parameters to populate
1364 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
1365 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
1368 * Line buffer depth supported by DSC panel or 0 its invalid
1370 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1372 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT];
1374 switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
1375 case DP_DSC_LINE_BUF_BIT_DEPTH_9:
1377 case DP_DSC_LINE_BUF_BIT_DEPTH_10:
1379 case DP_DSC_LINE_BUF_BIT_DEPTH_11:
1381 case DP_DSC_LINE_BUF_BIT_DEPTH_12:
1383 case DP_DSC_LINE_BUF_BIT_DEPTH_13:
1385 case DP_DSC_LINE_BUF_BIT_DEPTH_14:
1387 case DP_DSC_LINE_BUF_BIT_DEPTH_15:
1389 case DP_DSC_LINE_BUF_BIT_DEPTH_16:
1391 case DP_DSC_LINE_BUF_BIT_DEPTH_8:
1397 EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
1400 * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
1401 * values supported by the DSC sink.
1402 * @dsc_dpcd: DSC capabilities from DPCD
1403 * @dsc_bpc: An array to be filled by this helper with supported
1406 * Read the DSC DPCD from the sink device to parse the supported bits per
1407 * component values. This is used to populate the DSC parameters
1408 * in the &struct drm_dsc_config by the driver.
1409 * Driver creates an infoframe using these parameters to populate
1410 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
1411 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
1414 * Number of input BPC values parsed from the DPCD
1416 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
1420 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
1422 if (color_depth & DP_DSC_12_BPC)
1423 dsc_bpc[num_bpc++] = 12;
1424 if (color_depth & DP_DSC_10_BPC)
1425 dsc_bpc[num_bpc++] = 10;
1426 if (color_depth & DP_DSC_8_BPC)
1427 dsc_bpc[num_bpc++] = 8;
1431 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);