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21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/i2c.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <drm/display/drm_scdc_helper.h>
29 #include <drm/drm_print.h>
34 * Status and Control Data Channel (SCDC) is a mechanism introduced by the
35 * HDMI 2.0 specification. It is a point-to-point protocol that allows the
36 * HDMI source and HDMI sink to exchange data. The same I2C interface that
37 * is used to access EDID serves as the transport mechanism for SCDC.
40 #define SCDC_I2C_SLAVE_ADDRESS 0x54
43 * drm_scdc_read - read a block of data from SCDC
44 * @adapter: I2C controller
45 * @offset: start offset of block to read
46 * @buffer: return location for the block to read
47 * @size: size of the block to read
49 * Reads a block of data from SCDC, starting at a given offset.
52 * 0 on success, negative error code on failure.
54 ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer,
58 struct i2c_msg msgs[2] = {
60 .addr = SCDC_I2C_SLAVE_ADDRESS,
65 .addr = SCDC_I2C_SLAVE_ADDRESS,
72 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
75 if (ret != ARRAY_SIZE(msgs))
80 EXPORT_SYMBOL(drm_scdc_read);
83 * drm_scdc_write - write a block of data to SCDC
84 * @adapter: I2C controller
85 * @offset: start offset of block to write
86 * @buffer: block of data to write
87 * @size: size of the block to write
89 * Writes a block of data to SCDC, starting at a given offset.
92 * 0 on success, negative error code on failure.
94 ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset,
95 const void *buffer, size_t size)
97 struct i2c_msg msg = {
98 .addr = SCDC_I2C_SLAVE_ADDRESS,
106 data = kmalloc(1 + size, GFP_KERNEL);
112 memcpy(data, &offset, sizeof(offset));
113 memcpy(data + 1, buffer, size);
115 err = i2c_transfer(adapter, &msg, 1);
126 EXPORT_SYMBOL(drm_scdc_write);
129 * drm_scdc_get_scrambling_status - what is status of scrambling?
130 * @adapter: I2C adapter for DDC channel
132 * Reads the scrambler status over SCDC, and checks the
136 * True if the scrambling is enabled, false otherwise.
138 bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter)
143 ret = drm_scdc_readb(adapter, SCDC_SCRAMBLER_STATUS, &status);
145 DRM_DEBUG_KMS("Failed to read scrambling status: %d\n", ret);
149 return status & SCDC_SCRAMBLING_STATUS;
151 EXPORT_SYMBOL(drm_scdc_get_scrambling_status);
154 * drm_scdc_set_scrambling - enable scrambling
155 * @adapter: I2C adapter for DDC channel
156 * @enable: bool to indicate if scrambling is to be enabled/disabled
158 * Writes the TMDS config register over SCDC channel, and:
159 * enables scrambling when enable = 1
160 * disables scrambling when enable = 0
163 * True if scrambling is set/reset successfully, false otherwise.
165 bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable)
170 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
172 DRM_DEBUG_KMS("Failed to read TMDS config: %d\n", ret);
177 config |= SCDC_SCRAMBLING_ENABLE;
179 config &= ~SCDC_SCRAMBLING_ENABLE;
181 ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
183 DRM_DEBUG_KMS("Failed to enable scrambling: %d\n", ret);
189 EXPORT_SYMBOL(drm_scdc_set_scrambling);
192 * drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio
193 * @adapter: I2C adapter for DDC channel
194 * @set: ret or reset the high clock ratio
197 * TMDS clock ratio calculations go like this:
198 * TMDS character = 10 bit TMDS encoded value
200 * TMDS character rate = The rate at which TMDS characters are
203 * TMDS bit rate = 10x TMDS character rate
206 * TMDS clock rate for pixel clock < 340 MHz = 1x the character
207 * rate = 1/10 pixel clock rate
209 * TMDS clock rate for pixel clock > 340 MHz = 0.25x the character
210 * rate = 1/40 pixel clock rate
212 * Writes to the TMDS config register over SCDC channel, and:
213 * sets TMDS clock ratio to 1/40 when set = 1
215 * sets TMDS clock ratio to 1/10 when set = 0
218 * True if write is successful, false otherwise.
220 bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set)
225 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
227 DRM_DEBUG_KMS("Failed to read TMDS config: %d\n", ret);
232 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
234 config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
236 ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config);
238 DRM_DEBUG_KMS("Failed to set TMDS clock ratio: %d\n", ret);
243 * The spec says that a source should wait minimum 1ms and maximum
244 * 100ms after writing the TMDS config for clock ratio. Lets allow a
245 * wait of up to 2ms here.
247 usleep_range(1000, 2000);
250 EXPORT_SYMBOL(drm_scdc_set_high_tmds_clock_ratio);