1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
7 #include <linux/atomic.h>
8 #include <linux/auxiliary_bus.h>
9 #include <linux/bitfield.h>
10 #include <linux/bits.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/i2c.h>
16 #include <linux/iopoll.h>
17 #include <linux/module.h>
18 #include <linux/of_graph.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/pwm.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
24 #include <asm/unaligned.h>
26 #include <drm/display/drm_dp_aux_bus.h>
27 #include <drm/display/drm_dp_helper.h>
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_bridge.h>
31 #include <drm/drm_bridge_connector.h>
32 #include <drm/drm_edid.h>
33 #include <drm/drm_mipi_dsi.h>
34 #include <drm/drm_of.h>
35 #include <drm/drm_panel.h>
36 #include <drm/drm_print.h>
37 #include <drm/drm_probe_helper.h>
39 #define SN_DEVICE_REV_REG 0x08
40 #define SN_DPPLL_SRC_REG 0x0A
41 #define DPPLL_CLK_SRC_DSICLK BIT(0)
42 #define REFCLK_FREQ_MASK GENMASK(3, 1)
43 #define REFCLK_FREQ(x) ((x) << 1)
44 #define DPPLL_SRC_DP_PLL_LOCK BIT(7)
45 #define SN_PLL_ENABLE_REG 0x0D
46 #define SN_DSI_LANES_REG 0x10
47 #define CHA_DSI_LANES_MASK GENMASK(4, 3)
48 #define CHA_DSI_LANES(x) ((x) << 3)
49 #define SN_DSIA_CLK_FREQ_REG 0x12
50 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20
51 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
52 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C
53 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D
54 #define CHA_HSYNC_POLARITY BIT(7)
55 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30
56 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31
57 #define CHA_VSYNC_POLARITY BIT(7)
58 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34
59 #define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36
60 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38
61 #define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A
62 #define SN_LN_ASSIGN_REG 0x59
63 #define LN_ASSIGN_WIDTH 2
64 #define SN_ENH_FRAME_REG 0x5A
65 #define VSTREAM_ENABLE BIT(3)
66 #define LN_POLRS_OFFSET 4
67 #define LN_POLRS_MASK 0xf0
68 #define SN_DATA_FORMAT_REG 0x5B
69 #define BPP_18_RGB BIT(0)
70 #define SN_HPD_DISABLE_REG 0x5C
71 #define HPD_DISABLE BIT(0)
72 #define HPD_DEBOUNCED_STATE BIT(4)
73 #define SN_GPIO_IO_REG 0x5E
74 #define SN_GPIO_INPUT_SHIFT 4
75 #define SN_GPIO_OUTPUT_SHIFT 0
76 #define SN_GPIO_CTRL_REG 0x5F
77 #define SN_GPIO_MUX_INPUT 0
78 #define SN_GPIO_MUX_OUTPUT 1
79 #define SN_GPIO_MUX_SPECIAL 2
80 #define SN_GPIO_MUX_MASK 0x3
81 #define SN_AUX_WDATA_REG(x) (0x64 + (x))
82 #define SN_AUX_ADDR_19_16_REG 0x74
83 #define SN_AUX_ADDR_15_8_REG 0x75
84 #define SN_AUX_ADDR_7_0_REG 0x76
85 #define SN_AUX_ADDR_MASK GENMASK(19, 0)
86 #define SN_AUX_LENGTH_REG 0x77
87 #define SN_AUX_CMD_REG 0x78
88 #define AUX_CMD_SEND BIT(0)
89 #define AUX_CMD_REQ(x) ((x) << 4)
90 #define SN_AUX_RDATA_REG(x) (0x79 + (x))
91 #define SN_SSC_CONFIG_REG 0x93
92 #define DP_NUM_LANES_MASK GENMASK(5, 4)
93 #define DP_NUM_LANES(x) ((x) << 4)
94 #define SN_DATARATE_CONFIG_REG 0x94
95 #define DP_DATARATE_MASK GENMASK(7, 5)
96 #define DP_DATARATE(x) ((x) << 5)
97 #define SN_TRAINING_SETTING_REG 0x95
98 #define SCRAMBLE_DISABLE BIT(4)
99 #define SN_ML_TX_MODE_REG 0x96
100 #define ML_TX_MAIN_LINK_OFF 0
101 #define ML_TX_NORMAL_MODE BIT(0)
102 #define SN_PWM_PRE_DIV_REG 0xA0
103 #define SN_BACKLIGHT_SCALE_REG 0xA1
104 #define BACKLIGHT_SCALE_MAX 0xFFFF
105 #define SN_BACKLIGHT_REG 0xA3
106 #define SN_PWM_EN_INV_REG 0xA5
107 #define SN_PWM_INV_MASK BIT(0)
108 #define SN_PWM_EN_MASK BIT(1)
109 #define SN_AUX_CMD_STATUS_REG 0xF4
110 #define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3)
111 #define AUX_IRQ_STATUS_AUX_SHORT BIT(5)
112 #define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6)
114 #define MIN_DSI_CLK_FREQ_MHZ 40
116 /* fudge factor required to account for 8b/10b encoding */
117 #define DP_CLK_FUDGE_NUM 10
118 #define DP_CLK_FUDGE_DEN 8
120 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
121 #define SN_AUX_MAX_PAYLOAD_BYTES 16
123 #define SN_REGULATOR_SUPPLY_NUM 4
125 #define SN_MAX_DP_LANES 4
126 #define SN_NUM_GPIOS 4
127 #define SN_GPIO_PHYSICAL_OFFSET 1
129 #define SN_LINK_TRAINING_TRIES 10
131 #define SN_PWM_GPIO_IDX 3 /* 4th GPIO */
134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
138 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
140 * @dev: Pointer to the top level (i2c) device.
141 * @regmap: Regmap for accessing i2c.
142 * @aux: Our aux channel.
143 * @bridge: Our bridge.
144 * @connector: Our connector.
145 * @host_node: Remote DSI node.
146 * @dsi: Our MIPI DSI source.
147 * @refclk: Our reference clock.
148 * @next_bridge: The bridge on the eDP side.
149 * @enable_gpio: The GPIO we toggle to enable the bridge.
150 * @supplies: Data for bulk enabling/disabling our regulators.
151 * @dp_lanes: Count of dp_lanes we're using.
152 * @ln_assign: Value to program to the LN_ASSIGN register.
153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
154 * @comms_enabled: If true then communication over the aux channel is enabled.
155 * @comms_mutex: Protects modification of comms_enabled.
157 * @gchip: If we expose our GPIOs, this is used.
158 * @gchip_output: A cache of whether we've set GPIOs to output. This
159 * serves double-duty of keeping track of the direction and
160 * also keeping track of whether we've incremented the
161 * pm_runtime reference count for this pin, which we do
162 * whenever a pin is configured as an output. This is a
163 * bitmap so we can do atomic ops on it without an extra
164 * lock so concurrent users of our 4 GPIOs don't stomp on
165 * each other's read-modify-write.
167 * @pchip: pwm_chip if the PWM is exposed.
168 * @pwm_enabled: Used to track if the PWM signal is currently enabled.
169 * @pwm_pin_busy: Track if GPIO4 is currently requested for GPIO or PWM.
170 * @pwm_refclk_freq: Cache for the reference clock input to the PWM.
172 struct ti_sn65dsi86 {
173 struct auxiliary_device *bridge_aux;
174 struct auxiliary_device *gpio_aux;
175 struct auxiliary_device *aux_aux;
176 struct auxiliary_device *pwm_aux;
179 struct regmap *regmap;
180 struct drm_dp_aux aux;
181 struct drm_bridge bridge;
182 struct drm_connector *connector;
183 struct device_node *host_node;
184 struct mipi_dsi_device *dsi;
186 struct drm_bridge *next_bridge;
187 struct gpio_desc *enable_gpio;
188 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM];
193 struct mutex comms_mutex;
195 #if defined(CONFIG_OF_GPIO)
196 struct gpio_chip gchip;
197 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS);
199 #if defined(CONFIG_PWM)
200 struct pwm_chip pchip;
202 atomic_t pwm_pin_busy;
204 unsigned int pwm_refclk_freq;
207 static const struct regmap_range ti_sn65dsi86_volatile_ranges[] = {
208 { .range_min = 0, .range_max = 0xFF },
211 static const struct regmap_access_table ti_sn_bridge_volatile_table = {
212 .yes_ranges = ti_sn65dsi86_volatile_ranges,
213 .n_yes_ranges = ARRAY_SIZE(ti_sn65dsi86_volatile_ranges),
216 static const struct regmap_config ti_sn65dsi86_regmap_config = {
219 .volatile_table = &ti_sn_bridge_volatile_table,
220 .cache_type = REGCACHE_NONE,
221 .max_register = 0xFF,
224 static int __maybe_unused ti_sn65dsi86_read_u16(struct ti_sn65dsi86 *pdata,
225 unsigned int reg, u16 *val)
230 ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
234 *val = buf[0] | (buf[1] << 8);
239 static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata,
240 unsigned int reg, u16 val)
242 u8 buf[2] = { val & 0xff, val >> 8 };
244 regmap_bulk_write(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
247 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata)
249 u32 bit_rate_khz, clk_freq_khz;
250 struct drm_display_mode *mode =
251 &pdata->bridge.encoder->crtc->state->adjusted_mode;
253 bit_rate_khz = mode->clock *
254 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
255 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
260 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
261 static const u32 ti_sn_bridge_refclk_lut[] = {
269 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
270 static const u32 ti_sn_bridge_dsiclk_lut[] = {
278 static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata)
282 const u32 *refclk_lut;
283 size_t refclk_lut_size;
286 refclk_rate = clk_get_rate(pdata->refclk);
287 refclk_lut = ti_sn_bridge_refclk_lut;
288 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
289 clk_prepare_enable(pdata->refclk);
291 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
292 refclk_lut = ti_sn_bridge_dsiclk_lut;
293 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
296 /* for i equals to refclk_lut_size means default frequency */
297 for (i = 0; i < refclk_lut_size; i++)
298 if (refclk_lut[i] == refclk_rate)
301 /* avoid buffer overflow and "1" is the default rate in the datasheet. */
302 if (i >= refclk_lut_size)
305 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
309 * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG,
310 * regardless of its actual sourcing.
312 pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i];
315 static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata)
317 mutex_lock(&pdata->comms_mutex);
319 /* configure bridge ref_clk */
320 ti_sn_bridge_set_refclk_freq(pdata);
323 * HPD on this bridge chip is a bit useless. This is an eDP bridge
324 * so the HPD is an internal signal that's only there to signal that
325 * the panel is done powering up. ...but the bridge chip debounces
326 * this signal by between 100 ms and 400 ms (depending on process,
327 * voltage, and temperate--I measured it at about 200 ms). One
328 * particular panel asserted HPD 84 ms after it was powered on meaning
329 * that we saw HPD 284 ms after power on. ...but the same panel said
330 * that instead of looking at HPD you could just hardcode a delay of
331 * 200 ms. We'll assume that the panel driver will have the hardcoded
332 * delay in its prepare and always disable HPD.
334 * If HPD somehow makes sense on some future panel we'll have to
335 * change this to be conditional on someone specifying that HPD should
338 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
341 pdata->comms_enabled = true;
343 mutex_unlock(&pdata->comms_mutex);
346 static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 *pdata)
348 mutex_lock(&pdata->comms_mutex);
350 pdata->comms_enabled = false;
351 clk_disable_unprepare(pdata->refclk);
353 mutex_unlock(&pdata->comms_mutex);
356 static int __maybe_unused ti_sn65dsi86_resume(struct device *dev)
358 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
361 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
363 DRM_ERROR("failed to enable supplies %d\n", ret);
367 /* td2: min 100 us after regulators before enabling the GPIO */
368 usleep_range(100, 110);
370 gpiod_set_value_cansleep(pdata->enable_gpio, 1);
373 * If we have a reference clock we can enable communication w/ the
374 * panel (including the aux channel) w/out any need for an input clock
375 * so we can do it in resume which lets us read the EDID before
376 * pre_enable(). Without a reference clock we need the MIPI reference
377 * clock so reading early doesn't work.
380 ti_sn65dsi86_enable_comms(pdata);
385 static int __maybe_unused ti_sn65dsi86_suspend(struct device *dev)
387 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
391 ti_sn65dsi86_disable_comms(pdata);
393 gpiod_set_value_cansleep(pdata->enable_gpio, 0);
395 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
397 DRM_ERROR("failed to disable supplies %d\n", ret);
402 static const struct dev_pm_ops ti_sn65dsi86_pm_ops = {
403 SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend, ti_sn65dsi86_resume, NULL)
404 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
405 pm_runtime_force_resume)
408 static int status_show(struct seq_file *s, void *data)
410 struct ti_sn65dsi86 *pdata = s->private;
411 unsigned int reg, val;
413 seq_puts(s, "STATUS REGISTERS:\n");
415 pm_runtime_get_sync(pdata->dev);
417 /* IRQ Status Registers, see Table 31 in datasheet */
418 for (reg = 0xf0; reg <= 0xf8; reg++) {
419 regmap_read(pdata->regmap, reg, &val);
420 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val);
423 pm_runtime_put_autosuspend(pdata->dev);
428 DEFINE_SHOW_ATTRIBUTE(status);
430 static void ti_sn65dsi86_debugfs_remove(void *data)
432 debugfs_remove_recursive(data);
435 static void ti_sn65dsi86_debugfs_init(struct ti_sn65dsi86 *pdata)
437 struct device *dev = pdata->dev;
438 struct dentry *debugfs;
441 debugfs = debugfs_create_dir(dev_name(dev), NULL);
444 * We might get an error back if debugfs wasn't enabled in the kernel
445 * so let's just silently return upon failure.
447 if (IS_ERR_OR_NULL(debugfs))
450 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_debugfs_remove, debugfs);
454 debugfs_create_file("status", 0600, debugfs, pdata, &status_fops);
457 /* -----------------------------------------------------------------------------
458 * Auxiliary Devices (*not* AUX)
461 static void ti_sn65dsi86_uninit_aux(void *data)
463 auxiliary_device_uninit(data);
466 static void ti_sn65dsi86_delete_aux(void *data)
468 auxiliary_device_delete(data);
471 static void ti_sn65dsi86_aux_device_release(struct device *dev)
473 struct auxiliary_device *aux = container_of(dev, struct auxiliary_device, dev);
478 static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 *pdata,
479 struct auxiliary_device **aux_out,
482 struct device *dev = pdata->dev;
483 struct auxiliary_device *aux;
486 aux = kzalloc(sizeof(*aux), GFP_KERNEL);
491 aux->dev.parent = dev;
492 aux->dev.release = ti_sn65dsi86_aux_device_release;
493 device_set_of_node_from_dev(&aux->dev, dev);
494 ret = auxiliary_device_init(aux);
499 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_uninit_aux, aux);
503 ret = auxiliary_device_add(aux);
506 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_delete_aux, aux);
513 /* -----------------------------------------------------------------------------
517 static struct ti_sn65dsi86 *aux_to_ti_sn65dsi86(struct drm_dp_aux *aux)
519 return container_of(aux, struct ti_sn65dsi86, aux);
522 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
523 struct drm_dp_aux_msg *msg)
525 struct ti_sn65dsi86 *pdata = aux_to_ti_sn65dsi86(aux);
526 u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
527 u32 request_val = AUX_CMD_REQ(msg->request);
528 u8 *buf = msg->buffer;
529 unsigned int len = msg->size;
532 u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG];
534 if (len > SN_AUX_MAX_PAYLOAD_BYTES)
537 pm_runtime_get_sync(pdata->dev);
538 mutex_lock(&pdata->comms_mutex);
541 * If someone tries to do a DDC over AUX transaction before pre_enable()
542 * on a device without a dedicated reference clock then we just can't
543 * do it. Fail right away. This prevents non-refclk users from reading
544 * the EDID before enabling the panel but such is life.
546 if (!pdata->comms_enabled) {
552 case DP_AUX_NATIVE_WRITE:
553 case DP_AUX_I2C_WRITE:
554 case DP_AUX_NATIVE_READ:
555 case DP_AUX_I2C_READ:
556 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
557 /* Assume it's good */
565 BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32));
566 put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len,
568 regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len,
569 ARRAY_SIZE(addr_len));
571 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
572 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len);
574 /* Clear old status bits before start so we don't get confused */
575 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG,
576 AUX_IRQ_STATUS_NAT_I2C_FAIL |
577 AUX_IRQ_STATUS_AUX_RPLY_TOUT |
578 AUX_IRQ_STATUS_AUX_SHORT);
580 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
582 /* Zero delay loop because i2c transactions are slow already */
583 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
584 !(val & AUX_CMD_SEND), 0, 50 * 1000);
588 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
592 if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) {
594 * The hardware tried the message seven times per the DP spec
595 * but it hit a timeout. We ignore defers here because they're
596 * handled in hardware.
602 if (val & AUX_IRQ_STATUS_AUX_SHORT) {
603 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &len);
606 } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) {
608 case DP_AUX_I2C_WRITE:
609 case DP_AUX_I2C_READ:
610 msg->reply |= DP_AUX_I2C_REPLY_NACK;
612 case DP_AUX_NATIVE_READ:
613 case DP_AUX_NATIVE_WRITE:
614 msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
621 if (request != DP_AUX_NATIVE_WRITE && request != DP_AUX_I2C_WRITE && len != 0)
622 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len);
625 mutex_unlock(&pdata->comms_mutex);
626 pm_runtime_mark_last_busy(pdata->dev);
627 pm_runtime_put_autosuspend(pdata->dev);
634 static int ti_sn_aux_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us)
637 * The HPD in this chip is a bit useless (See comment in
638 * ti_sn65dsi86_enable_comms) so if our driver is expected to wait
639 * for HPD, we just assume it's asserted after the wait_us delay.
641 * In case we are asked to wait forever (wait_us=0) take conservative
647 usleep_range(wait_us, wait_us + 1000);
652 static int ti_sn_aux_probe(struct auxiliary_device *adev,
653 const struct auxiliary_device_id *id)
655 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
658 pdata->aux.name = "ti-sn65dsi86-aux";
659 pdata->aux.dev = &adev->dev;
660 pdata->aux.transfer = ti_sn_aux_transfer;
661 pdata->aux.wait_hpd_asserted = ti_sn_aux_wait_hpd_asserted;
662 drm_dp_aux_init(&pdata->aux);
664 ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux);
669 * The eDP to MIPI bridge parts don't work until the AUX channel is
670 * setup so we don't add it in the main driver probe, we add it now.
672 return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge");
675 static const struct auxiliary_device_id ti_sn_aux_id_table[] = {
676 { .name = "ti_sn65dsi86.aux", },
680 static struct auxiliary_driver ti_sn_aux_driver = {
682 .probe = ti_sn_aux_probe,
683 .id_table = ti_sn_aux_id_table,
686 /*------------------------------------------------------------------------------
690 static struct ti_sn65dsi86 *bridge_to_ti_sn65dsi86(struct drm_bridge *bridge)
692 return container_of(bridge, struct ti_sn65dsi86, bridge);
695 static int ti_sn_attach_host(struct auxiliary_device *adev, struct ti_sn65dsi86 *pdata)
698 struct mipi_dsi_host *host;
699 struct mipi_dsi_device *dsi;
700 struct device *dev = pdata->dev;
701 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
706 host = of_find_mipi_dsi_host_by_node(pdata->host_node);
708 return -EPROBE_DEFER;
710 dsi = devm_mipi_dsi_device_register_full(&adev->dev, host, &info);
714 /* TODO: setting to 4 MIPI lanes always for now */
716 dsi->format = MIPI_DSI_FMT_RGB888;
717 dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
719 /* check if continuous dsi clock is required or not */
720 pm_runtime_get_sync(dev);
721 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
722 pm_runtime_put_autosuspend(dev);
723 if (!(val & DPPLL_CLK_SRC_DSICLK))
724 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
728 return devm_mipi_dsi_attach(&adev->dev, dsi);
731 static int ti_sn_bridge_attach(struct drm_bridge *bridge,
732 enum drm_bridge_attach_flags flags)
734 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
737 pdata->aux.drm_dev = bridge->dev;
738 ret = drm_dp_aux_register(&pdata->aux);
740 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret);
745 * Attach the next bridge.
746 * We never want the next bridge to *also* create a connector.
748 ret = drm_bridge_attach(bridge->encoder, pdata->next_bridge,
749 &pdata->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
751 goto err_initted_aux;
753 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
756 pdata->connector = drm_bridge_connector_init(pdata->bridge.dev,
757 pdata->bridge.encoder);
758 if (IS_ERR(pdata->connector)) {
759 ret = PTR_ERR(pdata->connector);
760 goto err_initted_aux;
763 drm_connector_attach_encoder(pdata->connector, pdata->bridge.encoder);
768 drm_dp_aux_unregister(&pdata->aux);
772 static void ti_sn_bridge_detach(struct drm_bridge *bridge)
774 drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux);
777 static enum drm_mode_status
778 ti_sn_bridge_mode_valid(struct drm_bridge *bridge,
779 const struct drm_display_info *info,
780 const struct drm_display_mode *mode)
782 /* maximum supported resolution is 4K at 60 fps */
783 if (mode->clock > 594000)
784 return MODE_CLOCK_HIGH;
787 * The front and back porch registers are 8 bits, and pulse width
788 * registers are 15 bits, so reject any modes with larger periods.
791 if ((mode->hsync_start - mode->hdisplay) > 0xff)
792 return MODE_HBLANK_WIDE;
794 if ((mode->vsync_start - mode->vdisplay) > 0xff)
795 return MODE_VBLANK_WIDE;
797 if ((mode->hsync_end - mode->hsync_start) > 0x7fff)
798 return MODE_HSYNC_WIDE;
800 if ((mode->vsync_end - mode->vsync_start) > 0x7fff)
801 return MODE_VSYNC_WIDE;
803 if ((mode->htotal - mode->hsync_end) > 0xff)
804 return MODE_HBLANK_WIDE;
806 if ((mode->vtotal - mode->vsync_end) > 0xff)
807 return MODE_VBLANK_WIDE;
812 static void ti_sn_bridge_atomic_disable(struct drm_bridge *bridge,
813 struct drm_bridge_state *old_bridge_state)
815 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
817 /* disable video stream */
818 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
821 static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata)
823 unsigned int bit_rate_mhz, clk_freq_mhz;
825 struct drm_display_mode *mode =
826 &pdata->bridge.encoder->crtc->state->adjusted_mode;
828 /* set DSIA clk frequency */
829 bit_rate_mhz = (mode->clock / 1000) *
830 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
831 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
833 /* for each increment in val, frequency increases by 5MHz */
834 val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
835 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
836 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
839 static unsigned int ti_sn_bridge_get_bpp(struct drm_connector *connector)
841 if (connector->display_info.bpc <= 6)
848 * LUT index corresponds to register value and
849 * LUT values corresponds to dp data rate supported
850 * by the bridge in Mbps unit.
852 static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
853 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
856 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata, unsigned int bpp)
858 unsigned int bit_rate_khz, dp_rate_mhz;
860 struct drm_display_mode *mode =
861 &pdata->bridge.encoder->crtc->state->adjusted_mode;
863 /* Calculate minimum bit rate based on our pixel clock. */
864 bit_rate_khz = mode->clock * bpp;
866 /* Calculate minimum DP data rate, taking 80% as per DP spec */
867 dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
868 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
870 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
871 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz)
877 static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata)
879 unsigned int valid_rates = 0;
880 unsigned int rate_per_200khz;
881 unsigned int rate_mhz;
886 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val);
888 DRM_DEV_ERROR(pdata->dev,
889 "Can't read eDP rev (%d), assuming 1.1\n", ret);
890 dpcd_val = DP_EDP_11;
893 if (dpcd_val >= DP_EDP_14) {
894 /* eDP 1.4 devices must provide a custom table */
895 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
897 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES,
898 sink_rates, sizeof(sink_rates));
900 if (ret != sizeof(sink_rates)) {
901 DRM_DEV_ERROR(pdata->dev,
902 "Can't read supported rate table (%d)\n", ret);
904 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */
905 memset(sink_rates, 0, sizeof(sink_rates));
908 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
909 rate_per_200khz = le16_to_cpu(sink_rates[i]);
911 if (!rate_per_200khz)
914 rate_mhz = rate_per_200khz * 200 / 1000;
916 j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
918 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz)
919 valid_rates |= BIT(j);
923 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) {
924 if (valid_rates & BIT(i))
927 DRM_DEV_ERROR(pdata->dev,
928 "No matching eDP rates in table; falling back\n");
931 /* On older versions best we can do is use DP_MAX_LINK_RATE */
932 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val);
934 DRM_DEV_ERROR(pdata->dev,
935 "Can't read max rate (%d); assuming 5.4 GHz\n",
937 dpcd_val = DP_LINK_BW_5_4;
942 DRM_DEV_ERROR(pdata->dev,
943 "Unexpected max rate (%#x); assuming 5.4 GHz\n",
947 valid_rates |= BIT(7);
950 valid_rates |= BIT(4);
952 case DP_LINK_BW_1_62:
953 valid_rates |= BIT(1);
960 static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata)
962 struct drm_display_mode *mode =
963 &pdata->bridge.encoder->crtc->state->adjusted_mode;
964 u8 hsync_polarity = 0, vsync_polarity = 0;
966 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
967 hsync_polarity = CHA_HSYNC_POLARITY;
968 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
969 vsync_polarity = CHA_VSYNC_POLARITY;
971 ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
973 ti_sn65dsi86_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
975 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
976 (mode->hsync_end - mode->hsync_start) & 0xFF);
977 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
978 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
980 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
981 (mode->vsync_end - mode->vsync_start) & 0xFF);
982 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
983 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
986 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
987 (mode->htotal - mode->hsync_end) & 0xFF);
988 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
989 (mode->vtotal - mode->vsync_end) & 0xFF);
991 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
992 (mode->hsync_start - mode->hdisplay) & 0xFF);
993 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
994 (mode->vsync_start - mode->vdisplay) & 0xFF);
996 usleep_range(10000, 10500); /* 10ms delay recommended by spec */
999 static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86 *pdata)
1004 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data);
1006 DRM_DEV_ERROR(pdata->dev,
1007 "Can't read lane count (%d); assuming 4\n", ret);
1011 return data & DP_LANE_COUNT_MASK;
1014 static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx,
1015 const char **last_err_str)
1021 /* set dp clk frequency value */
1022 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
1023 DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx));
1026 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
1028 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
1029 val & DPPLL_SRC_DP_PLL_LOCK, 1000,
1032 *last_err_str = "DP_PLL_LOCK polling failed";
1037 * We'll try to link train several times. As part of link training
1038 * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If
1039 * the panel isn't ready quite it might respond NAK here which means
1040 * we need to try again.
1042 for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) {
1043 /* Semi auto link training mode */
1044 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
1045 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
1046 val == ML_TX_MAIN_LINK_OFF ||
1047 val == ML_TX_NORMAL_MODE, 1000,
1050 *last_err_str = "Training complete polling failed";
1051 } else if (val == ML_TX_MAIN_LINK_OFF) {
1052 *last_err_str = "Link training failed, link is off";
1060 /* If we saw quite a few retries, add a note about it */
1061 if (!ret && i > SN_LINK_TRAINING_TRIES / 2)
1062 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i);
1065 /* Disable the PLL if we failed */
1067 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1072 static void ti_sn_bridge_atomic_enable(struct drm_bridge *bridge,
1073 struct drm_bridge_state *old_bridge_state)
1075 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1076 struct drm_connector *connector;
1077 const char *last_err_str = "No supported DP rate";
1078 unsigned int valid_rates;
1085 connector = drm_atomic_get_new_connector_for_encoder(old_bridge_state->base.state,
1088 dev_err_ratelimited(pdata->dev, "Could not get the connector\n");
1092 max_dp_lanes = ti_sn_get_max_lanes(pdata);
1093 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes);
1095 /* DSI_A lane config */
1096 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes);
1097 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
1098 CHA_DSI_LANES_MASK, val);
1100 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign);
1101 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK,
1102 pdata->ln_polrs << LN_POLRS_OFFSET);
1104 /* set dsi clk frequency value */
1105 ti_sn_bridge_set_dsi_rate(pdata);
1108 * The SN65DSI86 only supports ASSR Display Authentication method and
1109 * this method is enabled for eDP panels. An eDP panel must support this
1110 * authentication method. We need to enable this method in the eDP panel
1111 * at DisplayPort address 0x0010A prior to link training.
1113 * As only ASSR is supported by SN65DSI86, for full DisplayPort displays
1114 * we need to disable the scrambler.
1116 if (pdata->bridge.type == DRM_MODE_CONNECTOR_eDP) {
1117 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
1118 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
1120 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG,
1121 SCRAMBLE_DISABLE, 0);
1123 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG,
1124 SCRAMBLE_DISABLE, SCRAMBLE_DISABLE);
1127 bpp = ti_sn_bridge_get_bpp(connector);
1128 /* Set the DP output format (18 bpp or 24 bpp) */
1129 val = bpp == 18 ? BPP_18_RGB : 0;
1130 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
1132 /* DP lane config */
1133 val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
1134 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
1137 valid_rates = ti_sn_bridge_read_valid_rates(pdata);
1139 /* Train until we run out of rates */
1140 for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata, bpp);
1141 dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
1143 if (!(valid_rates & BIT(dp_rate_idx)))
1146 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str);
1151 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret);
1155 /* config video parameters */
1156 ti_sn_bridge_set_video_timings(pdata);
1158 /* enable video stream */
1159 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
1163 static void ti_sn_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1164 struct drm_bridge_state *old_bridge_state)
1166 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1168 pm_runtime_get_sync(pdata->dev);
1171 ti_sn65dsi86_enable_comms(pdata);
1173 /* td7: min 100 us after enable before DSI data */
1174 usleep_range(100, 110);
1177 static void ti_sn_bridge_atomic_post_disable(struct drm_bridge *bridge,
1178 struct drm_bridge_state *old_bridge_state)
1180 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1182 /* semi auto link training mode OFF */
1183 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
1184 /* Num lanes to 0 as per power sequencing in data sheet */
1185 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0);
1186 /* disable DP PLL */
1187 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1190 ti_sn65dsi86_disable_comms(pdata);
1192 pm_runtime_put_sync(pdata->dev);
1195 static enum drm_connector_status ti_sn_bridge_detect(struct drm_bridge *bridge)
1197 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1200 pm_runtime_get_sync(pdata->dev);
1201 regmap_read(pdata->regmap, SN_HPD_DISABLE_REG, &val);
1202 pm_runtime_put_autosuspend(pdata->dev);
1204 return val & HPD_DEBOUNCED_STATE ? connector_status_connected
1205 : connector_status_disconnected;
1208 static struct edid *ti_sn_bridge_get_edid(struct drm_bridge *bridge,
1209 struct drm_connector *connector)
1211 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1213 return drm_get_edid(connector, &pdata->aux.ddc);
1216 static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
1217 .attach = ti_sn_bridge_attach,
1218 .detach = ti_sn_bridge_detach,
1219 .mode_valid = ti_sn_bridge_mode_valid,
1220 .get_edid = ti_sn_bridge_get_edid,
1221 .detect = ti_sn_bridge_detect,
1222 .atomic_pre_enable = ti_sn_bridge_atomic_pre_enable,
1223 .atomic_enable = ti_sn_bridge_atomic_enable,
1224 .atomic_disable = ti_sn_bridge_atomic_disable,
1225 .atomic_post_disable = ti_sn_bridge_atomic_post_disable,
1226 .atomic_reset = drm_atomic_helper_bridge_reset,
1227 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1228 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1231 static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata,
1232 struct device_node *np)
1234 u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 };
1235 u32 lane_polarities[SN_MAX_DP_LANES] = { };
1236 struct device_node *endpoint;
1243 * Read config from the device tree about lane remapping and lane
1244 * polarities. These are optional and we assume identity map and
1245 * normal polarity if nothing is specified. It's OK to specify just
1246 * data-lanes but not lane-polarities but not vice versa.
1248 * Error checking is light (we just make sure we don't crash or
1249 * buffer overrun) and we assume dts is well formed and specifying
1250 * mappings that the hardware supports.
1252 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1253 dp_lanes = drm_of_get_data_lanes_count(endpoint, 1, SN_MAX_DP_LANES);
1255 of_property_read_u32_array(endpoint, "data-lanes",
1256 lane_assignments, dp_lanes);
1257 of_property_read_u32_array(endpoint, "lane-polarities",
1258 lane_polarities, dp_lanes);
1260 dp_lanes = SN_MAX_DP_LANES;
1262 of_node_put(endpoint);
1265 * Convert into register format. Loop over all lanes even if
1266 * data-lanes had fewer elements so that we nicely initialize
1267 * the LN_ASSIGN register.
1269 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) {
1270 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i];
1271 ln_polrs = ln_polrs << 1 | lane_polarities[i];
1274 /* Stash in our struct for when we power on */
1275 pdata->dp_lanes = dp_lanes;
1276 pdata->ln_assign = ln_assign;
1277 pdata->ln_polrs = ln_polrs;
1280 static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 *pdata)
1282 struct device_node *np = pdata->dev->of_node;
1284 pdata->host_node = of_graph_get_remote_node(np, 0, 0);
1286 if (!pdata->host_node) {
1287 DRM_ERROR("remote dsi host node not found\n");
1294 static int ti_sn_bridge_probe(struct auxiliary_device *adev,
1295 const struct auxiliary_device_id *id)
1297 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1298 struct device_node *np = pdata->dev->of_node;
1301 pdata->next_bridge = devm_drm_of_get_bridge(&adev->dev, np, 1, 0);
1302 if (IS_ERR(pdata->next_bridge))
1303 return dev_err_probe(&adev->dev, PTR_ERR(pdata->next_bridge),
1304 "failed to create panel bridge\n");
1306 ti_sn_bridge_parse_lanes(pdata, np);
1308 ret = ti_sn_bridge_parse_dsi_host(pdata);
1312 pdata->bridge.funcs = &ti_sn_bridge_funcs;
1313 pdata->bridge.of_node = np;
1314 pdata->bridge.type = pdata->next_bridge->type == DRM_MODE_CONNECTOR_DisplayPort
1315 ? DRM_MODE_CONNECTOR_DisplayPort : DRM_MODE_CONNECTOR_eDP;
1317 if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort)
1318 pdata->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT;
1320 drm_bridge_add(&pdata->bridge);
1322 ret = ti_sn_attach_host(adev, pdata);
1324 dev_err_probe(&adev->dev, ret, "failed to attach dsi host\n");
1325 goto err_remove_bridge;
1331 drm_bridge_remove(&pdata->bridge);
1335 static void ti_sn_bridge_remove(struct auxiliary_device *adev)
1337 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1342 drm_bridge_remove(&pdata->bridge);
1344 of_node_put(pdata->host_node);
1347 static const struct auxiliary_device_id ti_sn_bridge_id_table[] = {
1348 { .name = "ti_sn65dsi86.bridge", },
1352 static struct auxiliary_driver ti_sn_bridge_driver = {
1354 .probe = ti_sn_bridge_probe,
1355 .remove = ti_sn_bridge_remove,
1356 .id_table = ti_sn_bridge_id_table,
1359 /* -----------------------------------------------------------------------------
1362 #if defined(CONFIG_PWM)
1363 static int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata)
1365 return atomic_xchg(&pdata->pwm_pin_busy, 1) ? -EBUSY : 0;
1368 static void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata)
1370 atomic_set(&pdata->pwm_pin_busy, 0);
1373 static struct ti_sn65dsi86 *pwm_chip_to_ti_sn_bridge(struct pwm_chip *chip)
1375 return container_of(chip, struct ti_sn65dsi86, pchip);
1378 static int ti_sn_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
1380 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1382 return ti_sn_pwm_pin_request(pdata);
1385 static void ti_sn_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
1387 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1389 ti_sn_pwm_pin_release(pdata);
1394 * - The PWM signal is not driven when the chip is powered down, or in its
1395 * reset state and the driver does not implement the "suspend state"
1396 * described in the documentation. In order to save power, state->enabled is
1397 * interpreted as denoting if the signal is expected to be valid, and is used
1398 * to determine if the chip needs to be kept powered.
1399 * - Changing both period and duty_cycle is not done atomically, neither is the
1400 * multi-byte register updates, so the output might briefly be undefined
1403 static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
1404 const struct pwm_state *state)
1406 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1407 unsigned int pwm_en_inv;
1408 unsigned int backlight;
1409 unsigned int pre_div;
1415 if (!pdata->pwm_enabled) {
1416 ret = pm_runtime_get_sync(pdata->dev);
1418 pm_runtime_put_sync(pdata->dev);
1423 if (state->enabled) {
1424 if (!pdata->pwm_enabled) {
1426 * The chip might have been powered down while we
1427 * didn't hold a PM runtime reference, so mux in the
1428 * PWM function on the GPIO pin again.
1430 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1431 SN_GPIO_MUX_MASK << (2 * SN_PWM_GPIO_IDX),
1432 SN_GPIO_MUX_SPECIAL << (2 * SN_PWM_GPIO_IDX));
1434 dev_err(pdata->dev, "failed to mux in PWM function\n");
1440 * Per the datasheet the PWM frequency is given by:
1443 * PWM_FREQ = -----------------------------------
1444 * PWM_PRE_DIV * BACKLIGHT_SCALE + 1
1446 * However, after careful review the author is convinced that
1447 * the documentation has lost some parenthesis around
1448 * "BACKLIGHT_SCALE + 1".
1450 * With the period T_pwm = 1/PWM_FREQ this can be written:
1452 * T_pwm * REFCLK_FREQ = PWM_PRE_DIV * (BACKLIGHT_SCALE + 1)
1454 * In order to keep BACKLIGHT_SCALE within its 16 bits,
1455 * PWM_PRE_DIV must be:
1457 * T_pwm * REFCLK_FREQ
1458 * PWM_PRE_DIV >= -------------------------
1459 * BACKLIGHT_SCALE_MAX + 1
1461 * To simplify the search and to favour higher resolution of
1462 * the duty cycle over accuracy of the period, the lowest
1463 * possible PWM_PRE_DIV is used. Finally the scale is
1466 * T_pwm * REFCLK_FREQ
1467 * BACKLIGHT_SCALE = ---------------------- - 1
1470 * Here T_pwm is represented in seconds, so appropriate scaling
1471 * to nanoseconds is necessary.
1474 /* Minimum T_pwm is 1 / REFCLK_FREQ */
1475 if (state->period <= NSEC_PER_SEC / pdata->pwm_refclk_freq) {
1481 * Maximum T_pwm is 255 * (65535 + 1) / REFCLK_FREQ
1482 * Limit period to this to avoid overflows
1484 period_max = div_u64((u64)NSEC_PER_SEC * 255 * (65535 + 1),
1485 pdata->pwm_refclk_freq);
1486 period = min(state->period, period_max);
1488 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq,
1489 (u64)NSEC_PER_SEC * (BACKLIGHT_SCALE_MAX + 1));
1490 scale = div64_u64(period * pdata->pwm_refclk_freq, (u64)NSEC_PER_SEC * pre_div) - 1;
1493 * The documentation has the duty ratio given as:
1496 * ------- = ---------------------
1497 * period BACKLIGHT_SCALE + 1
1499 * Solve for BACKLIGHT, substituting BACKLIGHT_SCALE according
1500 * to definition above and adjusting for nanosecond
1501 * representation of duty cycle gives us:
1503 backlight = div64_u64(state->duty_cycle * pdata->pwm_refclk_freq,
1504 (u64)NSEC_PER_SEC * pre_div);
1505 if (backlight > scale)
1508 ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div);
1510 dev_err(pdata->dev, "failed to update PWM_PRE_DIV\n");
1514 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_SCALE_REG, scale);
1515 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_REG, backlight);
1518 pwm_en_inv = FIELD_PREP(SN_PWM_EN_MASK, state->enabled) |
1519 FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED);
1520 ret = regmap_write(pdata->regmap, SN_PWM_EN_INV_REG, pwm_en_inv);
1522 dev_err(pdata->dev, "failed to update PWM_EN/PWM_INV\n");
1526 pdata->pwm_enabled = state->enabled;
1529 if (!pdata->pwm_enabled)
1530 pm_runtime_put_sync(pdata->dev);
1535 static int ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
1536 struct pwm_state *state)
1538 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1539 unsigned int pwm_en_inv;
1540 unsigned int pre_div;
1545 ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv);
1549 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, &scale);
1553 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, &backlight);
1557 ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div);
1561 state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv);
1562 if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv))
1563 state->polarity = PWM_POLARITY_INVERSED;
1565 state->polarity = PWM_POLARITY_NORMAL;
1567 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1),
1568 pdata->pwm_refclk_freq);
1569 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight,
1570 pdata->pwm_refclk_freq);
1572 if (state->duty_cycle > state->period)
1573 state->duty_cycle = state->period;
1578 static const struct pwm_ops ti_sn_pwm_ops = {
1579 .request = ti_sn_pwm_request,
1580 .free = ti_sn_pwm_free,
1581 .apply = ti_sn_pwm_apply,
1582 .get_state = ti_sn_pwm_get_state,
1585 static int ti_sn_pwm_probe(struct auxiliary_device *adev,
1586 const struct auxiliary_device_id *id)
1588 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1590 pdata->pchip.dev = pdata->dev;
1591 pdata->pchip.ops = &ti_sn_pwm_ops;
1592 pdata->pchip.npwm = 1;
1593 pdata->pchip.of_xlate = of_pwm_single_xlate;
1594 pdata->pchip.of_pwm_n_cells = 1;
1596 return pwmchip_add(&pdata->pchip);
1599 static void ti_sn_pwm_remove(struct auxiliary_device *adev)
1601 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1603 pwmchip_remove(&pdata->pchip);
1605 if (pdata->pwm_enabled)
1606 pm_runtime_put_sync(pdata->dev);
1609 static const struct auxiliary_device_id ti_sn_pwm_id_table[] = {
1610 { .name = "ti_sn65dsi86.pwm", },
1614 static struct auxiliary_driver ti_sn_pwm_driver = {
1616 .probe = ti_sn_pwm_probe,
1617 .remove = ti_sn_pwm_remove,
1618 .id_table = ti_sn_pwm_id_table,
1621 static int __init ti_sn_pwm_register(void)
1623 return auxiliary_driver_register(&ti_sn_pwm_driver);
1626 static void ti_sn_pwm_unregister(void)
1628 auxiliary_driver_unregister(&ti_sn_pwm_driver);
1632 static inline int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) { return 0; }
1633 static inline void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) {}
1635 static inline int ti_sn_pwm_register(void) { return 0; }
1636 static inline void ti_sn_pwm_unregister(void) {}
1639 /* -----------------------------------------------------------------------------
1642 #if defined(CONFIG_OF_GPIO)
1644 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip,
1645 const struct of_phandle_args *gpiospec,
1648 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells))
1651 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1)
1655 *flags = gpiospec->args[1];
1657 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET;
1660 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip,
1661 unsigned int offset)
1663 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1666 * We already have to keep track of the direction because we use
1667 * that to figure out whether we've powered the device. We can
1668 * just return that rather than (maybe) powering up the device
1669 * to ask its direction.
1671 return test_bit(offset, pdata->gchip_output) ?
1672 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1675 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset)
1677 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1682 * When the pin is an input we don't forcibly keep the bridge
1683 * powered--we just power it on to read the pin. NOTE: part of
1684 * the reason this works is that the bridge defaults (when
1685 * powered back on) to all 4 GPIOs being configured as GPIO input.
1686 * Also note that if something else is keeping the chip powered the
1687 * pm_runtime functions are lightweight increments of a refcount.
1689 pm_runtime_get_sync(pdata->dev);
1690 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val);
1691 pm_runtime_put_autosuspend(pdata->dev);
1696 return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset));
1699 static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset,
1702 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1705 if (!test_bit(offset, pdata->gchip_output)) {
1706 dev_err(pdata->dev, "Ignoring GPIO set while input\n");
1711 ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG,
1712 BIT(SN_GPIO_OUTPUT_SHIFT + offset),
1713 val << (SN_GPIO_OUTPUT_SHIFT + offset));
1715 dev_warn(pdata->dev,
1716 "Failed to set bridge GPIO %u: %d\n", offset, ret);
1719 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip,
1720 unsigned int offset)
1722 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1723 int shift = offset * 2;
1726 if (!test_and_clear_bit(offset, pdata->gchip_output))
1729 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1730 SN_GPIO_MUX_MASK << shift,
1731 SN_GPIO_MUX_INPUT << shift);
1733 set_bit(offset, pdata->gchip_output);
1738 * NOTE: if nobody else is powering the device this may fully power
1739 * it off and when it comes back it will have lost all state, but
1740 * that's OK because the default is input and we're now an input.
1742 pm_runtime_put_autosuspend(pdata->dev);
1747 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip,
1748 unsigned int offset, int val)
1750 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1751 int shift = offset * 2;
1754 if (test_and_set_bit(offset, pdata->gchip_output))
1757 pm_runtime_get_sync(pdata->dev);
1759 /* Set value first to avoid glitching */
1760 ti_sn_bridge_gpio_set(chip, offset, val);
1763 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1764 SN_GPIO_MUX_MASK << shift,
1765 SN_GPIO_MUX_OUTPUT << shift);
1767 clear_bit(offset, pdata->gchip_output);
1768 pm_runtime_put_autosuspend(pdata->dev);
1774 static int ti_sn_bridge_gpio_request(struct gpio_chip *chip, unsigned int offset)
1776 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1778 if (offset == SN_PWM_GPIO_IDX)
1779 return ti_sn_pwm_pin_request(pdata);
1784 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset)
1786 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1788 /* We won't keep pm_runtime if we're input, so switch there on free */
1789 ti_sn_bridge_gpio_direction_input(chip, offset);
1791 if (offset == SN_PWM_GPIO_IDX)
1792 ti_sn_pwm_pin_release(pdata);
1795 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = {
1796 "GPIO1", "GPIO2", "GPIO3", "GPIO4"
1799 static int ti_sn_gpio_probe(struct auxiliary_device *adev,
1800 const struct auxiliary_device_id *id)
1802 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1805 /* Only init if someone is going to use us as a GPIO controller */
1806 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller"))
1809 pdata->gchip.label = dev_name(pdata->dev);
1810 pdata->gchip.parent = pdata->dev;
1811 pdata->gchip.owner = THIS_MODULE;
1812 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate;
1813 pdata->gchip.of_gpio_n_cells = 2;
1814 pdata->gchip.request = ti_sn_bridge_gpio_request;
1815 pdata->gchip.free = ti_sn_bridge_gpio_free;
1816 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction;
1817 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input;
1818 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output;
1819 pdata->gchip.get = ti_sn_bridge_gpio_get;
1820 pdata->gchip.set = ti_sn_bridge_gpio_set;
1821 pdata->gchip.can_sleep = true;
1822 pdata->gchip.names = ti_sn_bridge_gpio_names;
1823 pdata->gchip.ngpio = SN_NUM_GPIOS;
1824 pdata->gchip.base = -1;
1825 ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata);
1827 dev_err(pdata->dev, "can't add gpio chip\n");
1832 static const struct auxiliary_device_id ti_sn_gpio_id_table[] = {
1833 { .name = "ti_sn65dsi86.gpio", },
1837 MODULE_DEVICE_TABLE(auxiliary, ti_sn_gpio_id_table);
1839 static struct auxiliary_driver ti_sn_gpio_driver = {
1841 .probe = ti_sn_gpio_probe,
1842 .id_table = ti_sn_gpio_id_table,
1845 static int __init ti_sn_gpio_register(void)
1847 return auxiliary_driver_register(&ti_sn_gpio_driver);
1850 static void ti_sn_gpio_unregister(void)
1852 auxiliary_driver_unregister(&ti_sn_gpio_driver);
1857 static inline int ti_sn_gpio_register(void) { return 0; }
1858 static inline void ti_sn_gpio_unregister(void) {}
1862 /* -----------------------------------------------------------------------------
1866 static void ti_sn65dsi86_runtime_disable(void *data)
1868 pm_runtime_dont_use_autosuspend(data);
1869 pm_runtime_disable(data);
1872 static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 *pdata)
1875 const char * const ti_sn_bridge_supply_names[] = {
1876 "vcca", "vcc", "vccio", "vpll",
1879 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
1880 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
1882 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
1886 static int ti_sn65dsi86_probe(struct i2c_client *client)
1888 struct device *dev = &client->dev;
1889 struct ti_sn65dsi86 *pdata;
1892 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1893 DRM_ERROR("device doesn't support I2C\n");
1897 pdata = devm_kzalloc(dev, sizeof(struct ti_sn65dsi86), GFP_KERNEL);
1900 dev_set_drvdata(dev, pdata);
1903 mutex_init(&pdata->comms_mutex);
1905 pdata->regmap = devm_regmap_init_i2c(client,
1906 &ti_sn65dsi86_regmap_config);
1907 if (IS_ERR(pdata->regmap))
1908 return dev_err_probe(dev, PTR_ERR(pdata->regmap),
1909 "regmap i2c init failed\n");
1911 pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable",
1913 if (IS_ERR(pdata->enable_gpio))
1914 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio),
1915 "failed to get enable gpio from DT\n");
1917 ret = ti_sn65dsi86_parse_regulators(pdata);
1919 return dev_err_probe(dev, ret, "failed to parse regulators\n");
1921 pdata->refclk = devm_clk_get_optional(dev, "refclk");
1922 if (IS_ERR(pdata->refclk))
1923 return dev_err_probe(dev, PTR_ERR(pdata->refclk),
1924 "failed to get reference clock\n");
1926 pm_runtime_enable(dev);
1927 pm_runtime_set_autosuspend_delay(pdata->dev, 500);
1928 pm_runtime_use_autosuspend(pdata->dev);
1929 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev);
1933 ti_sn65dsi86_debugfs_init(pdata);
1936 * Break ourselves up into a collection of aux devices. The only real
1937 * motiviation here is to solve the chicken-and-egg problem of probe
1938 * ordering. The bridge wants the panel to be there when it probes.
1939 * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards)
1940 * when it probes. The panel and maybe backlight might want the DDC
1941 * bus or the pwm_chip. Having sub-devices allows the some sub devices
1942 * to finish probing even if others return -EPROBE_DEFER and gets us
1943 * around the problems.
1946 if (IS_ENABLED(CONFIG_OF_GPIO)) {
1947 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio");
1952 if (IS_ENABLED(CONFIG_PWM)) {
1953 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->pwm_aux, "pwm");
1959 * NOTE: At the end of the AUX channel probe we'll add the aux device
1960 * for the bridge. This is because the bridge can't be used until the
1961 * AUX channel is there and this is a very simple solution to the
1962 * dependency problem.
1964 return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux");
1967 static struct i2c_device_id ti_sn65dsi86_id[] = {
1968 { "ti,sn65dsi86", 0},
1971 MODULE_DEVICE_TABLE(i2c, ti_sn65dsi86_id);
1973 static const struct of_device_id ti_sn65dsi86_match_table[] = {
1974 {.compatible = "ti,sn65dsi86"},
1977 MODULE_DEVICE_TABLE(of, ti_sn65dsi86_match_table);
1979 static struct i2c_driver ti_sn65dsi86_driver = {
1981 .name = "ti_sn65dsi86",
1982 .of_match_table = ti_sn65dsi86_match_table,
1983 .pm = &ti_sn65dsi86_pm_ops,
1985 .probe = ti_sn65dsi86_probe,
1986 .id_table = ti_sn65dsi86_id,
1989 static int __init ti_sn65dsi86_init(void)
1993 ret = i2c_add_driver(&ti_sn65dsi86_driver);
1997 ret = ti_sn_gpio_register();
1999 goto err_main_was_registered;
2001 ret = ti_sn_pwm_register();
2003 goto err_gpio_was_registered;
2005 ret = auxiliary_driver_register(&ti_sn_aux_driver);
2007 goto err_pwm_was_registered;
2009 ret = auxiliary_driver_register(&ti_sn_bridge_driver);
2011 goto err_aux_was_registered;
2015 err_aux_was_registered:
2016 auxiliary_driver_unregister(&ti_sn_aux_driver);
2017 err_pwm_was_registered:
2018 ti_sn_pwm_unregister();
2019 err_gpio_was_registered:
2020 ti_sn_gpio_unregister();
2021 err_main_was_registered:
2022 i2c_del_driver(&ti_sn65dsi86_driver);
2026 module_init(ti_sn65dsi86_init);
2028 static void __exit ti_sn65dsi86_exit(void)
2030 auxiliary_driver_unregister(&ti_sn_bridge_driver);
2031 auxiliary_driver_unregister(&ti_sn_aux_driver);
2032 ti_sn_pwm_unregister();
2033 ti_sn_gpio_unregister();
2034 i2c_del_driver(&ti_sn65dsi86_driver);
2036 module_exit(ti_sn65dsi86_exit);
2038 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>");
2039 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
2040 MODULE_LICENSE("GPL v2");