drivers/gpu/drm/bridge/ti-sn65dsi86.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
   5  */
   6
   7 #include <linux/bits.h>
   8 #include <linux/clk.h>
   9 #include <linux/debugfs.h>
  10 #include <linux/gpio/consumer.h>
  11 #include <linux/gpio/driver.h>
  12 #include <linux/i2c.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/module.h>
  15 #include <linux/of_graph.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regmap.h>
  18 #include <linux/regulator/consumer.h>
  19
  20 #include <drm/drm_atomic.h>
  21 #include <drm/drm_atomic_helper.h>
  22 #include <drm/drm_bridge.h>
  23 #include <drm/drm_dp_helper.h>
  24 #include <drm/drm_mipi_dsi.h>
  25 #include <drm/drm_of.h>
  26 #include <drm/drm_panel.h>
  27 #include <drm/drm_print.h>
  28 #include <drm/drm_probe_helper.h>
  29
  30 #define SN_DEVICE_REV_REG                       0x08
  31 #define SN_DPPLL_SRC_REG                        0x0A
  32 #define  DPPLL_CLK_SRC_DSICLK                   BIT(0)
  33 #define  REFCLK_FREQ_MASK                       GENMASK(3, 1)
  34 #define  REFCLK_FREQ(x)                         ((x) << 1)
  35 #define  DPPLL_SRC_DP_PLL_LOCK                  BIT(7)
  36 #define SN_PLL_ENABLE_REG                       0x0D
  37 #define SN_DSI_LANES_REG                        0x10
  38 #define  CHA_DSI_LANES_MASK                     GENMASK(4, 3)
  39 #define  CHA_DSI_LANES(x)                       ((x) << 3)
  40 #define SN_DSIA_CLK_FREQ_REG                    0x12
  41 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG       0x20
  42 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG    0x24
  43 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG        0x2C
  44 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG       0x2D
  45 #define  CHA_HSYNC_POLARITY                     BIT(7)
  46 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG        0x30
  47 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG       0x31
  48 #define  CHA_VSYNC_POLARITY                     BIT(7)
  49 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG        0x34
  50 #define SN_CHA_VERTICAL_BACK_PORCH_REG          0x36
  51 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG       0x38
  52 #define SN_CHA_VERTICAL_FRONT_PORCH_REG         0x3A
  53 #define SN_LN_ASSIGN_REG                        0x59
  54 #define  LN_ASSIGN_WIDTH                        2
  55 #define SN_ENH_FRAME_REG                        0x5A
  56 #define  VSTREAM_ENABLE                         BIT(3)
  57 #define  LN_POLRS_OFFSET                        4
  58 #define  LN_POLRS_MASK                          0xf0
  59 #define SN_DATA_FORMAT_REG                      0x5B
  60 #define  BPP_18_RGB                             BIT(0)
  61 #define SN_HPD_DISABLE_REG                      0x5C
  62 #define  HPD_DISABLE                            BIT(0)
  63 #define SN_GPIO_IO_REG                          0x5E
  64 #define  SN_GPIO_INPUT_SHIFT                    4
  65 #define  SN_GPIO_OUTPUT_SHIFT                   0
  66 #define SN_GPIO_CTRL_REG                        0x5F
  67 #define  SN_GPIO_MUX_INPUT                      0
  68 #define  SN_GPIO_MUX_OUTPUT                     1
  69 #define  SN_GPIO_MUX_SPECIAL                    2
  70 #define  SN_GPIO_MUX_MASK                       0x3
  71 #define SN_AUX_WDATA_REG(x)                     (0x64 + (x))
  72 #define SN_AUX_ADDR_19_16_REG                   0x74
  73 #define SN_AUX_ADDR_15_8_REG                    0x75
  74 #define SN_AUX_ADDR_7_0_REG                     0x76
  75 #define SN_AUX_LENGTH_REG                       0x77
  76 #define SN_AUX_CMD_REG                          0x78
  77 #define  AUX_CMD_SEND                           BIT(0)
  78 #define  AUX_CMD_REQ(x)                         ((x) << 4)
  79 #define SN_AUX_RDATA_REG(x)                     (0x79 + (x))
  80 #define SN_SSC_CONFIG_REG                       0x93
  81 #define  DP_NUM_LANES_MASK                      GENMASK(5, 4)
  82 #define  DP_NUM_LANES(x)                        ((x) << 4)
  83 #define SN_DATARATE_CONFIG_REG                  0x94
  84 #define  DP_DATARATE_MASK                       GENMASK(7, 5)
  85 #define  DP_DATARATE(x)                         ((x) << 5)
  86 #define SN_ML_TX_MODE_REG                       0x96
  87 #define  ML_TX_MAIN_LINK_OFF                    0
  88 #define  ML_TX_NORMAL_MODE                      BIT(0)
  89 #define SN_AUX_CMD_STATUS_REG                   0xF4
  90 #define  AUX_IRQ_STATUS_AUX_RPLY_TOUT           BIT(3)
  91 #define  AUX_IRQ_STATUS_AUX_SHORT               BIT(5)
  92 #define  AUX_IRQ_STATUS_NAT_I2C_FAIL            BIT(6)
  93
  94 #define MIN_DSI_CLK_FREQ_MHZ    40
  95
  96 /* fudge factor required to account for 8b/10b encoding */
  97 #define DP_CLK_FUDGE_NUM        10
  98 #define DP_CLK_FUDGE_DEN        8
  99
 100 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
 101 #define SN_AUX_MAX_PAYLOAD_BYTES        16
 102
 103 #define SN_REGULATOR_SUPPLY_NUM         4
 104
 105 #define SN_MAX_DP_LANES                 4
 106 #define SN_NUM_GPIOS                    4
 107 #define SN_GPIO_PHYSICAL_OFFSET         1
 108
 109 /**
 110  * struct ti_sn_bridge - Platform data for ti-sn65dsi86 driver.
 111  * @dev:          Pointer to our device.
 112  * @regmap:       Regmap for accessing i2c.
 113  * @aux:          Our aux channel.
 114  * @bridge:       Our bridge.
 115  * @connector:    Our connector.
 116  * @debugfs:      Used for managing our debugfs.
 117  * @host_node:    Remote DSI node.
 118  * @dsi:          Our MIPI DSI source.
 119  * @refclk:       Our reference clock.
 120  * @panel:        Our panel.
 121  * @enable_gpio:  The GPIO we toggle to enable the bridge.
 122  * @supplies:     Data for bulk enabling/disabling our regulators.
 123  * @dp_lanes:     Count of dp_lanes we're using.
 124  * @ln_assign:    Value to program to the LN_ASSIGN register.
 125  * @ln_polrs:     Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
 126  *
 127  * @gchip:        If we expose our GPIOs, this is used.
 128  * @gchip_output: A cache of whether we've set GPIOs to output.  This
 129  *                serves double-duty of keeping track of the direction and
 130  *                also keeping track of whether we've incremented the
 131  *                pm_runtime reference count for this pin, which we do
 132  *                whenever a pin is configured as an output.  This is a
 133  *                bitmap so we can do atomic ops on it without an extra
 134  *                lock so concurrent users of our 4 GPIOs don't stomp on
 135  *                each other's read-modify-write.
 136  */
 137 struct ti_sn_bridge {
 138         struct device                   *dev;
 139         struct regmap                   *regmap;
 140         struct drm_dp_aux               aux;
 141         struct drm_bridge               bridge;
 142         struct drm_connector            connector;
 143         struct dentry                   *debugfs;
 144         struct device_node              *host_node;
 145         struct mipi_dsi_device          *dsi;
 146         struct clk                      *refclk;
 147         struct drm_panel                *panel;
 148         struct gpio_desc                *enable_gpio;
 149         struct regulator_bulk_data      supplies[SN_REGULATOR_SUPPLY_NUM];
 150         int                             dp_lanes;
 151         u8                              ln_assign;
 152         u8                              ln_polrs;
 153
 154 #if defined(CONFIG_OF_GPIO)
 155         struct gpio_chip                gchip;
 156         DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS);
 157 #endif
 158 };
 159
 160 static const struct regmap_range ti_sn_bridge_volatile_ranges[] = {
 161         { .range_min = 0, .range_max = 0xFF },
 162 };
 163
 164 static const struct regmap_access_table ti_sn_bridge_volatile_table = {
 165         .yes_ranges = ti_sn_bridge_volatile_ranges,
 166         .n_yes_ranges = ARRAY_SIZE(ti_sn_bridge_volatile_ranges),
 167 };
 168
 169 static const struct regmap_config ti_sn_bridge_regmap_config = {
 170         .reg_bits = 8,
 171         .val_bits = 8,
 172         .volatile_table = &ti_sn_bridge_volatile_table,
 173         .cache_type = REGCACHE_NONE,
 174 };
 175
 176 static void ti_sn_bridge_write_u16(struct ti_sn_bridge *pdata,
 177                                    unsigned int reg, u16 val)
 178 {
 179         regmap_write(pdata->regmap, reg, val & 0xFF);
 180         regmap_write(pdata->regmap, reg + 1, val >> 8);
 181 }
 182
 183 static int __maybe_unused ti_sn_bridge_resume(struct device *dev)
 184 {
 185         struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
 186         int ret;
 187
 188         ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
 189         if (ret) {
 190                 DRM_ERROR("failed to enable supplies %d\n", ret);
 191                 return ret;
 192         }
 193
 194         gpiod_set_value(pdata->enable_gpio, 1);
 195
 196         return ret;
 197 }
 198
 199 static int __maybe_unused ti_sn_bridge_suspend(struct device *dev)
 200 {
 201         struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
 202         int ret;
 203
 204         gpiod_set_value(pdata->enable_gpio, 0);
 205
 206         ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
 207         if (ret)
 208                 DRM_ERROR("failed to disable supplies %d\n", ret);
 209
 210         return ret;
 211 }
 212
 213 static const struct dev_pm_ops ti_sn_bridge_pm_ops = {
 214         SET_RUNTIME_PM_OPS(ti_sn_bridge_suspend, ti_sn_bridge_resume, NULL)
 215         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 216                                 pm_runtime_force_resume)
 217 };
 218
 219 static int status_show(struct seq_file *s, void *data)
 220 {
 221         struct ti_sn_bridge *pdata = s->private;
 222         unsigned int reg, val;
 223
 224         seq_puts(s, "STATUS REGISTERS:\n");
 225
 226         pm_runtime_get_sync(pdata->dev);
 227
 228         /* IRQ Status Registers, see Table 31 in datasheet */
 229         for (reg = 0xf0; reg <= 0xf8; reg++) {
 230                 regmap_read(pdata->regmap, reg, &val);
 231                 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val);
 232         }
 233
 234         pm_runtime_put(pdata->dev);
 235
 236         return 0;
 237 }
 238
 239 DEFINE_SHOW_ATTRIBUTE(status);
 240
 241 static void ti_sn_debugfs_init(struct ti_sn_bridge *pdata)
 242 {
 243         pdata->debugfs = debugfs_create_dir(dev_name(pdata->dev), NULL);
 244
 245         debugfs_create_file("status", 0600, pdata->debugfs, pdata,
 246                         &status_fops);
 247 }
 248
 249 static void ti_sn_debugfs_remove(struct ti_sn_bridge *pdata)
 250 {
 251         debugfs_remove_recursive(pdata->debugfs);
 252         pdata->debugfs = NULL;
 253 }
 254
 255 /* Connector funcs */
 256 static struct ti_sn_bridge *
 257 connector_to_ti_sn_bridge(struct drm_connector *connector)
 258 {
 259         return container_of(connector, struct ti_sn_bridge, connector);
 260 }
 261
 262 static int ti_sn_bridge_connector_get_modes(struct drm_connector *connector)
 263 {
 264         struct ti_sn_bridge *pdata = connector_to_ti_sn_bridge(connector);
 265
 266         return drm_panel_get_modes(pdata->panel, connector);
 267 }
 268
 269 static enum drm_mode_status
 270 ti_sn_bridge_connector_mode_valid(struct drm_connector *connector,
 271                                   struct drm_display_mode *mode)
 272 {
 273         /* maximum supported resolution is 4K at 60 fps */
 274         if (mode->clock > 594000)
 275                 return MODE_CLOCK_HIGH;
 276
 277         return MODE_OK;
 278 }
 279
 280 static struct drm_connector_helper_funcs ti_sn_bridge_connector_helper_funcs = {
 281         .get_modes = ti_sn_bridge_connector_get_modes,
 282         .mode_valid = ti_sn_bridge_connector_mode_valid,
 283 };
 284
 285 static enum drm_connector_status
 286 ti_sn_bridge_connector_detect(struct drm_connector *connector, bool force)
 287 {
 288         /**
 289          * TODO: Currently if drm_panel is present, then always
 290          * return the status as connected. Need to add support to detect
 291          * device state for hot pluggable scenarios.
 292          */
 293         return connector_status_connected;
 294 }
 295
 296 static const struct drm_connector_funcs ti_sn_bridge_connector_funcs = {
 297         .fill_modes = drm_helper_probe_single_connector_modes,
 298         .detect = ti_sn_bridge_connector_detect,
 299         .destroy = drm_connector_cleanup,
 300         .reset = drm_atomic_helper_connector_reset,
 301         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 302         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 303 };
 304
 305 static struct ti_sn_bridge *bridge_to_ti_sn_bridge(struct drm_bridge *bridge)
 306 {
 307         return container_of(bridge, struct ti_sn_bridge, bridge);
 308 }
 309
 310 static int ti_sn_bridge_parse_regulators(struct ti_sn_bridge *pdata)
 311 {
 312         unsigned int i;
 313         const char * const ti_sn_bridge_supply_names[] = {
 314                 "vcca", "vcc", "vccio", "vpll",
 315         };
 316
 317         for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
 318                 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
 319
 320         return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
 321                                        pdata->supplies);
 322 }
 323
 324 static int ti_sn_bridge_attach(struct drm_bridge *bridge,
 325                                enum drm_bridge_attach_flags flags)
 326 {
 327         int ret, val;
 328         struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
 329         struct mipi_dsi_host *host;
 330         struct mipi_dsi_device *dsi;
 331         const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
 332                                                    .channel = 0,
 333                                                    .node = NULL,
 334                                                  };
 335
 336         if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
 337                 DRM_ERROR("Fix bridge driver to make connector optional!");
 338                 return -EINVAL;
 339         }
 340
 341         ret = drm_connector_init(bridge->dev, &pdata->connector,
 342                                  &ti_sn_bridge_connector_funcs,
 343                                  DRM_MODE_CONNECTOR_eDP);
 344         if (ret) {
 345                 DRM_ERROR("Failed to initialize connector with drm\n");
 346                 return ret;
 347         }
 348
 349         drm_connector_helper_add(&pdata->connector,
 350                                  &ti_sn_bridge_connector_helper_funcs);
 351         drm_connector_attach_encoder(&pdata->connector, bridge->encoder);
 352
 353         /*
 354          * TODO: ideally finding host resource and dsi dev registration needs
 355          * to be done in bridge probe. But some existing DSI host drivers will
 356          * wait for any of the drm_bridge/drm_panel to get added to the global
 357          * bridge/panel list, before completing their probe. So if we do the
 358          * dsi dev registration part in bridge probe, before populating in
 359          * the global bridge list, then it will cause deadlock as dsi host probe
 360          * will never complete, neither our bridge probe. So keeping it here
 361          * will satisfy most of the existing host drivers. Once the host driver
 362          * is fixed we can move the below code to bridge probe safely.
 363          */
 364         host = of_find_mipi_dsi_host_by_node(pdata->host_node);
 365         if (!host) {
 366                 DRM_ERROR("failed to find dsi host\n");
 367                 ret = -ENODEV;
 368                 goto err_dsi_host;
 369         }
 370
 371         dsi = mipi_dsi_device_register_full(host, &info);
 372         if (IS_ERR(dsi)) {
 373                 DRM_ERROR("failed to create dsi device\n");
 374                 ret = PTR_ERR(dsi);
 375                 goto err_dsi_host;
 376         }
 377
 378         /* TODO: setting to 4 MIPI lanes always for now */
 379         dsi->lanes = 4;
 380         dsi->format = MIPI_DSI_FMT_RGB888;
 381         dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
 382
 383         /* check if continuous dsi clock is required or not */
 384         pm_runtime_get_sync(pdata->dev);
 385         regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
 386         pm_runtime_put(pdata->dev);
 387         if (!(val & DPPLL_CLK_SRC_DSICLK))
 388                 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
 389
 390         ret = mipi_dsi_attach(dsi);
 391         if (ret < 0) {
 392                 DRM_ERROR("failed to attach dsi to host\n");
 393                 goto err_dsi_attach;
 394         }
 395         pdata->dsi = dsi;
 396
 397         return 0;
 398
 399 err_dsi_attach:
 400         mipi_dsi_device_unregister(dsi);
 401 err_dsi_host:
 402         drm_connector_cleanup(&pdata->connector);
 403         return ret;
 404 }
 405
 406 static void ti_sn_bridge_disable(struct drm_bridge *bridge)
 407 {
 408         struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
 409
 410         drm_panel_disable(pdata->panel);
 411
 412         /* disable video stream */
 413         regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
 414         /* semi auto link training mode OFF */
 415         regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
 416         /* disable DP PLL */
 417         regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
 418
 419         drm_panel_unprepare(pdata->panel);
 420 }
 421
 422 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn_bridge *pdata)
 423 {
 424         u32 bit_rate_khz, clk_freq_khz;
 425         struct drm_display_mode *mode =
 426                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 427
 428         bit_rate_khz = mode->clock *
 429                         mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
 430         clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
 431
 432         return clk_freq_khz;
 433 }
 434
 435 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
 436 static const u32 ti_sn_bridge_refclk_lut[] = {
 437         12000000,
 438         19200000,
 439         26000000,
 440         27000000,
 441         38400000,
 442 };
 443
 444 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
 445 static const u32 ti_sn_bridge_dsiclk_lut[] = {
 446         468000000,
 447         384000000,
 448         416000000,
 449         486000000,
 450         460800000,
 451 };
 452
 453 static void ti_sn_bridge_set_refclk_freq(struct ti_sn_bridge *pdata)
 454 {
 455         int i;
 456         u32 refclk_rate;
 457         const u32 *refclk_lut;
 458         size_t refclk_lut_size;
 459
 460         if (pdata->refclk) {
 461                 refclk_rate = clk_get_rate(pdata->refclk);
 462                 refclk_lut = ti_sn_bridge_refclk_lut;
 463                 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
 464                 clk_prepare_enable(pdata->refclk);
 465         } else {
 466                 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
 467                 refclk_lut = ti_sn_bridge_dsiclk_lut;
 468                 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
 469         }
 470
 471         /* for i equals to refclk_lut_size means default frequency */
 472         for (i = 0; i < refclk_lut_size; i++)
 473                 if (refclk_lut[i] == refclk_rate)
 474                         break;
 475
 476         regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
 477                            REFCLK_FREQ(i));
 478 }
 479
 480 static void ti_sn_bridge_set_dsi_rate(struct ti_sn_bridge *pdata)
 481 {
 482         unsigned int bit_rate_mhz, clk_freq_mhz;
 483         unsigned int val;
 484         struct drm_display_mode *mode =
 485                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 486
 487         /* set DSIA clk frequency */
 488         bit_rate_mhz = (mode->clock / 1000) *
 489                         mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
 490         clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
 491
 492         /* for each increment in val, frequency increases by 5MHz */
 493         val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
 494                 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
 495         regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
 496 }
 497
 498 static unsigned int ti_sn_bridge_get_bpp(struct ti_sn_bridge *pdata)
 499 {
 500         if (pdata->connector.display_info.bpc <= 6)
 501                 return 18;
 502         else
 503                 return 24;
 504 }
 505
 506 /*
 507  * LUT index corresponds to register value and
 508  * LUT values corresponds to dp data rate supported
 509  * by the bridge in Mbps unit.
 510  */
 511 static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
 512         0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
 513 };
 514
 515 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn_bridge *pdata)
 516 {
 517         unsigned int bit_rate_khz, dp_rate_mhz;
 518         unsigned int i;
 519         struct drm_display_mode *mode =
 520                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 521
 522         /* Calculate minimum bit rate based on our pixel clock. */
 523         bit_rate_khz = mode->clock * ti_sn_bridge_get_bpp(pdata);
 524
 525         /* Calculate minimum DP data rate, taking 80% as per DP spec */
 526         dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
 527                                    1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
 528
 529         for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
 530                 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz)
 531                         break;
 532
 533         return i;
 534 }
 535
 536 static void ti_sn_bridge_read_valid_rates(struct ti_sn_bridge *pdata,
 537                                           bool rate_valid[])
 538 {
 539         unsigned int rate_per_200khz;
 540         unsigned int rate_mhz;
 541         u8 dpcd_val;
 542         int ret;
 543         int i, j;
 544
 545         ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val);
 546         if (ret != 1) {
 547                 DRM_DEV_ERROR(pdata->dev,
 548                               "Can't read eDP rev (%d), assuming 1.1\n", ret);
 549                 dpcd_val = DP_EDP_11;
 550         }
 551
 552         if (dpcd_val >= DP_EDP_14) {
 553                 /* eDP 1.4 devices must provide a custom table */
 554                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
 555
 556                 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES,
 557                                        sink_rates, sizeof(sink_rates));
 558
 559                 if (ret != sizeof(sink_rates)) {
 560                         DRM_DEV_ERROR(pdata->dev,
 561                                 "Can't read supported rate table (%d)\n", ret);
 562
 563                         /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */
 564                         memset(sink_rates, 0, sizeof(sink_rates));
 565                 }
 566
 567                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
 568                         rate_per_200khz = le16_to_cpu(sink_rates[i]);
 569
 570                         if (!rate_per_200khz)
 571                                 break;
 572
 573                         rate_mhz = rate_per_200khz * 200 / 1000;
 574                         for (j = 0;
 575                              j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
 576                              j++) {
 577                                 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz)
 578                                         rate_valid[j] = true;
 579                         }
 580                 }
 581
 582                 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) {
 583                         if (rate_valid[i])
 584                                 return;
 585                 }
 586                 DRM_DEV_ERROR(pdata->dev,
 587                               "No matching eDP rates in table; falling back\n");
 588         }
 589
 590         /* On older versions best we can do is use DP_MAX_LINK_RATE */
 591         ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val);
 592         if (ret != 1) {
 593                 DRM_DEV_ERROR(pdata->dev,
 594                               "Can't read max rate (%d); assuming 5.4 GHz\n",
 595                               ret);
 596                 dpcd_val = DP_LINK_BW_5_4;
 597         }
 598
 599         switch (dpcd_val) {
 600         default:
 601                 DRM_DEV_ERROR(pdata->dev,
 602                               "Unexpected max rate (%#x); assuming 5.4 GHz\n",
 603                               (int)dpcd_val);
 604                 /* fall through */
 605         case DP_LINK_BW_5_4:
 606                 rate_valid[7] = 1;
 607                 /* fall through */
 608         case DP_LINK_BW_2_7:
 609                 rate_valid[4] = 1;
 610                 /* fall through */
 611         case DP_LINK_BW_1_62:
 612                 rate_valid[1] = 1;
 613                 break;
 614         }
 615 }
 616
 617 static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata)
 618 {
 619         struct drm_display_mode *mode =
 620                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 621         u8 hsync_polarity = 0, vsync_polarity = 0;
 622
 623         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 624                 hsync_polarity = CHA_HSYNC_POLARITY;
 625         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 626                 vsync_polarity = CHA_VSYNC_POLARITY;
 627
 628         ti_sn_bridge_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
 629                                mode->hdisplay);
 630         ti_sn_bridge_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
 631                                mode->vdisplay);
 632         regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
 633                      (mode->hsync_end - mode->hsync_start) & 0xFF);
 634         regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
 635                      (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
 636                      hsync_polarity);
 637         regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
 638                      (mode->vsync_end - mode->vsync_start) & 0xFF);
 639         regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
 640                      (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
 641                      vsync_polarity);
 642
 643         regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
 644                      (mode->htotal - mode->hsync_end) & 0xFF);
 645         regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
 646                      (mode->vtotal - mode->vsync_end) & 0xFF);
 647
 648         regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
 649                      (mode->hsync_start - mode->hdisplay) & 0xFF);
 650         regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
 651                      (mode->vsync_start - mode->vdisplay) & 0xFF);
 652
 653         usleep_range(10000, 10500); /* 10ms delay recommended by spec */
 654 }
 655
 656 static unsigned int ti_sn_get_max_lanes(struct ti_sn_bridge *pdata)
 657 {
 658         u8 data;
 659         int ret;
 660
 661         ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data);
 662         if (ret != 1) {
 663                 DRM_DEV_ERROR(pdata->dev,
 664                               "Can't read lane count (%d); assuming 4\n", ret);
 665                 return 4;
 666         }
 667
 668         return data & DP_LANE_COUNT_MASK;
 669 }
 670
 671 static int ti_sn_link_training(struct ti_sn_bridge *pdata, int dp_rate_idx,
 672                                const char **last_err_str)
 673 {
 674         unsigned int val;
 675         int ret;
 676
 677         /* set dp clk frequency value */
 678         regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
 679                            DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx));
 680
 681         /* enable DP PLL */
 682         regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
 683
 684         ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
 685                                        val & DPPLL_SRC_DP_PLL_LOCK, 1000,
 686                                        50 * 1000);
 687         if (ret) {
 688                 *last_err_str = "DP_PLL_LOCK polling failed";
 689                 goto exit;
 690         }
 691
 692         /* Semi auto link training mode */
 693         regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
 694         ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
 695                                        val == ML_TX_MAIN_LINK_OFF ||
 696                                        val == ML_TX_NORMAL_MODE, 1000,
 697                                        500 * 1000);
 698         if (ret) {
 699                 *last_err_str = "Training complete polling failed";
 700         } else if (val == ML_TX_MAIN_LINK_OFF) {
 701                 *last_err_str = "Link training failed, link is off";
 702                 ret = -EIO;
 703         }
 704
 705 exit:
 706         /* Disable the PLL if we failed */
 707         if (ret)
 708                 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
 709
 710         return ret;
 711 }
 712
 713 static void ti_sn_bridge_enable(struct drm_bridge *bridge)
 714 {
 715         struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
 716         bool rate_valid[ARRAY_SIZE(ti_sn_bridge_dp_rate_lut)] = { };
 717         const char *last_err_str = "No supported DP rate";
 718         int dp_rate_idx;
 719         unsigned int val;
 720         int ret = -EINVAL;
 721         int max_dp_lanes;
 722
 723         max_dp_lanes = ti_sn_get_max_lanes(pdata);
 724         pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes);
 725
 726         /* DSI_A lane config */
 727         val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes);
 728         regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
 729                            CHA_DSI_LANES_MASK, val);
 730
 731         regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign);
 732         regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK,
 733                            pdata->ln_polrs << LN_POLRS_OFFSET);
 734
 735         /* set dsi clk frequency value */
 736         ti_sn_bridge_set_dsi_rate(pdata);
 737
 738         /**
 739          * The SN65DSI86 only supports ASSR Display Authentication method and
 740          * this method is enabled by default. An eDP panel must support this
 741          * authentication method. We need to enable this method in the eDP panel
 742          * at DisplayPort address 0x0010A prior to link training.
 743          */
 744         drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
 745                            DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
 746
 747         /* Set the DP output format (18 bpp or 24 bpp) */
 748         val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0;
 749         regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
 750
 751         /* DP lane config */
 752         val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
 753         regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
 754                            val);
 755
 756         ti_sn_bridge_read_valid_rates(pdata, rate_valid);
 757
 758         /* Train until we run out of rates */
 759         for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata);
 760              dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
 761              dp_rate_idx++) {
 762                 if (!rate_valid[dp_rate_idx])
 763                         continue;
 764
 765                 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str);
 766                 if (!ret)
 767                         break;
 768         }
 769         if (ret) {
 770                 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret);
 771                 return;
 772         }
 773
 774         /* config video parameters */
 775         ti_sn_bridge_set_video_timings(pdata);
 776
 777         /* enable video stream */
 778         regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
 779                            VSTREAM_ENABLE);
 780
 781         drm_panel_enable(pdata->panel);
 782 }
 783
 784 static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge)
 785 {
 786         struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
 787
 788         pm_runtime_get_sync(pdata->dev);
 789
 790         /* configure bridge ref_clk */
 791         ti_sn_bridge_set_refclk_freq(pdata);
 792
 793         /*
 794          * HPD on this bridge chip is a bit useless.  This is an eDP bridge
 795          * so the HPD is an internal signal that's only there to signal that
 796          * the panel is done powering up.  ...but the bridge chip debounces
 797          * this signal by between 100 ms and 400 ms (depending on process,
 798          * voltage, and temperate--I measured it at about 200 ms).  One
 799          * particular panel asserted HPD 84 ms after it was powered on meaning
 800          * that we saw HPD 284 ms after power on.  ...but the same panel said
 801          * that instead of looking at HPD you could just hardcode a delay of
 802          * 200 ms.  We'll assume that the panel driver will have the hardcoded
 803          * delay in its prepare and always disable HPD.
 804          *
 805          * If HPD somehow makes sense on some future panel we'll have to
 806          * change this to be conditional on someone specifying that HPD should
 807          * be used.
 808          */
 809         regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
 810                            HPD_DISABLE);
 811
 812         drm_panel_prepare(pdata->panel);
 813 }
 814
 815 static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
 816 {
 817         struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
 818
 819         if (pdata->refclk)
 820                 clk_disable_unprepare(pdata->refclk);
 821
 822         pm_runtime_put_sync(pdata->dev);
 823 }
 824
 825 static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
 826         .attach = ti_sn_bridge_attach,
 827         .pre_enable = ti_sn_bridge_pre_enable,
 828         .enable = ti_sn_bridge_enable,
 829         .disable = ti_sn_bridge_disable,
 830         .post_disable = ti_sn_bridge_post_disable,
 831 };
 832
 833 static struct ti_sn_bridge *aux_to_ti_sn_bridge(struct drm_dp_aux *aux)
 834 {
 835         return container_of(aux, struct ti_sn_bridge, aux);
 836 }
 837
 838 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
 839                                   struct drm_dp_aux_msg *msg)
 840 {
 841         struct ti_sn_bridge *pdata = aux_to_ti_sn_bridge(aux);
 842         u32 request = msg->request & ~DP_AUX_I2C_MOT;
 843         u32 request_val = AUX_CMD_REQ(msg->request);
 844         u8 *buf = (u8 *)msg->buffer;
 845         unsigned int val;
 846         int ret, i;
 847
 848         if (msg->size > SN_AUX_MAX_PAYLOAD_BYTES)
 849                 return -EINVAL;
 850
 851         switch (request) {
 852         case DP_AUX_NATIVE_WRITE:
 853         case DP_AUX_I2C_WRITE:
 854         case DP_AUX_NATIVE_READ:
 855         case DP_AUX_I2C_READ:
 856                 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
 857                 break;
 858         default:
 859                 return -EINVAL;
 860         }
 861
 862         regmap_write(pdata->regmap, SN_AUX_ADDR_19_16_REG,
 863                      (msg->address >> 16) & 0xF);
 864         regmap_write(pdata->regmap, SN_AUX_ADDR_15_8_REG,
 865                      (msg->address >> 8) & 0xFF);
 866         regmap_write(pdata->regmap, SN_AUX_ADDR_7_0_REG, msg->address & 0xFF);
 867
 868         regmap_write(pdata->regmap, SN_AUX_LENGTH_REG, msg->size);
 869
 870         if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE) {
 871                 for (i = 0; i < msg->size; i++)
 872                         regmap_write(pdata->regmap, SN_AUX_WDATA_REG(i),
 873                                      buf[i]);
 874         }
 875
 876         /* Clear old status bits before start so we don't get confused */
 877         regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG,
 878                      AUX_IRQ_STATUS_NAT_I2C_FAIL |
 879                      AUX_IRQ_STATUS_AUX_RPLY_TOUT |
 880                      AUX_IRQ_STATUS_AUX_SHORT);
 881
 882         regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
 883
 884         ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
 885                                        !(val & AUX_CMD_SEND), 200,
 886                                        50 * 1000);
 887         if (ret)
 888                 return ret;
 889
 890         ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
 891         if (ret)
 892                 return ret;
 893         else if ((val & AUX_IRQ_STATUS_NAT_I2C_FAIL)
 894                  || (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT)
 895                  || (val & AUX_IRQ_STATUS_AUX_SHORT))
 896                 return -ENXIO;
 897
 898         if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
 899                 return msg->size;
 900
 901         for (i = 0; i < msg->size; i++) {
 902                 unsigned int val;
 903                 ret = regmap_read(pdata->regmap, SN_AUX_RDATA_REG(i),
 904                                   &val);
 905                 if (ret)
 906                         return ret;
 907
 908                 WARN_ON(val & ~0xFF);
 909                 buf[i] = (u8)(val & 0xFF);
 910         }
 911
 912         return msg->size;
 913 }
 914
 915 static int ti_sn_bridge_parse_dsi_host(struct ti_sn_bridge *pdata)
 916 {
 917         struct device_node *np = pdata->dev->of_node;
 918
 919         pdata->host_node = of_graph_get_remote_node(np, 0, 0);
 920
 921         if (!pdata->host_node) {
 922                 DRM_ERROR("remote dsi host node not found\n");
 923                 return -ENODEV;
 924         }
 925
 926         return 0;
 927 }
 928
 929 #if defined(CONFIG_OF_GPIO)
 930
 931 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip,
 932                                  const struct of_phandle_args *gpiospec,
 933                                  u32 *flags)
 934 {
 935         if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells))
 936                 return -EINVAL;
 937
 938         if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1)
 939                 return -EINVAL;
 940
 941         if (flags)
 942                 *flags = gpiospec->args[1];
 943
 944         return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET;
 945 }
 946
 947 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip,
 948                                            unsigned int offset)
 949 {
 950         struct ti_sn_bridge *pdata = gpiochip_get_data(chip);
 951
 952         /*
 953          * We already have to keep track of the direction because we use
 954          * that to figure out whether we've powered the device.  We can
 955          * just return that rather than (maybe) powering up the device
 956          * to ask its direction.
 957          */
 958         return test_bit(offset, pdata->gchip_output) ?
 959                 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
 960 }
 961
 962 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset)
 963 {
 964         struct ti_sn_bridge *pdata = gpiochip_get_data(chip);
 965         unsigned int val;
 966         int ret;
 967
 968         /*
 969          * When the pin is an input we don't forcibly keep the bridge
 970          * powered--we just power it on to read the pin.  NOTE: part of
 971          * the reason this works is that the bridge defaults (when
 972          * powered back on) to all 4 GPIOs being configured as GPIO input.
 973          * Also note that if something else is keeping the chip powered the
 974          * pm_runtime functions are lightweight increments of a refcount.
 975          */
 976         pm_runtime_get_sync(pdata->dev);
 977         ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val);
 978         pm_runtime_put(pdata->dev);
 979
 980         if (ret)
 981                 return ret;
 982
 983         return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset));
 984 }
 985
 986 static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset,
 987                                   int val)
 988 {
 989         struct ti_sn_bridge *pdata = gpiochip_get_data(chip);
 990         int ret;
 991
 992         if (!test_bit(offset, pdata->gchip_output)) {
 993                 dev_err(pdata->dev, "Ignoring GPIO set while input\n");
 994                 return;
 995         }
 996
 997         val &= 1;
 998         ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG,
 999                                  BIT(SN_GPIO_OUTPUT_SHIFT + offset),
1000                                  val << (SN_GPIO_OUTPUT_SHIFT + offset));
1001         if (ret)
1002                 dev_warn(pdata->dev,
1003                          "Failed to set bridge GPIO %u: %d\n", offset, ret);
1004 }
1005
1006 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip,
1007                                              unsigned int offset)
1008 {
1009         struct ti_sn_bridge *pdata = gpiochip_get_data(chip);
1010         int shift = offset * 2;
1011         int ret;
1012
1013         if (!test_and_clear_bit(offset, pdata->gchip_output))
1014                 return 0;
1015
1016         ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1017                                  SN_GPIO_MUX_MASK << shift,
1018                                  SN_GPIO_MUX_INPUT << shift);
1019         if (ret) {
1020                 set_bit(offset, pdata->gchip_output);
1021                 return ret;
1022         }
1023
1024         /*
1025          * NOTE: if nobody else is powering the device this may fully power
1026          * it off and when it comes back it will have lost all state, but
1027          * that's OK because the default is input and we're now an input.
1028          */
1029         pm_runtime_put(pdata->dev);
1030
1031         return 0;
1032 }
1033
1034 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip,
1035                                               unsigned int offset, int val)
1036 {
1037         struct ti_sn_bridge *pdata = gpiochip_get_data(chip);
1038         int shift = offset * 2;
1039         int ret;
1040
1041         if (test_and_set_bit(offset, pdata->gchip_output))
1042                 return 0;
1043
1044         pm_runtime_get_sync(pdata->dev);
1045
1046         /* Set value first to avoid glitching */
1047         ti_sn_bridge_gpio_set(chip, offset, val);
1048
1049         /* Set direction */
1050         ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1051                                  SN_GPIO_MUX_MASK << shift,
1052                                  SN_GPIO_MUX_OUTPUT << shift);
1053         if (ret) {
1054                 clear_bit(offset, pdata->gchip_output);
1055                 pm_runtime_put(pdata->dev);
1056         }
1057
1058         return ret;
1059 }
1060
1061 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset)
1062 {
1063         /* We won't keep pm_runtime if we're input, so switch there on free */
1064         ti_sn_bridge_gpio_direction_input(chip, offset);
1065 }
1066
1067 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = {
1068         "GPIO1", "GPIO2", "GPIO3", "GPIO4"
1069 };
1070
1071 static int ti_sn_setup_gpio_controller(struct ti_sn_bridge *pdata)
1072 {
1073         int ret;
1074
1075         /* Only init if someone is going to use us as a GPIO controller */
1076         if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller"))
1077                 return 0;
1078
1079         pdata->gchip.label = dev_name(pdata->dev);
1080         pdata->gchip.parent = pdata->dev;
1081         pdata->gchip.owner = THIS_MODULE;
1082         pdata->gchip.of_xlate = tn_sn_bridge_of_xlate;
1083         pdata->gchip.of_gpio_n_cells = 2;
1084         pdata->gchip.free = ti_sn_bridge_gpio_free;
1085         pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction;
1086         pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input;
1087         pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output;
1088         pdata->gchip.get = ti_sn_bridge_gpio_get;
1089         pdata->gchip.set = ti_sn_bridge_gpio_set;
1090         pdata->gchip.can_sleep = true;
1091         pdata->gchip.names = ti_sn_bridge_gpio_names;
1092         pdata->gchip.ngpio = SN_NUM_GPIOS;
1093         pdata->gchip.base = -1;
1094         ret = devm_gpiochip_add_data(pdata->dev, &pdata->gchip, pdata);
1095         if (ret)
1096                 dev_err(pdata->dev, "can't add gpio chip\n");
1097
1098         return ret;
1099 }
1100
1101 #else
1102
1103 static inline int ti_sn_setup_gpio_controller(struct ti_sn_bridge *pdata)
1104 {
1105         return 0;
1106 }
1107
1108 #endif
1109
1110 static void ti_sn_bridge_parse_lanes(struct ti_sn_bridge *pdata,
1111                                      struct device_node *np)
1112 {
1113         u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 };
1114         u32 lane_polarities[SN_MAX_DP_LANES] = { };
1115         struct device_node *endpoint;
1116         u8 ln_assign = 0;
1117         u8 ln_polrs = 0;
1118         int dp_lanes;
1119         int i;
1120
1121         /*
1122          * Read config from the device tree about lane remapping and lane
1123          * polarities.  These are optional and we assume identity map and
1124          * normal polarity if nothing is specified.  It's OK to specify just
1125          * data-lanes but not lane-polarities but not vice versa.
1126          *
1127          * Error checking is light (we just make sure we don't crash or
1128          * buffer overrun) and we assume dts is well formed and specifying
1129          * mappings that the hardware supports.
1130          */
1131         endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1132         dp_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
1133         if (dp_lanes > 0 && dp_lanes <= SN_MAX_DP_LANES) {
1134                 of_property_read_u32_array(endpoint, "data-lanes",
1135                                            lane_assignments, dp_lanes);
1136                 of_property_read_u32_array(endpoint, "lane-polarities",
1137                                            lane_polarities, dp_lanes);
1138         } else {
1139                 dp_lanes = SN_MAX_DP_LANES;
1140         }
1141         of_node_put(endpoint);
1142
1143         /*
1144          * Convert into register format.  Loop over all lanes even if
1145          * data-lanes had fewer elements so that we nicely initialize
1146          * the LN_ASSIGN register.
1147          */
1148         for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) {
1149                 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i];
1150                 ln_polrs = ln_polrs << 1 | lane_polarities[i];
1151         }
1152
1153         /* Stash in our struct for when we power on */
1154         pdata->dp_lanes = dp_lanes;
1155         pdata->ln_assign = ln_assign;
1156         pdata->ln_polrs = ln_polrs;
1157 }
1158
1159 static int ti_sn_bridge_probe(struct i2c_client *client,
1160                               const struct i2c_device_id *id)
1161 {
1162         struct ti_sn_bridge *pdata;
1163         int ret;
1164
1165         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1166                 DRM_ERROR("device doesn't support I2C\n");
1167                 return -ENODEV;
1168         }
1169
1170         pdata = devm_kzalloc(&client->dev, sizeof(struct ti_sn_bridge),
1171                              GFP_KERNEL);
1172         if (!pdata)
1173                 return -ENOMEM;
1174
1175         pdata->regmap = devm_regmap_init_i2c(client,
1176                                              &ti_sn_bridge_regmap_config);
1177         if (IS_ERR(pdata->regmap)) {
1178                 DRM_ERROR("regmap i2c init failed\n");
1179                 return PTR_ERR(pdata->regmap);
1180         }
1181
1182         pdata->dev = &client->dev;
1183
1184         ret = drm_of_find_panel_or_bridge(pdata->dev->of_node, 1, 0,
1185                                           &pdata->panel, NULL);
1186         if (ret) {
1187                 DRM_ERROR("could not find any panel node\n");
1188                 return ret;
1189         }
1190
1191         dev_set_drvdata(&client->dev, pdata);
1192
1193         pdata->enable_gpio = devm_gpiod_get(pdata->dev, "enable",
1194                                             GPIOD_OUT_LOW);
1195         if (IS_ERR(pdata->enable_gpio)) {
1196                 DRM_ERROR("failed to get enable gpio from DT\n");
1197                 ret = PTR_ERR(pdata->enable_gpio);
1198                 return ret;
1199         }
1200
1201         ti_sn_bridge_parse_lanes(pdata, client->dev.of_node);
1202
1203         ret = ti_sn_bridge_parse_regulators(pdata);
1204         if (ret) {
1205                 DRM_ERROR("failed to parse regulators\n");
1206                 return ret;
1207         }
1208
1209         pdata->refclk = devm_clk_get(pdata->dev, "refclk");
1210         if (IS_ERR(pdata->refclk)) {
1211                 ret = PTR_ERR(pdata->refclk);
1212                 if (ret == -EPROBE_DEFER)
1213                         return ret;
1214                 DRM_DEBUG_KMS("refclk not found\n");
1215                 pdata->refclk = NULL;
1216         }
1217
1218         ret = ti_sn_bridge_parse_dsi_host(pdata);
1219         if (ret)
1220                 return ret;
1221
1222         pm_runtime_enable(pdata->dev);
1223
1224         ret = ti_sn_setup_gpio_controller(pdata);
1225         if (ret) {
1226                 pm_runtime_disable(pdata->dev);
1227                 return ret;
1228         }
1229
1230         i2c_set_clientdata(client, pdata);
1231
1232         pdata->aux.name = "ti-sn65dsi86-aux";
1233         pdata->aux.dev = pdata->dev;
1234         pdata->aux.transfer = ti_sn_aux_transfer;
1235         drm_dp_aux_register(&pdata->aux);
1236
1237         pdata->bridge.funcs = &ti_sn_bridge_funcs;
1238         pdata->bridge.of_node = client->dev.of_node;
1239
1240         drm_bridge_add(&pdata->bridge);
1241
1242         ti_sn_debugfs_init(pdata);
1243
1244         return 0;
1245 }
1246
1247 static int ti_sn_bridge_remove(struct i2c_client *client)
1248 {
1249         struct ti_sn_bridge *pdata = i2c_get_clientdata(client);
1250
1251         if (!pdata)
1252                 return -EINVAL;
1253
1254         ti_sn_debugfs_remove(pdata);
1255
1256         of_node_put(pdata->host_node);
1257
1258         pm_runtime_disable(pdata->dev);
1259
1260         if (pdata->dsi) {
1261                 mipi_dsi_detach(pdata->dsi);
1262                 mipi_dsi_device_unregister(pdata->dsi);
1263         }
1264
1265         drm_bridge_remove(&pdata->bridge);
1266
1267         return 0;
1268 }
1269
1270 static struct i2c_device_id ti_sn_bridge_id[] = {
1271         { "ti,sn65dsi86", 0},
1272         {},
1273 };
1274 MODULE_DEVICE_TABLE(i2c, ti_sn_bridge_id);
1275
1276 static const struct of_device_id ti_sn_bridge_match_table[] = {
1277         {.compatible = "ti,sn65dsi86"},
1278         {},
1279 };
1280 MODULE_DEVICE_TABLE(of, ti_sn_bridge_match_table);
1281
1282 static struct i2c_driver ti_sn_bridge_driver = {
1283         .driver = {
1284                 .name = "ti_sn65dsi86",
1285                 .of_match_table = ti_sn_bridge_match_table,
1286                 .pm = &ti_sn_bridge_pm_ops,
1287         },
1288         .probe = ti_sn_bridge_probe,
1289         .remove = ti_sn_bridge_remove,
1290         .id_table = ti_sn_bridge_id,
1291 };
1292 module_i2c_driver(ti_sn_bridge_driver);
1293
1294 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>");
1295 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
1296 MODULE_LICENSE("GPL v2");