drivers/gpu/drm/bridge/ti-sn65dsi86.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
   5  */
   6
   7 #include <linux/atomic.h>
   8 #include <linux/auxiliary_bus.h>
   9 #include <linux/bitfield.h>
  10 #include <linux/bits.h>
  11 #include <linux/clk.h>
  12 #include <linux/debugfs.h>
  13 #include <linux/gpio/consumer.h>
  14 #include <linux/gpio/driver.h>
  15 #include <linux/i2c.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/module.h>
  18 #include <linux/of_graph.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/pwm.h>
  21 #include <linux/regmap.h>
  22 #include <linux/regulator/consumer.h>
  23
  24 #include <asm/unaligned.h>
  25
  26 #include <drm/drm_atomic.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_bridge.h>
  29 #include <drm/drm_dp_aux_bus.h>
  30 #include <drm/drm_dp_helper.h>
  31 #include <drm/drm_mipi_dsi.h>
  32 #include <drm/drm_of.h>
  33 #include <drm/drm_panel.h>
  34 #include <drm/drm_print.h>
  35 #include <drm/drm_probe_helper.h>
  36
  37 #define SN_DEVICE_REV_REG                       0x08
  38 #define SN_DPPLL_SRC_REG                        0x0A
  39 #define  DPPLL_CLK_SRC_DSICLK                   BIT(0)
  40 #define  REFCLK_FREQ_MASK                       GENMASK(3, 1)
  41 #define  REFCLK_FREQ(x)                         ((x) << 1)
  42 #define  DPPLL_SRC_DP_PLL_LOCK                  BIT(7)
  43 #define SN_PLL_ENABLE_REG                       0x0D
  44 #define SN_DSI_LANES_REG                        0x10
  45 #define  CHA_DSI_LANES_MASK                     GENMASK(4, 3)
  46 #define  CHA_DSI_LANES(x)                       ((x) << 3)
  47 #define SN_DSIA_CLK_FREQ_REG                    0x12
  48 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG       0x20
  49 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG    0x24
  50 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG        0x2C
  51 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG       0x2D
  52 #define  CHA_HSYNC_POLARITY                     BIT(7)
  53 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG        0x30
  54 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG       0x31
  55 #define  CHA_VSYNC_POLARITY                     BIT(7)
  56 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG        0x34
  57 #define SN_CHA_VERTICAL_BACK_PORCH_REG          0x36
  58 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG       0x38
  59 #define SN_CHA_VERTICAL_FRONT_PORCH_REG         0x3A
  60 #define SN_LN_ASSIGN_REG                        0x59
  61 #define  LN_ASSIGN_WIDTH                        2
  62 #define SN_ENH_FRAME_REG                        0x5A
  63 #define  VSTREAM_ENABLE                         BIT(3)
  64 #define  LN_POLRS_OFFSET                        4
  65 #define  LN_POLRS_MASK                          0xf0
  66 #define SN_DATA_FORMAT_REG                      0x5B
  67 #define  BPP_18_RGB                             BIT(0)
  68 #define SN_HPD_DISABLE_REG                      0x5C
  69 #define  HPD_DISABLE                            BIT(0)
  70 #define SN_GPIO_IO_REG                          0x5E
  71 #define  SN_GPIO_INPUT_SHIFT                    4
  72 #define  SN_GPIO_OUTPUT_SHIFT                   0
  73 #define SN_GPIO_CTRL_REG                        0x5F
  74 #define  SN_GPIO_MUX_INPUT                      0
  75 #define  SN_GPIO_MUX_OUTPUT                     1
  76 #define  SN_GPIO_MUX_SPECIAL                    2
  77 #define  SN_GPIO_MUX_MASK                       0x3
  78 #define SN_AUX_WDATA_REG(x)                     (0x64 + (x))
  79 #define SN_AUX_ADDR_19_16_REG                   0x74
  80 #define SN_AUX_ADDR_15_8_REG                    0x75
  81 #define SN_AUX_ADDR_7_0_REG                     0x76
  82 #define SN_AUX_ADDR_MASK                        GENMASK(19, 0)
  83 #define SN_AUX_LENGTH_REG                       0x77
  84 #define SN_AUX_CMD_REG                          0x78
  85 #define  AUX_CMD_SEND                           BIT(0)
  86 #define  AUX_CMD_REQ(x)                         ((x) << 4)
  87 #define SN_AUX_RDATA_REG(x)                     (0x79 + (x))
  88 #define SN_SSC_CONFIG_REG                       0x93
  89 #define  DP_NUM_LANES_MASK                      GENMASK(5, 4)
  90 #define  DP_NUM_LANES(x)                        ((x) << 4)
  91 #define SN_DATARATE_CONFIG_REG                  0x94
  92 #define  DP_DATARATE_MASK                       GENMASK(7, 5)
  93 #define  DP_DATARATE(x)                         ((x) << 5)
  94 #define SN_ML_TX_MODE_REG                       0x96
  95 #define  ML_TX_MAIN_LINK_OFF                    0
  96 #define  ML_TX_NORMAL_MODE                      BIT(0)
  97 #define SN_PWM_PRE_DIV_REG                      0xA0
  98 #define SN_BACKLIGHT_SCALE_REG                  0xA1
  99 #define  BACKLIGHT_SCALE_MAX                    0xFFFF
 100 #define SN_BACKLIGHT_REG                        0xA3
 101 #define SN_PWM_EN_INV_REG                       0xA5
 102 #define  SN_PWM_INV_MASK                        BIT(0)
 103 #define  SN_PWM_EN_MASK                         BIT(1)
 104 #define SN_AUX_CMD_STATUS_REG                   0xF4
 105 #define  AUX_IRQ_STATUS_AUX_RPLY_TOUT           BIT(3)
 106 #define  AUX_IRQ_STATUS_AUX_SHORT               BIT(5)
 107 #define  AUX_IRQ_STATUS_NAT_I2C_FAIL            BIT(6)
 108
 109 #define MIN_DSI_CLK_FREQ_MHZ    40
 110
 111 /* fudge factor required to account for 8b/10b encoding */
 112 #define DP_CLK_FUDGE_NUM        10
 113 #define DP_CLK_FUDGE_DEN        8
 114
 115 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
 116 #define SN_AUX_MAX_PAYLOAD_BYTES        16
 117
 118 #define SN_REGULATOR_SUPPLY_NUM         4
 119
 120 #define SN_MAX_DP_LANES                 4
 121 #define SN_NUM_GPIOS                    4
 122 #define SN_GPIO_PHYSICAL_OFFSET         1
 123
 124 #define SN_LINK_TRAINING_TRIES          10
 125
 126 #define SN_PWM_GPIO_IDX                 3 /* 4th GPIO */
 127
 128 /**
 129  * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
 130  * @bridge_aux:   AUX-bus sub device for MIPI-to-eDP bridge functionality.
 131  * @gpio_aux:     AUX-bus sub device for GPIO controller functionality.
 132  * @aux_aux:      AUX-bus sub device for eDP AUX channel functionality.
 133  * @pwm_aux:      AUX-bus sub device for PWM controller functionality.
 134  *
 135  * @dev:          Pointer to the top level (i2c) device.
 136  * @regmap:       Regmap for accessing i2c.
 137  * @aux:          Our aux channel.
 138  * @bridge:       Our bridge.
 139  * @connector:    Our connector.
 140  * @host_node:    Remote DSI node.
 141  * @dsi:          Our MIPI DSI source.
 142  * @refclk:       Our reference clock.
 143  * @next_bridge:  The bridge on the eDP side.
 144  * @enable_gpio:  The GPIO we toggle to enable the bridge.
 145  * @supplies:     Data for bulk enabling/disabling our regulators.
 146  * @dp_lanes:     Count of dp_lanes we're using.
 147  * @ln_assign:    Value to program to the LN_ASSIGN register.
 148  * @ln_polrs:     Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
 149  * @comms_enabled: If true then communication over the aux channel is enabled.
 150  * @comms_mutex:   Protects modification of comms_enabled.
 151  *
 152  * @gchip:        If we expose our GPIOs, this is used.
 153  * @gchip_output: A cache of whether we've set GPIOs to output.  This
 154  *                serves double-duty of keeping track of the direction and
 155  *                also keeping track of whether we've incremented the
 156  *                pm_runtime reference count for this pin, which we do
 157  *                whenever a pin is configured as an output.  This is a
 158  *                bitmap so we can do atomic ops on it without an extra
 159  *                lock so concurrent users of our 4 GPIOs don't stomp on
 160  *                each other's read-modify-write.
 161  *
 162  * @pchip:        pwm_chip if the PWM is exposed.
 163  * @pwm_enabled:  Used to track if the PWM signal is currently enabled.
 164  * @pwm_pin_busy: Track if GPIO4 is currently requested for GPIO or PWM.
 165  * @pwm_refclk_freq: Cache for the reference clock input to the PWM.
 166  */
 167 struct ti_sn65dsi86 {
 168         struct auxiliary_device         bridge_aux;
 169         struct auxiliary_device         gpio_aux;
 170         struct auxiliary_device         aux_aux;
 171         struct auxiliary_device         pwm_aux;
 172
 173         struct device                   *dev;
 174         struct regmap                   *regmap;
 175         struct drm_dp_aux               aux;
 176         struct drm_bridge               bridge;
 177         struct drm_connector            connector;
 178         struct device_node              *host_node;
 179         struct mipi_dsi_device          *dsi;
 180         struct clk                      *refclk;
 181         struct drm_bridge               *next_bridge;
 182         struct gpio_desc                *enable_gpio;
 183         struct regulator_bulk_data      supplies[SN_REGULATOR_SUPPLY_NUM];
 184         int                             dp_lanes;
 185         u8                              ln_assign;
 186         u8                              ln_polrs;
 187         bool                            comms_enabled;
 188         struct mutex                    comms_mutex;
 189
 190 #if defined(CONFIG_OF_GPIO)
 191         struct gpio_chip                gchip;
 192         DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS);
 193 #endif
 194 #if defined(CONFIG_PWM)
 195         struct pwm_chip                 pchip;
 196         bool                            pwm_enabled;
 197         atomic_t                        pwm_pin_busy;
 198 #endif
 199         unsigned int                    pwm_refclk_freq;
 200 };
 201
 202 static const struct regmap_range ti_sn65dsi86_volatile_ranges[] = {
 203         { .range_min = 0, .range_max = 0xFF },
 204 };
 205
 206 static const struct regmap_access_table ti_sn_bridge_volatile_table = {
 207         .yes_ranges = ti_sn65dsi86_volatile_ranges,
 208         .n_yes_ranges = ARRAY_SIZE(ti_sn65dsi86_volatile_ranges),
 209 };
 210
 211 static const struct regmap_config ti_sn65dsi86_regmap_config = {
 212         .reg_bits = 8,
 213         .val_bits = 8,
 214         .volatile_table = &ti_sn_bridge_volatile_table,
 215         .cache_type = REGCACHE_NONE,
 216 };
 217
 218 static int ti_sn65dsi86_read_u16(struct ti_sn65dsi86 *pdata,
 219                                  unsigned int reg, u16 *val)
 220 {
 221         u8 buf[2];
 222         int ret;
 223
 224         ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
 225         if (ret)
 226                 return ret;
 227
 228         *val = buf[0] | (buf[1] << 8);
 229
 230         return 0;
 231 }
 232
 233 static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata,
 234                                    unsigned int reg, u16 val)
 235 {
 236         u8 buf[2] = { val & 0xff, val >> 8 };
 237
 238         regmap_bulk_write(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
 239 }
 240
 241 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata)
 242 {
 243         u32 bit_rate_khz, clk_freq_khz;
 244         struct drm_display_mode *mode =
 245                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 246
 247         bit_rate_khz = mode->clock *
 248                         mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
 249         clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
 250
 251         return clk_freq_khz;
 252 }
 253
 254 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
 255 static const u32 ti_sn_bridge_refclk_lut[] = {
 256         12000000,
 257         19200000,
 258         26000000,
 259         27000000,
 260         38400000,
 261 };
 262
 263 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
 264 static const u32 ti_sn_bridge_dsiclk_lut[] = {
 265         468000000,
 266         384000000,
 267         416000000,
 268         486000000,
 269         460800000,
 270 };
 271
 272 static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata)
 273 {
 274         int i;
 275         u32 refclk_rate;
 276         const u32 *refclk_lut;
 277         size_t refclk_lut_size;
 278
 279         if (pdata->refclk) {
 280                 refclk_rate = clk_get_rate(pdata->refclk);
 281                 refclk_lut = ti_sn_bridge_refclk_lut;
 282                 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
 283                 clk_prepare_enable(pdata->refclk);
 284         } else {
 285                 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
 286                 refclk_lut = ti_sn_bridge_dsiclk_lut;
 287                 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
 288         }
 289
 290         /* for i equals to refclk_lut_size means default frequency */
 291         for (i = 0; i < refclk_lut_size; i++)
 292                 if (refclk_lut[i] == refclk_rate)
 293                         break;
 294
 295         regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
 296                            REFCLK_FREQ(i));
 297
 298         /*
 299          * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG,
 300          * regardless of its actual sourcing.
 301          */
 302         pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i];
 303 }
 304
 305 static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata)
 306 {
 307         mutex_lock(&pdata->comms_mutex);
 308
 309         /* configure bridge ref_clk */
 310         ti_sn_bridge_set_refclk_freq(pdata);
 311
 312         /*
 313          * HPD on this bridge chip is a bit useless.  This is an eDP bridge
 314          * so the HPD is an internal signal that's only there to signal that
 315          * the panel is done powering up.  ...but the bridge chip debounces
 316          * this signal by between 100 ms and 400 ms (depending on process,
 317          * voltage, and temperate--I measured it at about 200 ms).  One
 318          * particular panel asserted HPD 84 ms after it was powered on meaning
 319          * that we saw HPD 284 ms after power on.  ...but the same panel said
 320          * that instead of looking at HPD you could just hardcode a delay of
 321          * 200 ms.  We'll assume that the panel driver will have the hardcoded
 322          * delay in its prepare and always disable HPD.
 323          *
 324          * If HPD somehow makes sense on some future panel we'll have to
 325          * change this to be conditional on someone specifying that HPD should
 326          * be used.
 327          */
 328         regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
 329                            HPD_DISABLE);
 330
 331         pdata->comms_enabled = true;
 332
 333         mutex_unlock(&pdata->comms_mutex);
 334 }
 335
 336 static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 *pdata)
 337 {
 338         mutex_lock(&pdata->comms_mutex);
 339
 340         pdata->comms_enabled = false;
 341         clk_disable_unprepare(pdata->refclk);
 342
 343         mutex_unlock(&pdata->comms_mutex);
 344 }
 345
 346 static int __maybe_unused ti_sn65dsi86_resume(struct device *dev)
 347 {
 348         struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
 349         int ret;
 350
 351         ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
 352         if (ret) {
 353                 DRM_ERROR("failed to enable supplies %d\n", ret);
 354                 return ret;
 355         }
 356
 357         /* td2: min 100 us after regulators before enabling the GPIO */
 358         usleep_range(100, 110);
 359
 360         gpiod_set_value(pdata->enable_gpio, 1);
 361
 362         /*
 363          * If we have a reference clock we can enable communication w/ the
 364          * panel (including the aux channel) w/out any need for an input clock
 365          * so we can do it in resume which lets us read the EDID before
 366          * pre_enable(). Without a reference clock we need the MIPI reference
 367          * clock so reading early doesn't work.
 368          */
 369         if (pdata->refclk)
 370                 ti_sn65dsi86_enable_comms(pdata);
 371
 372         return ret;
 373 }
 374
 375 static int __maybe_unused ti_sn65dsi86_suspend(struct device *dev)
 376 {
 377         struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
 378         int ret;
 379
 380         if (pdata->refclk)
 381                 ti_sn65dsi86_disable_comms(pdata);
 382
 383         gpiod_set_value(pdata->enable_gpio, 0);
 384
 385         ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
 386         if (ret)
 387                 DRM_ERROR("failed to disable supplies %d\n", ret);
 388
 389         return ret;
 390 }
 391
 392 static const struct dev_pm_ops ti_sn65dsi86_pm_ops = {
 393         SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend, ti_sn65dsi86_resume, NULL)
 394         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 395                                 pm_runtime_force_resume)
 396 };
 397
 398 static int status_show(struct seq_file *s, void *data)
 399 {
 400         struct ti_sn65dsi86 *pdata = s->private;
 401         unsigned int reg, val;
 402
 403         seq_puts(s, "STATUS REGISTERS:\n");
 404
 405         pm_runtime_get_sync(pdata->dev);
 406
 407         /* IRQ Status Registers, see Table 31 in datasheet */
 408         for (reg = 0xf0; reg <= 0xf8; reg++) {
 409                 regmap_read(pdata->regmap, reg, &val);
 410                 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val);
 411         }
 412
 413         pm_runtime_put_autosuspend(pdata->dev);
 414
 415         return 0;
 416 }
 417
 418 DEFINE_SHOW_ATTRIBUTE(status);
 419
 420 static void ti_sn65dsi86_debugfs_remove(void *data)
 421 {
 422         debugfs_remove_recursive(data);
 423 }
 424
 425 static void ti_sn65dsi86_debugfs_init(struct ti_sn65dsi86 *pdata)
 426 {
 427         struct device *dev = pdata->dev;
 428         struct dentry *debugfs;
 429         int ret;
 430
 431         debugfs = debugfs_create_dir(dev_name(dev), NULL);
 432
 433         /*
 434          * We might get an error back if debugfs wasn't enabled in the kernel
 435          * so let's just silently return upon failure.
 436          */
 437         if (IS_ERR_OR_NULL(debugfs))
 438                 return;
 439
 440         ret = devm_add_action_or_reset(dev, ti_sn65dsi86_debugfs_remove, debugfs);
 441         if (ret)
 442                 return;
 443
 444         debugfs_create_file("status", 0600, debugfs, pdata, &status_fops);
 445 }
 446
 447 /* -----------------------------------------------------------------------------
 448  * Auxiliary Devices (*not* AUX)
 449  */
 450
 451 static void ti_sn65dsi86_uninit_aux(void *data)
 452 {
 453         auxiliary_device_uninit(data);
 454 }
 455
 456 static void ti_sn65dsi86_delete_aux(void *data)
 457 {
 458         auxiliary_device_delete(data);
 459 }
 460
 461 /*
 462  * AUX bus docs say that a non-NULL release is mandatory, but it makes no
 463  * sense for the model used here where all of the aux devices are allocated
 464  * in the single shared structure. We'll use this noop as a workaround.
 465  */
 466 static void ti_sn65dsi86_noop(struct device *dev) {}
 467
 468 static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 *pdata,
 469                                        struct auxiliary_device *aux,
 470                                        const char *name)
 471 {
 472         struct device *dev = pdata->dev;
 473         int ret;
 474
 475         aux->name = name;
 476         aux->dev.parent = dev;
 477         aux->dev.release = ti_sn65dsi86_noop;
 478         device_set_of_node_from_dev(&aux->dev, dev);
 479         ret = auxiliary_device_init(aux);
 480         if (ret)
 481                 return ret;
 482         ret = devm_add_action_or_reset(dev, ti_sn65dsi86_uninit_aux, aux);
 483         if (ret)
 484                 return ret;
 485
 486         ret = auxiliary_device_add(aux);
 487         if (ret)
 488                 return ret;
 489         ret = devm_add_action_or_reset(dev, ti_sn65dsi86_delete_aux, aux);
 490
 491         return ret;
 492 }
 493
 494 /* -----------------------------------------------------------------------------
 495  * AUX Adapter
 496  */
 497
 498 static struct ti_sn65dsi86 *aux_to_ti_sn65dsi86(struct drm_dp_aux *aux)
 499 {
 500         return container_of(aux, struct ti_sn65dsi86, aux);
 501 }
 502
 503 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
 504                                   struct drm_dp_aux_msg *msg)
 505 {
 506         struct ti_sn65dsi86 *pdata = aux_to_ti_sn65dsi86(aux);
 507         u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
 508         u32 request_val = AUX_CMD_REQ(msg->request);
 509         u8 *buf = msg->buffer;
 510         unsigned int len = msg->size;
 511         unsigned int val;
 512         int ret;
 513         u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG];
 514
 515         if (len > SN_AUX_MAX_PAYLOAD_BYTES)
 516                 return -EINVAL;
 517
 518         pm_runtime_get_sync(pdata->dev);
 519         mutex_lock(&pdata->comms_mutex);
 520
 521         /*
 522          * If someone tries to do a DDC over AUX transaction before pre_enable()
 523          * on a device without a dedicated reference clock then we just can't
 524          * do it. Fail right away. This prevents non-refclk users from reading
 525          * the EDID before enabling the panel but such is life.
 526          */
 527         if (!pdata->comms_enabled) {
 528                 ret = -EIO;
 529                 goto exit;
 530         }
 531
 532         switch (request) {
 533         case DP_AUX_NATIVE_WRITE:
 534         case DP_AUX_I2C_WRITE:
 535         case DP_AUX_NATIVE_READ:
 536         case DP_AUX_I2C_READ:
 537                 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
 538                 /* Assume it's good */
 539                 msg->reply = 0;
 540                 break;
 541         default:
 542                 ret = -EINVAL;
 543                 goto exit;
 544         }
 545
 546         BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32));
 547         put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len,
 548                            addr_len);
 549         regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len,
 550                           ARRAY_SIZE(addr_len));
 551
 552         if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
 553                 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len);
 554
 555         /* Clear old status bits before start so we don't get confused */
 556         regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG,
 557                      AUX_IRQ_STATUS_NAT_I2C_FAIL |
 558                      AUX_IRQ_STATUS_AUX_RPLY_TOUT |
 559                      AUX_IRQ_STATUS_AUX_SHORT);
 560
 561         regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
 562
 563         /* Zero delay loop because i2c transactions are slow already */
 564         ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
 565                                        !(val & AUX_CMD_SEND), 0, 50 * 1000);
 566         if (ret)
 567                 goto exit;
 568
 569         ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
 570         if (ret)
 571                 goto exit;
 572
 573         if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) {
 574                 /*
 575                  * The hardware tried the message seven times per the DP spec
 576                  * but it hit a timeout. We ignore defers here because they're
 577                  * handled in hardware.
 578                  */
 579                 ret = -ETIMEDOUT;
 580                 goto exit;
 581         }
 582
 583         if (val & AUX_IRQ_STATUS_AUX_SHORT) {
 584                 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &len);
 585                 if (ret)
 586                         goto exit;
 587         } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) {
 588                 switch (request) {
 589                 case DP_AUX_I2C_WRITE:
 590                 case DP_AUX_I2C_READ:
 591                         msg->reply |= DP_AUX_I2C_REPLY_NACK;
 592                         break;
 593                 case DP_AUX_NATIVE_READ:
 594                 case DP_AUX_NATIVE_WRITE:
 595                         msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
 596                         break;
 597                 }
 598                 len = 0;
 599                 goto exit;
 600         }
 601
 602         if (request != DP_AUX_NATIVE_WRITE && request != DP_AUX_I2C_WRITE && len != 0)
 603                 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len);
 604
 605 exit:
 606         mutex_unlock(&pdata->comms_mutex);
 607         pm_runtime_mark_last_busy(pdata->dev);
 608         pm_runtime_put_autosuspend(pdata->dev);
 609
 610         if (ret)
 611                 return ret;
 612         return len;
 613 }
 614
 615 static int ti_sn_aux_probe(struct auxiliary_device *adev,
 616                            const struct auxiliary_device_id *id)
 617 {
 618         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
 619         int ret;
 620
 621         pdata->aux.name = "ti-sn65dsi86-aux";
 622         pdata->aux.dev = &adev->dev;
 623         pdata->aux.transfer = ti_sn_aux_transfer;
 624         drm_dp_aux_init(&pdata->aux);
 625
 626         ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux);
 627         if (ret)
 628                 return ret;
 629
 630         /*
 631          * The eDP to MIPI bridge parts don't work until the AUX channel is
 632          * setup so we don't add it in the main driver probe, we add it now.
 633          */
 634         return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge");
 635 }
 636
 637 static const struct auxiliary_device_id ti_sn_aux_id_table[] = {
 638         { .name = "ti_sn65dsi86.aux", },
 639         {},
 640 };
 641
 642 static struct auxiliary_driver ti_sn_aux_driver = {
 643         .name = "aux",
 644         .probe = ti_sn_aux_probe,
 645         .id_table = ti_sn_aux_id_table,
 646 };
 647
 648 /* -----------------------------------------------------------------------------
 649  * DRM Connector Operations
 650  */
 651
 652 static struct ti_sn65dsi86 *
 653 connector_to_ti_sn65dsi86(struct drm_connector *connector)
 654 {
 655         return container_of(connector, struct ti_sn65dsi86, connector);
 656 }
 657
 658 static int ti_sn_bridge_connector_get_modes(struct drm_connector *connector)
 659 {
 660         struct ti_sn65dsi86 *pdata = connector_to_ti_sn65dsi86(connector);
 661
 662         return drm_bridge_get_modes(pdata->next_bridge, connector);
 663 }
 664
 665 static struct drm_connector_helper_funcs ti_sn_bridge_connector_helper_funcs = {
 666         .get_modes = ti_sn_bridge_connector_get_modes,
 667 };
 668
 669 static const struct drm_connector_funcs ti_sn_bridge_connector_funcs = {
 670         .fill_modes = drm_helper_probe_single_connector_modes,
 671         .destroy = drm_connector_cleanup,
 672         .reset = drm_atomic_helper_connector_reset,
 673         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 674         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 675 };
 676
 677 static int ti_sn_bridge_connector_init(struct ti_sn65dsi86 *pdata)
 678 {
 679         int ret;
 680
 681         ret = drm_connector_init(pdata->bridge.dev, &pdata->connector,
 682                                  &ti_sn_bridge_connector_funcs,
 683                                  DRM_MODE_CONNECTOR_eDP);
 684         if (ret) {
 685                 DRM_ERROR("Failed to initialize connector with drm\n");
 686                 return ret;
 687         }
 688
 689         drm_connector_helper_add(&pdata->connector,
 690                                  &ti_sn_bridge_connector_helper_funcs);
 691         drm_connector_attach_encoder(&pdata->connector, pdata->bridge.encoder);
 692
 693         return 0;
 694 }
 695
 696 /*------------------------------------------------------------------------------
 697  * DRM Bridge
 698  */
 699
 700 static struct ti_sn65dsi86 *bridge_to_ti_sn65dsi86(struct drm_bridge *bridge)
 701 {
 702         return container_of(bridge, struct ti_sn65dsi86, bridge);
 703 }
 704
 705 static int ti_sn_bridge_attach(struct drm_bridge *bridge,
 706                                enum drm_bridge_attach_flags flags)
 707 {
 708         int ret, val;
 709         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
 710         struct mipi_dsi_host *host;
 711         struct mipi_dsi_device *dsi;
 712         const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
 713                                                    .channel = 0,
 714                                                    .node = NULL,
 715                                                  };
 716
 717         if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
 718                 DRM_ERROR("Fix bridge driver to make connector optional!");
 719                 return -EINVAL;
 720         }
 721
 722         pdata->aux.drm_dev = bridge->dev;
 723         ret = drm_dp_aux_register(&pdata->aux);
 724         if (ret < 0) {
 725                 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret);
 726                 return ret;
 727         }
 728
 729         ret = ti_sn_bridge_connector_init(pdata);
 730         if (ret < 0)
 731                 goto err_conn_init;
 732
 733         /*
 734          * TODO: ideally finding host resource and dsi dev registration needs
 735          * to be done in bridge probe. But some existing DSI host drivers will
 736          * wait for any of the drm_bridge/drm_panel to get added to the global
 737          * bridge/panel list, before completing their probe. So if we do the
 738          * dsi dev registration part in bridge probe, before populating in
 739          * the global bridge list, then it will cause deadlock as dsi host probe
 740          * will never complete, neither our bridge probe. So keeping it here
 741          * will satisfy most of the existing host drivers. Once the host driver
 742          * is fixed we can move the below code to bridge probe safely.
 743          */
 744         host = of_find_mipi_dsi_host_by_node(pdata->host_node);
 745         if (!host) {
 746                 DRM_ERROR("failed to find dsi host\n");
 747                 ret = -ENODEV;
 748                 goto err_dsi_host;
 749         }
 750
 751         dsi = mipi_dsi_device_register_full(host, &info);
 752         if (IS_ERR(dsi)) {
 753                 DRM_ERROR("failed to create dsi device\n");
 754                 ret = PTR_ERR(dsi);
 755                 goto err_dsi_host;
 756         }
 757
 758         /* TODO: setting to 4 MIPI lanes always for now */
 759         dsi->lanes = 4;
 760         dsi->format = MIPI_DSI_FMT_RGB888;
 761         dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
 762
 763         /* check if continuous dsi clock is required or not */
 764         pm_runtime_get_sync(pdata->dev);
 765         regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
 766         pm_runtime_put_autosuspend(pdata->dev);
 767         if (!(val & DPPLL_CLK_SRC_DSICLK))
 768                 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
 769
 770         ret = mipi_dsi_attach(dsi);
 771         if (ret < 0) {
 772                 DRM_ERROR("failed to attach dsi to host\n");
 773                 goto err_dsi_attach;
 774         }
 775         pdata->dsi = dsi;
 776
 777         /* We never want the next bridge to *also* create a connector: */
 778         flags |= DRM_BRIDGE_ATTACH_NO_CONNECTOR;
 779
 780         /* Attach the next bridge */
 781         ret = drm_bridge_attach(bridge->encoder, pdata->next_bridge,
 782                                 &pdata->bridge, flags);
 783         if (ret < 0)
 784                 goto err_dsi_detach;
 785
 786         return 0;
 787
 788 err_dsi_detach:
 789         mipi_dsi_detach(dsi);
 790 err_dsi_attach:
 791         mipi_dsi_device_unregister(dsi);
 792 err_dsi_host:
 793         drm_connector_cleanup(&pdata->connector);
 794 err_conn_init:
 795         drm_dp_aux_unregister(&pdata->aux);
 796         return ret;
 797 }
 798
 799 static void ti_sn_bridge_detach(struct drm_bridge *bridge)
 800 {
 801         drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux);
 802 }
 803
 804 static enum drm_mode_status
 805 ti_sn_bridge_mode_valid(struct drm_bridge *bridge,
 806                         const struct drm_display_info *info,
 807                         const struct drm_display_mode *mode)
 808 {
 809         /* maximum supported resolution is 4K at 60 fps */
 810         if (mode->clock > 594000)
 811                 return MODE_CLOCK_HIGH;
 812
 813         return MODE_OK;
 814 }
 815
 816 static void ti_sn_bridge_disable(struct drm_bridge *bridge)
 817 {
 818         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
 819
 820         /* disable video stream */
 821         regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
 822 }
 823
 824 static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata)
 825 {
 826         unsigned int bit_rate_mhz, clk_freq_mhz;
 827         unsigned int val;
 828         struct drm_display_mode *mode =
 829                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 830
 831         /* set DSIA clk frequency */
 832         bit_rate_mhz = (mode->clock / 1000) *
 833                         mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
 834         clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
 835
 836         /* for each increment in val, frequency increases by 5MHz */
 837         val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
 838                 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
 839         regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
 840 }
 841
 842 static unsigned int ti_sn_bridge_get_bpp(struct ti_sn65dsi86 *pdata)
 843 {
 844         if (pdata->connector.display_info.bpc <= 6)
 845                 return 18;
 846         else
 847                 return 24;
 848 }
 849
 850 /*
 851  * LUT index corresponds to register value and
 852  * LUT values corresponds to dp data rate supported
 853  * by the bridge in Mbps unit.
 854  */
 855 static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
 856         0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
 857 };
 858
 859 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata)
 860 {
 861         unsigned int bit_rate_khz, dp_rate_mhz;
 862         unsigned int i;
 863         struct drm_display_mode *mode =
 864                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 865
 866         /* Calculate minimum bit rate based on our pixel clock. */
 867         bit_rate_khz = mode->clock * ti_sn_bridge_get_bpp(pdata);
 868
 869         /* Calculate minimum DP data rate, taking 80% as per DP spec */
 870         dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
 871                                    1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
 872
 873         for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
 874                 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz)
 875                         break;
 876
 877         return i;
 878 }
 879
 880 static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata)
 881 {
 882         unsigned int valid_rates = 0;
 883         unsigned int rate_per_200khz;
 884         unsigned int rate_mhz;
 885         u8 dpcd_val;
 886         int ret;
 887         int i, j;
 888
 889         ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val);
 890         if (ret != 1) {
 891                 DRM_DEV_ERROR(pdata->dev,
 892                               "Can't read eDP rev (%d), assuming 1.1\n", ret);
 893                 dpcd_val = DP_EDP_11;
 894         }
 895
 896         if (dpcd_val >= DP_EDP_14) {
 897                 /* eDP 1.4 devices must provide a custom table */
 898                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
 899
 900                 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES,
 901                                        sink_rates, sizeof(sink_rates));
 902
 903                 if (ret != sizeof(sink_rates)) {
 904                         DRM_DEV_ERROR(pdata->dev,
 905                                 "Can't read supported rate table (%d)\n", ret);
 906
 907                         /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */
 908                         memset(sink_rates, 0, sizeof(sink_rates));
 909                 }
 910
 911                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
 912                         rate_per_200khz = le16_to_cpu(sink_rates[i]);
 913
 914                         if (!rate_per_200khz)
 915                                 break;
 916
 917                         rate_mhz = rate_per_200khz * 200 / 1000;
 918                         for (j = 0;
 919                              j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
 920                              j++) {
 921                                 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz)
 922                                         valid_rates |= BIT(j);
 923                         }
 924                 }
 925
 926                 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) {
 927                         if (valid_rates & BIT(i))
 928                                 return valid_rates;
 929                 }
 930                 DRM_DEV_ERROR(pdata->dev,
 931                               "No matching eDP rates in table; falling back\n");
 932         }
 933
 934         /* On older versions best we can do is use DP_MAX_LINK_RATE */
 935         ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val);
 936         if (ret != 1) {
 937                 DRM_DEV_ERROR(pdata->dev,
 938                               "Can't read max rate (%d); assuming 5.4 GHz\n",
 939                               ret);
 940                 dpcd_val = DP_LINK_BW_5_4;
 941         }
 942
 943         switch (dpcd_val) {
 944         default:
 945                 DRM_DEV_ERROR(pdata->dev,
 946                               "Unexpected max rate (%#x); assuming 5.4 GHz\n",
 947                               (int)dpcd_val);
 948                 fallthrough;
 949         case DP_LINK_BW_5_4:
 950                 valid_rates |= BIT(7);
 951                 fallthrough;
 952         case DP_LINK_BW_2_7:
 953                 valid_rates |= BIT(4);
 954                 fallthrough;
 955         case DP_LINK_BW_1_62:
 956                 valid_rates |= BIT(1);
 957                 break;
 958         }
 959
 960         return valid_rates;
 961 }
 962
 963 static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata)
 964 {
 965         struct drm_display_mode *mode =
 966                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 967         u8 hsync_polarity = 0, vsync_polarity = 0;
 968
 969         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 970                 hsync_polarity = CHA_HSYNC_POLARITY;
 971         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 972                 vsync_polarity = CHA_VSYNC_POLARITY;
 973
 974         ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
 975                                mode->hdisplay);
 976         ti_sn65dsi86_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
 977                                mode->vdisplay);
 978         regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
 979                      (mode->hsync_end - mode->hsync_start) & 0xFF);
 980         regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
 981                      (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
 982                      hsync_polarity);
 983         regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
 984                      (mode->vsync_end - mode->vsync_start) & 0xFF);
 985         regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
 986                      (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
 987                      vsync_polarity);
 988
 989         regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
 990                      (mode->htotal - mode->hsync_end) & 0xFF);
 991         regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
 992                      (mode->vtotal - mode->vsync_end) & 0xFF);
 993
 994         regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
 995                      (mode->hsync_start - mode->hdisplay) & 0xFF);
 996         regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
 997                      (mode->vsync_start - mode->vdisplay) & 0xFF);
 998
 999         usleep_range(10000, 10500); /* 10ms delay recommended by spec */
1000 }
1001
1002 static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86 *pdata)
1003 {
1004         u8 data;
1005         int ret;
1006
1007         ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data);
1008         if (ret != 1) {
1009                 DRM_DEV_ERROR(pdata->dev,
1010                               "Can't read lane count (%d); assuming 4\n", ret);
1011                 return 4;
1012         }
1013
1014         return data & DP_LANE_COUNT_MASK;
1015 }
1016
1017 static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx,
1018                                const char **last_err_str)
1019 {
1020         unsigned int val;
1021         int ret;
1022         int i;
1023
1024         /* set dp clk frequency value */
1025         regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
1026                            DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx));
1027
1028         /* enable DP PLL */
1029         regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
1030
1031         ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
1032                                        val & DPPLL_SRC_DP_PLL_LOCK, 1000,
1033                                        50 * 1000);
1034         if (ret) {
1035                 *last_err_str = "DP_PLL_LOCK polling failed";
1036                 goto exit;
1037         }
1038
1039         /*
1040          * We'll try to link train several times.  As part of link training
1041          * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER.  If
1042          * the panel isn't ready quite it might respond NAK here which means
1043          * we need to try again.
1044          */
1045         for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) {
1046                 /* Semi auto link training mode */
1047                 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
1048                 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
1049                                                val == ML_TX_MAIN_LINK_OFF ||
1050                                                val == ML_TX_NORMAL_MODE, 1000,
1051                                                500 * 1000);
1052                 if (ret) {
1053                         *last_err_str = "Training complete polling failed";
1054                 } else if (val == ML_TX_MAIN_LINK_OFF) {
1055                         *last_err_str = "Link training failed, link is off";
1056                         ret = -EIO;
1057                         continue;
1058                 }
1059
1060                 break;
1061         }
1062
1063         /* If we saw quite a few retries, add a note about it */
1064         if (!ret && i > SN_LINK_TRAINING_TRIES / 2)
1065                 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i);
1066
1067 exit:
1068         /* Disable the PLL if we failed */
1069         if (ret)
1070                 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1071
1072         return ret;
1073 }
1074
1075 static void ti_sn_bridge_enable(struct drm_bridge *bridge)
1076 {
1077         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1078         const char *last_err_str = "No supported DP rate";
1079         unsigned int valid_rates;
1080         int dp_rate_idx;
1081         unsigned int val;
1082         int ret = -EINVAL;
1083         int max_dp_lanes;
1084
1085         max_dp_lanes = ti_sn_get_max_lanes(pdata);
1086         pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes);
1087
1088         /* DSI_A lane config */
1089         val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes);
1090         regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
1091                            CHA_DSI_LANES_MASK, val);
1092
1093         regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign);
1094         regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK,
1095                            pdata->ln_polrs << LN_POLRS_OFFSET);
1096
1097         /* set dsi clk frequency value */
1098         ti_sn_bridge_set_dsi_rate(pdata);
1099
1100         /*
1101          * The SN65DSI86 only supports ASSR Display Authentication method and
1102          * this method is enabled by default. An eDP panel must support this
1103          * authentication method. We need to enable this method in the eDP panel
1104          * at DisplayPort address 0x0010A prior to link training.
1105          */
1106         drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
1107                            DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
1108
1109         /* Set the DP output format (18 bpp or 24 bpp) */
1110         val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0;
1111         regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
1112
1113         /* DP lane config */
1114         val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
1115         regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
1116                            val);
1117
1118         valid_rates = ti_sn_bridge_read_valid_rates(pdata);
1119
1120         /* Train until we run out of rates */
1121         for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata);
1122              dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
1123              dp_rate_idx++) {
1124                 if (!(valid_rates & BIT(dp_rate_idx)))
1125                         continue;
1126
1127                 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str);
1128                 if (!ret)
1129                         break;
1130         }
1131         if (ret) {
1132                 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret);
1133                 return;
1134         }
1135
1136         /* config video parameters */
1137         ti_sn_bridge_set_video_timings(pdata);
1138
1139         /* enable video stream */
1140         regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
1141                            VSTREAM_ENABLE);
1142 }
1143
1144 static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge)
1145 {
1146         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1147
1148         pm_runtime_get_sync(pdata->dev);
1149
1150         if (!pdata->refclk)
1151                 ti_sn65dsi86_enable_comms(pdata);
1152
1153         /* td7: min 100 us after enable before DSI data */
1154         usleep_range(100, 110);
1155 }
1156
1157 static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
1158 {
1159         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1160
1161         /* semi auto link training mode OFF */
1162         regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
1163         /* Num lanes to 0 as per power sequencing in data sheet */
1164         regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0);
1165         /* disable DP PLL */
1166         regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1167
1168         if (!pdata->refclk)
1169                 ti_sn65dsi86_disable_comms(pdata);
1170
1171         pm_runtime_put_sync(pdata->dev);
1172 }
1173
1174 static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
1175         .attach = ti_sn_bridge_attach,
1176         .detach = ti_sn_bridge_detach,
1177         .mode_valid = ti_sn_bridge_mode_valid,
1178         .pre_enable = ti_sn_bridge_pre_enable,
1179         .enable = ti_sn_bridge_enable,
1180         .disable = ti_sn_bridge_disable,
1181         .post_disable = ti_sn_bridge_post_disable,
1182 };
1183
1184 static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata,
1185                                      struct device_node *np)
1186 {
1187         u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 };
1188         u32 lane_polarities[SN_MAX_DP_LANES] = { };
1189         struct device_node *endpoint;
1190         u8 ln_assign = 0;
1191         u8 ln_polrs = 0;
1192         int dp_lanes;
1193         int i;
1194
1195         /*
1196          * Read config from the device tree about lane remapping and lane
1197          * polarities.  These are optional and we assume identity map and
1198          * normal polarity if nothing is specified.  It's OK to specify just
1199          * data-lanes but not lane-polarities but not vice versa.
1200          *
1201          * Error checking is light (we just make sure we don't crash or
1202          * buffer overrun) and we assume dts is well formed and specifying
1203          * mappings that the hardware supports.
1204          */
1205         endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1206         dp_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
1207         if (dp_lanes > 0 && dp_lanes <= SN_MAX_DP_LANES) {
1208                 of_property_read_u32_array(endpoint, "data-lanes",
1209                                            lane_assignments, dp_lanes);
1210                 of_property_read_u32_array(endpoint, "lane-polarities",
1211                                            lane_polarities, dp_lanes);
1212         } else {
1213                 dp_lanes = SN_MAX_DP_LANES;
1214         }
1215         of_node_put(endpoint);
1216
1217         /*
1218          * Convert into register format.  Loop over all lanes even if
1219          * data-lanes had fewer elements so that we nicely initialize
1220          * the LN_ASSIGN register.
1221          */
1222         for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) {
1223                 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i];
1224                 ln_polrs = ln_polrs << 1 | lane_polarities[i];
1225         }
1226
1227         /* Stash in our struct for when we power on */
1228         pdata->dp_lanes = dp_lanes;
1229         pdata->ln_assign = ln_assign;
1230         pdata->ln_polrs = ln_polrs;
1231 }
1232
1233 static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 *pdata)
1234 {
1235         struct device_node *np = pdata->dev->of_node;
1236
1237         pdata->host_node = of_graph_get_remote_node(np, 0, 0);
1238
1239         if (!pdata->host_node) {
1240                 DRM_ERROR("remote dsi host node not found\n");
1241                 return -ENODEV;
1242         }
1243
1244         return 0;
1245 }
1246
1247 static int ti_sn_bridge_probe(struct auxiliary_device *adev,
1248                               const struct auxiliary_device_id *id)
1249 {
1250         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1251         struct device_node *np = pdata->dev->of_node;
1252         struct drm_panel *panel;
1253         int ret;
1254
1255         ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL);
1256         if (ret)
1257                 return dev_err_probe(&adev->dev, ret,
1258                                      "could not find any panel node\n");
1259
1260         pdata->next_bridge = devm_drm_panel_bridge_add(pdata->dev, panel);
1261         if (IS_ERR(pdata->next_bridge)) {
1262                 DRM_ERROR("failed to create panel bridge\n");
1263                 return PTR_ERR(pdata->next_bridge);
1264         }
1265
1266         ti_sn_bridge_parse_lanes(pdata, np);
1267
1268         ret = ti_sn_bridge_parse_dsi_host(pdata);
1269         if (ret)
1270                 return ret;
1271
1272         pdata->bridge.funcs = &ti_sn_bridge_funcs;
1273         pdata->bridge.of_node = np;
1274
1275         drm_bridge_add(&pdata->bridge);
1276
1277         return 0;
1278 }
1279
1280 static void ti_sn_bridge_remove(struct auxiliary_device *adev)
1281 {
1282         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1283
1284         if (!pdata)
1285                 return;
1286
1287         if (pdata->dsi) {
1288                 mipi_dsi_detach(pdata->dsi);
1289                 mipi_dsi_device_unregister(pdata->dsi);
1290         }
1291
1292         drm_bridge_remove(&pdata->bridge);
1293
1294         of_node_put(pdata->host_node);
1295 }
1296
1297 static const struct auxiliary_device_id ti_sn_bridge_id_table[] = {
1298         { .name = "ti_sn65dsi86.bridge", },
1299         {},
1300 };
1301
1302 static struct auxiliary_driver ti_sn_bridge_driver = {
1303         .name = "bridge",
1304         .probe = ti_sn_bridge_probe,
1305         .remove = ti_sn_bridge_remove,
1306         .id_table = ti_sn_bridge_id_table,
1307 };
1308
1309 /* -----------------------------------------------------------------------------
1310  * PWM Controller
1311  */
1312 #if defined(CONFIG_PWM)
1313 static int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata)
1314 {
1315         return atomic_xchg(&pdata->pwm_pin_busy, 1) ? -EBUSY : 0;
1316 }
1317
1318 static void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata)
1319 {
1320         atomic_set(&pdata->pwm_pin_busy, 0);
1321 }
1322
1323 static struct ti_sn65dsi86 *pwm_chip_to_ti_sn_bridge(struct pwm_chip *chip)
1324 {
1325         return container_of(chip, struct ti_sn65dsi86, pchip);
1326 }
1327
1328 static int ti_sn_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
1329 {
1330         struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1331
1332         return ti_sn_pwm_pin_request(pdata);
1333 }
1334
1335 static void ti_sn_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
1336 {
1337         struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1338
1339         ti_sn_pwm_pin_release(pdata);
1340 }
1341
1342 /*
1343  * Limitations:
1344  * - The PWM signal is not driven when the chip is powered down, or in its
1345  *   reset state and the driver does not implement the "suspend state"
1346  *   described in the documentation. In order to save power, state->enabled is
1347  *   interpreted as denoting if the signal is expected to be valid, and is used
1348  *   to determine if the chip needs to be kept powered.
1349  * - Changing both period and duty_cycle is not done atomically, neither is the
1350  *   multi-byte register updates, so the output might briefly be undefined
1351  *   during update.
1352  */
1353 static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
1354                            const struct pwm_state *state)
1355 {
1356         struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1357         unsigned int pwm_en_inv;
1358         unsigned int backlight;
1359         unsigned int pre_div;
1360         unsigned int scale;
1361         u64 period_max;
1362         u64 period;
1363         int ret;
1364
1365         if (!pdata->pwm_enabled) {
1366                 ret = pm_runtime_get_sync(pdata->dev);
1367                 if (ret < 0) {
1368                         pm_runtime_put_sync(pdata->dev);
1369                         return ret;
1370                 }
1371         }
1372
1373         if (state->enabled) {
1374                 if (!pdata->pwm_enabled) {
1375                         /*
1376                          * The chip might have been powered down while we
1377                          * didn't hold a PM runtime reference, so mux in the
1378                          * PWM function on the GPIO pin again.
1379                          */
1380                         ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1381                                                  SN_GPIO_MUX_MASK << (2 * SN_PWM_GPIO_IDX),
1382                                                  SN_GPIO_MUX_SPECIAL << (2 * SN_PWM_GPIO_IDX));
1383                         if (ret) {
1384                                 dev_err(pdata->dev, "failed to mux in PWM function\n");
1385                                 goto out;
1386                         }
1387                 }
1388
1389                 /*
1390                  * Per the datasheet the PWM frequency is given by:
1391                  *
1392                  *                          REFCLK_FREQ
1393                  *   PWM_FREQ = -----------------------------------
1394                  *               PWM_PRE_DIV * BACKLIGHT_SCALE + 1
1395                  *
1396                  * However, after careful review the author is convinced that
1397                  * the documentation has lost some parenthesis around
1398                  * "BACKLIGHT_SCALE + 1".
1399                  *
1400                  * With the period T_pwm = 1/PWM_FREQ this can be written:
1401                  *
1402                  *   T_pwm * REFCLK_FREQ = PWM_PRE_DIV * (BACKLIGHT_SCALE + 1)
1403                  *
1404                  * In order to keep BACKLIGHT_SCALE within its 16 bits,
1405                  * PWM_PRE_DIV must be:
1406                  *
1407                  *                     T_pwm * REFCLK_FREQ
1408                  *   PWM_PRE_DIV >= -------------------------
1409                  *                   BACKLIGHT_SCALE_MAX + 1
1410                  *
1411                  * To simplify the search and to favour higher resolution of
1412                  * the duty cycle over accuracy of the period, the lowest
1413                  * possible PWM_PRE_DIV is used. Finally the scale is
1414                  * calculated as:
1415                  *
1416                  *                      T_pwm * REFCLK_FREQ
1417                  *   BACKLIGHT_SCALE = ---------------------- - 1
1418                  *                          PWM_PRE_DIV
1419                  *
1420                  * Here T_pwm is represented in seconds, so appropriate scaling
1421                  * to nanoseconds is necessary.
1422                  */
1423
1424                 /* Minimum T_pwm is 1 / REFCLK_FREQ */
1425                 if (state->period <= NSEC_PER_SEC / pdata->pwm_refclk_freq) {
1426                         ret = -EINVAL;
1427                         goto out;
1428                 }
1429
1430                 /*
1431                  * Maximum T_pwm is 255 * (65535 + 1) / REFCLK_FREQ
1432                  * Limit period to this to avoid overflows
1433                  */
1434                 period_max = div_u64((u64)NSEC_PER_SEC * 255 * (65535 + 1),
1435                                      pdata->pwm_refclk_freq);
1436                 period = min(state->period, period_max);
1437
1438                 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq,
1439                                              (u64)NSEC_PER_SEC * (BACKLIGHT_SCALE_MAX + 1));
1440                 scale = div64_u64(period * pdata->pwm_refclk_freq, (u64)NSEC_PER_SEC * pre_div) - 1;
1441
1442                 /*
1443                  * The documentation has the duty ratio given as:
1444                  *
1445                  *     duty          BACKLIGHT
1446                  *   ------- = ---------------------
1447                  *    period    BACKLIGHT_SCALE + 1
1448                  *
1449                  * Solve for BACKLIGHT, substituting BACKLIGHT_SCALE according
1450                  * to definition above and adjusting for nanosecond
1451                  * representation of duty cycle gives us:
1452                  */
1453                 backlight = div64_u64(state->duty_cycle * pdata->pwm_refclk_freq,
1454                                       (u64)NSEC_PER_SEC * pre_div);
1455                 if (backlight > scale)
1456                         backlight = scale;
1457
1458                 ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div);
1459                 if (ret) {
1460                         dev_err(pdata->dev, "failed to update PWM_PRE_DIV\n");
1461                         goto out;
1462                 }
1463
1464                 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_SCALE_REG, scale);
1465                 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_REG, backlight);
1466         }
1467
1468         pwm_en_inv = FIELD_PREP(SN_PWM_EN_MASK, state->enabled) |
1469                      FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED);
1470         ret = regmap_write(pdata->regmap, SN_PWM_EN_INV_REG, pwm_en_inv);
1471         if (ret) {
1472                 dev_err(pdata->dev, "failed to update PWM_EN/PWM_INV\n");
1473                 goto out;
1474         }
1475
1476         pdata->pwm_enabled = state->enabled;
1477 out:
1478
1479         if (!pdata->pwm_enabled)
1480                 pm_runtime_put_sync(pdata->dev);
1481
1482         return ret;
1483 }
1484
1485 static void ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
1486                                 struct pwm_state *state)
1487 {
1488         struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1489         unsigned int pwm_en_inv;
1490         unsigned int pre_div;
1491         u16 backlight;
1492         u16 scale;
1493         int ret;
1494
1495         ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv);
1496         if (ret)
1497                 return;
1498
1499         ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, &scale);
1500         if (ret)
1501                 return;
1502
1503         ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, &backlight);
1504         if (ret)
1505                 return;
1506
1507         ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div);
1508         if (ret)
1509                 return;
1510
1511         state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv);
1512         if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv))
1513                 state->polarity = PWM_POLARITY_INVERSED;
1514         else
1515                 state->polarity = PWM_POLARITY_NORMAL;
1516
1517         state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1),
1518                                          pdata->pwm_refclk_freq);
1519         state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight,
1520                                              pdata->pwm_refclk_freq);
1521
1522         if (state->duty_cycle > state->period)
1523                 state->duty_cycle = state->period;
1524 }
1525
1526 static const struct pwm_ops ti_sn_pwm_ops = {
1527         .request = ti_sn_pwm_request,
1528         .free = ti_sn_pwm_free,
1529         .apply = ti_sn_pwm_apply,
1530         .get_state = ti_sn_pwm_get_state,
1531         .owner = THIS_MODULE,
1532 };
1533
1534 static int ti_sn_pwm_probe(struct auxiliary_device *adev,
1535                            const struct auxiliary_device_id *id)
1536 {
1537         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1538
1539         pdata->pchip.dev = pdata->dev;
1540         pdata->pchip.ops = &ti_sn_pwm_ops;
1541         pdata->pchip.npwm = 1;
1542         pdata->pchip.of_xlate = of_pwm_single_xlate;
1543         pdata->pchip.of_pwm_n_cells = 1;
1544
1545         return pwmchip_add(&pdata->pchip);
1546 }
1547
1548 static void ti_sn_pwm_remove(struct auxiliary_device *adev)
1549 {
1550         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1551
1552         pwmchip_remove(&pdata->pchip);
1553
1554         if (pdata->pwm_enabled)
1555                 pm_runtime_put_sync(pdata->dev);
1556 }
1557
1558 static const struct auxiliary_device_id ti_sn_pwm_id_table[] = {
1559         { .name = "ti_sn65dsi86.pwm", },
1560         {},
1561 };
1562
1563 static struct auxiliary_driver ti_sn_pwm_driver = {
1564         .name = "pwm",
1565         .probe = ti_sn_pwm_probe,
1566         .remove = ti_sn_pwm_remove,
1567         .id_table = ti_sn_pwm_id_table,
1568 };
1569
1570 static int __init ti_sn_pwm_register(void)
1571 {
1572         return auxiliary_driver_register(&ti_sn_pwm_driver);
1573 }
1574
1575 static void ti_sn_pwm_unregister(void)
1576 {
1577         auxiliary_driver_unregister(&ti_sn_pwm_driver);
1578 }
1579
1580 #else
1581 static inline int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) { return 0; }
1582 static inline void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) {}
1583
1584 static inline int ti_sn_pwm_register(void) { return 0; }
1585 static inline void ti_sn_pwm_unregister(void) {}
1586 #endif
1587
1588 /* -----------------------------------------------------------------------------
1589  * GPIO Controller
1590  */
1591 #if defined(CONFIG_OF_GPIO)
1592
1593 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip,
1594                                  const struct of_phandle_args *gpiospec,
1595                                  u32 *flags)
1596 {
1597         if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells))
1598                 return -EINVAL;
1599
1600         if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1)
1601                 return -EINVAL;
1602
1603         if (flags)
1604                 *flags = gpiospec->args[1];
1605
1606         return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET;
1607 }
1608
1609 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip,
1610                                            unsigned int offset)
1611 {
1612         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1613
1614         /*
1615          * We already have to keep track of the direction because we use
1616          * that to figure out whether we've powered the device.  We can
1617          * just return that rather than (maybe) powering up the device
1618          * to ask its direction.
1619          */
1620         return test_bit(offset, pdata->gchip_output) ?
1621                 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1622 }
1623
1624 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset)
1625 {
1626         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1627         unsigned int val;
1628         int ret;
1629
1630         /*
1631          * When the pin is an input we don't forcibly keep the bridge
1632          * powered--we just power it on to read the pin.  NOTE: part of
1633          * the reason this works is that the bridge defaults (when
1634          * powered back on) to all 4 GPIOs being configured as GPIO input.
1635          * Also note that if something else is keeping the chip powered the
1636          * pm_runtime functions are lightweight increments of a refcount.
1637          */
1638         pm_runtime_get_sync(pdata->dev);
1639         ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val);
1640         pm_runtime_put_autosuspend(pdata->dev);
1641
1642         if (ret)
1643                 return ret;
1644
1645         return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset));
1646 }
1647
1648 static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset,
1649                                   int val)
1650 {
1651         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1652         int ret;
1653
1654         if (!test_bit(offset, pdata->gchip_output)) {
1655                 dev_err(pdata->dev, "Ignoring GPIO set while input\n");
1656                 return;
1657         }
1658
1659         val &= 1;
1660         ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG,
1661                                  BIT(SN_GPIO_OUTPUT_SHIFT + offset),
1662                                  val << (SN_GPIO_OUTPUT_SHIFT + offset));
1663         if (ret)
1664                 dev_warn(pdata->dev,
1665                          "Failed to set bridge GPIO %u: %d\n", offset, ret);
1666 }
1667
1668 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip,
1669                                              unsigned int offset)
1670 {
1671         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1672         int shift = offset * 2;
1673         int ret;
1674
1675         if (!test_and_clear_bit(offset, pdata->gchip_output))
1676                 return 0;
1677
1678         ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1679                                  SN_GPIO_MUX_MASK << shift,
1680                                  SN_GPIO_MUX_INPUT << shift);
1681         if (ret) {
1682                 set_bit(offset, pdata->gchip_output);
1683                 return ret;
1684         }
1685
1686         /*
1687          * NOTE: if nobody else is powering the device this may fully power
1688          * it off and when it comes back it will have lost all state, but
1689          * that's OK because the default is input and we're now an input.
1690          */
1691         pm_runtime_put_autosuspend(pdata->dev);
1692
1693         return 0;
1694 }
1695
1696 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip,
1697                                               unsigned int offset, int val)
1698 {
1699         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1700         int shift = offset * 2;
1701         int ret;
1702
1703         if (test_and_set_bit(offset, pdata->gchip_output))
1704                 return 0;
1705
1706         pm_runtime_get_sync(pdata->dev);
1707
1708         /* Set value first to avoid glitching */
1709         ti_sn_bridge_gpio_set(chip, offset, val);
1710
1711         /* Set direction */
1712         ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1713                                  SN_GPIO_MUX_MASK << shift,
1714                                  SN_GPIO_MUX_OUTPUT << shift);
1715         if (ret) {
1716                 clear_bit(offset, pdata->gchip_output);
1717                 pm_runtime_put_autosuspend(pdata->dev);
1718         }
1719
1720         return ret;
1721 }
1722
1723 static int ti_sn_bridge_gpio_request(struct gpio_chip *chip, unsigned int offset)
1724 {
1725         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1726
1727         if (offset == SN_PWM_GPIO_IDX)
1728                 return ti_sn_pwm_pin_request(pdata);
1729
1730         return 0;
1731 }
1732
1733 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset)
1734 {
1735         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1736
1737         /* We won't keep pm_runtime if we're input, so switch there on free */
1738         ti_sn_bridge_gpio_direction_input(chip, offset);
1739
1740         if (offset == SN_PWM_GPIO_IDX)
1741                 ti_sn_pwm_pin_release(pdata);
1742 }
1743
1744 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = {
1745         "GPIO1", "GPIO2", "GPIO3", "GPIO4"
1746 };
1747
1748 static int ti_sn_gpio_probe(struct auxiliary_device *adev,
1749                             const struct auxiliary_device_id *id)
1750 {
1751         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1752         int ret;
1753
1754         /* Only init if someone is going to use us as a GPIO controller */
1755         if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller"))
1756                 return 0;
1757
1758         pdata->gchip.label = dev_name(pdata->dev);
1759         pdata->gchip.parent = pdata->dev;
1760         pdata->gchip.owner = THIS_MODULE;
1761         pdata->gchip.of_xlate = tn_sn_bridge_of_xlate;
1762         pdata->gchip.of_gpio_n_cells = 2;
1763         pdata->gchip.request = ti_sn_bridge_gpio_request;
1764         pdata->gchip.free = ti_sn_bridge_gpio_free;
1765         pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction;
1766         pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input;
1767         pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output;
1768         pdata->gchip.get = ti_sn_bridge_gpio_get;
1769         pdata->gchip.set = ti_sn_bridge_gpio_set;
1770         pdata->gchip.can_sleep = true;
1771         pdata->gchip.names = ti_sn_bridge_gpio_names;
1772         pdata->gchip.ngpio = SN_NUM_GPIOS;
1773         pdata->gchip.base = -1;
1774         ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata);
1775         if (ret)
1776                 dev_err(pdata->dev, "can't add gpio chip\n");
1777
1778         return ret;
1779 }
1780
1781 static const struct auxiliary_device_id ti_sn_gpio_id_table[] = {
1782         { .name = "ti_sn65dsi86.gpio", },
1783         {},
1784 };
1785
1786 MODULE_DEVICE_TABLE(auxiliary, ti_sn_gpio_id_table);
1787
1788 static struct auxiliary_driver ti_sn_gpio_driver = {
1789         .name = "gpio",
1790         .probe = ti_sn_gpio_probe,
1791         .id_table = ti_sn_gpio_id_table,
1792 };
1793
1794 static int __init ti_sn_gpio_register(void)
1795 {
1796         return auxiliary_driver_register(&ti_sn_gpio_driver);
1797 }
1798
1799 static void ti_sn_gpio_unregister(void)
1800 {
1801         auxiliary_driver_unregister(&ti_sn_gpio_driver);
1802 }
1803
1804 #else
1805
1806 static inline int ti_sn_gpio_register(void) { return 0; }
1807 static inline void ti_sn_gpio_unregister(void) {}
1808
1809 #endif
1810
1811 /* -----------------------------------------------------------------------------
1812  * Probe & Remove
1813  */
1814
1815 static void ti_sn65dsi86_runtime_disable(void *data)
1816 {
1817         pm_runtime_disable(data);
1818 }
1819
1820 static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 *pdata)
1821 {
1822         unsigned int i;
1823         const char * const ti_sn_bridge_supply_names[] = {
1824                 "vcca", "vcc", "vccio", "vpll",
1825         };
1826
1827         for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
1828                 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
1829
1830         return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
1831                                        pdata->supplies);
1832 }
1833
1834 static int ti_sn65dsi86_probe(struct i2c_client *client,
1835                               const struct i2c_device_id *id)
1836 {
1837         struct device *dev = &client->dev;
1838         struct ti_sn65dsi86 *pdata;
1839         int ret;
1840
1841         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1842                 DRM_ERROR("device doesn't support I2C\n");
1843                 return -ENODEV;
1844         }
1845
1846         pdata = devm_kzalloc(dev, sizeof(struct ti_sn65dsi86), GFP_KERNEL);
1847         if (!pdata)
1848                 return -ENOMEM;
1849         dev_set_drvdata(dev, pdata);
1850         pdata->dev = dev;
1851
1852         mutex_init(&pdata->comms_mutex);
1853
1854         pdata->regmap = devm_regmap_init_i2c(client,
1855                                              &ti_sn65dsi86_regmap_config);
1856         if (IS_ERR(pdata->regmap))
1857                 return dev_err_probe(dev, PTR_ERR(pdata->regmap),
1858                                      "regmap i2c init failed\n");
1859
1860         pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable",
1861                                                      GPIOD_OUT_LOW);
1862         if (IS_ERR(pdata->enable_gpio))
1863                 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio),
1864                                      "failed to get enable gpio from DT\n");
1865
1866         ret = ti_sn65dsi86_parse_regulators(pdata);
1867         if (ret)
1868                 return dev_err_probe(dev, ret, "failed to parse regulators\n");
1869
1870         pdata->refclk = devm_clk_get_optional(dev, "refclk");
1871         if (IS_ERR(pdata->refclk))
1872                 return dev_err_probe(dev, PTR_ERR(pdata->refclk),
1873                                      "failed to get reference clock\n");
1874
1875         pm_runtime_enable(dev);
1876         ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev);
1877         if (ret)
1878                 return ret;
1879         pm_runtime_set_autosuspend_delay(pdata->dev, 500);
1880         pm_runtime_use_autosuspend(pdata->dev);
1881
1882         ti_sn65dsi86_debugfs_init(pdata);
1883
1884         /*
1885          * Break ourselves up into a collection of aux devices. The only real
1886          * motiviation here is to solve the chicken-and-egg problem of probe
1887          * ordering. The bridge wants the panel to be there when it probes.
1888          * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards)
1889          * when it probes. The panel and maybe backlight might want the DDC
1890          * bus or the pwm_chip. Having sub-devices allows the some sub devices
1891          * to finish probing even if others return -EPROBE_DEFER and gets us
1892          * around the problems.
1893          */
1894
1895         if (IS_ENABLED(CONFIG_OF_GPIO)) {
1896                 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio");
1897                 if (ret)
1898                         return ret;
1899         }
1900
1901         if (IS_ENABLED(CONFIG_PWM)) {
1902                 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->pwm_aux, "pwm");
1903                 if (ret)
1904                         return ret;
1905         }
1906
1907         /*
1908          * NOTE: At the end of the AUX channel probe we'll add the aux device
1909          * for the bridge. This is because the bridge can't be used until the
1910          * AUX channel is there and this is a very simple solution to the
1911          * dependency problem.
1912          */
1913         return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux");
1914 }
1915
1916 static struct i2c_device_id ti_sn65dsi86_id[] = {
1917         { "ti,sn65dsi86", 0},
1918         {},
1919 };
1920 MODULE_DEVICE_TABLE(i2c, ti_sn65dsi86_id);
1921
1922 static const struct of_device_id ti_sn65dsi86_match_table[] = {
1923         {.compatible = "ti,sn65dsi86"},
1924         {},
1925 };
1926 MODULE_DEVICE_TABLE(of, ti_sn65dsi86_match_table);
1927
1928 static struct i2c_driver ti_sn65dsi86_driver = {
1929         .driver = {
1930                 .name = "ti_sn65dsi86",
1931                 .of_match_table = ti_sn65dsi86_match_table,
1932                 .pm = &ti_sn65dsi86_pm_ops,
1933         },
1934         .probe = ti_sn65dsi86_probe,
1935         .id_table = ti_sn65dsi86_id,
1936 };
1937
1938 static int __init ti_sn65dsi86_init(void)
1939 {
1940         int ret;
1941
1942         ret = i2c_add_driver(&ti_sn65dsi86_driver);
1943         if (ret)
1944                 return ret;
1945
1946         ret = ti_sn_gpio_register();
1947         if (ret)
1948                 goto err_main_was_registered;
1949
1950         ret = ti_sn_pwm_register();
1951         if (ret)
1952                 goto err_gpio_was_registered;
1953
1954         ret = auxiliary_driver_register(&ti_sn_aux_driver);
1955         if (ret)
1956                 goto err_pwm_was_registered;
1957
1958         ret = auxiliary_driver_register(&ti_sn_bridge_driver);
1959         if (ret)
1960                 goto err_aux_was_registered;
1961
1962         return 0;
1963
1964 err_aux_was_registered:
1965         auxiliary_driver_unregister(&ti_sn_aux_driver);
1966 err_pwm_was_registered:
1967         ti_sn_pwm_unregister();
1968 err_gpio_was_registered:
1969         ti_sn_gpio_unregister();
1970 err_main_was_registered:
1971         i2c_del_driver(&ti_sn65dsi86_driver);
1972
1973         return ret;
1974 }
1975 module_init(ti_sn65dsi86_init);
1976
1977 static void __exit ti_sn65dsi86_exit(void)
1978 {
1979         auxiliary_driver_unregister(&ti_sn_bridge_driver);
1980         auxiliary_driver_unregister(&ti_sn_aux_driver);
1981         ti_sn_pwm_unregister();
1982         ti_sn_gpio_unregister();
1983         i2c_del_driver(&ti_sn65dsi86_driver);
1984 }
1985 module_exit(ti_sn65dsi86_exit);
1986
1987 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>");
1988 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
1989 MODULE_LICENSE("GPL v2");