drivers/gpu/drm/bridge/tc358768.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
   4  *  Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/device.h>
   9 #include <linux/gpio/consumer.h>
  10 #include <linux/i2c.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/regmap.h>
  14 #include <linux/regulator/consumer.h>
  15 #include <linux/slab.h>
  16
  17 #include <drm/drm_atomic_helper.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_drv.h>
  20 #include <drm/drm_mipi_dsi.h>
  21 #include <drm/drm_of.h>
  22 #include <drm/drm_panel.h>
  23 #include <video/mipi_display.h>
  24 #include <video/videomode.h>
  25
  26 /* Global (16-bit addressable) */
  27 #define TC358768_CHIPID                 0x0000
  28 #define TC358768_SYSCTL                 0x0002
  29 #define TC358768_CONFCTL                0x0004
  30 #define TC358768_VSDLY                  0x0006
  31 #define TC358768_DATAFMT                0x0008
  32 #define TC358768_GPIOEN                 0x000E
  33 #define TC358768_GPIODIR                0x0010
  34 #define TC358768_GPIOIN                 0x0012
  35 #define TC358768_GPIOOUT                0x0014
  36 #define TC358768_PLLCTL0                0x0016
  37 #define TC358768_PLLCTL1                0x0018
  38 #define TC358768_CMDBYTE                0x0022
  39 #define TC358768_PP_MISC                0x0032
  40 #define TC358768_DSITX_DT               0x0050
  41 #define TC358768_FIFOSTATUS             0x00F8
  42
  43 /* Debug (16-bit addressable) */
  44 #define TC358768_VBUFCTRL               0x00E0
  45 #define TC358768_DBG_WIDTH              0x00E2
  46 #define TC358768_DBG_VBLANK             0x00E4
  47 #define TC358768_DBG_DATA               0x00E8
  48
  49 /* TX PHY (32-bit addressable) */
  50 #define TC358768_CLW_DPHYCONTTX         0x0100
  51 #define TC358768_D0W_DPHYCONTTX         0x0104
  52 #define TC358768_D1W_DPHYCONTTX         0x0108
  53 #define TC358768_D2W_DPHYCONTTX         0x010C
  54 #define TC358768_D3W_DPHYCONTTX         0x0110
  55 #define TC358768_CLW_CNTRL              0x0140
  56 #define TC358768_D0W_CNTRL              0x0144
  57 #define TC358768_D1W_CNTRL              0x0148
  58 #define TC358768_D2W_CNTRL              0x014C
  59 #define TC358768_D3W_CNTRL              0x0150
  60
  61 /* TX PPI (32-bit addressable) */
  62 #define TC358768_STARTCNTRL             0x0204
  63 #define TC358768_DSITXSTATUS            0x0208
  64 #define TC358768_LINEINITCNT            0x0210
  65 #define TC358768_LPTXTIMECNT            0x0214
  66 #define TC358768_TCLK_HEADERCNT         0x0218
  67 #define TC358768_TCLK_TRAILCNT          0x021C
  68 #define TC358768_THS_HEADERCNT          0x0220
  69 #define TC358768_TWAKEUP                0x0224
  70 #define TC358768_TCLK_POSTCNT           0x0228
  71 #define TC358768_THS_TRAILCNT           0x022C
  72 #define TC358768_HSTXVREGCNT            0x0230
  73 #define TC358768_HSTXVREGEN             0x0234
  74 #define TC358768_TXOPTIONCNTRL          0x0238
  75 #define TC358768_BTACNTRL1              0x023C
  76
  77 /* TX CTRL (32-bit addressable) */
  78 #define TC358768_DSI_CONTROL            0x040C
  79 #define TC358768_DSI_STATUS             0x0410
  80 #define TC358768_DSI_INT                0x0414
  81 #define TC358768_DSI_INT_ENA            0x0418
  82 #define TC358768_DSICMD_RDFIFO          0x0430
  83 #define TC358768_DSI_ACKERR             0x0434
  84 #define TC358768_DSI_ACKERR_INTENA      0x0438
  85 #define TC358768_DSI_ACKERR_HALT        0x043c
  86 #define TC358768_DSI_RXERR              0x0440
  87 #define TC358768_DSI_RXERR_INTENA       0x0444
  88 #define TC358768_DSI_RXERR_HALT         0x0448
  89 #define TC358768_DSI_ERR                0x044C
  90 #define TC358768_DSI_ERR_INTENA         0x0450
  91 #define TC358768_DSI_ERR_HALT           0x0454
  92 #define TC358768_DSI_CONFW              0x0500
  93 #define TC358768_DSI_LPCMD              0x0500
  94 #define TC358768_DSI_RESET              0x0504
  95 #define TC358768_DSI_INT_CLR            0x050C
  96 #define TC358768_DSI_START              0x0518
  97
  98 /* DSITX CTRL (16-bit addressable) */
  99 #define TC358768_DSICMD_TX              0x0600
 100 #define TC358768_DSICMD_TYPE            0x0602
 101 #define TC358768_DSICMD_WC              0x0604
 102 #define TC358768_DSICMD_WD0             0x0610
 103 #define TC358768_DSICMD_WD1             0x0612
 104 #define TC358768_DSICMD_WD2             0x0614
 105 #define TC358768_DSICMD_WD3             0x0616
 106 #define TC358768_DSI_EVENT              0x0620
 107 #define TC358768_DSI_VSW                0x0622
 108 #define TC358768_DSI_VBPR               0x0624
 109 #define TC358768_DSI_VACT               0x0626
 110 #define TC358768_DSI_HSW                0x0628
 111 #define TC358768_DSI_HBPR               0x062A
 112 #define TC358768_DSI_HACT               0x062C
 113
 114 /* TC358768_DSI_CONTROL (0x040C) register */
 115 #define TC358768_DSI_CONTROL_DIS_MODE   BIT(15)
 116 #define TC358768_DSI_CONTROL_TXMD       BIT(7)
 117 #define TC358768_DSI_CONTROL_HSCKMD     BIT(5)
 118 #define TC358768_DSI_CONTROL_EOTDIS     BIT(0)
 119
 120 /* TC358768_DSI_CONFW (0x0500) register */
 121 #define TC358768_DSI_CONFW_MODE_SET     (5 << 29)
 122 #define TC358768_DSI_CONFW_MODE_CLR     (6 << 29)
 123 #define TC358768_DSI_CONFW_ADDR_DSI_CONTROL     (0x3 << 24)
 124
 125 static const char * const tc358768_supplies[] = {
 126         "vddc", "vddmipi", "vddio"
 127 };
 128
 129 struct tc358768_dsi_output {
 130         struct mipi_dsi_device *dev;
 131         struct drm_panel *panel;
 132         struct drm_bridge *bridge;
 133 };
 134
 135 struct tc358768_priv {
 136         struct device *dev;
 137         struct regmap *regmap;
 138         struct gpio_desc *reset_gpio;
 139         struct regulator_bulk_data supplies[ARRAY_SIZE(tc358768_supplies)];
 140         struct clk *refclk;
 141         int enabled;
 142         int error;
 143
 144         struct mipi_dsi_host dsi_host;
 145         struct drm_bridge bridge;
 146         struct tc358768_dsi_output output;
 147
 148         u32 pd_lines; /* number of Parallel Port Input Data Lines */
 149         u32 dsi_lanes; /* number of DSI Lanes */
 150
 151         /* Parameters for PLL programming */
 152         u32 fbd;        /* PLL feedback divider */
 153         u32 prd;        /* PLL input divider */
 154         u32 frs;        /* PLL Freqency range for HSCK (post divider) */
 155
 156         u32 dsiclk;     /* pll_clk / 2 */
 157 };
 158
 159 static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_host
 160                                                          *host)
 161 {
 162         return container_of(host, struct tc358768_priv, dsi_host);
 163 }
 164
 165 static inline struct tc358768_priv *bridge_to_tc358768(struct drm_bridge
 166                                                        *bridge)
 167 {
 168         return container_of(bridge, struct tc358768_priv, bridge);
 169 }
 170
 171 static int tc358768_clear_error(struct tc358768_priv *priv)
 172 {
 173         int ret = priv->error;
 174
 175         priv->error = 0;
 176         return ret;
 177 }
 178
 179 static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val)
 180 {
 181         /* work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
 182         int tmpval = val;
 183         size_t count = 2;
 184
 185         if (priv->error)
 186                 return;
 187
 188         /* 16-bit register? */
 189         if (reg < 0x100 || reg >= 0x600)
 190                 count = 1;
 191
 192         priv->error = regmap_bulk_write(priv->regmap, reg, &tmpval, count);
 193 }
 194
 195 static void tc358768_read(struct tc358768_priv *priv, u32 reg, u32 *val)
 196 {
 197         size_t count = 2;
 198
 199         if (priv->error)
 200                 return;
 201
 202         /* 16-bit register? */
 203         if (reg < 0x100 || reg >= 0x600) {
 204                 *val = 0;
 205                 count = 1;
 206         }
 207
 208         priv->error = regmap_bulk_read(priv->regmap, reg, val, count);
 209 }
 210
 211 static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask,
 212                                  u32 val)
 213 {
 214         u32 tmp, orig;
 215
 216         tc358768_read(priv, reg, &orig);
 217         tmp = orig & ~mask;
 218         tmp |= val & mask;
 219         if (tmp != orig)
 220                 tc358768_write(priv, reg, tmp);
 221 }
 222
 223 static int tc358768_sw_reset(struct tc358768_priv *priv)
 224 {
 225         /* Assert Reset */
 226         tc358768_write(priv, TC358768_SYSCTL, 1);
 227         /* Release Reset, Exit Sleep */
 228         tc358768_write(priv, TC358768_SYSCTL, 0);
 229
 230         return tc358768_clear_error(priv);
 231 }
 232
 233 static void tc358768_hw_enable(struct tc358768_priv *priv)
 234 {
 235         int ret;
 236
 237         if (priv->enabled)
 238                 return;
 239
 240         ret = clk_prepare_enable(priv->refclk);
 241         if (ret < 0)
 242                 dev_err(priv->dev, "error enabling refclk (%d)\n", ret);
 243
 244         ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
 245         if (ret < 0)
 246                 dev_err(priv->dev, "error enabling regulators (%d)\n", ret);
 247
 248         if (priv->reset_gpio)
 249                 usleep_range(200, 300);
 250
 251         /*
 252          * The RESX is active low (GPIO_ACTIVE_LOW).
 253          * DEASSERT (value = 0) the reset_gpio to enable the chip
 254          */
 255         gpiod_set_value_cansleep(priv->reset_gpio, 0);
 256
 257         /* wait for encoder clocks to stabilize */
 258         usleep_range(1000, 2000);
 259
 260         priv->enabled = true;
 261 }
 262
 263 static void tc358768_hw_disable(struct tc358768_priv *priv)
 264 {
 265         int ret;
 266
 267         if (!priv->enabled)
 268                 return;
 269
 270         /*
 271          * The RESX is active low (GPIO_ACTIVE_LOW).
 272          * ASSERT (value = 1) the reset_gpio to disable the chip
 273          */
 274         gpiod_set_value_cansleep(priv->reset_gpio, 1);
 275
 276         ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
 277                                      priv->supplies);
 278         if (ret < 0)
 279                 dev_err(priv->dev, "error disabling regulators (%d)\n", ret);
 280
 281         clk_disable_unprepare(priv->refclk);
 282
 283         priv->enabled = false;
 284 }
 285
 286 static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk)
 287 {
 288         return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->pd_lines);
 289 }
 290
 291 static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk)
 292 {
 293         return (u32)div_u64((u64)pclk * priv->pd_lines, priv->dsi_lanes);
 294 }
 295
 296 static int tc358768_calc_pll(struct tc358768_priv *priv,
 297                              const struct drm_display_mode *mode,
 298                              bool verify_only)
 299 {
 300         static const u32 frs_limits[] = {
 301                 1000000000,
 302                 500000000,
 303                 250000000,
 304                 125000000,
 305                 62500000
 306         };
 307         unsigned long refclk;
 308         u32 prd, target_pll, i, max_pll, min_pll;
 309         u32 frs, best_diff, best_pll, best_prd, best_fbd;
 310
 311         target_pll = tc358768_pclk_to_pll(priv, mode->clock * 1000);
 312
 313         /* pll_clk = RefClk * [(FBD + 1)/ (PRD + 1)] * [1 / (2^FRS)] */
 314
 315         for (i = 0; i < ARRAY_SIZE(frs_limits); i++)
 316                 if (target_pll >= frs_limits[i])
 317                         break;
 318
 319         if (i == ARRAY_SIZE(frs_limits) || i == 0)
 320                 return -EINVAL;
 321
 322         frs = i - 1;
 323         max_pll = frs_limits[i - 1];
 324         min_pll = frs_limits[i];
 325
 326         refclk = clk_get_rate(priv->refclk);
 327
 328         best_diff = UINT_MAX;
 329         best_pll = 0;
 330         best_prd = 0;
 331         best_fbd = 0;
 332
 333         for (prd = 0; prd < 16; ++prd) {
 334                 u32 divisor = (prd + 1) * (1 << frs);
 335                 u32 fbd;
 336
 337                 for (fbd = 0; fbd < 512; ++fbd) {
 338                         u32 pll, diff;
 339
 340                         pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor);
 341
 342                         if (pll >= max_pll || pll < min_pll)
 343                                 continue;
 344
 345                         diff = max(pll, target_pll) - min(pll, target_pll);
 346
 347                         if (diff < best_diff) {
 348                                 best_diff = diff;
 349                                 best_pll = pll;
 350                                 best_prd = prd;
 351                                 best_fbd = fbd;
 352
 353                                 if (best_diff == 0)
 354                                         goto found;
 355                         }
 356                 }
 357         }
 358
 359         if (best_diff == UINT_MAX) {
 360                 dev_err(priv->dev, "could not find suitable PLL setup\n");
 361                 return -EINVAL;
 362         }
 363
 364 found:
 365         if (verify_only)
 366                 return 0;
 367
 368         priv->fbd = best_fbd;
 369         priv->prd = best_prd;
 370         priv->frs = frs;
 371         priv->dsiclk = best_pll / 2;
 372
 373         return 0;
 374 }
 375
 376 static int tc358768_dsi_host_attach(struct mipi_dsi_host *host,
 377                                     struct mipi_dsi_device *dev)
 378 {
 379         struct tc358768_priv *priv = dsi_host_to_tc358768(host);
 380         struct drm_bridge *bridge;
 381         struct drm_panel *panel;
 382         struct device_node *ep;
 383         int ret;
 384
 385         if (dev->lanes > 4) {
 386                 dev_err(priv->dev, "unsupported number of data lanes(%u)\n",
 387                         dev->lanes);
 388                 return -EINVAL;
 389         }
 390
 391         /*
 392          * tc358768 supports both Video and Pulse mode, but the driver only
 393          * implements Video (event) mode currently
 394          */
 395         if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) {
 396                 dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n");
 397                 return -ENOTSUPP;
 398         }
 399
 400         /*
 401          * tc358768 supports RGB888, RGB666, RGB666_PACKED and RGB565, but only
 402          * RGB888 is verified.
 403          */
 404         if (dev->format != MIPI_DSI_FMT_RGB888) {
 405                 dev_warn(priv->dev, "Only MIPI_DSI_FMT_RGB888 tested!\n");
 406                 return -ENOTSUPP;
 407         }
 408
 409         ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, &panel,
 410                                           &bridge);
 411         if (ret)
 412                 return ret;
 413
 414         if (panel) {
 415                 bridge = drm_panel_bridge_add_typed(panel,
 416                                                     DRM_MODE_CONNECTOR_DSI);
 417                 if (IS_ERR(bridge))
 418                         return PTR_ERR(bridge);
 419         }
 420
 421         priv->output.dev = dev;
 422         priv->output.bridge = bridge;
 423         priv->output.panel = panel;
 424
 425         priv->dsi_lanes = dev->lanes;
 426
 427         /* get input ep (port0/endpoint0) */
 428         ret = -EINVAL;
 429         ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0);
 430         if (ep) {
 431                 ret = of_property_read_u32(ep, "data-lines", &priv->pd_lines);
 432
 433                 of_node_put(ep);
 434         }
 435
 436         if (ret)
 437                 priv->pd_lines = mipi_dsi_pixel_format_to_bpp(dev->format);
 438
 439         drm_bridge_add(&priv->bridge);
 440
 441         return 0;
 442 }
 443
 444 static int tc358768_dsi_host_detach(struct mipi_dsi_host *host,
 445                                     struct mipi_dsi_device *dev)
 446 {
 447         struct tc358768_priv *priv = dsi_host_to_tc358768(host);
 448
 449         drm_bridge_remove(&priv->bridge);
 450         if (priv->output.panel)
 451                 drm_panel_bridge_remove(priv->output.bridge);
 452
 453         return 0;
 454 }
 455
 456 static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host,
 457                                           const struct mipi_dsi_msg *msg)
 458 {
 459         struct tc358768_priv *priv = dsi_host_to_tc358768(host);
 460         struct mipi_dsi_packet packet;
 461         int ret;
 462
 463         if (!priv->enabled) {
 464                 dev_err(priv->dev, "Bridge is not enabled\n");
 465                 return -ENODEV;
 466         }
 467
 468         if (msg->rx_len) {
 469                 dev_warn(priv->dev, "MIPI rx is not supported\n");
 470                 return -ENOTSUPP;
 471         }
 472
 473         if (msg->tx_len > 8) {
 474                 dev_warn(priv->dev, "Maximum 8 byte MIPI tx is supported\n");
 475                 return -ENOTSUPP;
 476         }
 477
 478         ret = mipi_dsi_create_packet(&packet, msg);
 479         if (ret)
 480                 return ret;
 481
 482         if (mipi_dsi_packet_format_is_short(msg->type)) {
 483                 tc358768_write(priv, TC358768_DSICMD_TYPE,
 484                                (0x10 << 8) | (packet.header[0] & 0x3f));
 485                 tc358768_write(priv, TC358768_DSICMD_WC, 0);
 486                 tc358768_write(priv, TC358768_DSICMD_WD0,
 487                                (packet.header[2] << 8) | packet.header[1]);
 488         } else {
 489                 int i;
 490
 491                 tc358768_write(priv, TC358768_DSICMD_TYPE,
 492                                (0x40 << 8) | (packet.header[0] & 0x3f));
 493                 tc358768_write(priv, TC358768_DSICMD_WC, packet.payload_length);
 494                 for (i = 0; i < packet.payload_length; i += 2) {
 495                         u16 val = packet.payload[i];
 496
 497                         if (i + 1 < packet.payload_length)
 498                                 val |= packet.payload[i + 1] << 8;
 499
 500                         tc358768_write(priv, TC358768_DSICMD_WD0 + i, val);
 501                 }
 502         }
 503
 504         /* start transfer */
 505         tc358768_write(priv, TC358768_DSICMD_TX, 1);
 506
 507         ret = tc358768_clear_error(priv);
 508         if (ret)
 509                 dev_warn(priv->dev, "Software disable failed: %d\n", ret);
 510         else
 511                 ret = packet.size;
 512
 513         return ret;
 514 }
 515
 516 static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = {
 517         .attach = tc358768_dsi_host_attach,
 518         .detach = tc358768_dsi_host_detach,
 519         .transfer = tc358768_dsi_host_transfer,
 520 };
 521
 522 static int tc358768_bridge_attach(struct drm_bridge *bridge,
 523                                   enum drm_bridge_attach_flags flags)
 524 {
 525         struct tc358768_priv *priv = bridge_to_tc358768(bridge);
 526
 527         if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) {
 528                 dev_err(priv->dev, "needs atomic updates support\n");
 529                 return -ENOTSUPP;
 530         }
 531
 532         return drm_bridge_attach(bridge->encoder, priv->output.bridge, bridge,
 533                                  flags);
 534 }
 535
 536 static enum drm_mode_status
 537 tc358768_bridge_mode_valid(struct drm_bridge *bridge,
 538                            const struct drm_display_info *info,
 539                            const struct drm_display_mode *mode)
 540 {
 541         struct tc358768_priv *priv = bridge_to_tc358768(bridge);
 542
 543         if (tc358768_calc_pll(priv, mode, true))
 544                 return MODE_CLOCK_RANGE;
 545
 546         return MODE_OK;
 547 }
 548
 549 static void tc358768_bridge_disable(struct drm_bridge *bridge)
 550 {
 551         struct tc358768_priv *priv = bridge_to_tc358768(bridge);
 552         int ret;
 553
 554         /* set FrmStop */
 555         tc358768_update_bits(priv, TC358768_PP_MISC, BIT(15), BIT(15));
 556
 557         /* wait at least for one frame */
 558         msleep(50);
 559
 560         /* clear PP_en */
 561         tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), 0);
 562
 563         /* set RstPtr */
 564         tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), BIT(14));
 565
 566         ret = tc358768_clear_error(priv);
 567         if (ret)
 568                 dev_warn(priv->dev, "Software disable failed: %d\n", ret);
 569 }
 570
 571 static void tc358768_bridge_post_disable(struct drm_bridge *bridge)
 572 {
 573         struct tc358768_priv *priv = bridge_to_tc358768(bridge);
 574
 575         tc358768_hw_disable(priv);
 576 }
 577
 578 static int tc358768_setup_pll(struct tc358768_priv *priv,
 579                               const struct drm_display_mode *mode)
 580 {
 581         u32 fbd, prd, frs;
 582         int ret;
 583
 584         ret = tc358768_calc_pll(priv, mode, false);
 585         if (ret) {
 586                 dev_err(priv->dev, "PLL calculation failed: %d\n", ret);
 587                 return ret;
 588         }
 589
 590         fbd = priv->fbd;
 591         prd = priv->prd;
 592         frs = priv->frs;
 593
 594         dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n",
 595                 clk_get_rate(priv->refclk), fbd, prd, frs);
 596         dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, DSIByteClk %u\n",
 597                 priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4);
 598         dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n",
 599                 tc358768_pll_to_pclk(priv, priv->dsiclk * 2),
 600                 mode->clock * 1000);
 601
 602         /* PRD[15:12] FBD[8:0] */
 603         tc358768_write(priv, TC358768_PLLCTL0, (prd << 12) | fbd);
 604
 605         /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */
 606         tc358768_write(priv, TC358768_PLLCTL1,
 607                        (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0));
 608
 609         /* wait for lock */
 610         usleep_range(1000, 2000);
 611
 612         /* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */
 613         tc358768_write(priv, TC358768_PLLCTL1,
 614                        (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0));
 615
 616         return tc358768_clear_error(priv);
 617 }
 618
 619 #define TC358768_PRECISION      1000
 620 static u32 tc358768_ns_to_cnt(u32 ns, u32 period_nsk)
 621 {
 622         return (ns * TC358768_PRECISION + period_nsk) / period_nsk;
 623 }
 624
 625 static u32 tc358768_to_ns(u32 nsk)
 626 {
 627         return (nsk / TC358768_PRECISION);
 628 }
 629
 630 static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
 631 {
 632         struct tc358768_priv *priv = bridge_to_tc358768(bridge);
 633         struct mipi_dsi_device *dsi_dev = priv->output.dev;
 634         unsigned long mode_flags = dsi_dev->mode_flags;
 635         u32 val, val2, lptxcnt, hact, data_type;
 636         const struct drm_display_mode *mode;
 637         u32 dsibclk_nsk, dsiclk_nsk, ui_nsk, phy_delay_nsk;
 638         u32 dsiclk, dsibclk, video_start;
 639         const u32 internal_delay = 40;
 640         int ret, i;
 641
 642         if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
 643                 dev_warn_once(priv->dev, "Non-continuous mode unimplemented, falling back to continuous\n");
 644                 mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS;
 645         }
 646
 647         tc358768_hw_enable(priv);
 648
 649         ret = tc358768_sw_reset(priv);
 650         if (ret) {
 651                 dev_err(priv->dev, "Software reset failed: %d\n", ret);
 652                 tc358768_hw_disable(priv);
 653                 return;
 654         }
 655
 656         mode = &bridge->encoder->crtc->state->adjusted_mode;
 657         ret = tc358768_setup_pll(priv, mode);
 658         if (ret) {
 659                 dev_err(priv->dev, "PLL setup failed: %d\n", ret);
 660                 tc358768_hw_disable(priv);
 661                 return;
 662         }
 663
 664         dsiclk = priv->dsiclk;
 665         dsibclk = dsiclk / 4;
 666
 667         /* Data Format Control Register */
 668         val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */
 669         switch (dsi_dev->format) {
 670         case MIPI_DSI_FMT_RGB888:
 671                 val |= (0x3 << 4);
 672                 hact = mode->hdisplay * 3;
 673                 video_start = (mode->htotal - mode->hsync_start) * 3;
 674                 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
 675                 break;
 676         case MIPI_DSI_FMT_RGB666:
 677                 val |= (0x4 << 4);
 678                 hact = mode->hdisplay * 3;
 679                 video_start = (mode->htotal - mode->hsync_start) * 3;
 680                 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
 681                 break;
 682
 683         case MIPI_DSI_FMT_RGB666_PACKED:
 684                 val |= (0x4 << 4) | BIT(3);
 685                 hact = mode->hdisplay * 18 / 8;
 686                 video_start = (mode->htotal - mode->hsync_start) * 18 / 8;
 687                 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
 688                 break;
 689
 690         case MIPI_DSI_FMT_RGB565:
 691                 val |= (0x5 << 4);
 692                 hact = mode->hdisplay * 2;
 693                 video_start = (mode->htotal - mode->hsync_start) * 2;
 694                 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
 695                 break;
 696         default:
 697                 dev_err(priv->dev, "Invalid data format (%u)\n",
 698                         dsi_dev->format);
 699                 tc358768_hw_disable(priv);
 700                 return;
 701         }
 702
 703         /* VSDly[9:0] */
 704         video_start = max(video_start, internal_delay + 1) - internal_delay;
 705         tc358768_write(priv, TC358768_VSDLY, video_start);
 706
 707         tc358768_write(priv, TC358768_DATAFMT, val);
 708         tc358768_write(priv, TC358768_DSITX_DT, data_type);
 709
 710         /* Enable D-PHY (HiZ->LP11) */
 711         tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000);
 712         /* Enable lanes */
 713         for (i = 0; i < dsi_dev->lanes; i++)
 714                 tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000);
 715
 716         /* DSI Timings */
 717         dsibclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION,
 718                                   dsibclk);
 719         dsiclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION, dsiclk);
 720         ui_nsk = dsiclk_nsk / 2;
 721         phy_delay_nsk = dsibclk_nsk + 2 * dsiclk_nsk;
 722         dev_dbg(priv->dev, "dsiclk_nsk: %u\n", dsiclk_nsk);
 723         dev_dbg(priv->dev, "ui_nsk: %u\n", ui_nsk);
 724         dev_dbg(priv->dev, "dsibclk_nsk: %u\n", dsibclk_nsk);
 725         dev_dbg(priv->dev, "phy_delay_nsk: %u\n", phy_delay_nsk);
 726
 727         /* LP11 > 100us for D-PHY Rx Init */
 728         val = tc358768_ns_to_cnt(100 * 1000, dsibclk_nsk) - 1;
 729         dev_dbg(priv->dev, "LINEINITCNT: 0x%x\n", val);
 730         tc358768_write(priv, TC358768_LINEINITCNT, val);
 731
 732         /* LPTimeCnt > 50ns */
 733         val = tc358768_ns_to_cnt(50, dsibclk_nsk) - 1;
 734         lptxcnt = val;
 735         dev_dbg(priv->dev, "LPTXTIMECNT: 0x%x\n", val);
 736         tc358768_write(priv, TC358768_LPTXTIMECNT, val);
 737
 738         /* 38ns < TCLK_PREPARE < 95ns */
 739         val = tc358768_ns_to_cnt(65, dsibclk_nsk) - 1;
 740         /* TCLK_PREPARE > 300ns */
 741         val2 = tc358768_ns_to_cnt(300 + tc358768_to_ns(3 * ui_nsk),
 742                                   dsibclk_nsk);
 743         val |= (val2 - tc358768_to_ns(phy_delay_nsk - dsibclk_nsk)) << 8;
 744         dev_dbg(priv->dev, "TCLK_HEADERCNT: 0x%x\n", val);
 745         tc358768_write(priv, TC358768_TCLK_HEADERCNT, val);
 746
 747         /* TCLK_TRAIL > 60ns + 3*UI */
 748         val = 60 + tc358768_to_ns(3 * ui_nsk);
 749         val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 5;
 750         dev_dbg(priv->dev, "TCLK_TRAILCNT: 0x%x\n", val);
 751         tc358768_write(priv, TC358768_TCLK_TRAILCNT, val);
 752
 753         /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */
 754         val = 50 + tc358768_to_ns(4 * ui_nsk);
 755         val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1;
 756         /* THS_ZERO > 145ns + 10*UI */
 757         val2 = tc358768_ns_to_cnt(145 - tc358768_to_ns(ui_nsk), dsibclk_nsk);
 758         val |= (val2 - tc358768_to_ns(phy_delay_nsk)) << 8;
 759         dev_dbg(priv->dev, "THS_HEADERCNT: 0x%x\n", val);
 760         tc358768_write(priv, TC358768_THS_HEADERCNT, val);
 761
 762         /* TWAKEUP > 1ms in lptxcnt steps */
 763         val = tc358768_ns_to_cnt(1020000, dsibclk_nsk);
 764         val = val / (lptxcnt + 1) - 1;
 765         dev_dbg(priv->dev, "TWAKEUP: 0x%x\n", val);
 766         tc358768_write(priv, TC358768_TWAKEUP, val);
 767
 768         /* TCLK_POSTCNT > 60ns + 52*UI */
 769         val = tc358768_ns_to_cnt(60 + tc358768_to_ns(52 * ui_nsk),
 770                                  dsibclk_nsk) - 3;
 771         dev_dbg(priv->dev, "TCLK_POSTCNT: 0x%x\n", val);
 772         tc358768_write(priv, TC358768_TCLK_POSTCNT, val);
 773
 774         /* 60ns + 4*UI < THS_PREPARE < 105ns + 12*UI */
 775         val = tc358768_ns_to_cnt(60 + tc358768_to_ns(15 * ui_nsk),
 776                                  dsibclk_nsk) - 5;
 777         dev_dbg(priv->dev, "THS_TRAILCNT: 0x%x\n", val);
 778         tc358768_write(priv, TC358768_THS_TRAILCNT, val);
 779
 780         val = BIT(0);
 781         for (i = 0; i < dsi_dev->lanes; i++)
 782                 val |= BIT(i + 1);
 783         tc358768_write(priv, TC358768_HSTXVREGEN, val);
 784
 785         if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
 786                 tc358768_write(priv, TC358768_TXOPTIONCNTRL, 0x1);
 787
 788         /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */
 789         val = tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4);
 790         val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1;
 791         val2 = tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk),
 792                                   dsibclk_nsk) - 2;
 793         val = val << 16 | val2;
 794         dev_dbg(priv->dev, "BTACNTRL1: 0x%x\n", val);
 795         tc358768_write(priv, TC358768_BTACNTRL1, val);
 796
 797         /* START[0] */
 798         tc358768_write(priv, TC358768_STARTCNTRL, 1);
 799
 800         if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
 801                 /* Set pulse mode */
 802                 tc358768_write(priv, TC358768_DSI_EVENT, 0);
 803
 804                 /* vact */
 805                 tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay);
 806
 807                 /* vsw */
 808                 tc358768_write(priv, TC358768_DSI_VSW,
 809                                mode->vsync_end - mode->vsync_start);
 810                 /* vbp */
 811                 tc358768_write(priv, TC358768_DSI_VBPR,
 812                                mode->vtotal - mode->vsync_end);
 813
 814                 /* hsw * byteclk * ndl / pclk */
 815                 val = (u32)div_u64((mode->hsync_end - mode->hsync_start) *
 816                                    ((u64)priv->dsiclk / 4) * priv->dsi_lanes,
 817                                    mode->clock * 1000);
 818                 tc358768_write(priv, TC358768_DSI_HSW, val);
 819
 820                 /* hbp * byteclk * ndl / pclk */
 821                 val = (u32)div_u64((mode->htotal - mode->hsync_end) *
 822                                    ((u64)priv->dsiclk / 4) * priv->dsi_lanes,
 823                                    mode->clock * 1000);
 824                 tc358768_write(priv, TC358768_DSI_HBPR, val);
 825         } else {
 826                 /* Set event mode */
 827                 tc358768_write(priv, TC358768_DSI_EVENT, 1);
 828
 829                 /* vact */
 830                 tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay);
 831
 832                 /* vsw (+ vbp) */
 833                 tc358768_write(priv, TC358768_DSI_VSW,
 834                                mode->vtotal - mode->vsync_start);
 835                 /* vbp (not used in event mode) */
 836                 tc358768_write(priv, TC358768_DSI_VBPR, 0);
 837
 838                 /* (hsw + hbp) * byteclk * ndl / pclk */
 839                 val = (u32)div_u64((mode->htotal - mode->hsync_start) *
 840                                    ((u64)priv->dsiclk / 4) * priv->dsi_lanes,
 841                                    mode->clock * 1000);
 842                 tc358768_write(priv, TC358768_DSI_HSW, val);
 843
 844                 /* hbp (not used in event mode) */
 845                 tc358768_write(priv, TC358768_DSI_HBPR, 0);
 846         }
 847
 848         /* hact (bytes) */
 849         tc358768_write(priv, TC358768_DSI_HACT, hact);
 850
 851         /* VSYNC polarity */
 852         if (!(mode->flags & DRM_MODE_FLAG_NVSYNC))
 853                 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), BIT(5));
 854         /* HSYNC polarity */
 855         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 856                 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), BIT(0));
 857
 858         /* Start DSI Tx */
 859         tc358768_write(priv, TC358768_DSI_START, 0x1);
 860
 861         /* Configure DSI_Control register */
 862         val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
 863         val |= TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD |
 864                0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS;
 865         tc358768_write(priv, TC358768_DSI_CONFW, val);
 866
 867         val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
 868         val |= (dsi_dev->lanes - 1) << 1;
 869
 870         if (!(dsi_dev->mode_flags & MIPI_DSI_MODE_LPM))
 871                 val |= TC358768_DSI_CONTROL_TXMD;
 872
 873         if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
 874                 val |= TC358768_DSI_CONTROL_HSCKMD;
 875
 876         if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
 877                 val |= TC358768_DSI_CONTROL_EOTDIS;
 878
 879         tc358768_write(priv, TC358768_DSI_CONFW, val);
 880
 881         val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
 882         val |= TC358768_DSI_CONTROL_DIS_MODE; /* DSI mode */
 883         tc358768_write(priv, TC358768_DSI_CONFW, val);
 884
 885         ret = tc358768_clear_error(priv);
 886         if (ret) {
 887                 dev_err(priv->dev, "Bridge pre_enable failed: %d\n", ret);
 888                 tc358768_bridge_disable(bridge);
 889                 tc358768_bridge_post_disable(bridge);
 890         }
 891 }
 892
 893 static void tc358768_bridge_enable(struct drm_bridge *bridge)
 894 {
 895         struct tc358768_priv *priv = bridge_to_tc358768(bridge);
 896         int ret;
 897
 898         if (!priv->enabled) {
 899                 dev_err(priv->dev, "Bridge is not enabled\n");
 900                 return;
 901         }
 902
 903         /* clear FrmStop and RstPtr */
 904         tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0);
 905
 906         /* set PP_en */
 907         tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), BIT(6));
 908
 909         ret = tc358768_clear_error(priv);
 910         if (ret) {
 911                 dev_err(priv->dev, "Bridge enable failed: %d\n", ret);
 912                 tc358768_bridge_disable(bridge);
 913                 tc358768_bridge_post_disable(bridge);
 914         }
 915 }
 916
 917 static const struct drm_bridge_funcs tc358768_bridge_funcs = {
 918         .attach = tc358768_bridge_attach,
 919         .mode_valid = tc358768_bridge_mode_valid,
 920         .pre_enable = tc358768_bridge_pre_enable,
 921         .enable = tc358768_bridge_enable,
 922         .disable = tc358768_bridge_disable,
 923         .post_disable = tc358768_bridge_post_disable,
 924 };
 925
 926 static const struct drm_bridge_timings default_tc358768_timings = {
 927         .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
 928                  | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
 929                  | DRM_BUS_FLAG_DE_HIGH,
 930 };
 931
 932 static bool tc358768_is_reserved_reg(unsigned int reg)
 933 {
 934         switch (reg) {
 935         case 0x114 ... 0x13f:
 936         case 0x200:
 937         case 0x20c:
 938         case 0x400 ... 0x408:
 939         case 0x41c ... 0x42f:
 940                 return true;
 941         default:
 942                 return false;
 943         }
 944 }
 945
 946 static bool tc358768_writeable_reg(struct device *dev, unsigned int reg)
 947 {
 948         if (tc358768_is_reserved_reg(reg))
 949                 return false;
 950
 951         switch (reg) {
 952         case TC358768_CHIPID:
 953         case TC358768_FIFOSTATUS:
 954         case TC358768_DSITXSTATUS ... (TC358768_DSITXSTATUS + 2):
 955         case TC358768_DSI_CONTROL ... (TC358768_DSI_INT_ENA + 2):
 956         case TC358768_DSICMD_RDFIFO ... (TC358768_DSI_ERR_HALT + 2):
 957                 return false;
 958         default:
 959                 return true;
 960         }
 961 }
 962
 963 static bool tc358768_readable_reg(struct device *dev, unsigned int reg)
 964 {
 965         if (tc358768_is_reserved_reg(reg))
 966                 return false;
 967
 968         switch (reg) {
 969         case TC358768_STARTCNTRL:
 970         case TC358768_DSI_CONFW ... (TC358768_DSI_CONFW + 2):
 971         case TC358768_DSI_INT_CLR ... (TC358768_DSI_INT_CLR + 2):
 972         case TC358768_DSI_START ... (TC358768_DSI_START + 2):
 973         case TC358768_DBG_DATA:
 974                 return false;
 975         default:
 976                 return true;
 977         }
 978 }
 979
 980 static const struct regmap_config tc358768_regmap_config = {
 981         .name = "tc358768",
 982         .reg_bits = 16,
 983         .val_bits = 16,
 984         .max_register = TC358768_DSI_HACT,
 985         .cache_type = REGCACHE_NONE,
 986         .writeable_reg = tc358768_writeable_reg,
 987         .readable_reg = tc358768_readable_reg,
 988         .reg_format_endian = REGMAP_ENDIAN_BIG,
 989         .val_format_endian = REGMAP_ENDIAN_BIG,
 990 };
 991
 992 static const struct i2c_device_id tc358768_i2c_ids[] = {
 993         { "tc358768", 0 },
 994         { "tc358778", 0 },
 995         { }
 996 };
 997 MODULE_DEVICE_TABLE(i2c, tc358768_i2c_ids);
 998
 999 static const struct of_device_id tc358768_of_ids[] = {
1000         { .compatible = "toshiba,tc358768", },
1001         { .compatible = "toshiba,tc358778", },
1002         { }
1003 };
1004 MODULE_DEVICE_TABLE(of, tc358768_of_ids);
1005
1006 static int tc358768_get_regulators(struct tc358768_priv *priv)
1007 {
1008         int i, ret;
1009
1010         for (i = 0; i < ARRAY_SIZE(priv->supplies); ++i)
1011                 priv->supplies[i].supply = tc358768_supplies[i];
1012
1013         ret = devm_regulator_bulk_get(priv->dev, ARRAY_SIZE(priv->supplies),
1014                                       priv->supplies);
1015         if (ret < 0)
1016                 dev_err(priv->dev, "failed to get regulators: %d\n", ret);
1017
1018         return ret;
1019 }
1020
1021 static int tc358768_i2c_probe(struct i2c_client *client,
1022                               const struct i2c_device_id *id)
1023 {
1024         struct tc358768_priv *priv;
1025         struct device *dev = &client->dev;
1026         struct device_node *np = dev->of_node;
1027         int ret;
1028
1029         if (!np)
1030                 return -ENODEV;
1031
1032         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1033         if (!priv)
1034                 return -ENOMEM;
1035
1036         dev_set_drvdata(dev, priv);
1037         priv->dev = dev;
1038
1039         ret = tc358768_get_regulators(priv);
1040         if (ret)
1041                 return ret;
1042
1043         priv->refclk = devm_clk_get(dev, "refclk");
1044         if (IS_ERR(priv->refclk))
1045                 return PTR_ERR(priv->refclk);
1046
1047         /*
1048          * RESX is low active, to disable tc358768 initially (keep in reset)
1049          * the gpio line must be LOW. This is the ASSERTED state of
1050          * GPIO_ACTIVE_LOW (GPIOD_OUT_HIGH == ASSERTED).
1051          */
1052         priv->reset_gpio  = devm_gpiod_get_optional(dev, "reset",
1053                                                     GPIOD_OUT_HIGH);
1054         if (IS_ERR(priv->reset_gpio))
1055                 return PTR_ERR(priv->reset_gpio);
1056
1057         priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config);
1058         if (IS_ERR(priv->regmap)) {
1059                 dev_err(dev, "Failed to init regmap\n");
1060                 return PTR_ERR(priv->regmap);
1061         }
1062
1063         priv->dsi_host.dev = dev;
1064         priv->dsi_host.ops = &tc358768_dsi_host_ops;
1065
1066         priv->bridge.funcs = &tc358768_bridge_funcs;
1067         priv->bridge.timings = &default_tc358768_timings;
1068         priv->bridge.of_node = np;
1069
1070         i2c_set_clientdata(client, priv);
1071
1072         return mipi_dsi_host_register(&priv->dsi_host);
1073 }
1074
1075 static int tc358768_i2c_remove(struct i2c_client *client)
1076 {
1077         struct tc358768_priv *priv = i2c_get_clientdata(client);
1078
1079         mipi_dsi_host_unregister(&priv->dsi_host);
1080
1081         return 0;
1082 }
1083
1084 static struct i2c_driver tc358768_driver = {
1085         .driver = {
1086                 .name = "tc358768",
1087                 .of_match_table = tc358768_of_ids,
1088         },
1089         .id_table = tc358768_i2c_ids,
1090         .probe = tc358768_i2c_probe,
1091         .remove = tc358768_i2c_remove,
1092 };
1093 module_i2c_driver(tc358768_driver);
1094
1095 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
1096 MODULE_DESCRIPTION("TC358768AXBG/TC358778XBG DSI bridge");
1097 MODULE_LICENSE("GPL v2");