drivers/gpu/drm/bridge/tc358767.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver
   4  *
   5  * The TC358767/TC358867/TC9595 can operate in multiple modes.
   6  * All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP .
   7  *
   8  * Copyright (C) 2016 CogentEmbedded Inc
   9  * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
  10  *
  11  * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
  12  *
  13  * Copyright (C) 2016 Zodiac Inflight Innovations
  14  *
  15  * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c
  16  *
  17  * Copyright (C) 2012 Texas Instruments
  18  * Author: Rob Clark <robdclark@gmail.com>
  19  */
  20
  21 #include <linux/bitfield.h>
  22 #include <linux/clk.h>
  23 #include <linux/device.h>
  24 #include <linux/gpio/consumer.h>
  25 #include <linux/i2c.h>
  26 #include <linux/kernel.h>
  27 #include <linux/media-bus-format.h>
  28 #include <linux/module.h>
  29 #include <linux/regmap.h>
  30 #include <linux/slab.h>
  31
  32 #include <drm/display/drm_dp_helper.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_bridge.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_mipi_dsi.h>
  37 #include <drm/drm_of.h>
  38 #include <drm/drm_panel.h>
  39 #include <drm/drm_print.h>
  40 #include <drm/drm_probe_helper.h>
  41
  42 /* Registers */
  43
  44 /* PPI layer registers */
  45 #define PPI_STARTPPI            0x0104 /* START control bit */
  46 #define PPI_LPTXTIMECNT         0x0114 /* LPTX timing signal */
  47 #define LPX_PERIOD                      3
  48 #define PPI_LANEENABLE          0x0134
  49 #define PPI_TX_RX_TA            0x013c
  50 #define TTA_GET                         0x40000
  51 #define TTA_SURE                        6
  52 #define PPI_D0S_ATMR            0x0144
  53 #define PPI_D1S_ATMR            0x0148
  54 #define PPI_D0S_CLRSIPOCOUNT    0x0164 /* Assertion timer for Lane 0 */
  55 #define PPI_D1S_CLRSIPOCOUNT    0x0168 /* Assertion timer for Lane 1 */
  56 #define PPI_D2S_CLRSIPOCOUNT    0x016c /* Assertion timer for Lane 2 */
  57 #define PPI_D3S_CLRSIPOCOUNT    0x0170 /* Assertion timer for Lane 3 */
  58 #define PPI_START_FUNCTION              BIT(0)
  59
  60 /* DSI layer registers */
  61 #define DSI_STARTDSI            0x0204 /* START control bit of DSI-TX */
  62 #define DSI_LANEENABLE          0x0210 /* Enables each lane */
  63 #define DSI_RX_START                    BIT(0)
  64
  65 /* Lane enable PPI and DSI register bits */
  66 #define LANEENABLE_CLEN         BIT(0)
  67 #define LANEENABLE_L0EN         BIT(1)
  68 #define LANEENABLE_L1EN         BIT(2)
  69 #define LANEENABLE_L2EN         BIT(1)
  70 #define LANEENABLE_L3EN         BIT(2)
  71
  72 /* Display Parallel Input Interface */
  73 #define DPIPXLFMT               0x0440
  74 #define VS_POL_ACTIVE_LOW               (1 << 10)
  75 #define HS_POL_ACTIVE_LOW               (1 << 9)
  76 #define DE_POL_ACTIVE_HIGH              (0 << 8)
  77 #define SUB_CFG_TYPE_CONFIG1            (0 << 2) /* LSB aligned */
  78 #define SUB_CFG_TYPE_CONFIG2            (1 << 2) /* Loosely Packed */
  79 #define SUB_CFG_TYPE_CONFIG3            (2 << 2) /* LSB aligned 8-bit */
  80 #define DPI_BPP_RGB888                  (0 << 0)
  81 #define DPI_BPP_RGB666                  (1 << 0)
  82 #define DPI_BPP_RGB565                  (2 << 0)
  83
  84 /* Display Parallel Output Interface */
  85 #define POCTRL                  0x0448
  86 #define POCTRL_S2P                      BIT(7)
  87 #define POCTRL_PCLK_POL                 BIT(3)
  88 #define POCTRL_VS_POL                   BIT(2)
  89 #define POCTRL_HS_POL                   BIT(1)
  90 #define POCTRL_DE_POL                   BIT(0)
  91
  92 /* Video Path */
  93 #define VPCTRL0                 0x0450
  94 #define VSDELAY                 GENMASK(31, 20)
  95 #define OPXLFMT_RGB666                  (0 << 8)
  96 #define OPXLFMT_RGB888                  (1 << 8)
  97 #define FRMSYNC_DISABLED                (0 << 4) /* Video Timing Gen Disabled */
  98 #define FRMSYNC_ENABLED                 (1 << 4) /* Video Timing Gen Enabled */
  99 #define MSF_DISABLED                    (0 << 0) /* Magic Square FRC disabled */
 100 #define MSF_ENABLED                     (1 << 0) /* Magic Square FRC enabled */
 101 #define HTIM01                  0x0454
 102 #define HPW                     GENMASK(8, 0)
 103 #define HBPR                    GENMASK(24, 16)
 104 #define HTIM02                  0x0458
 105 #define HDISPR                  GENMASK(10, 0)
 106 #define HFPR                    GENMASK(24, 16)
 107 #define VTIM01                  0x045c
 108 #define VSPR                    GENMASK(7, 0)
 109 #define VBPR                    GENMASK(23, 16)
 110 #define VTIM02                  0x0460
 111 #define VFPR                    GENMASK(23, 16)
 112 #define VDISPR                  GENMASK(10, 0)
 113 #define VFUEN0                  0x0464
 114 #define VFUEN                           BIT(0)   /* Video Frame Timing Upload */
 115
 116 /* System */
 117 #define TC_IDREG                0x0500
 118 #define SYSSTAT                 0x0508
 119 #define SYSCTRL                 0x0510
 120 #define DP0_AUDSRC_NO_INPUT             (0 << 3)
 121 #define DP0_AUDSRC_I2S_RX               (1 << 3)
 122 #define DP0_VIDSRC_NO_INPUT             (0 << 0)
 123 #define DP0_VIDSRC_DSI_RX               (1 << 0)
 124 #define DP0_VIDSRC_DPI_RX               (2 << 0)
 125 #define DP0_VIDSRC_COLOR_BAR            (3 << 0)
 126 #define SYSRSTENB               0x050c
 127 #define ENBI2C                          (1 << 0)
 128 #define ENBLCD0                         (1 << 2)
 129 #define ENBBM                           (1 << 3)
 130 #define ENBDSIRX                        (1 << 4)
 131 #define ENBREG                          (1 << 5)
 132 #define ENBHDCP                         (1 << 8)
 133 #define GPIOM                   0x0540
 134 #define GPIOC                   0x0544
 135 #define GPIOO                   0x0548
 136 #define GPIOI                   0x054c
 137 #define INTCTL_G                0x0560
 138 #define INTSTS_G                0x0564
 139
 140 #define INT_SYSERR              BIT(16)
 141 #define INT_GPIO_H(x)           (1 << (x == 0 ? 2 : 10))
 142 #define INT_GPIO_LC(x)          (1 << (x == 0 ? 3 : 11))
 143
 144 #define INT_GP0_LCNT            0x0584
 145 #define INT_GP1_LCNT            0x0588
 146
 147 /* Control */
 148 #define DP0CTL                  0x0600
 149 #define VID_MN_GEN                      BIT(6)   /* Auto-generate M/N values */
 150 #define EF_EN                           BIT(5)   /* Enable Enhanced Framing */
 151 #define VID_EN                          BIT(1)   /* Video transmission enable */
 152 #define DP_EN                           BIT(0)   /* Enable DPTX function */
 153
 154 /* Clocks */
 155 #define DP0_VIDMNGEN0           0x0610
 156 #define DP0_VIDMNGEN1           0x0614
 157 #define DP0_VMNGENSTATUS        0x0618
 158
 159 /* Main Channel */
 160 #define DP0_SECSAMPLE           0x0640
 161 #define DP0_VIDSYNCDELAY        0x0644
 162 #define VID_SYNC_DLY            GENMASK(15, 0)
 163 #define THRESH_DLY              GENMASK(31, 16)
 164
 165 #define DP0_TOTALVAL            0x0648
 166 #define H_TOTAL                 GENMASK(15, 0)
 167 #define V_TOTAL                 GENMASK(31, 16)
 168 #define DP0_STARTVAL            0x064c
 169 #define H_START                 GENMASK(15, 0)
 170 #define V_START                 GENMASK(31, 16)
 171 #define DP0_ACTIVEVAL           0x0650
 172 #define H_ACT                   GENMASK(15, 0)
 173 #define V_ACT                   GENMASK(31, 16)
 174
 175 #define DP0_SYNCVAL             0x0654
 176 #define VS_WIDTH                GENMASK(30, 16)
 177 #define HS_WIDTH                GENMASK(14, 0)
 178 #define SYNCVAL_HS_POL_ACTIVE_LOW       (1 << 15)
 179 #define SYNCVAL_VS_POL_ACTIVE_LOW       (1 << 31)
 180 #define DP0_MISC                0x0658
 181 #define TU_SIZE_RECOMMENDED             (63) /* LSCLK cycles per TU */
 182 #define MAX_TU_SYMBOL           GENMASK(28, 23)
 183 #define TU_SIZE                 GENMASK(21, 16)
 184 #define BPC_6                           (0 << 5)
 185 #define BPC_8                           (1 << 5)
 186
 187 /* AUX channel */
 188 #define DP0_AUXCFG0             0x0660
 189 #define DP0_AUXCFG0_BSIZE       GENMASK(11, 8)
 190 #define DP0_AUXCFG0_ADDR_ONLY   BIT(4)
 191 #define DP0_AUXCFG1             0x0664
 192 #define AUX_RX_FILTER_EN                BIT(16)
 193
 194 #define DP0_AUXADDR             0x0668
 195 #define DP0_AUXWDATA(i)         (0x066c + (i) * 4)
 196 #define DP0_AUXRDATA(i)         (0x067c + (i) * 4)
 197 #define DP0_AUXSTATUS           0x068c
 198 #define AUX_BYTES               GENMASK(15, 8)
 199 #define AUX_STATUS              GENMASK(7, 4)
 200 #define AUX_TIMEOUT             BIT(1)
 201 #define AUX_BUSY                BIT(0)
 202 #define DP0_AUXI2CADR           0x0698
 203
 204 /* Link Training */
 205 #define DP0_SRCCTRL             0x06a0
 206 #define DP0_SRCCTRL_SCRMBLDIS           BIT(13)
 207 #define DP0_SRCCTRL_EN810B              BIT(12)
 208 #define DP0_SRCCTRL_NOTP                (0 << 8)
 209 #define DP0_SRCCTRL_TP1                 (1 << 8)
 210 #define DP0_SRCCTRL_TP2                 (2 << 8)
 211 #define DP0_SRCCTRL_LANESKEW            BIT(7)
 212 #define DP0_SRCCTRL_SSCG                BIT(3)
 213 #define DP0_SRCCTRL_LANES_1             (0 << 2)
 214 #define DP0_SRCCTRL_LANES_2             (1 << 2)
 215 #define DP0_SRCCTRL_BW27                (1 << 1)
 216 #define DP0_SRCCTRL_BW162               (0 << 1)
 217 #define DP0_SRCCTRL_AUTOCORRECT         BIT(0)
 218 #define DP0_LTSTAT              0x06d0
 219 #define LT_LOOPDONE                     BIT(13)
 220 #define LT_STATUS_MASK                  (0x1f << 8)
 221 #define LT_CHANNEL1_EQ_BITS             (DP_CHANNEL_EQ_BITS << 4)
 222 #define LT_INTERLANE_ALIGN_DONE         BIT(3)
 223 #define LT_CHANNEL0_EQ_BITS             (DP_CHANNEL_EQ_BITS)
 224 #define DP0_SNKLTCHGREQ         0x06d4
 225 #define DP0_LTLOOPCTRL          0x06d8
 226 #define DP0_SNKLTCTRL           0x06e4
 227
 228 #define DP1_SRCCTRL             0x07a0
 229
 230 /* PHY */
 231 #define DP_PHY_CTRL             0x0800
 232 #define DP_PHY_RST                      BIT(28)  /* DP PHY Global Soft Reset */
 233 #define BGREN                           BIT(25)  /* AUX PHY BGR Enable */
 234 #define PWR_SW_EN                       BIT(24)  /* PHY Power Switch Enable */
 235 #define PHY_M1_RST                      BIT(12)  /* Reset PHY1 Main Channel */
 236 #define PHY_RDY                         BIT(16)  /* PHY Main Channels Ready */
 237 #define PHY_M0_RST                      BIT(8)   /* Reset PHY0 Main Channel */
 238 #define PHY_2LANE                       BIT(2)   /* PHY Enable 2 lanes */
 239 #define PHY_A0_EN                       BIT(1)   /* PHY Aux Channel0 Enable */
 240 #define PHY_M0_EN                       BIT(0)   /* PHY Main Channel0 Enable */
 241
 242 /* PLL */
 243 #define DP0_PLLCTRL             0x0900
 244 #define DP1_PLLCTRL             0x0904  /* not defined in DS */
 245 #define PXL_PLLCTRL             0x0908
 246 #define PLLUPDATE                       BIT(2)
 247 #define PLLBYP                          BIT(1)
 248 #define PLLEN                           BIT(0)
 249 #define PXL_PLLPARAM            0x0914
 250 #define IN_SEL_REFCLK                   (0 << 14)
 251 #define SYS_PLLPARAM            0x0918
 252 #define REF_FREQ_38M4                   (0 << 8) /* 38.4 MHz */
 253 #define REF_FREQ_19M2                   (1 << 8) /* 19.2 MHz */
 254 #define REF_FREQ_26M                    (2 << 8) /* 26 MHz */
 255 #define REF_FREQ_13M                    (3 << 8) /* 13 MHz */
 256 #define SYSCLK_SEL_LSCLK                (0 << 4)
 257 #define LSCLK_DIV_1                     (0 << 0)
 258 #define LSCLK_DIV_2                     (1 << 0)
 259
 260 /* Test & Debug */
 261 #define TSTCTL                  0x0a00
 262 #define COLOR_R                 GENMASK(31, 24)
 263 #define COLOR_G                 GENMASK(23, 16)
 264 #define COLOR_B                 GENMASK(15, 8)
 265 #define ENI2CFILTER             BIT(4)
 266 #define COLOR_BAR_MODE          GENMASK(1, 0)
 267 #define COLOR_BAR_MODE_BARS     2
 268 #define PLL_DBG                 0x0a04
 269
 270 static bool tc_test_pattern;
 271 module_param_named(test, tc_test_pattern, bool, 0644);
 272
 273 struct tc_edp_link {
 274         u8                      dpcd[DP_RECEIVER_CAP_SIZE];
 275         unsigned int            rate;
 276         u8                      num_lanes;
 277         u8                      assr;
 278         bool                    scrambler_dis;
 279         bool                    spread;
 280 };
 281
 282 struct tc_data {
 283         struct device           *dev;
 284         struct regmap           *regmap;
 285         struct drm_dp_aux       aux;
 286
 287         struct drm_bridge       bridge;
 288         struct drm_bridge       *panel_bridge;
 289         struct drm_connector    connector;
 290
 291         struct mipi_dsi_device  *dsi;
 292
 293         /* link settings */
 294         struct tc_edp_link      link;
 295
 296         /* current mode */
 297         struct drm_display_mode mode;
 298
 299         u32                     rev;
 300         u8                      assr;
 301
 302         struct gpio_desc        *sd_gpio;
 303         struct gpio_desc        *reset_gpio;
 304         struct clk              *refclk;
 305
 306         /* do we have IRQ */
 307         bool                    have_irq;
 308
 309         /* Input connector type, DSI and not DPI. */
 310         bool                    input_connector_dsi;
 311
 312         /* HPD pin number (0 or 1) or -ENODEV */
 313         int                     hpd_pin;
 314 };
 315
 316 static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
 317 {
 318         return container_of(a, struct tc_data, aux);
 319 }
 320
 321 static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
 322 {
 323         return container_of(b, struct tc_data, bridge);
 324 }
 325
 326 static inline struct tc_data *connector_to_tc(struct drm_connector *c)
 327 {
 328         return container_of(c, struct tc_data, connector);
 329 }
 330
 331 static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr,
 332                                   unsigned int cond_mask,
 333                                   unsigned int cond_value,
 334                                   unsigned long sleep_us, u64 timeout_us)
 335 {
 336         unsigned int val;
 337
 338         return regmap_read_poll_timeout(tc->regmap, addr, val,
 339                                         (val & cond_mask) == cond_value,
 340                                         sleep_us, timeout_us);
 341 }
 342
 343 static int tc_aux_wait_busy(struct tc_data *tc)
 344 {
 345         return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 100, 100000);
 346 }
 347
 348 static int tc_aux_write_data(struct tc_data *tc, const void *data,
 349                              size_t size)
 350 {
 351         u32 auxwdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)] = { 0 };
 352         int ret, count = ALIGN(size, sizeof(u32));
 353
 354         memcpy(auxwdata, data, size);
 355
 356         ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count);
 357         if (ret)
 358                 return ret;
 359
 360         return size;
 361 }
 362
 363 static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size)
 364 {
 365         u32 auxrdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)];
 366         int ret, count = ALIGN(size, sizeof(u32));
 367
 368         ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count);
 369         if (ret)
 370                 return ret;
 371
 372         memcpy(data, auxrdata, size);
 373
 374         return size;
 375 }
 376
 377 static u32 tc_auxcfg0(struct drm_dp_aux_msg *msg, size_t size)
 378 {
 379         u32 auxcfg0 = msg->request;
 380
 381         if (size)
 382                 auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1);
 383         else
 384                 auxcfg0 |= DP0_AUXCFG0_ADDR_ONLY;
 385
 386         return auxcfg0;
 387 }
 388
 389 static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
 390                                struct drm_dp_aux_msg *msg)
 391 {
 392         struct tc_data *tc = aux_to_tc(aux);
 393         size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size);
 394         u8 request = msg->request & ~DP_AUX_I2C_MOT;
 395         u32 auxstatus;
 396         int ret;
 397
 398         ret = tc_aux_wait_busy(tc);
 399         if (ret)
 400                 return ret;
 401
 402         switch (request) {
 403         case DP_AUX_NATIVE_READ:
 404         case DP_AUX_I2C_READ:
 405                 break;
 406         case DP_AUX_NATIVE_WRITE:
 407         case DP_AUX_I2C_WRITE:
 408                 if (size) {
 409                         ret = tc_aux_write_data(tc, msg->buffer, size);
 410                         if (ret < 0)
 411                                 return ret;
 412                 }
 413                 break;
 414         default:
 415                 return -EINVAL;
 416         }
 417
 418         /* Store address */
 419         ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address);
 420         if (ret)
 421                 return ret;
 422         /* Start transfer */
 423         ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size));
 424         if (ret)
 425                 return ret;
 426
 427         ret = tc_aux_wait_busy(tc);
 428         if (ret)
 429                 return ret;
 430
 431         ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus);
 432         if (ret)
 433                 return ret;
 434
 435         if (auxstatus & AUX_TIMEOUT)
 436                 return -ETIMEDOUT;
 437         /*
 438          * For some reason address-only DP_AUX_I2C_WRITE (MOT), still
 439          * reports 1 byte transferred in its status. To deal we that
 440          * we ignore aux_bytes field if we know that this was an
 441          * address-only transfer
 442          */
 443         if (size)
 444                 size = FIELD_GET(AUX_BYTES, auxstatus);
 445         msg->reply = FIELD_GET(AUX_STATUS, auxstatus);
 446
 447         switch (request) {
 448         case DP_AUX_NATIVE_READ:
 449         case DP_AUX_I2C_READ:
 450                 if (size)
 451                         return tc_aux_read_data(tc, msg->buffer, size);
 452                 break;
 453         }
 454
 455         return size;
 456 }
 457
 458 static const char * const training_pattern1_errors[] = {
 459         "No errors",
 460         "Aux write error",
 461         "Aux read error",
 462         "Max voltage reached error",
 463         "Loop counter expired error",
 464         "res", "res", "res"
 465 };
 466
 467 static const char * const training_pattern2_errors[] = {
 468         "No errors",
 469         "Aux write error",
 470         "Aux read error",
 471         "Clock recovery failed error",
 472         "Loop counter expired error",
 473         "res", "res", "res"
 474 };
 475
 476 static u32 tc_srcctrl(struct tc_data *tc)
 477 {
 478         /*
 479          * No training pattern, skew lane 1 data by two LSCLK cycles with
 480          * respect to lane 0 data, AutoCorrect Mode = 0
 481          */
 482         u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_EN810B;
 483
 484         if (tc->link.scrambler_dis)
 485                 reg |= DP0_SRCCTRL_SCRMBLDIS;   /* Scrambler Disabled */
 486         if (tc->link.spread)
 487                 reg |= DP0_SRCCTRL_SSCG;        /* Spread Spectrum Enable */
 488         if (tc->link.num_lanes == 2)
 489                 reg |= DP0_SRCCTRL_LANES_2;     /* Two Main Channel Lanes */
 490         if (tc->link.rate != 162000)
 491                 reg |= DP0_SRCCTRL_BW27;        /* 2.7 Gbps link */
 492         return reg;
 493 }
 494
 495 static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl)
 496 {
 497         int ret;
 498
 499         ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN);
 500         if (ret)
 501                 return ret;
 502
 503         /* Wait for PLL to lock: up to 7.5 ms, depending on refclk */
 504         usleep_range(15000, 20000);
 505
 506         return 0;
 507 }
 508
 509 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
 510 {
 511         int ret;
 512         int i_pre, best_pre = 1;
 513         int i_post, best_post = 1;
 514         int div, best_div = 1;
 515         int mul, best_mul = 1;
 516         int delta, best_delta;
 517         int ext_div[] = {1, 2, 3, 5, 7};
 518         int clk_min, clk_max;
 519         int best_pixelclock = 0;
 520         int vco_hi = 0;
 521         u32 pxl_pllparam;
 522
 523         /*
 524          * refclk * mul / (ext_pre_div * pre_div) should be in range:
 525          * - DPI ..... 0 to 100 MHz
 526          * - (e)DP ... 150 to 650 MHz
 527          */
 528         if (tc->bridge.type == DRM_MODE_CONNECTOR_DPI) {
 529                 clk_min = 0;
 530                 clk_max = 100000000;
 531         } else {
 532                 clk_min = 150000000;
 533                 clk_max = 650000000;
 534         }
 535
 536         dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
 537                 refclk);
 538         best_delta = pixelclock;
 539         /* Loop over all possible ext_divs, skipping invalid configurations */
 540         for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) {
 541                 /*
 542                  * refclk / ext_pre_div should be in the 1 to 200 MHz range.
 543                  * We don't allow any refclk > 200 MHz, only check lower bounds.
 544                  */
 545                 if (refclk / ext_div[i_pre] < 1000000)
 546                         continue;
 547                 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
 548                         for (div = 1; div <= 16; div++) {
 549                                 u32 clk;
 550                                 u64 tmp;
 551
 552                                 tmp = pixelclock * ext_div[i_pre] *
 553                                       ext_div[i_post] * div;
 554                                 do_div(tmp, refclk);
 555                                 mul = tmp;
 556
 557                                 /* Check limits */
 558                                 if ((mul < 1) || (mul > 128))
 559                                         continue;
 560
 561                                 clk = (refclk / ext_div[i_pre] / div) * mul;
 562                                 if ((clk > clk_max) || (clk < clk_min))
 563                                         continue;
 564
 565                                 clk = clk / ext_div[i_post];
 566                                 delta = clk - pixelclock;
 567
 568                                 if (abs(delta) < abs(best_delta)) {
 569                                         best_pre = i_pre;
 570                                         best_post = i_post;
 571                                         best_div = div;
 572                                         best_mul = mul;
 573                                         best_delta = delta;
 574                                         best_pixelclock = clk;
 575                                 }
 576                         }
 577                 }
 578         }
 579         if (best_pixelclock == 0) {
 580                 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
 581                         pixelclock);
 582                 return -EINVAL;
 583         }
 584
 585         dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock,
 586                 best_delta);
 587         dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
 588                 ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
 589
 590         /* if VCO >= 300 MHz */
 591         if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
 592                 vco_hi = 1;
 593         /* see DS */
 594         if (best_div == 16)
 595                 best_div = 0;
 596         if (best_mul == 128)
 597                 best_mul = 0;
 598
 599         /* Power up PLL and switch to bypass */
 600         ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
 601         if (ret)
 602                 return ret;
 603
 604         pxl_pllparam  = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */
 605         pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */
 606         pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */
 607         pxl_pllparam |= IN_SEL_REFCLK; /* Use RefClk as PLL input */
 608         pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */
 609         pxl_pllparam |= best_mul; /* Multiplier for PLL */
 610
 611         ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam);
 612         if (ret)
 613                 return ret;
 614
 615         /* Force PLL parameter update and disable bypass */
 616         return tc_pllupdate(tc, PXL_PLLCTRL);
 617 }
 618
 619 static int tc_pxl_pll_dis(struct tc_data *tc)
 620 {
 621         /* Enable PLL bypass, power down PLL */
 622         return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
 623 }
 624
 625 static int tc_stream_clock_calc(struct tc_data *tc)
 626 {
 627         /*
 628          * If the Stream clock and Link Symbol clock are
 629          * asynchronous with each other, the value of M changes over
 630          * time. This way of generating link clock and stream
 631          * clock is called Asynchronous Clock mode. The value M
 632          * must change while the value N stays constant. The
 633          * value of N in this Asynchronous Clock mode must be set
 634          * to 2^15 or 32,768.
 635          *
 636          * LSCLK = 1/10 of high speed link clock
 637          *
 638          * f_STRMCLK = M/N * f_LSCLK
 639          * M/N = f_STRMCLK / f_LSCLK
 640          *
 641          */
 642         return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768);
 643 }
 644
 645 static int tc_set_syspllparam(struct tc_data *tc)
 646 {
 647         unsigned long rate;
 648         u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
 649
 650         rate = clk_get_rate(tc->refclk);
 651         switch (rate) {
 652         case 38400000:
 653                 pllparam |= REF_FREQ_38M4;
 654                 break;
 655         case 26000000:
 656                 pllparam |= REF_FREQ_26M;
 657                 break;
 658         case 19200000:
 659                 pllparam |= REF_FREQ_19M2;
 660                 break;
 661         case 13000000:
 662                 pllparam |= REF_FREQ_13M;
 663                 break;
 664         default:
 665                 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
 666                 return -EINVAL;
 667         }
 668
 669         return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam);
 670 }
 671
 672 static int tc_aux_link_setup(struct tc_data *tc)
 673 {
 674         int ret;
 675         u32 dp0_auxcfg1;
 676
 677         /* Setup DP-PHY / PLL */
 678         ret = tc_set_syspllparam(tc);
 679         if (ret)
 680                 goto err;
 681
 682         ret = regmap_write(tc->regmap, DP_PHY_CTRL,
 683                            BGREN | PWR_SW_EN | PHY_A0_EN);
 684         if (ret)
 685                 goto err;
 686         /*
 687          * Initially PLLs are in bypass. Force PLL parameter update,
 688          * disable PLL bypass, enable PLL
 689          */
 690         ret = tc_pllupdate(tc, DP0_PLLCTRL);
 691         if (ret)
 692                 goto err;
 693
 694         ret = tc_pllupdate(tc, DP1_PLLCTRL);
 695         if (ret)
 696                 goto err;
 697
 698         ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 100, 100000);
 699         if (ret == -ETIMEDOUT) {
 700                 dev_err(tc->dev, "Timeout waiting for PHY to become ready");
 701                 return ret;
 702         } else if (ret) {
 703                 goto err;
 704         }
 705
 706         /* Setup AUX link */
 707         dp0_auxcfg1  = AUX_RX_FILTER_EN;
 708         dp0_auxcfg1 |= 0x06 << 8; /* Aux Bit Period Calculator Threshold */
 709         dp0_auxcfg1 |= 0x3f << 0; /* Aux Response Timeout Timer */
 710
 711         ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1);
 712         if (ret)
 713                 goto err;
 714
 715         /* Register DP AUX channel */
 716         tc->aux.name = "TC358767 AUX i2c adapter";
 717         tc->aux.dev = tc->dev;
 718         tc->aux.transfer = tc_aux_transfer;
 719         drm_dp_aux_init(&tc->aux);
 720
 721         return 0;
 722 err:
 723         dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
 724         return ret;
 725 }
 726
 727 static int tc_get_display_props(struct tc_data *tc)
 728 {
 729         u8 revision, num_lanes;
 730         unsigned int rate;
 731         int ret;
 732         u8 reg;
 733
 734         /* Read DP Rx Link Capability */
 735         ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd,
 736                                DP_RECEIVER_CAP_SIZE);
 737         if (ret < 0)
 738                 goto err_dpcd_read;
 739
 740         revision = tc->link.dpcd[DP_DPCD_REV];
 741         rate = drm_dp_max_link_rate(tc->link.dpcd);
 742         num_lanes = drm_dp_max_lane_count(tc->link.dpcd);
 743
 744         if (rate != 162000 && rate != 270000) {
 745                 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
 746                 rate = 270000;
 747         }
 748
 749         tc->link.rate = rate;
 750
 751         if (num_lanes > 2) {
 752                 dev_dbg(tc->dev, "Falling to 2 lanes\n");
 753                 num_lanes = 2;
 754         }
 755
 756         tc->link.num_lanes = num_lanes;
 757
 758         ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, &reg);
 759         if (ret < 0)
 760                 goto err_dpcd_read;
 761         tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5;
 762
 763         ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, &reg);
 764         if (ret < 0)
 765                 goto err_dpcd_read;
 766
 767         tc->link.scrambler_dis = false;
 768         /* read assr */
 769         ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, &reg);
 770         if (ret < 0)
 771                 goto err_dpcd_read;
 772         tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
 773
 774         dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
 775                 revision >> 4, revision & 0x0f,
 776                 (tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
 777                 tc->link.num_lanes,
 778                 drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
 779                 "enhanced" : "default");
 780         dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n",
 781                 tc->link.spread ? "0.5%" : "0.0%",
 782                 tc->link.scrambler_dis ? "disabled" : "enabled");
 783         dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
 784                 tc->link.assr, tc->assr);
 785
 786         return 0;
 787
 788 err_dpcd_read:
 789         dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
 790         return ret;
 791 }
 792
 793 static int tc_set_common_video_mode(struct tc_data *tc,
 794                                     const struct drm_display_mode *mode)
 795 {
 796         int left_margin = mode->htotal - mode->hsync_end;
 797         int right_margin = mode->hsync_start - mode->hdisplay;
 798         int hsync_len = mode->hsync_end - mode->hsync_start;
 799         int upper_margin = mode->vtotal - mode->vsync_end;
 800         int lower_margin = mode->vsync_start - mode->vdisplay;
 801         int vsync_len = mode->vsync_end - mode->vsync_start;
 802         int ret;
 803
 804         dev_dbg(tc->dev, "set mode %dx%d\n",
 805                 mode->hdisplay, mode->vdisplay);
 806         dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
 807                 left_margin, right_margin, hsync_len);
 808         dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
 809                 upper_margin, lower_margin, vsync_len);
 810         dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
 811
 812
 813         /*
 814          * LCD Ctl Frame Size
 815          * datasheet is not clear of vsdelay in case of DPI
 816          * assume we do not need any delay when DPI is a source of
 817          * sync signals
 818          */
 819         ret = regmap_write(tc->regmap, VPCTRL0,
 820                            FIELD_PREP(VSDELAY, right_margin + 10) |
 821                            OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
 822         if (ret)
 823                 return ret;
 824
 825         ret = regmap_write(tc->regmap, HTIM01,
 826                            FIELD_PREP(HBPR, ALIGN(left_margin, 2)) |
 827                            FIELD_PREP(HPW, ALIGN(hsync_len, 2)));
 828         if (ret)
 829                 return ret;
 830
 831         ret = regmap_write(tc->regmap, HTIM02,
 832                            FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) |
 833                            FIELD_PREP(HFPR, ALIGN(right_margin, 2)));
 834         if (ret)
 835                 return ret;
 836
 837         ret = regmap_write(tc->regmap, VTIM01,
 838                            FIELD_PREP(VBPR, upper_margin) |
 839                            FIELD_PREP(VSPR, vsync_len));
 840         if (ret)
 841                 return ret;
 842
 843         ret = regmap_write(tc->regmap, VTIM02,
 844                            FIELD_PREP(VFPR, lower_margin) |
 845                            FIELD_PREP(VDISPR, mode->vdisplay));
 846         if (ret)
 847                 return ret;
 848
 849         ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */
 850         if (ret)
 851                 return ret;
 852
 853         /* Test pattern settings */
 854         ret = regmap_write(tc->regmap, TSTCTL,
 855                            FIELD_PREP(COLOR_R, 120) |
 856                            FIELD_PREP(COLOR_G, 20) |
 857                            FIELD_PREP(COLOR_B, 99) |
 858                            ENI2CFILTER |
 859                            FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS));
 860
 861         return ret;
 862 }
 863
 864 static int tc_set_dpi_video_mode(struct tc_data *tc,
 865                                  const struct drm_display_mode *mode)
 866 {
 867         u32 value = POCTRL_S2P;
 868
 869         if (tc->mode.flags & DRM_MODE_FLAG_NHSYNC)
 870                 value |= POCTRL_HS_POL;
 871
 872         if (tc->mode.flags & DRM_MODE_FLAG_NVSYNC)
 873                 value |= POCTRL_VS_POL;
 874
 875         return regmap_write(tc->regmap, POCTRL, value);
 876 }
 877
 878 static int tc_set_edp_video_mode(struct tc_data *tc,
 879                                  const struct drm_display_mode *mode)
 880 {
 881         int ret;
 882         int vid_sync_dly;
 883         int max_tu_symbol;
 884
 885         int left_margin = mode->htotal - mode->hsync_end;
 886         int hsync_len = mode->hsync_end - mode->hsync_start;
 887         int upper_margin = mode->vtotal - mode->vsync_end;
 888         int vsync_len = mode->vsync_end - mode->vsync_start;
 889         u32 dp0_syncval;
 890         u32 bits_per_pixel = 24;
 891         u32 in_bw, out_bw;
 892         u32 dpipxlfmt;
 893
 894         /*
 895          * Recommended maximum number of symbols transferred in a transfer unit:
 896          * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
 897          *              (output active video bandwidth in bytes))
 898          * Must be less than tu_size.
 899          */
 900
 901         in_bw = mode->clock * bits_per_pixel / 8;
 902         out_bw = tc->link.num_lanes * tc->link.rate;
 903         max_tu_symbol = DIV_ROUND_UP(in_bw * TU_SIZE_RECOMMENDED, out_bw);
 904
 905         /* DP Main Stream Attributes */
 906         vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
 907         ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY,
 908                  FIELD_PREP(THRESH_DLY, max_tu_symbol) |
 909                  FIELD_PREP(VID_SYNC_DLY, vid_sync_dly));
 910
 911         ret = regmap_write(tc->regmap, DP0_TOTALVAL,
 912                            FIELD_PREP(H_TOTAL, mode->htotal) |
 913                            FIELD_PREP(V_TOTAL, mode->vtotal));
 914         if (ret)
 915                 return ret;
 916
 917         ret = regmap_write(tc->regmap, DP0_STARTVAL,
 918                            FIELD_PREP(H_START, left_margin + hsync_len) |
 919                            FIELD_PREP(V_START, upper_margin + vsync_len));
 920         if (ret)
 921                 return ret;
 922
 923         ret = regmap_write(tc->regmap, DP0_ACTIVEVAL,
 924                            FIELD_PREP(V_ACT, mode->vdisplay) |
 925                            FIELD_PREP(H_ACT, mode->hdisplay));
 926         if (ret)
 927                 return ret;
 928
 929         dp0_syncval = FIELD_PREP(VS_WIDTH, vsync_len) |
 930                       FIELD_PREP(HS_WIDTH, hsync_len);
 931
 932         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 933                 dp0_syncval |= SYNCVAL_VS_POL_ACTIVE_LOW;
 934
 935         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 936                 dp0_syncval |= SYNCVAL_HS_POL_ACTIVE_LOW;
 937
 938         ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval);
 939         if (ret)
 940                 return ret;
 941
 942         dpipxlfmt = DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888;
 943
 944         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 945                 dpipxlfmt |= VS_POL_ACTIVE_LOW;
 946
 947         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 948                 dpipxlfmt |= HS_POL_ACTIVE_LOW;
 949
 950         ret = regmap_write(tc->regmap, DPIPXLFMT, dpipxlfmt);
 951         if (ret)
 952                 return ret;
 953
 954         ret = regmap_write(tc->regmap, DP0_MISC,
 955                            FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) |
 956                            FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) |
 957                            BPC_8);
 958         return ret;
 959 }
 960
 961 static int tc_wait_link_training(struct tc_data *tc)
 962 {
 963         u32 value;
 964         int ret;
 965
 966         ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE,
 967                               LT_LOOPDONE, 500, 100000);
 968         if (ret) {
 969                 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n");
 970                 return ret;
 971         }
 972
 973         ret = regmap_read(tc->regmap, DP0_LTSTAT, &value);
 974         if (ret)
 975                 return ret;
 976
 977         return (value >> 8) & 0x7;
 978 }
 979
 980 static int tc_main_link_enable(struct tc_data *tc)
 981 {
 982         struct drm_dp_aux *aux = &tc->aux;
 983         struct device *dev = tc->dev;
 984         u32 dp_phy_ctrl;
 985         u32 value;
 986         int ret;
 987         u8 tmp[DP_LINK_STATUS_SIZE];
 988
 989         dev_dbg(tc->dev, "link enable\n");
 990
 991         ret = regmap_read(tc->regmap, DP0CTL, &value);
 992         if (ret)
 993                 return ret;
 994
 995         if (WARN_ON(value & DP_EN)) {
 996                 ret = regmap_write(tc->regmap, DP0CTL, 0);
 997                 if (ret)
 998                         return ret;
 999         }
1000
1001         ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc));
1002         if (ret)
1003                 return ret;
1004         /* SSCG and BW27 on DP1 must be set to the same as on DP0 */
1005         ret = regmap_write(tc->regmap, DP1_SRCCTRL,
1006                  (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
1007                  ((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
1008         if (ret)
1009                 return ret;
1010
1011         ret = tc_set_syspllparam(tc);
1012         if (ret)
1013                 return ret;
1014
1015         /* Setup Main Link */
1016         dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
1017         if (tc->link.num_lanes == 2)
1018                 dp_phy_ctrl |= PHY_2LANE;
1019
1020         ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
1021         if (ret)
1022                 return ret;
1023
1024         /* PLL setup */
1025         ret = tc_pllupdate(tc, DP0_PLLCTRL);
1026         if (ret)
1027                 return ret;
1028
1029         ret = tc_pllupdate(tc, DP1_PLLCTRL);
1030         if (ret)
1031                 return ret;
1032
1033         /* Reset/Enable Main Links */
1034         dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
1035         ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
1036         usleep_range(100, 200);
1037         dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
1038         ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
1039
1040         ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 500, 100000);
1041         if (ret) {
1042                 dev_err(dev, "timeout waiting for phy become ready");
1043                 return ret;
1044         }
1045
1046         /* Set misc: 8 bits per color */
1047         ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
1048         if (ret)
1049                 return ret;
1050
1051         /*
1052          * ASSR mode
1053          * on TC358767 side ASSR configured through strap pin
1054          * seems there is no way to change this setting from SW
1055          *
1056          * check is tc configured for same mode
1057          */
1058         if (tc->assr != tc->link.assr) {
1059                 dev_dbg(dev, "Trying to set display to ASSR: %d\n",
1060                         tc->assr);
1061                 /* try to set ASSR on display side */
1062                 tmp[0] = tc->assr;
1063                 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);
1064                 if (ret < 0)
1065                         goto err_dpcd_read;
1066                 /* read back */
1067                 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
1068                 if (ret < 0)
1069                         goto err_dpcd_read;
1070
1071                 if (tmp[0] != tc->assr) {
1072                         dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
1073                                 tc->assr);
1074                         /* trying with disabled scrambler */
1075                         tc->link.scrambler_dis = true;
1076                 }
1077         }
1078
1079         /* Setup Link & DPRx Config for Training */
1080         tmp[0] = drm_dp_link_rate_to_bw_code(tc->link.rate);
1081         tmp[1] = tc->link.num_lanes;
1082
1083         if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
1084                 tmp[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
1085
1086         ret = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, tmp, 2);
1087         if (ret < 0)
1088                 goto err_dpcd_write;
1089
1090         /* DOWNSPREAD_CTRL */
1091         tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
1092         /* MAIN_LINK_CHANNEL_CODING_SET */
1093         tmp[1] =  DP_SET_ANSI_8B10B;
1094         ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
1095         if (ret < 0)
1096                 goto err_dpcd_write;
1097
1098         /* Reset voltage-swing & pre-emphasis */
1099         tmp[0] = tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 |
1100                           DP_TRAIN_PRE_EMPH_LEVEL_0;
1101         ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2);
1102         if (ret < 0)
1103                 goto err_dpcd_write;
1104
1105         /* Clock-Recovery */
1106
1107         /* Set DPCD 0x102 for Training Pattern 1 */
1108         ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1109                            DP_LINK_SCRAMBLING_DISABLE |
1110                            DP_TRAINING_PATTERN_1);
1111         if (ret)
1112                 return ret;
1113
1114         ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL,
1115                            (15 << 28) | /* Defer Iteration Count */
1116                            (15 << 24) | /* Loop Iteration Count */
1117                            (0xd << 0)); /* Loop Timer Delay */
1118         if (ret)
1119                 return ret;
1120
1121         ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1122                            tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1123                            DP0_SRCCTRL_AUTOCORRECT |
1124                            DP0_SRCCTRL_TP1);
1125         if (ret)
1126                 return ret;
1127
1128         /* Enable DP0 to start Link Training */
1129         ret = regmap_write(tc->regmap, DP0CTL,
1130                            (drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
1131                                 EF_EN : 0) | DP_EN);
1132         if (ret)
1133                 return ret;
1134
1135         /* wait */
1136
1137         ret = tc_wait_link_training(tc);
1138         if (ret < 0)
1139                 return ret;
1140
1141         if (ret) {
1142                 dev_err(tc->dev, "Link training phase 1 failed: %s\n",
1143                         training_pattern1_errors[ret]);
1144                 return -ENODEV;
1145         }
1146
1147         /* Channel Equalization */
1148
1149         /* Set DPCD 0x102 for Training Pattern 2 */
1150         ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1151                            DP_LINK_SCRAMBLING_DISABLE |
1152                            DP_TRAINING_PATTERN_2);
1153         if (ret)
1154                 return ret;
1155
1156         ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1157                            tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1158                            DP0_SRCCTRL_AUTOCORRECT |
1159                            DP0_SRCCTRL_TP2);
1160         if (ret)
1161                 return ret;
1162
1163         /* wait */
1164         ret = tc_wait_link_training(tc);
1165         if (ret < 0)
1166                 return ret;
1167
1168         if (ret) {
1169                 dev_err(tc->dev, "Link training phase 2 failed: %s\n",
1170                         training_pattern2_errors[ret]);
1171                 return -ENODEV;
1172         }
1173
1174         /*
1175          * Toshiba's documentation suggests to first clear DPCD 0x102, then
1176          * clear the training pattern bit in DP0_SRCCTRL. Testing shows
1177          * that the link sometimes drops if those steps are done in that order,
1178          * but if the steps are done in reverse order, the link stays up.
1179          *
1180          * So we do the steps differently than documented here.
1181          */
1182
1183         /* Clear Training Pattern, set AutoCorrect Mode = 1 */
1184         ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) |
1185                            DP0_SRCCTRL_AUTOCORRECT);
1186         if (ret)
1187                 return ret;
1188
1189         /* Clear DPCD 0x102 */
1190         /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
1191         tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
1192         ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]);
1193         if (ret < 0)
1194                 goto err_dpcd_write;
1195
1196         /* Check link status */
1197         ret = drm_dp_dpcd_read_link_status(aux, tmp);
1198         if (ret < 0)
1199                 goto err_dpcd_read;
1200
1201         ret = 0;
1202
1203         value = tmp[0] & DP_CHANNEL_EQ_BITS;
1204
1205         if (value != DP_CHANNEL_EQ_BITS) {
1206                 dev_err(tc->dev, "Lane 0 failed: %x\n", value);
1207                 ret = -ENODEV;
1208         }
1209
1210         if (tc->link.num_lanes == 2) {
1211                 value = (tmp[0] >> 4) & DP_CHANNEL_EQ_BITS;
1212
1213                 if (value != DP_CHANNEL_EQ_BITS) {
1214                         dev_err(tc->dev, "Lane 1 failed: %x\n", value);
1215                         ret = -ENODEV;
1216                 }
1217
1218                 if (!(tmp[2] & DP_INTERLANE_ALIGN_DONE)) {
1219                         dev_err(tc->dev, "Interlane align failed\n");
1220                         ret = -ENODEV;
1221                 }
1222         }
1223
1224         if (ret) {
1225                 dev_err(dev, "0x0202 LANE0_1_STATUS:            0x%02x\n", tmp[0]);
1226                 dev_err(dev, "0x0203 LANE2_3_STATUS             0x%02x\n", tmp[1]);
1227                 dev_err(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", tmp[2]);
1228                 dev_err(dev, "0x0205 SINK_STATUS:               0x%02x\n", tmp[3]);
1229                 dev_err(dev, "0x0206 ADJUST_REQUEST_LANE0_1:    0x%02x\n", tmp[4]);
1230                 dev_err(dev, "0x0207 ADJUST_REQUEST_LANE2_3:    0x%02x\n", tmp[5]);
1231                 return ret;
1232         }
1233
1234         return 0;
1235 err_dpcd_read:
1236         dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1237         return ret;
1238 err_dpcd_write:
1239         dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1240         return ret;
1241 }
1242
1243 static int tc_main_link_disable(struct tc_data *tc)
1244 {
1245         int ret;
1246
1247         dev_dbg(tc->dev, "link disable\n");
1248
1249         ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0);
1250         if (ret)
1251                 return ret;
1252
1253         ret = regmap_write(tc->regmap, DP0CTL, 0);
1254         if (ret)
1255                 return ret;
1256
1257         return regmap_update_bits(tc->regmap, DP_PHY_CTRL,
1258                                   PHY_M0_RST | PHY_M1_RST | PHY_M0_EN,
1259                                   PHY_M0_RST | PHY_M1_RST);
1260 }
1261
1262 static int tc_dsi_rx_enable(struct tc_data *tc)
1263 {
1264         u32 value;
1265         int ret;
1266
1267         regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 25);
1268         regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 25);
1269         regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 25);
1270         regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 25);
1271         regmap_write(tc->regmap, PPI_D0S_ATMR, 0);
1272         regmap_write(tc->regmap, PPI_D1S_ATMR, 0);
1273         regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
1274         regmap_write(tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD);
1275
1276         value = ((LANEENABLE_L0EN << tc->dsi->lanes) - LANEENABLE_L0EN) |
1277                 LANEENABLE_CLEN;
1278         regmap_write(tc->regmap, PPI_LANEENABLE, value);
1279         regmap_write(tc->regmap, DSI_LANEENABLE, value);
1280
1281         /* Set input interface */
1282         value = DP0_AUDSRC_NO_INPUT;
1283         if (tc_test_pattern)
1284                 value |= DP0_VIDSRC_COLOR_BAR;
1285         else
1286                 value |= DP0_VIDSRC_DSI_RX;
1287         ret = regmap_write(tc->regmap, SYSCTRL, value);
1288         if (ret)
1289                 return ret;
1290
1291         usleep_range(120, 150);
1292
1293         regmap_write(tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION);
1294         regmap_write(tc->regmap, DSI_STARTDSI, DSI_RX_START);
1295
1296         return 0;
1297 }
1298
1299 static int tc_dpi_rx_enable(struct tc_data *tc)
1300 {
1301         u32 value;
1302
1303         /* Set input interface */
1304         value = DP0_AUDSRC_NO_INPUT;
1305         if (tc_test_pattern)
1306                 value |= DP0_VIDSRC_COLOR_BAR;
1307         else
1308                 value |= DP0_VIDSRC_DPI_RX;
1309         return regmap_write(tc->regmap, SYSCTRL, value);
1310 }
1311
1312 static int tc_dpi_stream_enable(struct tc_data *tc)
1313 {
1314         int ret;
1315
1316         dev_dbg(tc->dev, "enable video stream\n");
1317
1318         /* Setup PLL */
1319         ret = tc_set_syspllparam(tc);
1320         if (ret)
1321                 return ret;
1322
1323         /*
1324          * Initially PLLs are in bypass. Force PLL parameter update,
1325          * disable PLL bypass, enable PLL
1326          */
1327         ret = tc_pllupdate(tc, DP0_PLLCTRL);
1328         if (ret)
1329                 return ret;
1330
1331         ret = tc_pllupdate(tc, DP1_PLLCTRL);
1332         if (ret)
1333                 return ret;
1334
1335         /* Pixel PLL must always be enabled for DPI mode */
1336         ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
1337                             1000 * tc->mode.clock);
1338         if (ret)
1339                 return ret;
1340
1341         ret = tc_set_common_video_mode(tc, &tc->mode);
1342         if (ret)
1343                 return ret;
1344
1345         ret = tc_set_dpi_video_mode(tc, &tc->mode);
1346         if (ret)
1347                 return ret;
1348
1349         return tc_dsi_rx_enable(tc);
1350 }
1351
1352 static int tc_dpi_stream_disable(struct tc_data *tc)
1353 {
1354         dev_dbg(tc->dev, "disable video stream\n");
1355
1356         tc_pxl_pll_dis(tc);
1357
1358         return 0;
1359 }
1360
1361 static int tc_edp_stream_enable(struct tc_data *tc)
1362 {
1363         int ret;
1364         u32 value;
1365
1366         dev_dbg(tc->dev, "enable video stream\n");
1367
1368         /*
1369          * Pixel PLL must be enabled for DSI input mode and test pattern.
1370          *
1371          * Per TC9595XBG datasheet Revision 0.1 2018-12-27 Figure 4.18
1372          * "Clock Mode Selection and Clock Sources", either Pixel PLL
1373          * or DPI_PCLK supplies StrmClk. DPI_PCLK is only available in
1374          * case valid Pixel Clock are supplied to the chip DPI input.
1375          * In case built-in test pattern is desired OR DSI input mode
1376          * is used, DPI_PCLK is not available and thus Pixel PLL must
1377          * be used instead.
1378          */
1379         if (tc->input_connector_dsi || tc_test_pattern) {
1380                 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
1381                                     1000 * tc->mode.clock);
1382                 if (ret)
1383                         return ret;
1384         }
1385
1386         ret = tc_set_common_video_mode(tc, &tc->mode);
1387         if (ret)
1388                 return ret;
1389
1390         ret = tc_set_edp_video_mode(tc, &tc->mode);
1391         if (ret)
1392                 return ret;
1393
1394         /* Set M/N */
1395         ret = tc_stream_clock_calc(tc);
1396         if (ret)
1397                 return ret;
1398
1399         value = VID_MN_GEN | DP_EN;
1400         if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
1401                 value |= EF_EN;
1402         ret = regmap_write(tc->regmap, DP0CTL, value);
1403         if (ret)
1404                 return ret;
1405         /*
1406          * VID_EN assertion should be delayed by at least N * LSCLK
1407          * cycles from the time VID_MN_GEN is enabled in order to
1408          * generate stable values for VID_M. LSCLK is 270 MHz or
1409          * 162 MHz, VID_N is set to 32768 in  tc_stream_clock_calc(),
1410          * so a delay of at least 203 us should suffice.
1411          */
1412         usleep_range(500, 1000);
1413         value |= VID_EN;
1414         ret = regmap_write(tc->regmap, DP0CTL, value);
1415         if (ret)
1416                 return ret;
1417
1418         /* Set input interface */
1419         if (tc->input_connector_dsi)
1420                 return tc_dsi_rx_enable(tc);
1421         else
1422                 return tc_dpi_rx_enable(tc);
1423 }
1424
1425 static int tc_edp_stream_disable(struct tc_data *tc)
1426 {
1427         int ret;
1428
1429         dev_dbg(tc->dev, "disable video stream\n");
1430
1431         ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0);
1432         if (ret)
1433                 return ret;
1434
1435         tc_pxl_pll_dis(tc);
1436
1437         return 0;
1438 }
1439
1440 static void
1441 tc_dpi_bridge_atomic_enable(struct drm_bridge *bridge,
1442                             struct drm_bridge_state *old_bridge_state)
1443
1444 {
1445         struct tc_data *tc = bridge_to_tc(bridge);
1446         int ret;
1447
1448         ret = tc_dpi_stream_enable(tc);
1449         if (ret < 0) {
1450                 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1451                 tc_main_link_disable(tc);
1452                 return;
1453         }
1454 }
1455
1456 static void
1457 tc_dpi_bridge_atomic_disable(struct drm_bridge *bridge,
1458                              struct drm_bridge_state *old_bridge_state)
1459 {
1460         struct tc_data *tc = bridge_to_tc(bridge);
1461         int ret;
1462
1463         ret = tc_dpi_stream_disable(tc);
1464         if (ret < 0)
1465                 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1466 }
1467
1468 static void
1469 tc_edp_bridge_atomic_enable(struct drm_bridge *bridge,
1470                             struct drm_bridge_state *old_bridge_state)
1471 {
1472         struct tc_data *tc = bridge_to_tc(bridge);
1473         int ret;
1474
1475         ret = tc_get_display_props(tc);
1476         if (ret < 0) {
1477                 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1478                 return;
1479         }
1480
1481         ret = tc_main_link_enable(tc);
1482         if (ret < 0) {
1483                 dev_err(tc->dev, "main link enable error: %d\n", ret);
1484                 return;
1485         }
1486
1487         ret = tc_edp_stream_enable(tc);
1488         if (ret < 0) {
1489                 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1490                 tc_main_link_disable(tc);
1491                 return;
1492         }
1493 }
1494
1495 static void
1496 tc_edp_bridge_atomic_disable(struct drm_bridge *bridge,
1497                              struct drm_bridge_state *old_bridge_state)
1498 {
1499         struct tc_data *tc = bridge_to_tc(bridge);
1500         int ret;
1501
1502         ret = tc_edp_stream_disable(tc);
1503         if (ret < 0)
1504                 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1505
1506         ret = tc_main_link_disable(tc);
1507         if (ret < 0)
1508                 dev_err(tc->dev, "main link disable error: %d\n", ret);
1509 }
1510
1511 static int tc_dpi_atomic_check(struct drm_bridge *bridge,
1512                                struct drm_bridge_state *bridge_state,
1513                                struct drm_crtc_state *crtc_state,
1514                                struct drm_connector_state *conn_state)
1515 {
1516         /* DSI->DPI interface clock limitation: upto 100 MHz */
1517         if (crtc_state->adjusted_mode.clock > 100000)
1518                 return -EINVAL;
1519
1520         return 0;
1521 }
1522
1523 static int tc_edp_atomic_check(struct drm_bridge *bridge,
1524                                struct drm_bridge_state *bridge_state,
1525                                struct drm_crtc_state *crtc_state,
1526                                struct drm_connector_state *conn_state)
1527 {
1528         /* DPI->(e)DP interface clock limitation: upto 154 MHz */
1529         if (crtc_state->adjusted_mode.clock > 154000)
1530                 return -EINVAL;
1531
1532         return 0;
1533 }
1534
1535 static enum drm_mode_status
1536 tc_dpi_mode_valid(struct drm_bridge *bridge,
1537                   const struct drm_display_info *info,
1538                   const struct drm_display_mode *mode)
1539 {
1540         /* DPI interface clock limitation: upto 100 MHz */
1541         if (mode->clock > 100000)
1542                 return MODE_CLOCK_HIGH;
1543
1544         return MODE_OK;
1545 }
1546
1547 static enum drm_mode_status
1548 tc_edp_mode_valid(struct drm_bridge *bridge,
1549                   const struct drm_display_info *info,
1550                   const struct drm_display_mode *mode)
1551 {
1552         struct tc_data *tc = bridge_to_tc(bridge);
1553         u32 req, avail;
1554         u32 bits_per_pixel = 24;
1555
1556         /* DPI interface clock limitation: upto 154 MHz */
1557         if (mode->clock > 154000)
1558                 return MODE_CLOCK_HIGH;
1559
1560         req = mode->clock * bits_per_pixel / 8;
1561         avail = tc->link.num_lanes * tc->link.rate;
1562
1563         if (req > avail)
1564                 return MODE_BAD;
1565
1566         return MODE_OK;
1567 }
1568
1569 static void tc_bridge_mode_set(struct drm_bridge *bridge,
1570                                const struct drm_display_mode *mode,
1571                                const struct drm_display_mode *adj)
1572 {
1573         struct tc_data *tc = bridge_to_tc(bridge);
1574
1575         drm_mode_copy(&tc->mode, mode);
1576 }
1577
1578 static struct edid *tc_get_edid(struct drm_bridge *bridge,
1579                                 struct drm_connector *connector)
1580 {
1581         struct tc_data *tc = bridge_to_tc(bridge);
1582
1583         return drm_get_edid(connector, &tc->aux.ddc);
1584 }
1585
1586 static int tc_connector_get_modes(struct drm_connector *connector)
1587 {
1588         struct tc_data *tc = connector_to_tc(connector);
1589         int num_modes;
1590         struct edid *edid;
1591         int ret;
1592
1593         ret = tc_get_display_props(tc);
1594         if (ret < 0) {
1595                 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1596                 return 0;
1597         }
1598
1599         if (tc->panel_bridge) {
1600                 num_modes = drm_bridge_get_modes(tc->panel_bridge, connector);
1601                 if (num_modes > 0)
1602                         return num_modes;
1603         }
1604
1605         edid = tc_get_edid(&tc->bridge, connector);
1606         num_modes = drm_add_edid_modes(connector, edid);
1607         kfree(edid);
1608
1609         return num_modes;
1610 }
1611
1612 static const struct drm_connector_helper_funcs tc_connector_helper_funcs = {
1613         .get_modes = tc_connector_get_modes,
1614 };
1615
1616 static enum drm_connector_status tc_bridge_detect(struct drm_bridge *bridge)
1617 {
1618         struct tc_data *tc = bridge_to_tc(bridge);
1619         bool conn;
1620         u32 val;
1621         int ret;
1622
1623         ret = regmap_read(tc->regmap, GPIOI, &val);
1624         if (ret)
1625                 return connector_status_unknown;
1626
1627         conn = val & BIT(tc->hpd_pin);
1628
1629         if (conn)
1630                 return connector_status_connected;
1631         else
1632                 return connector_status_disconnected;
1633 }
1634
1635 static enum drm_connector_status
1636 tc_connector_detect(struct drm_connector *connector, bool force)
1637 {
1638         struct tc_data *tc = connector_to_tc(connector);
1639
1640         if (tc->hpd_pin >= 0)
1641                 return tc_bridge_detect(&tc->bridge);
1642
1643         if (tc->panel_bridge)
1644                 return connector_status_connected;
1645         else
1646                 return connector_status_unknown;
1647 }
1648
1649 static const struct drm_connector_funcs tc_connector_funcs = {
1650         .detect = tc_connector_detect,
1651         .fill_modes = drm_helper_probe_single_connector_modes,
1652         .destroy = drm_connector_cleanup,
1653         .reset = drm_atomic_helper_connector_reset,
1654         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1655         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1656 };
1657
1658 static int tc_dpi_bridge_attach(struct drm_bridge *bridge,
1659                                 enum drm_bridge_attach_flags flags)
1660 {
1661         struct tc_data *tc = bridge_to_tc(bridge);
1662
1663         if (!tc->panel_bridge)
1664                 return 0;
1665
1666         return drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge,
1667                                  &tc->bridge, flags);
1668 }
1669
1670 static int tc_edp_bridge_attach(struct drm_bridge *bridge,
1671                                 enum drm_bridge_attach_flags flags)
1672 {
1673         u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1674         struct tc_data *tc = bridge_to_tc(bridge);
1675         struct drm_device *drm = bridge->dev;
1676         int ret;
1677
1678         if (tc->panel_bridge) {
1679                 /* If a connector is required then this driver shall create it */
1680                 ret = drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge,
1681                                         &tc->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
1682                 if (ret)
1683                         return ret;
1684         }
1685
1686         if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
1687                 return 0;
1688
1689         tc->aux.drm_dev = drm;
1690         ret = drm_dp_aux_register(&tc->aux);
1691         if (ret < 0)
1692                 return ret;
1693
1694         /* Create DP/eDP connector */
1695         drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1696         ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, tc->bridge.type);
1697         if (ret)
1698                 goto aux_unregister;
1699
1700         /* Don't poll if don't have HPD connected */
1701         if (tc->hpd_pin >= 0) {
1702                 if (tc->have_irq)
1703                         tc->connector.polled = DRM_CONNECTOR_POLL_HPD;
1704                 else
1705                         tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
1706                                                DRM_CONNECTOR_POLL_DISCONNECT;
1707         }
1708
1709         drm_display_info_set_bus_formats(&tc->connector.display_info,
1710                                          &bus_format, 1);
1711         tc->connector.display_info.bus_flags =
1712                 DRM_BUS_FLAG_DE_HIGH |
1713                 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE |
1714                 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE;
1715         drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1716
1717         return 0;
1718 aux_unregister:
1719         drm_dp_aux_unregister(&tc->aux);
1720         return ret;
1721 }
1722
1723 static void tc_edp_bridge_detach(struct drm_bridge *bridge)
1724 {
1725         drm_dp_aux_unregister(&bridge_to_tc(bridge)->aux);
1726 }
1727
1728 #define MAX_INPUT_SEL_FORMATS   1
1729
1730 static u32 *
1731 tc_dpi_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
1732                                  struct drm_bridge_state *bridge_state,
1733                                  struct drm_crtc_state *crtc_state,
1734                                  struct drm_connector_state *conn_state,
1735                                  u32 output_fmt,
1736                                  unsigned int *num_input_fmts)
1737 {
1738         u32 *input_fmts;
1739
1740         *num_input_fmts = 0;
1741
1742         input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
1743                              GFP_KERNEL);
1744         if (!input_fmts)
1745                 return NULL;
1746
1747         /* This is the DSI-end bus format */
1748         input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
1749         *num_input_fmts = 1;
1750
1751         return input_fmts;
1752 }
1753
1754 static const struct drm_bridge_funcs tc_dpi_bridge_funcs = {
1755         .attach = tc_dpi_bridge_attach,
1756         .mode_valid = tc_dpi_mode_valid,
1757         .mode_set = tc_bridge_mode_set,
1758         .atomic_check = tc_dpi_atomic_check,
1759         .atomic_enable = tc_dpi_bridge_atomic_enable,
1760         .atomic_disable = tc_dpi_bridge_atomic_disable,
1761         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1762         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1763         .atomic_reset = drm_atomic_helper_bridge_reset,
1764         .atomic_get_input_bus_fmts = tc_dpi_atomic_get_input_bus_fmts,
1765 };
1766
1767 static const struct drm_bridge_funcs tc_edp_bridge_funcs = {
1768         .attach = tc_edp_bridge_attach,
1769         .detach = tc_edp_bridge_detach,
1770         .mode_valid = tc_edp_mode_valid,
1771         .mode_set = tc_bridge_mode_set,
1772         .atomic_check = tc_edp_atomic_check,
1773         .atomic_enable = tc_edp_bridge_atomic_enable,
1774         .atomic_disable = tc_edp_bridge_atomic_disable,
1775         .detect = tc_bridge_detect,
1776         .get_edid = tc_get_edid,
1777         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1778         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1779         .atomic_reset = drm_atomic_helper_bridge_reset,
1780 };
1781
1782 static bool tc_readable_reg(struct device *dev, unsigned int reg)
1783 {
1784         switch (reg) {
1785         /* DSI D-PHY Layer */
1786         case 0x004:
1787         case 0x020:
1788         case 0x024:
1789         case 0x028:
1790         case 0x02c:
1791         case 0x030:
1792         case 0x038:
1793         case 0x040:
1794         case 0x044:
1795         case 0x048:
1796         case 0x04c:
1797         case 0x050:
1798         case 0x054:
1799         /* DSI PPI Layer */
1800         case PPI_STARTPPI:
1801         case 0x108:
1802         case 0x110:
1803         case PPI_LPTXTIMECNT:
1804         case PPI_LANEENABLE:
1805         case PPI_TX_RX_TA:
1806         case 0x140:
1807         case PPI_D0S_ATMR:
1808         case PPI_D1S_ATMR:
1809         case 0x14c:
1810         case 0x150:
1811         case PPI_D0S_CLRSIPOCOUNT:
1812         case PPI_D1S_CLRSIPOCOUNT:
1813         case PPI_D2S_CLRSIPOCOUNT:
1814         case PPI_D3S_CLRSIPOCOUNT:
1815         case 0x180:
1816         case 0x184:
1817         case 0x188:
1818         case 0x18c:
1819         case 0x190:
1820         case 0x1a0:
1821         case 0x1a4:
1822         case 0x1a8:
1823         case 0x1ac:
1824         case 0x1b0:
1825         case 0x1c0:
1826         case 0x1c4:
1827         case 0x1c8:
1828         case 0x1cc:
1829         case 0x1d0:
1830         case 0x1e0:
1831         case 0x1e4:
1832         case 0x1f0:
1833         case 0x1f4:
1834         /* DSI Protocol Layer */
1835         case DSI_STARTDSI:
1836         case 0x208:
1837         case DSI_LANEENABLE:
1838         case 0x214:
1839         case 0x218:
1840         case 0x220:
1841         case 0x224:
1842         case 0x228:
1843         case 0x230:
1844         /* DSI General */
1845         case 0x300:
1846         /* DSI Application Layer */
1847         case 0x400:
1848         case 0x404:
1849         /* DPI */
1850         case DPIPXLFMT:
1851         /* Parallel Output */
1852         case POCTRL:
1853         /* Video Path0 Configuration */
1854         case VPCTRL0:
1855         case HTIM01:
1856         case HTIM02:
1857         case VTIM01:
1858         case VTIM02:
1859         case VFUEN0:
1860         /* System */
1861         case TC_IDREG:
1862         case 0x504:
1863         case SYSSTAT:
1864         case SYSRSTENB:
1865         case SYSCTRL:
1866         /* I2C */
1867         case 0x520:
1868         /* GPIO */
1869         case GPIOM:
1870         case GPIOC:
1871         case GPIOO:
1872         case GPIOI:
1873         /* Interrupt */
1874         case INTCTL_G:
1875         case INTSTS_G:
1876         case 0x570:
1877         case 0x574:
1878         case INT_GP0_LCNT:
1879         case INT_GP1_LCNT:
1880         /* DisplayPort Control */
1881         case DP0CTL:
1882         /* DisplayPort Clock */
1883         case DP0_VIDMNGEN0:
1884         case DP0_VIDMNGEN1:
1885         case DP0_VMNGENSTATUS:
1886         case 0x628:
1887         case 0x62c:
1888         case 0x630:
1889         /* DisplayPort Main Channel */
1890         case DP0_SECSAMPLE:
1891         case DP0_VIDSYNCDELAY:
1892         case DP0_TOTALVAL:
1893         case DP0_STARTVAL:
1894         case DP0_ACTIVEVAL:
1895         case DP0_SYNCVAL:
1896         case DP0_MISC:
1897         /* DisplayPort Aux Channel */
1898         case DP0_AUXCFG0:
1899         case DP0_AUXCFG1:
1900         case DP0_AUXADDR:
1901         case 0x66c:
1902         case 0x670:
1903         case 0x674:
1904         case 0x678:
1905         case 0x67c:
1906         case 0x680:
1907         case 0x684:
1908         case 0x688:
1909         case DP0_AUXSTATUS:
1910         case DP0_AUXI2CADR:
1911         /* DisplayPort Link Training */
1912         case DP0_SRCCTRL:
1913         case DP0_LTSTAT:
1914         case DP0_SNKLTCHGREQ:
1915         case DP0_LTLOOPCTRL:
1916         case DP0_SNKLTCTRL:
1917         case 0x6e8:
1918         case 0x6ec:
1919         case 0x6f0:
1920         case 0x6f4:
1921         /* DisplayPort Audio */
1922         case 0x700:
1923         case 0x704:
1924         case 0x708:
1925         case 0x70c:
1926         case 0x710:
1927         case 0x714:
1928         case 0x718:
1929         case 0x71c:
1930         case 0x720:
1931         /* DisplayPort Source Control */
1932         case DP1_SRCCTRL:
1933         /* DisplayPort PHY */
1934         case DP_PHY_CTRL:
1935         case 0x810:
1936         case 0x814:
1937         case 0x820:
1938         case 0x840:
1939         /* I2S */
1940         case 0x880:
1941         case 0x888:
1942         case 0x88c:
1943         case 0x890:
1944         case 0x894:
1945         case 0x898:
1946         case 0x89c:
1947         case 0x8a0:
1948         case 0x8a4:
1949         case 0x8a8:
1950         case 0x8ac:
1951         case 0x8b0:
1952         case 0x8b4:
1953         /* PLL */
1954         case DP0_PLLCTRL:
1955         case DP1_PLLCTRL:
1956         case PXL_PLLCTRL:
1957         case PXL_PLLPARAM:
1958         case SYS_PLLPARAM:
1959         /* HDCP */
1960         case 0x980:
1961         case 0x984:
1962         case 0x988:
1963         case 0x98c:
1964         case 0x990:
1965         case 0x994:
1966         case 0x998:
1967         case 0x99c:
1968         case 0x9a0:
1969         case 0x9a4:
1970         case 0x9a8:
1971         case 0x9ac:
1972         /* Debug */
1973         case TSTCTL:
1974         case PLL_DBG:
1975                 return true;
1976         }
1977         return false;
1978 }
1979
1980 static const struct regmap_range tc_volatile_ranges[] = {
1981         regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS),
1982         regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ),
1983         regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL),
1984         regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),
1985         regmap_reg_range(VFUEN0, VFUEN0),
1986         regmap_reg_range(INTSTS_G, INTSTS_G),
1987         regmap_reg_range(GPIOI, GPIOI),
1988 };
1989
1990 static const struct regmap_access_table tc_volatile_table = {
1991         .yes_ranges = tc_volatile_ranges,
1992         .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges),
1993 };
1994
1995 static bool tc_writeable_reg(struct device *dev, unsigned int reg)
1996 {
1997         return (reg != TC_IDREG) &&
1998                (reg != DP0_LTSTAT) &&
1999                (reg != DP0_SNKLTCHGREQ);
2000 }
2001
2002 static const struct regmap_config tc_regmap_config = {
2003         .name = "tc358767",
2004         .reg_bits = 16,
2005         .val_bits = 32,
2006         .reg_stride = 4,
2007         .max_register = PLL_DBG,
2008         .cache_type = REGCACHE_MAPLE,
2009         .readable_reg = tc_readable_reg,
2010         .volatile_table = &tc_volatile_table,
2011         .writeable_reg = tc_writeable_reg,
2012         .reg_format_endian = REGMAP_ENDIAN_BIG,
2013         .val_format_endian = REGMAP_ENDIAN_LITTLE,
2014 };
2015
2016 static irqreturn_t tc_irq_handler(int irq, void *arg)
2017 {
2018         struct tc_data *tc = arg;
2019         u32 val;
2020         int r;
2021
2022         r = regmap_read(tc->regmap, INTSTS_G, &val);
2023         if (r)
2024                 return IRQ_NONE;
2025
2026         if (!val)
2027                 return IRQ_NONE;
2028
2029         if (val & INT_SYSERR) {
2030                 u32 stat = 0;
2031
2032                 regmap_read(tc->regmap, SYSSTAT, &stat);
2033
2034                 dev_err(tc->dev, "syserr %x\n", stat);
2035         }
2036
2037         if (tc->hpd_pin >= 0 && tc->bridge.dev) {
2038                 /*
2039                  * H is triggered when the GPIO goes high.
2040                  *
2041                  * LC is triggered when the GPIO goes low and stays low for
2042                  * the duration of LCNT
2043                  */
2044                 bool h = val & INT_GPIO_H(tc->hpd_pin);
2045                 bool lc = val & INT_GPIO_LC(tc->hpd_pin);
2046
2047                 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin,
2048                         h ? "H" : "", lc ? "LC" : "");
2049
2050                 if (h || lc)
2051                         drm_kms_helper_hotplug_event(tc->bridge.dev);
2052         }
2053
2054         regmap_write(tc->regmap, INTSTS_G, val);
2055
2056         return IRQ_HANDLED;
2057 }
2058
2059 static int tc_mipi_dsi_host_attach(struct tc_data *tc)
2060 {
2061         struct device *dev = tc->dev;
2062         struct device_node *host_node;
2063         struct device_node *endpoint;
2064         struct mipi_dsi_device *dsi;
2065         struct mipi_dsi_host *host;
2066         const struct mipi_dsi_device_info info = {
2067                 .type = "tc358767",
2068                 .channel = 0,
2069                 .node = NULL,
2070         };
2071         int dsi_lanes, ret;
2072
2073         endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
2074         dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4);
2075         host_node = of_graph_get_remote_port_parent(endpoint);
2076         host = of_find_mipi_dsi_host_by_node(host_node);
2077         of_node_put(host_node);
2078         of_node_put(endpoint);
2079
2080         if (!host)
2081                 return -EPROBE_DEFER;
2082
2083         if (dsi_lanes < 0)
2084                 return dsi_lanes;
2085
2086         dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
2087         if (IS_ERR(dsi))
2088                 return dev_err_probe(dev, PTR_ERR(dsi),
2089                                      "failed to create dsi device\n");
2090
2091         tc->dsi = dsi;
2092         dsi->lanes = dsi_lanes;
2093         dsi->format = MIPI_DSI_FMT_RGB888;
2094         dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
2095                           MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;
2096
2097         ret = devm_mipi_dsi_attach(dev, dsi);
2098         if (ret < 0) {
2099                 dev_err(dev, "failed to attach dsi to host: %d\n", ret);
2100                 return ret;
2101         }
2102
2103         return 0;
2104 }
2105
2106 static int tc_probe_dpi_bridge_endpoint(struct tc_data *tc)
2107 {
2108         struct device *dev = tc->dev;
2109         struct drm_bridge *bridge;
2110         struct drm_panel *panel;
2111         int ret;
2112
2113         /* port@1 is the DPI input/output port */
2114         ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, &bridge);
2115         if (ret && ret != -ENODEV)
2116                 return ret;
2117
2118         if (panel) {
2119                 bridge = devm_drm_panel_bridge_add(dev, panel);
2120                 if (IS_ERR(bridge))
2121                         return PTR_ERR(bridge);
2122         }
2123
2124         if (bridge) {
2125                 tc->panel_bridge = bridge;
2126                 tc->bridge.type = DRM_MODE_CONNECTOR_DPI;
2127                 tc->bridge.funcs = &tc_dpi_bridge_funcs;
2128
2129                 return 0;
2130         }
2131
2132         return ret;
2133 }
2134
2135 static int tc_probe_edp_bridge_endpoint(struct tc_data *tc)
2136 {
2137         struct device *dev = tc->dev;
2138         struct drm_panel *panel;
2139         int ret;
2140
2141         /* port@2 is the output port */
2142         ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, NULL);
2143         if (ret && ret != -ENODEV)
2144                 return ret;
2145
2146         if (panel) {
2147                 struct drm_bridge *panel_bridge;
2148
2149                 panel_bridge = devm_drm_panel_bridge_add(dev, panel);
2150                 if (IS_ERR(panel_bridge))
2151                         return PTR_ERR(panel_bridge);
2152
2153                 tc->panel_bridge = panel_bridge;
2154                 tc->bridge.type = DRM_MODE_CONNECTOR_eDP;
2155         } else {
2156                 tc->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
2157         }
2158
2159         tc->bridge.funcs = &tc_edp_bridge_funcs;
2160         if (tc->hpd_pin >= 0)
2161                 tc->bridge.ops |= DRM_BRIDGE_OP_DETECT;
2162         tc->bridge.ops |= DRM_BRIDGE_OP_EDID;
2163
2164         return 0;
2165 }
2166
2167 static int tc_probe_bridge_endpoint(struct tc_data *tc)
2168 {
2169         struct device *dev = tc->dev;
2170         struct of_endpoint endpoint;
2171         struct device_node *node = NULL;
2172         const u8 mode_dpi_to_edp = BIT(1) | BIT(2);
2173         const u8 mode_dpi_to_dp = BIT(1);
2174         const u8 mode_dsi_to_edp = BIT(0) | BIT(2);
2175         const u8 mode_dsi_to_dp = BIT(0);
2176         const u8 mode_dsi_to_dpi = BIT(0) | BIT(1);
2177         u8 mode = 0;
2178
2179         /*
2180          * Determine bridge configuration.
2181          *
2182          * Port allocation:
2183          * port@0 - DSI input
2184          * port@1 - DPI input/output
2185          * port@2 - eDP output
2186          *
2187          * Possible connections:
2188          * DPI -> port@1 -> port@2 -> eDP :: [port@0 is not connected]
2189          * DSI -> port@0 -> port@2 -> eDP :: [port@1 is not connected]
2190          * DSI -> port@0 -> port@1 -> DPI :: [port@2 is not connected]
2191          */
2192
2193         for_each_endpoint_of_node(dev->of_node, node) {
2194                 of_graph_parse_endpoint(node, &endpoint);
2195                 if (endpoint.port > 2) {
2196                         of_node_put(node);
2197                         return -EINVAL;
2198                 }
2199                 mode |= BIT(endpoint.port);
2200         }
2201
2202         if (mode == mode_dpi_to_edp || mode == mode_dpi_to_dp) {
2203                 tc->input_connector_dsi = false;
2204                 return tc_probe_edp_bridge_endpoint(tc);
2205         } else if (mode == mode_dsi_to_dpi) {
2206                 tc->input_connector_dsi = true;
2207                 return tc_probe_dpi_bridge_endpoint(tc);
2208         } else if (mode == mode_dsi_to_edp || mode == mode_dsi_to_dp) {
2209                 tc->input_connector_dsi = true;
2210                 return tc_probe_edp_bridge_endpoint(tc);
2211         }
2212
2213         dev_warn(dev, "Invalid mode (0x%x) is not supported!\n", mode);
2214
2215         return -EINVAL;
2216 }
2217
2218 static int tc_probe(struct i2c_client *client)
2219 {
2220         struct device *dev = &client->dev;
2221         struct tc_data *tc;
2222         int ret;
2223
2224         tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
2225         if (!tc)
2226                 return -ENOMEM;
2227
2228         tc->dev = dev;
2229
2230         ret = tc_probe_bridge_endpoint(tc);
2231         if (ret)
2232                 return ret;
2233
2234         tc->refclk = devm_clk_get_enabled(dev, "ref");
2235         if (IS_ERR(tc->refclk))
2236                 return dev_err_probe(dev, PTR_ERR(tc->refclk),
2237                                      "Failed to get and enable the ref clk\n");
2238
2239         /* tRSTW = 100 cycles , at 13 MHz that is ~7.69 us */
2240         usleep_range(10, 15);
2241
2242         /* Shut down GPIO is optional */
2243         tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
2244         if (IS_ERR(tc->sd_gpio))
2245                 return PTR_ERR(tc->sd_gpio);
2246
2247         if (tc->sd_gpio) {
2248                 gpiod_set_value_cansleep(tc->sd_gpio, 0);
2249                 usleep_range(5000, 10000);
2250         }
2251
2252         /* Reset GPIO is optional */
2253         tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
2254         if (IS_ERR(tc->reset_gpio))
2255                 return PTR_ERR(tc->reset_gpio);
2256
2257         if (tc->reset_gpio) {
2258                 gpiod_set_value_cansleep(tc->reset_gpio, 1);
2259                 usleep_range(5000, 10000);
2260         }
2261
2262         tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
2263         if (IS_ERR(tc->regmap)) {
2264                 ret = PTR_ERR(tc->regmap);
2265                 dev_err(dev, "Failed to initialize regmap: %d\n", ret);
2266                 return ret;
2267         }
2268
2269         ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin",
2270                                    &tc->hpd_pin);
2271         if (ret) {
2272                 tc->hpd_pin = -ENODEV;
2273         } else {
2274                 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) {
2275                         dev_err(dev, "failed to parse HPD number\n");
2276                         return -EINVAL;
2277                 }
2278         }
2279
2280         if (client->irq > 0) {
2281                 /* enable SysErr */
2282                 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR);
2283
2284                 ret = devm_request_threaded_irq(dev, client->irq,
2285                                                 NULL, tc_irq_handler,
2286                                                 IRQF_ONESHOT,
2287                                                 "tc358767-irq", tc);
2288                 if (ret) {
2289                         dev_err(dev, "failed to register dp interrupt\n");
2290                         return ret;
2291                 }
2292
2293                 tc->have_irq = true;
2294         }
2295
2296         ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
2297         if (ret) {
2298                 dev_err(tc->dev, "can not read device ID: %d\n", ret);
2299                 return ret;
2300         }
2301
2302         if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
2303                 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
2304                 return -EINVAL;
2305         }
2306
2307         tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
2308
2309         if (!tc->reset_gpio) {
2310                 /*
2311                  * If the reset pin isn't present, do a software reset. It isn't
2312                  * as thorough as the hardware reset, as we can't reset the I2C
2313                  * communication block for obvious reasons, but it's getting the
2314                  * chip into a defined state.
2315                  */
2316                 regmap_update_bits(tc->regmap, SYSRSTENB,
2317                                 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
2318                                 0);
2319                 regmap_update_bits(tc->regmap, SYSRSTENB,
2320                                 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
2321                                 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP);
2322                 usleep_range(5000, 10000);
2323         }
2324
2325         if (tc->hpd_pin >= 0) {
2326                 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT;
2327                 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin);
2328
2329                 /* Set LCNT to 2ms */
2330                 regmap_write(tc->regmap, lcnt_reg,
2331                              clk_get_rate(tc->refclk) * 2 / 1000);
2332                 /* We need the "alternate" mode for HPD */
2333                 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin));
2334
2335                 if (tc->have_irq) {
2336                         /* enable H & LC */
2337                         regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc);
2338                 }
2339         }
2340
2341         if (tc->bridge.type != DRM_MODE_CONNECTOR_DPI) { /* (e)DP output */
2342                 ret = tc_aux_link_setup(tc);
2343                 if (ret)
2344                         return ret;
2345         }
2346
2347         tc->bridge.of_node = dev->of_node;
2348         drm_bridge_add(&tc->bridge);
2349
2350         i2c_set_clientdata(client, tc);
2351
2352         if (tc->input_connector_dsi) {                  /* DSI input */
2353                 ret = tc_mipi_dsi_host_attach(tc);
2354                 if (ret) {
2355                         drm_bridge_remove(&tc->bridge);
2356                         return ret;
2357                 }
2358         }
2359
2360         return 0;
2361 }
2362
2363 static void tc_remove(struct i2c_client *client)
2364 {
2365         struct tc_data *tc = i2c_get_clientdata(client);
2366
2367         drm_bridge_remove(&tc->bridge);
2368 }
2369
2370 static const struct i2c_device_id tc358767_i2c_ids[] = {
2371         { "tc358767", 0 },
2372         { }
2373 };
2374 MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids);
2375
2376 static const struct of_device_id tc358767_of_ids[] = {
2377         { .compatible = "toshiba,tc358767", },
2378         { }
2379 };
2380 MODULE_DEVICE_TABLE(of, tc358767_of_ids);
2381
2382 static struct i2c_driver tc358767_driver = {
2383         .driver = {
2384                 .name = "tc358767",
2385                 .of_match_table = tc358767_of_ids,
2386         },
2387         .id_table = tc358767_i2c_ids,
2388         .probe = tc_probe,
2389         .remove = tc_remove,
2390 };
2391 module_i2c_driver(tc358767_driver);
2392
2393 MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>");
2394 MODULE_DESCRIPTION("tc358767 eDP encoder driver");
2395 MODULE_LICENSE("GPL");