drivers/gpu/drm/bridge/tc358767.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * tc358767 eDP bridge driver
   4  *
   5  * Copyright (C) 2016 CogentEmbedded Inc
   6  * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
   7  *
   8  * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
   9  *
  10  * Copyright (C) 2016 Zodiac Inflight Innovations
  11  *
  12  * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c
  13  *
  14  * Copyright (C) 2012 Texas Instruments
  15  * Author: Rob Clark <robdclark@gmail.com>
  16  */
  17
  18 #include <linux/bitfield.h>
  19 #include <linux/clk.h>
  20 #include <linux/device.h>
  21 #include <linux/gpio/consumer.h>
  22 #include <linux/i2c.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/regmap.h>
  26 #include <linux/slab.h>
  27
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_bridge.h>
  30 #include <drm/drm_dp_helper.h>
  31 #include <drm/drm_edid.h>
  32 #include <drm/drm_of.h>
  33 #include <drm/drm_panel.h>
  34 #include <drm/drm_print.h>
  35 #include <drm/drm_probe_helper.h>
  36
  37 /* Registers */
  38
  39 /* Display Parallel Interface */
  40 #define DPIPXLFMT               0x0440
  41 #define VS_POL_ACTIVE_LOW               (1 << 10)
  42 #define HS_POL_ACTIVE_LOW               (1 << 9)
  43 #define DE_POL_ACTIVE_HIGH              (0 << 8)
  44 #define SUB_CFG_TYPE_CONFIG1            (0 << 2) /* LSB aligned */
  45 #define SUB_CFG_TYPE_CONFIG2            (1 << 2) /* Loosely Packed */
  46 #define SUB_CFG_TYPE_CONFIG3            (2 << 2) /* LSB aligned 8-bit */
  47 #define DPI_BPP_RGB888                  (0 << 0)
  48 #define DPI_BPP_RGB666                  (1 << 0)
  49 #define DPI_BPP_RGB565                  (2 << 0)
  50
  51 /* Video Path */
  52 #define VPCTRL0                 0x0450
  53 #define VSDELAY                 GENMASK(31, 20)
  54 #define OPXLFMT_RGB666                  (0 << 8)
  55 #define OPXLFMT_RGB888                  (1 << 8)
  56 #define FRMSYNC_DISABLED                (0 << 4) /* Video Timing Gen Disabled */
  57 #define FRMSYNC_ENABLED                 (1 << 4) /* Video Timing Gen Enabled */
  58 #define MSF_DISABLED                    (0 << 0) /* Magic Square FRC disabled */
  59 #define MSF_ENABLED                     (1 << 0) /* Magic Square FRC enabled */
  60 #define HTIM01                  0x0454
  61 #define HPW                     GENMASK(8, 0)
  62 #define HBPR                    GENMASK(24, 16)
  63 #define HTIM02                  0x0458
  64 #define HDISPR                  GENMASK(10, 0)
  65 #define HFPR                    GENMASK(24, 16)
  66 #define VTIM01                  0x045c
  67 #define VSPR                    GENMASK(7, 0)
  68 #define VBPR                    GENMASK(23, 16)
  69 #define VTIM02                  0x0460
  70 #define VFPR                    GENMASK(23, 16)
  71 #define VDISPR                  GENMASK(10, 0)
  72 #define VFUEN0                  0x0464
  73 #define VFUEN                           BIT(0)   /* Video Frame Timing Upload */
  74
  75 /* System */
  76 #define TC_IDREG                0x0500
  77 #define SYSSTAT                 0x0508
  78 #define SYSCTRL                 0x0510
  79 #define DP0_AUDSRC_NO_INPUT             (0 << 3)
  80 #define DP0_AUDSRC_I2S_RX               (1 << 3)
  81 #define DP0_VIDSRC_NO_INPUT             (0 << 0)
  82 #define DP0_VIDSRC_DSI_RX               (1 << 0)
  83 #define DP0_VIDSRC_DPI_RX               (2 << 0)
  84 #define DP0_VIDSRC_COLOR_BAR            (3 << 0)
  85 #define SYSRSTENB               0x050c
  86 #define ENBI2C                          (1 << 0)
  87 #define ENBLCD0                         (1 << 2)
  88 #define ENBBM                           (1 << 3)
  89 #define ENBDSIRX                        (1 << 4)
  90 #define ENBREG                          (1 << 5)
  91 #define ENBHDCP                         (1 << 8)
  92 #define GPIOM                   0x0540
  93 #define GPIOC                   0x0544
  94 #define GPIOO                   0x0548
  95 #define GPIOI                   0x054c
  96 #define INTCTL_G                0x0560
  97 #define INTSTS_G                0x0564
  98
  99 #define INT_SYSERR              BIT(16)
 100 #define INT_GPIO_H(x)           (1 << (x == 0 ? 2 : 10))
 101 #define INT_GPIO_LC(x)          (1 << (x == 0 ? 3 : 11))
 102
 103 #define INT_GP0_LCNT            0x0584
 104 #define INT_GP1_LCNT            0x0588
 105
 106 /* Control */
 107 #define DP0CTL                  0x0600
 108 #define VID_MN_GEN                      BIT(6)   /* Auto-generate M/N values */
 109 #define EF_EN                           BIT(5)   /* Enable Enhanced Framing */
 110 #define VID_EN                          BIT(1)   /* Video transmission enable */
 111 #define DP_EN                           BIT(0)   /* Enable DPTX function */
 112
 113 /* Clocks */
 114 #define DP0_VIDMNGEN0           0x0610
 115 #define DP0_VIDMNGEN1           0x0614
 116 #define DP0_VMNGENSTATUS        0x0618
 117
 118 /* Main Channel */
 119 #define DP0_SECSAMPLE           0x0640
 120 #define DP0_VIDSYNCDELAY        0x0644
 121 #define VID_SYNC_DLY            GENMASK(15, 0)
 122 #define THRESH_DLY              GENMASK(31, 16)
 123
 124 #define DP0_TOTALVAL            0x0648
 125 #define H_TOTAL                 GENMASK(15, 0)
 126 #define V_TOTAL                 GENMASK(31, 16)
 127 #define DP0_STARTVAL            0x064c
 128 #define H_START                 GENMASK(15, 0)
 129 #define V_START                 GENMASK(31, 16)
 130 #define DP0_ACTIVEVAL           0x0650
 131 #define H_ACT                   GENMASK(15, 0)
 132 #define V_ACT                   GENMASK(31, 16)
 133
 134 #define DP0_SYNCVAL             0x0654
 135 #define VS_WIDTH                GENMASK(30, 16)
 136 #define HS_WIDTH                GENMASK(14, 0)
 137 #define SYNCVAL_HS_POL_ACTIVE_LOW       (1 << 15)
 138 #define SYNCVAL_VS_POL_ACTIVE_LOW       (1 << 31)
 139 #define DP0_MISC                0x0658
 140 #define TU_SIZE_RECOMMENDED             (63) /* LSCLK cycles per TU */
 141 #define MAX_TU_SYMBOL           GENMASK(28, 23)
 142 #define TU_SIZE                 GENMASK(21, 16)
 143 #define BPC_6                           (0 << 5)
 144 #define BPC_8                           (1 << 5)
 145
 146 /* AUX channel */
 147 #define DP0_AUXCFG0             0x0660
 148 #define DP0_AUXCFG0_BSIZE       GENMASK(11, 8)
 149 #define DP0_AUXCFG0_ADDR_ONLY   BIT(4)
 150 #define DP0_AUXCFG1             0x0664
 151 #define AUX_RX_FILTER_EN                BIT(16)
 152
 153 #define DP0_AUXADDR             0x0668
 154 #define DP0_AUXWDATA(i)         (0x066c + (i) * 4)
 155 #define DP0_AUXRDATA(i)         (0x067c + (i) * 4)
 156 #define DP0_AUXSTATUS           0x068c
 157 #define AUX_BYTES               GENMASK(15, 8)
 158 #define AUX_STATUS              GENMASK(7, 4)
 159 #define AUX_TIMEOUT             BIT(1)
 160 #define AUX_BUSY                BIT(0)
 161 #define DP0_AUXI2CADR           0x0698
 162
 163 /* Link Training */
 164 #define DP0_SRCCTRL             0x06a0
 165 #define DP0_SRCCTRL_SCRMBLDIS           BIT(13)
 166 #define DP0_SRCCTRL_EN810B              BIT(12)
 167 #define DP0_SRCCTRL_NOTP                (0 << 8)
 168 #define DP0_SRCCTRL_TP1                 (1 << 8)
 169 #define DP0_SRCCTRL_TP2                 (2 << 8)
 170 #define DP0_SRCCTRL_LANESKEW            BIT(7)
 171 #define DP0_SRCCTRL_SSCG                BIT(3)
 172 #define DP0_SRCCTRL_LANES_1             (0 << 2)
 173 #define DP0_SRCCTRL_LANES_2             (1 << 2)
 174 #define DP0_SRCCTRL_BW27                (1 << 1)
 175 #define DP0_SRCCTRL_BW162               (0 << 1)
 176 #define DP0_SRCCTRL_AUTOCORRECT         BIT(0)
 177 #define DP0_LTSTAT              0x06d0
 178 #define LT_LOOPDONE                     BIT(13)
 179 #define LT_STATUS_MASK                  (0x1f << 8)
 180 #define LT_CHANNEL1_EQ_BITS             (DP_CHANNEL_EQ_BITS << 4)
 181 #define LT_INTERLANE_ALIGN_DONE         BIT(3)
 182 #define LT_CHANNEL0_EQ_BITS             (DP_CHANNEL_EQ_BITS)
 183 #define DP0_SNKLTCHGREQ         0x06d4
 184 #define DP0_LTLOOPCTRL          0x06d8
 185 #define DP0_SNKLTCTRL           0x06e4
 186
 187 #define DP1_SRCCTRL             0x07a0
 188
 189 /* PHY */
 190 #define DP_PHY_CTRL             0x0800
 191 #define DP_PHY_RST                      BIT(28)  /* DP PHY Global Soft Reset */
 192 #define BGREN                           BIT(25)  /* AUX PHY BGR Enable */
 193 #define PWR_SW_EN                       BIT(24)  /* PHY Power Switch Enable */
 194 #define PHY_M1_RST                      BIT(12)  /* Reset PHY1 Main Channel */
 195 #define PHY_RDY                         BIT(16)  /* PHY Main Channels Ready */
 196 #define PHY_M0_RST                      BIT(8)   /* Reset PHY0 Main Channel */
 197 #define PHY_2LANE                       BIT(2)   /* PHY Enable 2 lanes */
 198 #define PHY_A0_EN                       BIT(1)   /* PHY Aux Channel0 Enable */
 199 #define PHY_M0_EN                       BIT(0)   /* PHY Main Channel0 Enable */
 200
 201 /* PLL */
 202 #define DP0_PLLCTRL             0x0900
 203 #define DP1_PLLCTRL             0x0904  /* not defined in DS */
 204 #define PXL_PLLCTRL             0x0908
 205 #define PLLUPDATE                       BIT(2)
 206 #define PLLBYP                          BIT(1)
 207 #define PLLEN                           BIT(0)
 208 #define PXL_PLLPARAM            0x0914
 209 #define IN_SEL_REFCLK                   (0 << 14)
 210 #define SYS_PLLPARAM            0x0918
 211 #define REF_FREQ_38M4                   (0 << 8) /* 38.4 MHz */
 212 #define REF_FREQ_19M2                   (1 << 8) /* 19.2 MHz */
 213 #define REF_FREQ_26M                    (2 << 8) /* 26 MHz */
 214 #define REF_FREQ_13M                    (3 << 8) /* 13 MHz */
 215 #define SYSCLK_SEL_LSCLK                (0 << 4)
 216 #define LSCLK_DIV_1                     (0 << 0)
 217 #define LSCLK_DIV_2                     (1 << 0)
 218
 219 /* Test & Debug */
 220 #define TSTCTL                  0x0a00
 221 #define COLOR_R                 GENMASK(31, 24)
 222 #define COLOR_G                 GENMASK(23, 16)
 223 #define COLOR_B                 GENMASK(15, 8)
 224 #define ENI2CFILTER             BIT(4)
 225 #define COLOR_BAR_MODE          GENMASK(1, 0)
 226 #define COLOR_BAR_MODE_BARS     2
 227 #define PLL_DBG                 0x0a04
 228
 229 static bool tc_test_pattern;
 230 module_param_named(test, tc_test_pattern, bool, 0644);
 231
 232 struct tc_edp_link {
 233         u8                      dpcd[DP_RECEIVER_CAP_SIZE];
 234         unsigned int            rate;
 235         u8                      num_lanes;
 236         u8                      assr;
 237         bool                    scrambler_dis;
 238         bool                    spread;
 239 };
 240
 241 struct tc_data {
 242         struct device           *dev;
 243         struct regmap           *regmap;
 244         struct drm_dp_aux       aux;
 245
 246         struct drm_bridge       bridge;
 247         struct drm_bridge       *panel_bridge;
 248         struct drm_connector    connector;
 249
 250         /* link settings */
 251         struct tc_edp_link      link;
 252
 253         /* current mode */
 254         struct drm_display_mode mode;
 255
 256         u32                     rev;
 257         u8                      assr;
 258
 259         struct gpio_desc        *sd_gpio;
 260         struct gpio_desc        *reset_gpio;
 261         struct clk              *refclk;
 262
 263         /* do we have IRQ */
 264         bool                    have_irq;
 265
 266         /* HPD pin number (0 or 1) or -ENODEV */
 267         int                     hpd_pin;
 268 };
 269
 270 static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
 271 {
 272         return container_of(a, struct tc_data, aux);
 273 }
 274
 275 static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
 276 {
 277         return container_of(b, struct tc_data, bridge);
 278 }
 279
 280 static inline struct tc_data *connector_to_tc(struct drm_connector *c)
 281 {
 282         return container_of(c, struct tc_data, connector);
 283 }
 284
 285 static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr,
 286                                   unsigned int cond_mask,
 287                                   unsigned int cond_value,
 288                                   unsigned long sleep_us, u64 timeout_us)
 289 {
 290         unsigned int val;
 291
 292         return regmap_read_poll_timeout(tc->regmap, addr, val,
 293                                         (val & cond_mask) == cond_value,
 294                                         sleep_us, timeout_us);
 295 }
 296
 297 static int tc_aux_wait_busy(struct tc_data *tc)
 298 {
 299         return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 100, 100000);
 300 }
 301
 302 static int tc_aux_write_data(struct tc_data *tc, const void *data,
 303                              size_t size)
 304 {
 305         u32 auxwdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)] = { 0 };
 306         int ret, count = ALIGN(size, sizeof(u32));
 307
 308         memcpy(auxwdata, data, size);
 309
 310         ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count);
 311         if (ret)
 312                 return ret;
 313
 314         return size;
 315 }
 316
 317 static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size)
 318 {
 319         u32 auxrdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)];
 320         int ret, count = ALIGN(size, sizeof(u32));
 321
 322         ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count);
 323         if (ret)
 324                 return ret;
 325
 326         memcpy(data, auxrdata, size);
 327
 328         return size;
 329 }
 330
 331 static u32 tc_auxcfg0(struct drm_dp_aux_msg *msg, size_t size)
 332 {
 333         u32 auxcfg0 = msg->request;
 334
 335         if (size)
 336                 auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1);
 337         else
 338                 auxcfg0 |= DP0_AUXCFG0_ADDR_ONLY;
 339
 340         return auxcfg0;
 341 }
 342
 343 static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
 344                                struct drm_dp_aux_msg *msg)
 345 {
 346         struct tc_data *tc = aux_to_tc(aux);
 347         size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size);
 348         u8 request = msg->request & ~DP_AUX_I2C_MOT;
 349         u32 auxstatus;
 350         int ret;
 351
 352         ret = tc_aux_wait_busy(tc);
 353         if (ret)
 354                 return ret;
 355
 356         switch (request) {
 357         case DP_AUX_NATIVE_READ:
 358         case DP_AUX_I2C_READ:
 359                 break;
 360         case DP_AUX_NATIVE_WRITE:
 361         case DP_AUX_I2C_WRITE:
 362                 if (size) {
 363                         ret = tc_aux_write_data(tc, msg->buffer, size);
 364                         if (ret < 0)
 365                                 return ret;
 366                 }
 367                 break;
 368         default:
 369                 return -EINVAL;
 370         }
 371
 372         /* Store address */
 373         ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address);
 374         if (ret)
 375                 return ret;
 376         /* Start transfer */
 377         ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size));
 378         if (ret)
 379                 return ret;
 380
 381         ret = tc_aux_wait_busy(tc);
 382         if (ret)
 383                 return ret;
 384
 385         ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus);
 386         if (ret)
 387                 return ret;
 388
 389         if (auxstatus & AUX_TIMEOUT)
 390                 return -ETIMEDOUT;
 391         /*
 392          * For some reason address-only DP_AUX_I2C_WRITE (MOT), still
 393          * reports 1 byte transferred in its status. To deal we that
 394          * we ignore aux_bytes field if we know that this was an
 395          * address-only transfer
 396          */
 397         if (size)
 398                 size = FIELD_GET(AUX_BYTES, auxstatus);
 399         msg->reply = FIELD_GET(AUX_STATUS, auxstatus);
 400
 401         switch (request) {
 402         case DP_AUX_NATIVE_READ:
 403         case DP_AUX_I2C_READ:
 404                 if (size)
 405                         return tc_aux_read_data(tc, msg->buffer, size);
 406                 break;
 407         }
 408
 409         return size;
 410 }
 411
 412 static const char * const training_pattern1_errors[] = {
 413         "No errors",
 414         "Aux write error",
 415         "Aux read error",
 416         "Max voltage reached error",
 417         "Loop counter expired error",
 418         "res", "res", "res"
 419 };
 420
 421 static const char * const training_pattern2_errors[] = {
 422         "No errors",
 423         "Aux write error",
 424         "Aux read error",
 425         "Clock recovery failed error",
 426         "Loop counter expired error",
 427         "res", "res", "res"
 428 };
 429
 430 static u32 tc_srcctrl(struct tc_data *tc)
 431 {
 432         /*
 433          * No training pattern, skew lane 1 data by two LSCLK cycles with
 434          * respect to lane 0 data, AutoCorrect Mode = 0
 435          */
 436         u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_EN810B;
 437
 438         if (tc->link.scrambler_dis)
 439                 reg |= DP0_SRCCTRL_SCRMBLDIS;   /* Scrambler Disabled */
 440         if (tc->link.spread)
 441                 reg |= DP0_SRCCTRL_SSCG;        /* Spread Spectrum Enable */
 442         if (tc->link.num_lanes == 2)
 443                 reg |= DP0_SRCCTRL_LANES_2;     /* Two Main Channel Lanes */
 444         if (tc->link.rate != 162000)
 445                 reg |= DP0_SRCCTRL_BW27;        /* 2.7 Gbps link */
 446         return reg;
 447 }
 448
 449 static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl)
 450 {
 451         int ret;
 452
 453         ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN);
 454         if (ret)
 455                 return ret;
 456
 457         /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */
 458         usleep_range(3000, 6000);
 459
 460         return 0;
 461 }
 462
 463 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
 464 {
 465         int ret;
 466         int i_pre, best_pre = 1;
 467         int i_post, best_post = 1;
 468         int div, best_div = 1;
 469         int mul, best_mul = 1;
 470         int delta, best_delta;
 471         int ext_div[] = {1, 2, 3, 5, 7};
 472         int best_pixelclock = 0;
 473         int vco_hi = 0;
 474         u32 pxl_pllparam;
 475
 476         dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
 477                 refclk);
 478         best_delta = pixelclock;
 479         /* Loop over all possible ext_divs, skipping invalid configurations */
 480         for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) {
 481                 /*
 482                  * refclk / ext_pre_div should be in the 1 to 200 MHz range.
 483                  * We don't allow any refclk > 200 MHz, only check lower bounds.
 484                  */
 485                 if (refclk / ext_div[i_pre] < 1000000)
 486                         continue;
 487                 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
 488                         for (div = 1; div <= 16; div++) {
 489                                 u32 clk;
 490                                 u64 tmp;
 491
 492                                 tmp = pixelclock * ext_div[i_pre] *
 493                                       ext_div[i_post] * div;
 494                                 do_div(tmp, refclk);
 495                                 mul = tmp;
 496
 497                                 /* Check limits */
 498                                 if ((mul < 1) || (mul > 128))
 499                                         continue;
 500
 501                                 clk = (refclk / ext_div[i_pre] / div) * mul;
 502                                 /*
 503                                  * refclk * mul / (ext_pre_div * pre_div)
 504                                  * should be in the 150 to 650 MHz range
 505                                  */
 506                                 if ((clk > 650000000) || (clk < 150000000))
 507                                         continue;
 508
 509                                 clk = clk / ext_div[i_post];
 510                                 delta = clk - pixelclock;
 511
 512                                 if (abs(delta) < abs(best_delta)) {
 513                                         best_pre = i_pre;
 514                                         best_post = i_post;
 515                                         best_div = div;
 516                                         best_mul = mul;
 517                                         best_delta = delta;
 518                                         best_pixelclock = clk;
 519                                 }
 520                         }
 521                 }
 522         }
 523         if (best_pixelclock == 0) {
 524                 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
 525                         pixelclock);
 526                 return -EINVAL;
 527         }
 528
 529         dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock,
 530                 best_delta);
 531         dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
 532                 ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
 533
 534         /* if VCO >= 300 MHz */
 535         if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
 536                 vco_hi = 1;
 537         /* see DS */
 538         if (best_div == 16)
 539                 best_div = 0;
 540         if (best_mul == 128)
 541                 best_mul = 0;
 542
 543         /* Power up PLL and switch to bypass */
 544         ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
 545         if (ret)
 546                 return ret;
 547
 548         pxl_pllparam  = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */
 549         pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */
 550         pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */
 551         pxl_pllparam |= IN_SEL_REFCLK; /* Use RefClk as PLL input */
 552         pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */
 553         pxl_pllparam |= best_mul; /* Multiplier for PLL */
 554
 555         ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam);
 556         if (ret)
 557                 return ret;
 558
 559         /* Force PLL parameter update and disable bypass */
 560         return tc_pllupdate(tc, PXL_PLLCTRL);
 561 }
 562
 563 static int tc_pxl_pll_dis(struct tc_data *tc)
 564 {
 565         /* Enable PLL bypass, power down PLL */
 566         return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
 567 }
 568
 569 static int tc_stream_clock_calc(struct tc_data *tc)
 570 {
 571         /*
 572          * If the Stream clock and Link Symbol clock are
 573          * asynchronous with each other, the value of M changes over
 574          * time. This way of generating link clock and stream
 575          * clock is called Asynchronous Clock mode. The value M
 576          * must change while the value N stays constant. The
 577          * value of N in this Asynchronous Clock mode must be set
 578          * to 2^15 or 32,768.
 579          *
 580          * LSCLK = 1/10 of high speed link clock
 581          *
 582          * f_STRMCLK = M/N * f_LSCLK
 583          * M/N = f_STRMCLK / f_LSCLK
 584          *
 585          */
 586         return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768);
 587 }
 588
 589 static int tc_set_syspllparam(struct tc_data *tc)
 590 {
 591         unsigned long rate;
 592         u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
 593
 594         rate = clk_get_rate(tc->refclk);
 595         switch (rate) {
 596         case 38400000:
 597                 pllparam |= REF_FREQ_38M4;
 598                 break;
 599         case 26000000:
 600                 pllparam |= REF_FREQ_26M;
 601                 break;
 602         case 19200000:
 603                 pllparam |= REF_FREQ_19M2;
 604                 break;
 605         case 13000000:
 606                 pllparam |= REF_FREQ_13M;
 607                 break;
 608         default:
 609                 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
 610                 return -EINVAL;
 611         }
 612
 613         return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam);
 614 }
 615
 616 static int tc_aux_link_setup(struct tc_data *tc)
 617 {
 618         int ret;
 619         u32 dp0_auxcfg1;
 620
 621         /* Setup DP-PHY / PLL */
 622         ret = tc_set_syspllparam(tc);
 623         if (ret)
 624                 goto err;
 625
 626         ret = regmap_write(tc->regmap, DP_PHY_CTRL,
 627                            BGREN | PWR_SW_EN | PHY_A0_EN);
 628         if (ret)
 629                 goto err;
 630         /*
 631          * Initially PLLs are in bypass. Force PLL parameter update,
 632          * disable PLL bypass, enable PLL
 633          */
 634         ret = tc_pllupdate(tc, DP0_PLLCTRL);
 635         if (ret)
 636                 goto err;
 637
 638         ret = tc_pllupdate(tc, DP1_PLLCTRL);
 639         if (ret)
 640                 goto err;
 641
 642         ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 100, 100000);
 643         if (ret == -ETIMEDOUT) {
 644                 dev_err(tc->dev, "Timeout waiting for PHY to become ready");
 645                 return ret;
 646         } else if (ret) {
 647                 goto err;
 648         }
 649
 650         /* Setup AUX link */
 651         dp0_auxcfg1  = AUX_RX_FILTER_EN;
 652         dp0_auxcfg1 |= 0x06 << 8; /* Aux Bit Period Calculator Threshold */
 653         dp0_auxcfg1 |= 0x3f << 0; /* Aux Response Timeout Timer */
 654
 655         ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1);
 656         if (ret)
 657                 goto err;
 658
 659         return 0;
 660 err:
 661         dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
 662         return ret;
 663 }
 664
 665 static int tc_get_display_props(struct tc_data *tc)
 666 {
 667         u8 revision, num_lanes;
 668         unsigned int rate;
 669         int ret;
 670         u8 reg;
 671
 672         /* Read DP Rx Link Capability */
 673         ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd,
 674                                DP_RECEIVER_CAP_SIZE);
 675         if (ret < 0)
 676                 goto err_dpcd_read;
 677
 678         revision = tc->link.dpcd[DP_DPCD_REV];
 679         rate = drm_dp_max_link_rate(tc->link.dpcd);
 680         num_lanes = drm_dp_max_lane_count(tc->link.dpcd);
 681
 682         if (rate != 162000 && rate != 270000) {
 683                 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
 684                 rate = 270000;
 685         }
 686
 687         tc->link.rate = rate;
 688
 689         if (num_lanes > 2) {
 690                 dev_dbg(tc->dev, "Falling to 2 lanes\n");
 691                 num_lanes = 2;
 692         }
 693
 694         tc->link.num_lanes = num_lanes;
 695
 696         ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, &reg);
 697         if (ret < 0)
 698                 goto err_dpcd_read;
 699         tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5;
 700
 701         ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, &reg);
 702         if (ret < 0)
 703                 goto err_dpcd_read;
 704
 705         tc->link.scrambler_dis = false;
 706         /* read assr */
 707         ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, &reg);
 708         if (ret < 0)
 709                 goto err_dpcd_read;
 710         tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
 711
 712         dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
 713                 revision >> 4, revision & 0x0f,
 714                 (tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
 715                 tc->link.num_lanes,
 716                 drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
 717                 "enhanced" : "default");
 718         dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n",
 719                 tc->link.spread ? "0.5%" : "0.0%",
 720                 tc->link.scrambler_dis ? "disabled" : "enabled");
 721         dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
 722                 tc->link.assr, tc->assr);
 723
 724         return 0;
 725
 726 err_dpcd_read:
 727         dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
 728         return ret;
 729 }
 730
 731 static int tc_set_video_mode(struct tc_data *tc,
 732                              const struct drm_display_mode *mode)
 733 {
 734         int ret;
 735         int vid_sync_dly;
 736         int max_tu_symbol;
 737
 738         int left_margin = mode->htotal - mode->hsync_end;
 739         int right_margin = mode->hsync_start - mode->hdisplay;
 740         int hsync_len = mode->hsync_end - mode->hsync_start;
 741         int upper_margin = mode->vtotal - mode->vsync_end;
 742         int lower_margin = mode->vsync_start - mode->vdisplay;
 743         int vsync_len = mode->vsync_end - mode->vsync_start;
 744         u32 dp0_syncval;
 745         u32 bits_per_pixel = 24;
 746         u32 in_bw, out_bw;
 747
 748         /*
 749          * Recommended maximum number of symbols transferred in a transfer unit:
 750          * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
 751          *              (output active video bandwidth in bytes))
 752          * Must be less than tu_size.
 753          */
 754
 755         in_bw = mode->clock * bits_per_pixel / 8;
 756         out_bw = tc->link.num_lanes * tc->link.rate;
 757         max_tu_symbol = DIV_ROUND_UP(in_bw * TU_SIZE_RECOMMENDED, out_bw);
 758
 759         dev_dbg(tc->dev, "set mode %dx%d\n",
 760                 mode->hdisplay, mode->vdisplay);
 761         dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
 762                 left_margin, right_margin, hsync_len);
 763         dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
 764                 upper_margin, lower_margin, vsync_len);
 765         dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
 766
 767
 768         /*
 769          * LCD Ctl Frame Size
 770          * datasheet is not clear of vsdelay in case of DPI
 771          * assume we do not need any delay when DPI is a source of
 772          * sync signals
 773          */
 774         ret = regmap_write(tc->regmap, VPCTRL0,
 775                            FIELD_PREP(VSDELAY, 0) |
 776                            OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
 777         if (ret)
 778                 return ret;
 779
 780         ret = regmap_write(tc->regmap, HTIM01,
 781                            FIELD_PREP(HBPR, ALIGN(left_margin, 2)) |
 782                            FIELD_PREP(HPW, ALIGN(hsync_len, 2)));
 783         if (ret)
 784                 return ret;
 785
 786         ret = regmap_write(tc->regmap, HTIM02,
 787                            FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) |
 788                            FIELD_PREP(HFPR, ALIGN(right_margin, 2)));
 789         if (ret)
 790                 return ret;
 791
 792         ret = regmap_write(tc->regmap, VTIM01,
 793                            FIELD_PREP(VBPR, upper_margin) |
 794                            FIELD_PREP(VSPR, vsync_len));
 795         if (ret)
 796                 return ret;
 797
 798         ret = regmap_write(tc->regmap, VTIM02,
 799                            FIELD_PREP(VFPR, lower_margin) |
 800                            FIELD_PREP(VDISPR, mode->vdisplay));
 801         if (ret)
 802                 return ret;
 803
 804         ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */
 805         if (ret)
 806                 return ret;
 807
 808         /* Test pattern settings */
 809         ret = regmap_write(tc->regmap, TSTCTL,
 810                            FIELD_PREP(COLOR_R, 120) |
 811                            FIELD_PREP(COLOR_G, 20) |
 812                            FIELD_PREP(COLOR_B, 99) |
 813                            ENI2CFILTER |
 814                            FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS));
 815         if (ret)
 816                 return ret;
 817
 818         /* DP Main Stream Attributes */
 819         vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
 820         ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY,
 821                  FIELD_PREP(THRESH_DLY, max_tu_symbol) |
 822                  FIELD_PREP(VID_SYNC_DLY, vid_sync_dly));
 823
 824         ret = regmap_write(tc->regmap, DP0_TOTALVAL,
 825                            FIELD_PREP(H_TOTAL, mode->htotal) |
 826                            FIELD_PREP(V_TOTAL, mode->vtotal));
 827         if (ret)
 828                 return ret;
 829
 830         ret = regmap_write(tc->regmap, DP0_STARTVAL,
 831                            FIELD_PREP(H_START, left_margin + hsync_len) |
 832                            FIELD_PREP(V_START, upper_margin + vsync_len));
 833         if (ret)
 834                 return ret;
 835
 836         ret = regmap_write(tc->regmap, DP0_ACTIVEVAL,
 837                            FIELD_PREP(V_ACT, mode->vdisplay) |
 838                            FIELD_PREP(H_ACT, mode->hdisplay));
 839         if (ret)
 840                 return ret;
 841
 842         dp0_syncval = FIELD_PREP(VS_WIDTH, vsync_len) |
 843                       FIELD_PREP(HS_WIDTH, hsync_len);
 844
 845         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 846                 dp0_syncval |= SYNCVAL_VS_POL_ACTIVE_LOW;
 847
 848         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 849                 dp0_syncval |= SYNCVAL_HS_POL_ACTIVE_LOW;
 850
 851         ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval);
 852         if (ret)
 853                 return ret;
 854
 855         ret = regmap_write(tc->regmap, DPIPXLFMT,
 856                            VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
 857                            DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 |
 858                            DPI_BPP_RGB888);
 859         if (ret)
 860                 return ret;
 861
 862         ret = regmap_write(tc->regmap, DP0_MISC,
 863                            FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) |
 864                            FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) |
 865                            BPC_8);
 866         if (ret)
 867                 return ret;
 868
 869         return 0;
 870 }
 871
 872 static int tc_wait_link_training(struct tc_data *tc)
 873 {
 874         u32 value;
 875         int ret;
 876
 877         ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE,
 878                               LT_LOOPDONE, 500, 100000);
 879         if (ret) {
 880                 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n");
 881                 return ret;
 882         }
 883
 884         ret = regmap_read(tc->regmap, DP0_LTSTAT, &value);
 885         if (ret)
 886                 return ret;
 887
 888         return (value >> 8) & 0x7;
 889 }
 890
 891 static int tc_main_link_enable(struct tc_data *tc)
 892 {
 893         struct drm_dp_aux *aux = &tc->aux;
 894         struct device *dev = tc->dev;
 895         u32 dp_phy_ctrl;
 896         u32 value;
 897         int ret;
 898         u8 tmp[DP_LINK_STATUS_SIZE];
 899
 900         dev_dbg(tc->dev, "link enable\n");
 901
 902         ret = regmap_read(tc->regmap, DP0CTL, &value);
 903         if (ret)
 904                 return ret;
 905
 906         if (WARN_ON(value & DP_EN)) {
 907                 ret = regmap_write(tc->regmap, DP0CTL, 0);
 908                 if (ret)
 909                         return ret;
 910         }
 911
 912         ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc));
 913         if (ret)
 914                 return ret;
 915         /* SSCG and BW27 on DP1 must be set to the same as on DP0 */
 916         ret = regmap_write(tc->regmap, DP1_SRCCTRL,
 917                  (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
 918                  ((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
 919         if (ret)
 920                 return ret;
 921
 922         ret = tc_set_syspllparam(tc);
 923         if (ret)
 924                 return ret;
 925
 926         /* Setup Main Link */
 927         dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
 928         if (tc->link.num_lanes == 2)
 929                 dp_phy_ctrl |= PHY_2LANE;
 930
 931         ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
 932         if (ret)
 933                 return ret;
 934
 935         /* PLL setup */
 936         ret = tc_pllupdate(tc, DP0_PLLCTRL);
 937         if (ret)
 938                 return ret;
 939
 940         ret = tc_pllupdate(tc, DP1_PLLCTRL);
 941         if (ret)
 942                 return ret;
 943
 944         /* Reset/Enable Main Links */
 945         dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
 946         ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
 947         usleep_range(100, 200);
 948         dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
 949         ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
 950
 951         ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 500, 100000);
 952         if (ret) {
 953                 dev_err(dev, "timeout waiting for phy become ready");
 954                 return ret;
 955         }
 956
 957         /* Set misc: 8 bits per color */
 958         ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
 959         if (ret)
 960                 return ret;
 961
 962         /*
 963          * ASSR mode
 964          * on TC358767 side ASSR configured through strap pin
 965          * seems there is no way to change this setting from SW
 966          *
 967          * check is tc configured for same mode
 968          */
 969         if (tc->assr != tc->link.assr) {
 970                 dev_dbg(dev, "Trying to set display to ASSR: %d\n",
 971                         tc->assr);
 972                 /* try to set ASSR on display side */
 973                 tmp[0] = tc->assr;
 974                 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);
 975                 if (ret < 0)
 976                         goto err_dpcd_read;
 977                 /* read back */
 978                 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
 979                 if (ret < 0)
 980                         goto err_dpcd_read;
 981
 982                 if (tmp[0] != tc->assr) {
 983                         dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
 984                                 tc->assr);
 985                         /* trying with disabled scrambler */
 986                         tc->link.scrambler_dis = true;
 987                 }
 988         }
 989
 990         /* Setup Link & DPRx Config for Training */
 991         tmp[0] = drm_dp_link_rate_to_bw_code(tc->link.rate);
 992         tmp[1] = tc->link.num_lanes;
 993
 994         if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
 995                 tmp[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 996
 997         ret = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, tmp, 2);
 998         if (ret < 0)
 999                 goto err_dpcd_write;
1000
1001         /* DOWNSPREAD_CTRL */
1002         tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
1003         /* MAIN_LINK_CHANNEL_CODING_SET */
1004         tmp[1] =  DP_SET_ANSI_8B10B;
1005         ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
1006         if (ret < 0)
1007                 goto err_dpcd_write;
1008
1009         /* Reset voltage-swing & pre-emphasis */
1010         tmp[0] = tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 |
1011                           DP_TRAIN_PRE_EMPH_LEVEL_0;
1012         ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2);
1013         if (ret < 0)
1014                 goto err_dpcd_write;
1015
1016         /* Clock-Recovery */
1017
1018         /* Set DPCD 0x102 for Training Pattern 1 */
1019         ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1020                            DP_LINK_SCRAMBLING_DISABLE |
1021                            DP_TRAINING_PATTERN_1);
1022         if (ret)
1023                 return ret;
1024
1025         ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL,
1026                            (15 << 28) | /* Defer Iteration Count */
1027                            (15 << 24) | /* Loop Iteration Count */
1028                            (0xd << 0)); /* Loop Timer Delay */
1029         if (ret)
1030                 return ret;
1031
1032         ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1033                            tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1034                            DP0_SRCCTRL_AUTOCORRECT |
1035                            DP0_SRCCTRL_TP1);
1036         if (ret)
1037                 return ret;
1038
1039         /* Enable DP0 to start Link Training */
1040         ret = regmap_write(tc->regmap, DP0CTL,
1041                            (drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
1042                                 EF_EN : 0) | DP_EN);
1043         if (ret)
1044                 return ret;
1045
1046         /* wait */
1047
1048         ret = tc_wait_link_training(tc);
1049         if (ret < 0)
1050                 return ret;
1051
1052         if (ret) {
1053                 dev_err(tc->dev, "Link training phase 1 failed: %s\n",
1054                         training_pattern1_errors[ret]);
1055                 return -ENODEV;
1056         }
1057
1058         /* Channel Equalization */
1059
1060         /* Set DPCD 0x102 for Training Pattern 2 */
1061         ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1062                            DP_LINK_SCRAMBLING_DISABLE |
1063                            DP_TRAINING_PATTERN_2);
1064         if (ret)
1065                 return ret;
1066
1067         ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1068                            tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1069                            DP0_SRCCTRL_AUTOCORRECT |
1070                            DP0_SRCCTRL_TP2);
1071         if (ret)
1072                 return ret;
1073
1074         /* wait */
1075         ret = tc_wait_link_training(tc);
1076         if (ret < 0)
1077                 return ret;
1078
1079         if (ret) {
1080                 dev_err(tc->dev, "Link training phase 2 failed: %s\n",
1081                         training_pattern2_errors[ret]);
1082                 return -ENODEV;
1083         }
1084
1085         /*
1086          * Toshiba's documentation suggests to first clear DPCD 0x102, then
1087          * clear the training pattern bit in DP0_SRCCTRL. Testing shows
1088          * that the link sometimes drops if those steps are done in that order,
1089          * but if the steps are done in reverse order, the link stays up.
1090          *
1091          * So we do the steps differently than documented here.
1092          */
1093
1094         /* Clear Training Pattern, set AutoCorrect Mode = 1 */
1095         ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) |
1096                            DP0_SRCCTRL_AUTOCORRECT);
1097         if (ret)
1098                 return ret;
1099
1100         /* Clear DPCD 0x102 */
1101         /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
1102         tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
1103         ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]);
1104         if (ret < 0)
1105                 goto err_dpcd_write;
1106
1107         /* Check link status */
1108         ret = drm_dp_dpcd_read_link_status(aux, tmp);
1109         if (ret < 0)
1110                 goto err_dpcd_read;
1111
1112         ret = 0;
1113
1114         value = tmp[0] & DP_CHANNEL_EQ_BITS;
1115
1116         if (value != DP_CHANNEL_EQ_BITS) {
1117                 dev_err(tc->dev, "Lane 0 failed: %x\n", value);
1118                 ret = -ENODEV;
1119         }
1120
1121         if (tc->link.num_lanes == 2) {
1122                 value = (tmp[0] >> 4) & DP_CHANNEL_EQ_BITS;
1123
1124                 if (value != DP_CHANNEL_EQ_BITS) {
1125                         dev_err(tc->dev, "Lane 1 failed: %x\n", value);
1126                         ret = -ENODEV;
1127                 }
1128
1129                 if (!(tmp[2] & DP_INTERLANE_ALIGN_DONE)) {
1130                         dev_err(tc->dev, "Interlane align failed\n");
1131                         ret = -ENODEV;
1132                 }
1133         }
1134
1135         if (ret) {
1136                 dev_err(dev, "0x0202 LANE0_1_STATUS:            0x%02x\n", tmp[0]);
1137                 dev_err(dev, "0x0203 LANE2_3_STATUS             0x%02x\n", tmp[1]);
1138                 dev_err(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", tmp[2]);
1139                 dev_err(dev, "0x0205 SINK_STATUS:               0x%02x\n", tmp[3]);
1140                 dev_err(dev, "0x0206 ADJUST_REQUEST_LANE0_1:    0x%02x\n", tmp[4]);
1141                 dev_err(dev, "0x0207 ADJUST_REQUEST_LANE2_3:    0x%02x\n", tmp[5]);
1142                 return ret;
1143         }
1144
1145         return 0;
1146 err_dpcd_read:
1147         dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1148         return ret;
1149 err_dpcd_write:
1150         dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1151         return ret;
1152 }
1153
1154 static int tc_main_link_disable(struct tc_data *tc)
1155 {
1156         int ret;
1157
1158         dev_dbg(tc->dev, "link disable\n");
1159
1160         ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0);
1161         if (ret)
1162                 return ret;
1163
1164         return regmap_write(tc->regmap, DP0CTL, 0);
1165 }
1166
1167 static int tc_stream_enable(struct tc_data *tc)
1168 {
1169         int ret;
1170         u32 value;
1171
1172         dev_dbg(tc->dev, "enable video stream\n");
1173
1174         /* PXL PLL setup */
1175         if (tc_test_pattern) {
1176                 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
1177                                     1000 * tc->mode.clock);
1178                 if (ret)
1179                         return ret;
1180         }
1181
1182         ret = tc_set_video_mode(tc, &tc->mode);
1183         if (ret)
1184                 return ret;
1185
1186         /* Set M/N */
1187         ret = tc_stream_clock_calc(tc);
1188         if (ret)
1189                 return ret;
1190
1191         value = VID_MN_GEN | DP_EN;
1192         if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
1193                 value |= EF_EN;
1194         ret = regmap_write(tc->regmap, DP0CTL, value);
1195         if (ret)
1196                 return ret;
1197         /*
1198          * VID_EN assertion should be delayed by at least N * LSCLK
1199          * cycles from the time VID_MN_GEN is enabled in order to
1200          * generate stable values for VID_M. LSCLK is 270 MHz or
1201          * 162 MHz, VID_N is set to 32768 in  tc_stream_clock_calc(),
1202          * so a delay of at least 203 us should suffice.
1203          */
1204         usleep_range(500, 1000);
1205         value |= VID_EN;
1206         ret = regmap_write(tc->regmap, DP0CTL, value);
1207         if (ret)
1208                 return ret;
1209         /* Set input interface */
1210         value = DP0_AUDSRC_NO_INPUT;
1211         if (tc_test_pattern)
1212                 value |= DP0_VIDSRC_COLOR_BAR;
1213         else
1214                 value |= DP0_VIDSRC_DPI_RX;
1215         ret = regmap_write(tc->regmap, SYSCTRL, value);
1216         if (ret)
1217                 return ret;
1218
1219         return 0;
1220 }
1221
1222 static int tc_stream_disable(struct tc_data *tc)
1223 {
1224         int ret;
1225
1226         dev_dbg(tc->dev, "disable video stream\n");
1227
1228         ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0);
1229         if (ret)
1230                 return ret;
1231
1232         tc_pxl_pll_dis(tc);
1233
1234         return 0;
1235 }
1236
1237 static void tc_bridge_enable(struct drm_bridge *bridge)
1238 {
1239         struct tc_data *tc = bridge_to_tc(bridge);
1240         int ret;
1241
1242         ret = tc_get_display_props(tc);
1243         if (ret < 0) {
1244                 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1245                 return;
1246         }
1247
1248         ret = tc_main_link_enable(tc);
1249         if (ret < 0) {
1250                 dev_err(tc->dev, "main link enable error: %d\n", ret);
1251                 return;
1252         }
1253
1254         ret = tc_stream_enable(tc);
1255         if (ret < 0) {
1256                 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1257                 tc_main_link_disable(tc);
1258                 return;
1259         }
1260 }
1261
1262 static void tc_bridge_disable(struct drm_bridge *bridge)
1263 {
1264         struct tc_data *tc = bridge_to_tc(bridge);
1265         int ret;
1266
1267         ret = tc_stream_disable(tc);
1268         if (ret < 0)
1269                 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1270
1271         ret = tc_main_link_disable(tc);
1272         if (ret < 0)
1273                 dev_err(tc->dev, "main link disable error: %d\n", ret);
1274 }
1275
1276 static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
1277                                  const struct drm_display_mode *mode,
1278                                  struct drm_display_mode *adj)
1279 {
1280         /* Fixup sync polarities, both hsync and vsync are active low */
1281         adj->flags = mode->flags;
1282         adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1283         adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1284
1285         return true;
1286 }
1287
1288 static enum drm_mode_status tc_mode_valid(struct drm_bridge *bridge,
1289                                           const struct drm_display_info *info,
1290                                           const struct drm_display_mode *mode)
1291 {
1292         struct tc_data *tc = bridge_to_tc(bridge);
1293         u32 req, avail;
1294         u32 bits_per_pixel = 24;
1295
1296         /* DPI interface clock limitation: upto 154 MHz */
1297         if (mode->clock > 154000)
1298                 return MODE_CLOCK_HIGH;
1299
1300         req = mode->clock * bits_per_pixel / 8;
1301         avail = tc->link.num_lanes * tc->link.rate;
1302
1303         if (req > avail)
1304                 return MODE_BAD;
1305
1306         return MODE_OK;
1307 }
1308
1309 static void tc_bridge_mode_set(struct drm_bridge *bridge,
1310                                const struct drm_display_mode *mode,
1311                                const struct drm_display_mode *adj)
1312 {
1313         struct tc_data *tc = bridge_to_tc(bridge);
1314
1315         tc->mode = *mode;
1316 }
1317
1318 static struct edid *tc_get_edid(struct drm_bridge *bridge,
1319                                 struct drm_connector *connector)
1320 {
1321         struct tc_data *tc = bridge_to_tc(bridge);
1322
1323         return drm_get_edid(connector, &tc->aux.ddc);
1324 }
1325
1326 static int tc_connector_get_modes(struct drm_connector *connector)
1327 {
1328         struct tc_data *tc = connector_to_tc(connector);
1329         int num_modes;
1330         struct edid *edid;
1331         int ret;
1332
1333         ret = tc_get_display_props(tc);
1334         if (ret < 0) {
1335                 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1336                 return 0;
1337         }
1338
1339         if (tc->panel_bridge) {
1340                 num_modes = drm_bridge_get_modes(tc->panel_bridge, connector);
1341                 if (num_modes > 0)
1342                         return num_modes;
1343         }
1344
1345         edid = tc_get_edid(&tc->bridge, connector);
1346         num_modes = drm_add_edid_modes(connector, edid);
1347         kfree(edid);
1348
1349         return num_modes;
1350 }
1351
1352 static const struct drm_connector_helper_funcs tc_connector_helper_funcs = {
1353         .get_modes = tc_connector_get_modes,
1354 };
1355
1356 static enum drm_connector_status tc_bridge_detect(struct drm_bridge *bridge)
1357 {
1358         struct tc_data *tc = bridge_to_tc(bridge);
1359         bool conn;
1360         u32 val;
1361         int ret;
1362
1363         ret = regmap_read(tc->regmap, GPIOI, &val);
1364         if (ret)
1365                 return connector_status_unknown;
1366
1367         conn = val & BIT(tc->hpd_pin);
1368
1369         if (conn)
1370                 return connector_status_connected;
1371         else
1372                 return connector_status_disconnected;
1373 }
1374
1375 static enum drm_connector_status
1376 tc_connector_detect(struct drm_connector *connector, bool force)
1377 {
1378         struct tc_data *tc = connector_to_tc(connector);
1379
1380         if (tc->hpd_pin >= 0)
1381                 return tc_bridge_detect(&tc->bridge);
1382
1383         if (tc->panel_bridge)
1384                 return connector_status_connected;
1385         else
1386                 return connector_status_unknown;
1387 }
1388
1389 static const struct drm_connector_funcs tc_connector_funcs = {
1390         .detect = tc_connector_detect,
1391         .fill_modes = drm_helper_probe_single_connector_modes,
1392         .destroy = drm_connector_cleanup,
1393         .reset = drm_atomic_helper_connector_reset,
1394         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1395         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1396 };
1397
1398 static int tc_bridge_attach(struct drm_bridge *bridge,
1399                             enum drm_bridge_attach_flags flags)
1400 {
1401         u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1402         struct tc_data *tc = bridge_to_tc(bridge);
1403         struct drm_device *drm = bridge->dev;
1404         int ret;
1405
1406         if (tc->panel_bridge) {
1407                 /* If a connector is required then this driver shall create it */
1408                 ret = drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge,
1409                                         &tc->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
1410                 if (ret)
1411                         return ret;
1412         }
1413
1414         if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
1415                 return 0;
1416
1417         /* Create DP/eDP connector */
1418         drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1419         ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, tc->bridge.type);
1420         if (ret)
1421                 return ret;
1422
1423         /* Don't poll if don't have HPD connected */
1424         if (tc->hpd_pin >= 0) {
1425                 if (tc->have_irq)
1426                         tc->connector.polled = DRM_CONNECTOR_POLL_HPD;
1427                 else
1428                         tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
1429                                                DRM_CONNECTOR_POLL_DISCONNECT;
1430         }
1431
1432         drm_display_info_set_bus_formats(&tc->connector.display_info,
1433                                          &bus_format, 1);
1434         tc->connector.display_info.bus_flags =
1435                 DRM_BUS_FLAG_DE_HIGH |
1436                 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE |
1437                 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE;
1438         drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1439
1440         return 0;
1441 }
1442
1443 static const struct drm_bridge_funcs tc_bridge_funcs = {
1444         .attach = tc_bridge_attach,
1445         .mode_valid = tc_mode_valid,
1446         .mode_set = tc_bridge_mode_set,
1447         .enable = tc_bridge_enable,
1448         .disable = tc_bridge_disable,
1449         .mode_fixup = tc_bridge_mode_fixup,
1450         .detect = tc_bridge_detect,
1451         .get_edid = tc_get_edid,
1452 };
1453
1454 static bool tc_readable_reg(struct device *dev, unsigned int reg)
1455 {
1456         return reg != SYSCTRL;
1457 }
1458
1459 static const struct regmap_range tc_volatile_ranges[] = {
1460         regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS),
1461         regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ),
1462         regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL),
1463         regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),
1464         regmap_reg_range(VFUEN0, VFUEN0),
1465         regmap_reg_range(INTSTS_G, INTSTS_G),
1466         regmap_reg_range(GPIOI, GPIOI),
1467 };
1468
1469 static const struct regmap_access_table tc_volatile_table = {
1470         .yes_ranges = tc_volatile_ranges,
1471         .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges),
1472 };
1473
1474 static bool tc_writeable_reg(struct device *dev, unsigned int reg)
1475 {
1476         return (reg != TC_IDREG) &&
1477                (reg != DP0_LTSTAT) &&
1478                (reg != DP0_SNKLTCHGREQ);
1479 }
1480
1481 static const struct regmap_config tc_regmap_config = {
1482         .name = "tc358767",
1483         .reg_bits = 16,
1484         .val_bits = 32,
1485         .reg_stride = 4,
1486         .max_register = PLL_DBG,
1487         .cache_type = REGCACHE_RBTREE,
1488         .readable_reg = tc_readable_reg,
1489         .volatile_table = &tc_volatile_table,
1490         .writeable_reg = tc_writeable_reg,
1491         .reg_format_endian = REGMAP_ENDIAN_BIG,
1492         .val_format_endian = REGMAP_ENDIAN_LITTLE,
1493 };
1494
1495 static irqreturn_t tc_irq_handler(int irq, void *arg)
1496 {
1497         struct tc_data *tc = arg;
1498         u32 val;
1499         int r;
1500
1501         r = regmap_read(tc->regmap, INTSTS_G, &val);
1502         if (r)
1503                 return IRQ_NONE;
1504
1505         if (!val)
1506                 return IRQ_NONE;
1507
1508         if (val & INT_SYSERR) {
1509                 u32 stat = 0;
1510
1511                 regmap_read(tc->regmap, SYSSTAT, &stat);
1512
1513                 dev_err(tc->dev, "syserr %x\n", stat);
1514         }
1515
1516         if (tc->hpd_pin >= 0 && tc->bridge.dev) {
1517                 /*
1518                  * H is triggered when the GPIO goes high.
1519                  *
1520                  * LC is triggered when the GPIO goes low and stays low for
1521                  * the duration of LCNT
1522                  */
1523                 bool h = val & INT_GPIO_H(tc->hpd_pin);
1524                 bool lc = val & INT_GPIO_LC(tc->hpd_pin);
1525
1526                 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin,
1527                         h ? "H" : "", lc ? "LC" : "");
1528
1529                 if (h || lc)
1530                         drm_kms_helper_hotplug_event(tc->bridge.dev);
1531         }
1532
1533         regmap_write(tc->regmap, INTSTS_G, val);
1534
1535         return IRQ_HANDLED;
1536 }
1537
1538 static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
1539 {
1540         struct device *dev = &client->dev;
1541         struct drm_panel *panel;
1542         struct tc_data *tc;
1543         int ret;
1544
1545         tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
1546         if (!tc)
1547                 return -ENOMEM;
1548
1549         tc->dev = dev;
1550
1551         /* port@2 is the output port */
1552         ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, NULL);
1553         if (ret && ret != -ENODEV)
1554                 return ret;
1555
1556         if (panel) {
1557                 struct drm_bridge *panel_bridge;
1558
1559                 panel_bridge = devm_drm_panel_bridge_add(dev, panel);
1560                 if (IS_ERR(panel_bridge))
1561                         return PTR_ERR(panel_bridge);
1562
1563                 tc->panel_bridge = panel_bridge;
1564                 tc->bridge.type = DRM_MODE_CONNECTOR_eDP;
1565         } else {
1566                 tc->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
1567         }
1568
1569         /* Shut down GPIO is optional */
1570         tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
1571         if (IS_ERR(tc->sd_gpio))
1572                 return PTR_ERR(tc->sd_gpio);
1573
1574         if (tc->sd_gpio) {
1575                 gpiod_set_value_cansleep(tc->sd_gpio, 0);
1576                 usleep_range(5000, 10000);
1577         }
1578
1579         /* Reset GPIO is optional */
1580         tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1581         if (IS_ERR(tc->reset_gpio))
1582                 return PTR_ERR(tc->reset_gpio);
1583
1584         if (tc->reset_gpio) {
1585                 gpiod_set_value_cansleep(tc->reset_gpio, 1);
1586                 usleep_range(5000, 10000);
1587         }
1588
1589         tc->refclk = devm_clk_get(dev, "ref");
1590         if (IS_ERR(tc->refclk)) {
1591                 ret = PTR_ERR(tc->refclk);
1592                 dev_err(dev, "Failed to get refclk: %d\n", ret);
1593                 return ret;
1594         }
1595
1596         tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
1597         if (IS_ERR(tc->regmap)) {
1598                 ret = PTR_ERR(tc->regmap);
1599                 dev_err(dev, "Failed to initialize regmap: %d\n", ret);
1600                 return ret;
1601         }
1602
1603         ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin",
1604                                    &tc->hpd_pin);
1605         if (ret) {
1606                 tc->hpd_pin = -ENODEV;
1607         } else {
1608                 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) {
1609                         dev_err(dev, "failed to parse HPD number\n");
1610                         return ret;
1611                 }
1612         }
1613
1614         if (client->irq > 0) {
1615                 /* enable SysErr */
1616                 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR);
1617
1618                 ret = devm_request_threaded_irq(dev, client->irq,
1619                                                 NULL, tc_irq_handler,
1620                                                 IRQF_ONESHOT,
1621                                                 "tc358767-irq", tc);
1622                 if (ret) {
1623                         dev_err(dev, "failed to register dp interrupt\n");
1624                         return ret;
1625                 }
1626
1627                 tc->have_irq = true;
1628         }
1629
1630         ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
1631         if (ret) {
1632                 dev_err(tc->dev, "can not read device ID: %d\n", ret);
1633                 return ret;
1634         }
1635
1636         if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
1637                 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
1638                 return -EINVAL;
1639         }
1640
1641         tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
1642
1643         if (!tc->reset_gpio) {
1644                 /*
1645                  * If the reset pin isn't present, do a software reset. It isn't
1646                  * as thorough as the hardware reset, as we can't reset the I2C
1647                  * communication block for obvious reasons, but it's getting the
1648                  * chip into a defined state.
1649                  */
1650                 regmap_update_bits(tc->regmap, SYSRSTENB,
1651                                 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
1652                                 0);
1653                 regmap_update_bits(tc->regmap, SYSRSTENB,
1654                                 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
1655                                 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP);
1656                 usleep_range(5000, 10000);
1657         }
1658
1659         if (tc->hpd_pin >= 0) {
1660                 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT;
1661                 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin);
1662
1663                 /* Set LCNT to 2ms */
1664                 regmap_write(tc->regmap, lcnt_reg,
1665                              clk_get_rate(tc->refclk) * 2 / 1000);
1666                 /* We need the "alternate" mode for HPD */
1667                 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin));
1668
1669                 if (tc->have_irq) {
1670                         /* enable H & LC */
1671                         regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc);
1672                 }
1673         }
1674
1675         ret = tc_aux_link_setup(tc);
1676         if (ret)
1677                 return ret;
1678
1679         /* Register DP AUX channel */
1680         tc->aux.name = "TC358767 AUX i2c adapter";
1681         tc->aux.dev = tc->dev;
1682         tc->aux.transfer = tc_aux_transfer;
1683         ret = drm_dp_aux_register(&tc->aux);
1684         if (ret)
1685                 return ret;
1686
1687         tc->bridge.funcs = &tc_bridge_funcs;
1688         if (tc->hpd_pin >= 0)
1689                 tc->bridge.ops |= DRM_BRIDGE_OP_DETECT;
1690         tc->bridge.ops |= DRM_BRIDGE_OP_EDID;
1691
1692         tc->bridge.of_node = dev->of_node;
1693         drm_bridge_add(&tc->bridge);
1694
1695         i2c_set_clientdata(client, tc);
1696
1697         return 0;
1698 }
1699
1700 static int tc_remove(struct i2c_client *client)
1701 {
1702         struct tc_data *tc = i2c_get_clientdata(client);
1703
1704         drm_bridge_remove(&tc->bridge);
1705         drm_dp_aux_unregister(&tc->aux);
1706
1707         return 0;
1708 }
1709
1710 static const struct i2c_device_id tc358767_i2c_ids[] = {
1711         { "tc358767", 0 },
1712         { }
1713 };
1714 MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids);
1715
1716 static const struct of_device_id tc358767_of_ids[] = {
1717         { .compatible = "toshiba,tc358767", },
1718         { }
1719 };
1720 MODULE_DEVICE_TABLE(of, tc358767_of_ids);
1721
1722 static struct i2c_driver tc358767_driver = {
1723         .driver = {
1724                 .name = "tc358767",
1725                 .of_match_table = tc358767_of_ids,
1726         },
1727         .id_table = tc358767_i2c_ids,
1728         .probe = tc_probe,
1729         .remove = tc_remove,
1730 };
1731 module_i2c_driver(tc358767_driver);
1732
1733 MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>");
1734 MODULE_DESCRIPTION("tc358767 eDP encoder driver");
1735 MODULE_LICENSE("GPL");