drivers/gpu/drm/bridge/synopsys/dw-hdmi.c

   1 /*
   2  * DesignWare High-Definition Multimedia Interface (HDMI) driver
   3  *
   4  * Copyright (C) 2013-2015 Mentor Graphics Inc.
   5  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   6  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  */
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/hdmi.h>
  18 #include <linux/irq.h>
  19 #include <linux/module.h>
  20 #include <linux/mutex.h>
  21 #include <linux/of_device.h>
  22 #include <linux/pinctrl/consumer.h>
  23 #include <linux/regmap.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/spinlock.h>
  26
  27 #include <media/cec-notifier.h>
  28
  29 #include <uapi/linux/media-bus-format.h>
  30 #include <uapi/linux/videodev2.h>
  31
  32 #include <drm/bridge/dw_hdmi.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drm_encoder_slave.h>
  36 #include <drm/drm_of.h>
  37 #include <drm/drm_print.h>
  38 #include <drm/drm_probe_helper.h>
  39 #include <drm/drm_scdc_helper.h>
  40
  41 #include "dw-hdmi-audio.h"
  42 #include "dw-hdmi-cec.h"
  43 #include "dw-hdmi.h"
  44
  45 #define DDC_SEGMENT_ADDR        0x30
  46
  47 #define HDMI_EDID_LEN           512
  48
  49 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
  50 #define SCDC_MIN_SOURCE_VERSION 0x1
  51
  52 #define HDMI14_MAX_TMDSCLK      340000000
  53
  54 enum hdmi_datamap {
  55         RGB444_8B = 0x01,
  56         RGB444_10B = 0x03,
  57         RGB444_12B = 0x05,
  58         RGB444_16B = 0x07,
  59         YCbCr444_8B = 0x09,
  60         YCbCr444_10B = 0x0B,
  61         YCbCr444_12B = 0x0D,
  62         YCbCr444_16B = 0x0F,
  63         YCbCr422_8B = 0x16,
  64         YCbCr422_10B = 0x14,
  65         YCbCr422_12B = 0x12,
  66 };
  67
  68 static const u16 csc_coeff_default[3][4] = {
  69         { 0x2000, 0x0000, 0x0000, 0x0000 },
  70         { 0x0000, 0x2000, 0x0000, 0x0000 },
  71         { 0x0000, 0x0000, 0x2000, 0x0000 }
  72 };
  73
  74 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
  75         { 0x2000, 0x6926, 0x74fd, 0x010e },
  76         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
  77         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
  78 };
  79
  80 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
  81         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
  82         { 0x2000, 0x3264, 0x0000, 0x7e6d },
  83         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
  84 };
  85
  86 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
  87         { 0x2591, 0x1322, 0x074b, 0x0000 },
  88         { 0x6535, 0x2000, 0x7acc, 0x0200 },
  89         { 0x6acd, 0x7534, 0x2000, 0x0200 }
  90 };
  91
  92 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
  93         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
  94         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
  95         { 0x6756, 0x78ab, 0x2000, 0x0200 }
  96 };
  97
  98 struct hdmi_vmode {
  99         bool mdataenablepolarity;
 100
 101         unsigned int mpixelclock;
 102         unsigned int mpixelrepetitioninput;
 103         unsigned int mpixelrepetitionoutput;
 104         unsigned int mtmdsclock;
 105 };
 106
 107 struct hdmi_data_info {
 108         unsigned int enc_in_bus_format;
 109         unsigned int enc_out_bus_format;
 110         unsigned int enc_in_encoding;
 111         unsigned int enc_out_encoding;
 112         unsigned int pix_repet_factor;
 113         unsigned int hdcp_enable;
 114         struct hdmi_vmode video_mode;
 115 };
 116
 117 struct dw_hdmi_i2c {
 118         struct i2c_adapter      adap;
 119
 120         struct mutex            lock;   /* used to serialize data transfers */
 121         struct completion       cmp;
 122         u8                      stat;
 123
 124         u8                      slave_reg;
 125         bool                    is_regaddr;
 126         bool                    is_segment;
 127 };
 128
 129 struct dw_hdmi_phy_data {
 130         enum dw_hdmi_phy_type type;
 131         const char *name;
 132         unsigned int gen;
 133         bool has_svsret;
 134         int (*configure)(struct dw_hdmi *hdmi,
 135                          const struct dw_hdmi_plat_data *pdata,
 136                          unsigned long mpixelclock);
 137 };
 138
 139 struct dw_hdmi {
 140         struct drm_connector connector;
 141         struct drm_bridge bridge;
 142
 143         unsigned int version;
 144
 145         struct platform_device *audio;
 146         struct platform_device *cec;
 147         struct device *dev;
 148         struct clk *isfr_clk;
 149         struct clk *iahb_clk;
 150         struct clk *cec_clk;
 151         struct dw_hdmi_i2c *i2c;
 152
 153         struct hdmi_data_info hdmi_data;
 154         const struct dw_hdmi_plat_data *plat_data;
 155
 156         int vic;
 157
 158         u8 edid[HDMI_EDID_LEN];
 159
 160         struct {
 161                 const struct dw_hdmi_phy_ops *ops;
 162                 const char *name;
 163                 void *data;
 164                 bool enabled;
 165         } phy;
 166
 167         struct drm_display_mode previous_mode;
 168
 169         struct i2c_adapter *ddc;
 170         void __iomem *regs;
 171         bool sink_is_hdmi;
 172         bool sink_has_audio;
 173
 174         struct pinctrl *pinctrl;
 175         struct pinctrl_state *default_state;
 176         struct pinctrl_state *unwedge_state;
 177
 178         struct mutex mutex;             /* for state below and previous_mode */
 179         enum drm_connector_force force; /* mutex-protected force state */
 180         bool disabled;                  /* DRM has disabled our bridge */
 181         bool bridge_is_on;              /* indicates the bridge is on */
 182         bool rxsense;                   /* rxsense state */
 183         u8 phy_mask;                    /* desired phy int mask settings */
 184         u8 mc_clkdis;                   /* clock disable register */
 185
 186         spinlock_t audio_lock;
 187         struct mutex audio_mutex;
 188         unsigned int sample_rate;
 189         unsigned int audio_cts;
 190         unsigned int audio_n;
 191         bool audio_enable;
 192
 193         unsigned int reg_shift;
 194         struct regmap *regm;
 195         void (*enable_audio)(struct dw_hdmi *hdmi);
 196         void (*disable_audio)(struct dw_hdmi *hdmi);
 197
 198         struct cec_notifier *cec_notifier;
 199 };
 200
 201 #define HDMI_IH_PHY_STAT0_RX_SENSE \
 202         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
 203          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
 204
 205 #define HDMI_PHY_RX_SENSE \
 206         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
 207          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
 208
 209 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 210 {
 211         regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
 212 }
 213
 214 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 215 {
 216         unsigned int val = 0;
 217
 218         regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
 219
 220         return val;
 221 }
 222
 223 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 224 {
 225         regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
 226 }
 227
 228 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 229                              u8 shift, u8 mask)
 230 {
 231         hdmi_modb(hdmi, data << shift, mask, reg);
 232 }
 233
 234 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
 235 {
 236         /* Software reset */
 237         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
 238
 239         /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
 240         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
 241
 242         /* Set done, not acknowledged and arbitration interrupt polarities */
 243         hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
 244         hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
 245                     HDMI_I2CM_CTLINT);
 246
 247         /* Clear DONE and ERROR interrupts */
 248         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 249                     HDMI_IH_I2CM_STAT0);
 250
 251         /* Mute DONE and ERROR interrupts */
 252         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 253                     HDMI_IH_MUTE_I2CM_STAT0);
 254 }
 255
 256 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi)
 257 {
 258         /* If no unwedge state then give up */
 259         if (IS_ERR(hdmi->unwedge_state))
 260                 return false;
 261
 262         dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n");
 263
 264         /*
 265          * This is a huge hack to workaround a problem where the dw_hdmi i2c
 266          * bus could sometimes get wedged.  Once wedged there doesn't appear
 267          * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ)
 268          * other than pulsing the SDA line.
 269          *
 270          * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi)
 271          * by:
 272          * 1. Remux the pin as a GPIO output, driven low.
 273          * 2. Wait a little while.  1 ms seems to work, but we'll do 10.
 274          * 3. Immediately jump to remux the pin as dw_hdmi i2c again.
 275          *
 276          * At the moment of remuxing, the line will still be low due to its
 277          * recent stint as an output, but then it will be pulled high by the
 278          * (presumed) external pullup.  dw_hdmi seems to see this as a rising
 279          * edge and that seems to get it out of its jam.
 280          *
 281          * This wedging was only ever seen on one TV, and only on one of
 282          * its HDMI ports.  It happened when the TV was powered on while the
 283          * device was plugged in.  A scope trace shows the TV bringing both SDA
 284          * and SCL low, then bringing them both back up at roughly the same
 285          * time.  Presumably this confuses dw_hdmi because it saw activity but
 286          * no real STOP (maybe it thinks there's another master on the bus?).
 287          * Giving it a clean rising edge of SDA while SCL is already high
 288          * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out
 289          * of its stupor.
 290          *
 291          * Note that after coming back alive, transfers seem to immediately
 292          * resume, so if we unwedge due to a timeout we should wait a little
 293          * longer for our transfer to finish, since it might have just started
 294          * now.
 295          */
 296         pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state);
 297         msleep(10);
 298         pinctrl_select_state(hdmi->pinctrl, hdmi->default_state);
 299
 300         return true;
 301 }
 302
 303 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi)
 304 {
 305         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 306         int stat;
 307
 308         stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 309         if (!stat) {
 310                 /* If we can't unwedge, return timeout */
 311                 if (!dw_hdmi_i2c_unwedge(hdmi))
 312                         return -EAGAIN;
 313
 314                 /* We tried to unwedge; give it another chance */
 315                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 316                 if (!stat)
 317                         return -EAGAIN;
 318         }
 319
 320         /* Check for error condition on the bus */
 321         if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 322                 return -EIO;
 323
 324         return 0;
 325 }
 326
 327 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
 328                             unsigned char *buf, unsigned int length)
 329 {
 330         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 331         int ret;
 332
 333         if (!i2c->is_regaddr) {
 334                 dev_dbg(hdmi->dev, "set read register address to 0\n");
 335                 i2c->slave_reg = 0x00;
 336                 i2c->is_regaddr = true;
 337         }
 338
 339         while (length--) {
 340                 reinit_completion(&i2c->cmp);
 341
 342                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 343                 if (i2c->is_segment)
 344                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
 345                                     HDMI_I2CM_OPERATION);
 346                 else
 347                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
 348                                     HDMI_I2CM_OPERATION);
 349
 350                 ret = dw_hdmi_i2c_wait(hdmi);
 351                 if (ret)
 352                         return ret;
 353
 354                 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
 355         }
 356         i2c->is_segment = false;
 357
 358         return 0;
 359 }
 360
 361 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
 362                              unsigned char *buf, unsigned int length)
 363 {
 364         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 365         int ret;
 366
 367         if (!i2c->is_regaddr) {
 368                 /* Use the first write byte as register address */
 369                 i2c->slave_reg = buf[0];
 370                 length--;
 371                 buf++;
 372                 i2c->is_regaddr = true;
 373         }
 374
 375         while (length--) {
 376                 reinit_completion(&i2c->cmp);
 377
 378                 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
 379                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 380                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
 381                             HDMI_I2CM_OPERATION);
 382
 383                 ret = dw_hdmi_i2c_wait(hdmi);
 384                 if (ret)
 385                         return ret;
 386         }
 387
 388         return 0;
 389 }
 390
 391 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
 392                             struct i2c_msg *msgs, int num)
 393 {
 394         struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
 395         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 396         u8 addr = msgs[0].addr;
 397         int i, ret = 0;
 398
 399         dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
 400
 401         for (i = 0; i < num; i++) {
 402                 if (msgs[i].len == 0) {
 403                         dev_dbg(hdmi->dev,
 404                                 "unsupported transfer %d/%d, no data\n",
 405                                 i + 1, num);
 406                         return -EOPNOTSUPP;
 407                 }
 408         }
 409
 410         mutex_lock(&i2c->lock);
 411
 412         /* Unmute DONE and ERROR interrupts */
 413         hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
 414
 415         /* Set slave device address taken from the first I2C message */
 416         hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
 417
 418         /* Set slave device register address on transfer */
 419         i2c->is_regaddr = false;
 420
 421         /* Set segment pointer for I2C extended read mode operation */
 422         i2c->is_segment = false;
 423
 424         for (i = 0; i < num; i++) {
 425                 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
 426                         i + 1, num, msgs[i].len, msgs[i].flags);
 427                 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
 428                         i2c->is_segment = true;
 429                         hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
 430                         hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
 431                 } else {
 432                         if (msgs[i].flags & I2C_M_RD)
 433                                 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
 434                                                        msgs[i].len);
 435                         else
 436                                 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
 437                                                         msgs[i].len);
 438                 }
 439                 if (ret < 0)
 440                         break;
 441         }
 442
 443         if (!ret)
 444                 ret = num;
 445
 446         /* Mute DONE and ERROR interrupts */
 447         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 448                     HDMI_IH_MUTE_I2CM_STAT0);
 449
 450         mutex_unlock(&i2c->lock);
 451
 452         return ret;
 453 }
 454
 455 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
 456 {
 457         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 458 }
 459
 460 static const struct i2c_algorithm dw_hdmi_algorithm = {
 461         .master_xfer    = dw_hdmi_i2c_xfer,
 462         .functionality  = dw_hdmi_i2c_func,
 463 };
 464
 465 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
 466 {
 467         struct i2c_adapter *adap;
 468         struct dw_hdmi_i2c *i2c;
 469         int ret;
 470
 471         i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
 472         if (!i2c)
 473                 return ERR_PTR(-ENOMEM);
 474
 475         mutex_init(&i2c->lock);
 476         init_completion(&i2c->cmp);
 477
 478         adap = &i2c->adap;
 479         adap->class = I2C_CLASS_DDC;
 480         adap->owner = THIS_MODULE;
 481         adap->dev.parent = hdmi->dev;
 482         adap->algo = &dw_hdmi_algorithm;
 483         strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
 484         i2c_set_adapdata(adap, hdmi);
 485
 486         ret = i2c_add_adapter(adap);
 487         if (ret) {
 488                 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
 489                 devm_kfree(hdmi->dev, i2c);
 490                 return ERR_PTR(ret);
 491         }
 492
 493         hdmi->i2c = i2c;
 494
 495         dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
 496
 497         return adap;
 498 }
 499
 500 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 501                            unsigned int n)
 502 {
 503         /* Must be set/cleared first */
 504         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 505
 506         /* nshift factor = 0 */
 507         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 508
 509         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 510                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 511         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 512         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 513
 514         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 515         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 516         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 517 }
 518
 519 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
 520 {
 521         unsigned int n = (128 * freq) / 1000;
 522         unsigned int mult = 1;
 523
 524         while (freq > 48000) {
 525                 mult *= 2;
 526                 freq /= 2;
 527         }
 528
 529         switch (freq) {
 530         case 32000:
 531                 if (pixel_clk == 25175000)
 532                         n = 4576;
 533                 else if (pixel_clk == 27027000)
 534                         n = 4096;
 535                 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
 536                         n = 11648;
 537                 else
 538                         n = 4096;
 539                 n *= mult;
 540                 break;
 541
 542         case 44100:
 543                 if (pixel_clk == 25175000)
 544                         n = 7007;
 545                 else if (pixel_clk == 74176000)
 546                         n = 17836;
 547                 else if (pixel_clk == 148352000)
 548                         n = 8918;
 549                 else
 550                         n = 6272;
 551                 n *= mult;
 552                 break;
 553
 554         case 48000:
 555                 if (pixel_clk == 25175000)
 556                         n = 6864;
 557                 else if (pixel_clk == 27027000)
 558                         n = 6144;
 559                 else if (pixel_clk == 74176000)
 560                         n = 11648;
 561                 else if (pixel_clk == 148352000)
 562                         n = 5824;
 563                 else
 564                         n = 6144;
 565                 n *= mult;
 566                 break;
 567
 568         default:
 569                 break;
 570         }
 571
 572         return n;
 573 }
 574
 575 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 576         unsigned long pixel_clk, unsigned int sample_rate)
 577 {
 578         unsigned long ftdms = pixel_clk;
 579         unsigned int n, cts;
 580         u64 tmp;
 581
 582         n = hdmi_compute_n(sample_rate, pixel_clk);
 583
 584         /*
 585          * Compute the CTS value from the N value.  Note that CTS and N
 586          * can be up to 20 bits in total, so we need 64-bit math.  Also
 587          * note that our TDMS clock is not fully accurate; it is accurate
 588          * to kHz.  This can introduce an unnecessary remainder in the
 589          * calculation below, so we don't try to warn about that.
 590          */
 591         tmp = (u64)ftdms * n;
 592         do_div(tmp, 128 * sample_rate);
 593         cts = tmp;
 594
 595         dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
 596                 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
 597                 n, cts);
 598
 599         spin_lock_irq(&hdmi->audio_lock);
 600         hdmi->audio_n = n;
 601         hdmi->audio_cts = cts;
 602         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
 603         spin_unlock_irq(&hdmi->audio_lock);
 604 }
 605
 606 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 607 {
 608         mutex_lock(&hdmi->audio_mutex);
 609         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
 610         mutex_unlock(&hdmi->audio_mutex);
 611 }
 612
 613 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 614 {
 615         mutex_lock(&hdmi->audio_mutex);
 616         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
 617                                  hdmi->sample_rate);
 618         mutex_unlock(&hdmi->audio_mutex);
 619 }
 620
 621 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 622 {
 623         mutex_lock(&hdmi->audio_mutex);
 624         hdmi->sample_rate = rate;
 625         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
 626                                  hdmi->sample_rate);
 627         mutex_unlock(&hdmi->audio_mutex);
 628 }
 629 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
 630
 631 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
 632 {
 633         if (enable)
 634                 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
 635         else
 636                 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
 637         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
 638 }
 639
 640 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
 641 {
 642         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 643 }
 644
 645 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
 646 {
 647         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
 648 }
 649
 650 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
 651 {
 652         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 653         hdmi_enable_audio_clk(hdmi, true);
 654 }
 655
 656 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
 657 {
 658         hdmi_enable_audio_clk(hdmi, false);
 659 }
 660
 661 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
 662 {
 663         unsigned long flags;
 664
 665         spin_lock_irqsave(&hdmi->audio_lock, flags);
 666         hdmi->audio_enable = true;
 667         if (hdmi->enable_audio)
 668                 hdmi->enable_audio(hdmi);
 669         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 670 }
 671 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
 672
 673 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 674 {
 675         unsigned long flags;
 676
 677         spin_lock_irqsave(&hdmi->audio_lock, flags);
 678         hdmi->audio_enable = false;
 679         if (hdmi->disable_audio)
 680                 hdmi->disable_audio(hdmi);
 681         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 682 }
 683 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 684
 685 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
 686 {
 687         switch (bus_format) {
 688         case MEDIA_BUS_FMT_RGB888_1X24:
 689         case MEDIA_BUS_FMT_RGB101010_1X30:
 690         case MEDIA_BUS_FMT_RGB121212_1X36:
 691         case MEDIA_BUS_FMT_RGB161616_1X48:
 692                 return true;
 693
 694         default:
 695                 return false;
 696         }
 697 }
 698
 699 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
 700 {
 701         switch (bus_format) {
 702         case MEDIA_BUS_FMT_YUV8_1X24:
 703         case MEDIA_BUS_FMT_YUV10_1X30:
 704         case MEDIA_BUS_FMT_YUV12_1X36:
 705         case MEDIA_BUS_FMT_YUV16_1X48:
 706                 return true;
 707
 708         default:
 709                 return false;
 710         }
 711 }
 712
 713 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
 714 {
 715         switch (bus_format) {
 716         case MEDIA_BUS_FMT_UYVY8_1X16:
 717         case MEDIA_BUS_FMT_UYVY10_1X20:
 718         case MEDIA_BUS_FMT_UYVY12_1X24:
 719                 return true;
 720
 721         default:
 722                 return false;
 723         }
 724 }
 725
 726 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
 727 {
 728         switch (bus_format) {
 729         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 730         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 731         case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
 732         case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
 733                 return true;
 734
 735         default:
 736                 return false;
 737         }
 738 }
 739
 740 static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
 741 {
 742         switch (bus_format) {
 743         case MEDIA_BUS_FMT_RGB888_1X24:
 744         case MEDIA_BUS_FMT_YUV8_1X24:
 745         case MEDIA_BUS_FMT_UYVY8_1X16:
 746         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 747                 return 8;
 748
 749         case MEDIA_BUS_FMT_RGB101010_1X30:
 750         case MEDIA_BUS_FMT_YUV10_1X30:
 751         case MEDIA_BUS_FMT_UYVY10_1X20:
 752         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 753                 return 10;
 754
 755         case MEDIA_BUS_FMT_RGB121212_1X36:
 756         case MEDIA_BUS_FMT_YUV12_1X36:
 757         case MEDIA_BUS_FMT_UYVY12_1X24:
 758         case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
 759                 return 12;
 760
 761         case MEDIA_BUS_FMT_RGB161616_1X48:
 762         case MEDIA_BUS_FMT_YUV16_1X48:
 763         case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
 764                 return 16;
 765
 766         default:
 767                 return 0;
 768         }
 769 }
 770
 771 /*
 772  * this submodule is responsible for the video data synchronization.
 773  * for example, for RGB 4:4:4 input, the data map is defined as
 774  *                      pin{47~40} <==> R[7:0]
 775  *                      pin{31~24} <==> G[7:0]
 776  *                      pin{15~8}  <==> B[7:0]
 777  */
 778 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 779 {
 780         int color_format = 0;
 781         u8 val;
 782
 783         switch (hdmi->hdmi_data.enc_in_bus_format) {
 784         case MEDIA_BUS_FMT_RGB888_1X24:
 785                 color_format = 0x01;
 786                 break;
 787         case MEDIA_BUS_FMT_RGB101010_1X30:
 788                 color_format = 0x03;
 789                 break;
 790         case MEDIA_BUS_FMT_RGB121212_1X36:
 791                 color_format = 0x05;
 792                 break;
 793         case MEDIA_BUS_FMT_RGB161616_1X48:
 794                 color_format = 0x07;
 795                 break;
 796
 797         case MEDIA_BUS_FMT_YUV8_1X24:
 798         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 799                 color_format = 0x09;
 800                 break;
 801         case MEDIA_BUS_FMT_YUV10_1X30:
 802         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 803                 color_format = 0x0B;
 804                 break;
 805         case MEDIA_BUS_FMT_YUV12_1X36:
 806         case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
 807                 color_format = 0x0D;
 808                 break;
 809         case MEDIA_BUS_FMT_YUV16_1X48:
 810         case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
 811                 color_format = 0x0F;
 812                 break;
 813
 814         case MEDIA_BUS_FMT_UYVY8_1X16:
 815                 color_format = 0x16;
 816                 break;
 817         case MEDIA_BUS_FMT_UYVY10_1X20:
 818                 color_format = 0x14;
 819                 break;
 820         case MEDIA_BUS_FMT_UYVY12_1X24:
 821                 color_format = 0x12;
 822                 break;
 823
 824         default:
 825                 return;
 826         }
 827
 828         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 829                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 830                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 831         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 832
 833         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 834         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 835                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 836                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 837         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 838         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 839         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 840         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 841         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 842         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 843         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 844 }
 845
 846 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 847 {
 848         return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format;
 849 }
 850
 851 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 852 {
 853         if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
 854                 return 0;
 855
 856         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
 857             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
 858                 return 1;
 859
 860         return 0;
 861 }
 862
 863 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 864 {
 865         if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
 866                 return 0;
 867
 868         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
 869             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
 870                 return 1;
 871
 872         return 0;
 873 }
 874
 875 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 876 {
 877         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 878         unsigned i;
 879         u32 csc_scale = 1;
 880
 881         if (is_color_space_conversion(hdmi)) {
 882                 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
 883                         if (hdmi->hdmi_data.enc_out_encoding ==
 884                                                 V4L2_YCBCR_ENC_601)
 885                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 886                         else
 887                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 888                 } else if (hdmi_bus_fmt_is_rgb(
 889                                         hdmi->hdmi_data.enc_in_bus_format)) {
 890                         if (hdmi->hdmi_data.enc_out_encoding ==
 891                                                 V4L2_YCBCR_ENC_601)
 892                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 893                         else
 894                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 895                         csc_scale = 0;
 896                 }
 897         }
 898
 899         /* The CSC registers are sequential, alternating MSB then LSB */
 900         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 901                 u16 coeff_a = (*csc_coeff)[0][i];
 902                 u16 coeff_b = (*csc_coeff)[1][i];
 903                 u16 coeff_c = (*csc_coeff)[2][i];
 904
 905                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 906                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 907                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 908                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 909                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 910                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 911         }
 912
 913         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 914                   HDMI_CSC_SCALE);
 915 }
 916
 917 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 918 {
 919         int color_depth = 0;
 920         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 921         int decimation = 0;
 922
 923         /* YCC422 interpolation to 444 mode */
 924         if (is_color_space_interpolation(hdmi))
 925                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 926         else if (is_color_space_decimation(hdmi))
 927                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 928
 929         switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
 930         case 8:
 931                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 932                 break;
 933         case 10:
 934                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 935                 break;
 936         case 12:
 937                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 938                 break;
 939         case 16:
 940                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 941                 break;
 942
 943         default:
 944                 return;
 945         }
 946
 947         /* Configure the CSC registers */
 948         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 949         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 950                   HDMI_CSC_SCALE);
 951
 952         dw_hdmi_update_csc_coeffs(hdmi);
 953 }
 954
 955 /*
 956  * HDMI video packetizer is used to packetize the data.
 957  * for example, if input is YCC422 mode or repeater is used,
 958  * data should be repacked this module can be bypassed.
 959  */
 960 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 961 {
 962         unsigned int color_depth = 0;
 963         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 964         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 965         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 966         u8 val, vp_conf;
 967
 968         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
 969             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
 970             hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
 971                 switch (hdmi_bus_fmt_color_depth(
 972                                         hdmi->hdmi_data.enc_out_bus_format)) {
 973                 case 8:
 974                         color_depth = 4;
 975                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 976                         break;
 977                 case 10:
 978                         color_depth = 5;
 979                         break;
 980                 case 12:
 981                         color_depth = 6;
 982                         break;
 983                 case 16:
 984                         color_depth = 7;
 985                         break;
 986                 default:
 987                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 988                 }
 989         } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
 990                 switch (hdmi_bus_fmt_color_depth(
 991                                         hdmi->hdmi_data.enc_out_bus_format)) {
 992                 case 0:
 993                 case 8:
 994                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 995                         break;
 996                 case 10:
 997                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 998                         break;
 999                 case 12:
1000                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
1001                         break;
1002
1003                 default:
1004                         return;
1005                 }
1006                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
1007         } else {
1008                 return;
1009         }
1010
1011         /* set the packetizer registers */
1012         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
1013                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
1014                 ((hdmi_data->pix_repet_factor <<
1015                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
1016                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
1017         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
1018
1019         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
1020                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
1021
1022         /* Data from pixel repeater block */
1023         if (hdmi_data->pix_repet_factor > 1) {
1024                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
1025                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
1026         } else { /* data from packetizer block */
1027                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
1028                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
1029         }
1030
1031         hdmi_modb(hdmi, vp_conf,
1032                   HDMI_VP_CONF_PR_EN_MASK |
1033                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
1034
1035         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
1036                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
1037
1038         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
1039
1040         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
1041                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1042                           HDMI_VP_CONF_PP_EN_ENABLE |
1043                           HDMI_VP_CONF_YCC422_EN_DISABLE;
1044         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
1045                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1046                           HDMI_VP_CONF_PP_EN_DISABLE |
1047                           HDMI_VP_CONF_YCC422_EN_ENABLE;
1048         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
1049                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
1050                           HDMI_VP_CONF_PP_EN_DISABLE |
1051                           HDMI_VP_CONF_YCC422_EN_DISABLE;
1052         } else {
1053                 return;
1054         }
1055
1056         hdmi_modb(hdmi, vp_conf,
1057                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
1058                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
1059
1060         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
1061                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
1062                   HDMI_VP_STUFF_PP_STUFFING_MASK |
1063                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
1064
1065         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
1066                   HDMI_VP_CONF);
1067 }
1068
1069 /* -----------------------------------------------------------------------------
1070  * Synopsys PHY Handling
1071  */
1072
1073 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
1074                                        unsigned char bit)
1075 {
1076         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
1077                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
1078 }
1079
1080 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
1081 {
1082         u32 val;
1083
1084         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1085                 if (msec-- == 0)
1086                         return false;
1087                 udelay(1000);
1088         }
1089         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1090
1091         return true;
1092 }
1093
1094 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1095                            unsigned char addr)
1096 {
1097         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1098         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1099         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1100                     HDMI_PHY_I2CM_DATAO_1_ADDR);
1101         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1102                     HDMI_PHY_I2CM_DATAO_0_ADDR);
1103         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1104                     HDMI_PHY_I2CM_OPERATION_ADDR);
1105         hdmi_phy_wait_i2c_done(hdmi, 1000);
1106 }
1107 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
1108
1109 /* Filter out invalid setups to avoid configuring SCDC and scrambling */
1110 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi)
1111 {
1112         struct drm_display_info *display = &hdmi->connector.display_info;
1113
1114         /* Completely disable SCDC support for older controllers */
1115         if (hdmi->version < 0x200a)
1116                 return false;
1117
1118         /* Disable if no DDC bus */
1119         if (!hdmi->ddc)
1120                 return false;
1121
1122         /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
1123         if (!display->hdmi.scdc.supported ||
1124             !display->hdmi.scdc.scrambling.supported)
1125                 return false;
1126
1127         /*
1128          * Disable if display only support low TMDS rates and scrambling
1129          * for low rates is not supported either
1130          */
1131         if (!display->hdmi.scdc.scrambling.low_rates &&
1132             display->max_tmds_clock <= 340000)
1133                 return false;
1134
1135         return true;
1136 }
1137
1138 /*
1139  * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:
1140  * - The Source shall suspend transmission of the TMDS clock and data
1141  * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it
1142  * from a 0 to a 1 or from a 1 to a 0
1143  * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from
1144  * the time the TMDS_Bit_Clock_Ratio bit is written until resuming
1145  * transmission of TMDS clock and data
1146  *
1147  * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio()
1148  * helper should called right before enabling the TMDS Clock and Data in
1149  * the PHY configuration callback.
1150  */
1151 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi)
1152 {
1153         unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1154
1155         /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1156         if (dw_hdmi_support_scdc(hdmi)) {
1157                 if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1158                         drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1);
1159                 else
1160                         drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0);
1161         }
1162 }
1163 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio);
1164
1165 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1166 {
1167         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1168                          HDMI_PHY_CONF0_PDZ_OFFSET,
1169                          HDMI_PHY_CONF0_PDZ_MASK);
1170 }
1171
1172 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1173 {
1174         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1175                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
1176                          HDMI_PHY_CONF0_ENTMDS_MASK);
1177 }
1178
1179 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
1180 {
1181         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1182                          HDMI_PHY_CONF0_SVSRET_OFFSET,
1183                          HDMI_PHY_CONF0_SVSRET_MASK);
1184 }
1185
1186 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1187 {
1188         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1189                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1190                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1191 }
1192 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq);
1193
1194 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1195 {
1196         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1197                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1198                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1199 }
1200 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron);
1201
1202 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1203 {
1204         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1205                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1206                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1207 }
1208
1209 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1210 {
1211         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1212                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1213                          HDMI_PHY_CONF0_SELDIPIF_MASK);
1214 }
1215
1216 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi)
1217 {
1218         /* PHY reset. The reset signal is active high on Gen2 PHYs. */
1219         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1220         hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1221 }
1222 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset);
1223
1224 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
1225 {
1226         hdmi_phy_test_clear(hdmi, 1);
1227         hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR);
1228         hdmi_phy_test_clear(hdmi, 0);
1229 }
1230 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr);
1231
1232 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1233 {
1234         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1235         unsigned int i;
1236         u16 val;
1237
1238         if (phy->gen == 1) {
1239                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1240                 dw_hdmi_phy_enable_powerdown(hdmi, true);
1241                 return;
1242         }
1243
1244         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1245
1246         /*
1247          * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
1248          * to low power mode.
1249          */
1250         for (i = 0; i < 5; ++i) {
1251                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1252                 if (!(val & HDMI_PHY_TX_PHY_LOCK))
1253                         break;
1254
1255                 usleep_range(1000, 2000);
1256         }
1257
1258         if (val & HDMI_PHY_TX_PHY_LOCK)
1259                 dev_warn(hdmi->dev, "PHY failed to power down\n");
1260         else
1261                 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1262
1263         dw_hdmi_phy_gen2_pddq(hdmi, 1);
1264 }
1265
1266 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1267 {
1268         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1269         unsigned int i;
1270         u8 val;
1271
1272         if (phy->gen == 1) {
1273                 dw_hdmi_phy_enable_powerdown(hdmi, false);
1274
1275                 /* Toggle TMDS enable. */
1276                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1277                 dw_hdmi_phy_enable_tmds(hdmi, 1);
1278                 return 0;
1279         }
1280
1281         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1282         dw_hdmi_phy_gen2_pddq(hdmi, 0);
1283
1284         /* Wait for PHY PLL lock */
1285         for (i = 0; i < 5; ++i) {
1286                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1287                 if (val)
1288                         break;
1289
1290                 usleep_range(1000, 2000);
1291         }
1292
1293         if (!val) {
1294                 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1295                 return -ETIMEDOUT;
1296         }
1297
1298         dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1299         return 0;
1300 }
1301
1302 /*
1303  * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1304  * information the DWC MHL PHY has the same register layout and is thus also
1305  * supported by this function.
1306  */
1307 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
1308                 const struct dw_hdmi_plat_data *pdata,
1309                 unsigned long mpixelclock)
1310 {
1311         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1312         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1313         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1314
1315         /* TOFIX Will need 420 specific PHY configuration tables */
1316
1317         /* PLL/MPLL Cfg - always match on final entry */
1318         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1319                 if (mpixelclock <= mpll_config->mpixelclock)
1320                         break;
1321
1322         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1323                 if (mpixelclock <= curr_ctrl->mpixelclock)
1324                         break;
1325
1326         for (; phy_config->mpixelclock != ~0UL; phy_config++)
1327                 if (mpixelclock <= phy_config->mpixelclock)
1328                         break;
1329
1330         if (mpll_config->mpixelclock == ~0UL ||
1331             curr_ctrl->mpixelclock == ~0UL ||
1332             phy_config->mpixelclock == ~0UL)
1333                 return -EINVAL;
1334
1335         dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1336                               HDMI_3D_TX_PHY_CPCE_CTRL);
1337         dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1338                               HDMI_3D_TX_PHY_GMPCTRL);
1339         dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1340                               HDMI_3D_TX_PHY_CURRCTRL);
1341
1342         dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1343         dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1344                               HDMI_3D_TX_PHY_MSM_CTRL);
1345
1346         dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1347         dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1348                               HDMI_3D_TX_PHY_CKSYMTXCTRL);
1349         dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1350                               HDMI_3D_TX_PHY_VLEVCTRL);
1351
1352         /* Override and disable clock termination. */
1353         dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1354                               HDMI_3D_TX_PHY_CKCALCTRL);
1355
1356         return 0;
1357 }
1358
1359 static int hdmi_phy_configure(struct dw_hdmi *hdmi)
1360 {
1361         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1362         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1363         unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
1364         unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1365         int ret;
1366
1367         dw_hdmi_phy_power_off(hdmi);
1368
1369         dw_hdmi_set_high_tmds_clock_ratio(hdmi);
1370
1371         /* Leave low power consumption mode by asserting SVSRET. */
1372         if (phy->has_svsret)
1373                 dw_hdmi_phy_enable_svsret(hdmi, 1);
1374
1375         dw_hdmi_phy_reset(hdmi);
1376
1377         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1378
1379         dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
1380
1381         /* Write to the PHY as configured by the platform */
1382         if (pdata->configure_phy)
1383                 ret = pdata->configure_phy(hdmi, pdata, mpixelclock);
1384         else
1385                 ret = phy->configure(hdmi, pdata, mpixelclock);
1386         if (ret) {
1387                 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1388                         mpixelclock);
1389                 return ret;
1390         }
1391
1392         /* Wait for resuming transmission of TMDS clock and data */
1393         if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1394                 msleep(100);
1395
1396         return dw_hdmi_phy_power_on(hdmi);
1397 }
1398
1399 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1400                             struct drm_display_mode *mode)
1401 {
1402         int i, ret;
1403
1404         /* HDMI Phy spec says to do the phy initialization sequence twice */
1405         for (i = 0; i < 2; i++) {
1406                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1407                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1408
1409                 ret = hdmi_phy_configure(hdmi);
1410                 if (ret)
1411                         return ret;
1412         }
1413
1414         return 0;
1415 }
1416
1417 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1418 {
1419         dw_hdmi_phy_power_off(hdmi);
1420 }
1421
1422 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1423                                                void *data)
1424 {
1425         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1426                 connector_status_connected : connector_status_disconnected;
1427 }
1428 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd);
1429
1430 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
1431                             bool force, bool disabled, bool rxsense)
1432 {
1433         u8 old_mask = hdmi->phy_mask;
1434
1435         if (force || disabled || !rxsense)
1436                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1437         else
1438                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1439
1440         if (old_mask != hdmi->phy_mask)
1441                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1442 }
1443 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd);
1444
1445 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
1446 {
1447         /*
1448          * Configure the PHY RX SENSE and HPD interrupts polarities and clear
1449          * any pending interrupt.
1450          */
1451         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1452         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1453                     HDMI_IH_PHY_STAT0);
1454
1455         /* Enable cable hot plug irq. */
1456         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1457
1458         /* Clear and unmute interrupts. */
1459         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1460                     HDMI_IH_PHY_STAT0);
1461         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1462                     HDMI_IH_MUTE_PHY_STAT0);
1463 }
1464 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd);
1465
1466 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
1467         .init = dw_hdmi_phy_init,
1468         .disable = dw_hdmi_phy_disable,
1469         .read_hpd = dw_hdmi_phy_read_hpd,
1470         .update_hpd = dw_hdmi_phy_update_hpd,
1471         .setup_hpd = dw_hdmi_phy_setup_hpd,
1472 };
1473
1474 /* -----------------------------------------------------------------------------
1475  * HDMI TX Setup
1476  */
1477
1478 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1479 {
1480         u8 de;
1481
1482         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1483                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1484         else
1485                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1486
1487         /* disable rx detect */
1488         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1489                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1490
1491         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1492
1493         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1494                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1495 }
1496
1497 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1498 {
1499         struct hdmi_avi_infoframe frame;
1500         u8 val;
1501
1502         /* Initialise info frame from DRM mode */
1503         drm_hdmi_avi_infoframe_from_display_mode(&frame,
1504                                                  &hdmi->connector, mode);
1505
1506         if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1507                 frame.colorspace = HDMI_COLORSPACE_YUV444;
1508         else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1509                 frame.colorspace = HDMI_COLORSPACE_YUV422;
1510         else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1511                 frame.colorspace = HDMI_COLORSPACE_YUV420;
1512         else
1513                 frame.colorspace = HDMI_COLORSPACE_RGB;
1514
1515         /* Set up colorimetry */
1516         switch (hdmi->hdmi_data.enc_out_encoding) {
1517         case V4L2_YCBCR_ENC_601:
1518                 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1519                         frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1520                 else
1521                         frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1522                 frame.extended_colorimetry =
1523                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1524                 break;
1525         case V4L2_YCBCR_ENC_709:
1526                 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1527                         frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1528                 else
1529                         frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1530                 frame.extended_colorimetry =
1531                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1532                 break;
1533         default: /* Carries no data */
1534                 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1535                 frame.extended_colorimetry =
1536                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1537                 break;
1538         }
1539
1540         frame.scan_mode = HDMI_SCAN_MODE_NONE;
1541
1542         /*
1543          * The Designware IP uses a different byte format from standard
1544          * AVI info frames, though generally the bits are in the correct
1545          * bytes.
1546          */
1547
1548         /*
1549          * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1550          * scan info in bits 4,5 rather than 0,1 and active aspect present in
1551          * bit 6 rather than 4.
1552          */
1553         val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
1554         if (frame.active_aspect & 15)
1555                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1556         if (frame.top_bar || frame.bottom_bar)
1557                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1558         if (frame.left_bar || frame.right_bar)
1559                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1560         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1561
1562         /* AVI data byte 2 differences: none */
1563         val = ((frame.colorimetry & 0x3) << 6) |
1564               ((frame.picture_aspect & 0x3) << 4) |
1565               (frame.active_aspect & 0xf);
1566         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1567
1568         /* AVI data byte 3 differences: none */
1569         val = ((frame.extended_colorimetry & 0x7) << 4) |
1570               ((frame.quantization_range & 0x3) << 2) |
1571               (frame.nups & 0x3);
1572         if (frame.itc)
1573                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1574         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1575
1576         /* AVI data byte 4 differences: none */
1577         val = frame.video_code & 0x7f;
1578         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1579
1580         /* AVI Data Byte 5- set up input and output pixel repetition */
1581         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1582                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1583                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1584                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1585                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1586                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1587         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1588
1589         /*
1590          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1591          * ycc range in bits 2,3 rather than 6,7
1592          */
1593         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1594               (frame.content_type & 0x3);
1595         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1596
1597         /* AVI Data Bytes 6-13 */
1598         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1599         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1600         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1601         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1602         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1603         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1604         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1605         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1606 }
1607
1608 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1609                                                  struct drm_display_mode *mode)
1610 {
1611         struct hdmi_vendor_infoframe frame;
1612         u8 buffer[10];
1613         ssize_t err;
1614
1615         err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1616                                                           &hdmi->connector,
1617                                                           mode);
1618         if (err < 0)
1619                 /*
1620                  * Going into that statement does not means vendor infoframe
1621                  * fails. It just informed us that vendor infoframe is not
1622                  * needed for the selected mode. Only 4k or stereoscopic 3D
1623                  * mode requires vendor infoframe. So just simply return.
1624                  */
1625                 return;
1626
1627         err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1628         if (err < 0) {
1629                 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1630                         err);
1631                 return;
1632         }
1633         hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1634                         HDMI_FC_DATAUTO0_VSD_MASK);
1635
1636         /* Set the length of HDMI vendor specific InfoFrame payload */
1637         hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1638
1639         /* Set 24bit IEEE Registration Identifier */
1640         hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1641         hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1642         hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1643
1644         /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1645         hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1646         hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1647
1648         if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1649                 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1650
1651         /* Packet frame interpolation */
1652         hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1653
1654         /* Auto packets per frame and line spacing */
1655         hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1656
1657         /* Configures the Frame Composer On RDRB mode */
1658         hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1659                         HDMI_FC_DATAUTO0_VSD_MASK);
1660 }
1661
1662 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1663                              const struct drm_display_mode *mode)
1664 {
1665         u8 inv_val, bytes;
1666         struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi;
1667         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1668         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1669         unsigned int vdisplay, hdisplay;
1670
1671         vmode->mtmdsclock = vmode->mpixelclock = mode->clock * 1000;
1672
1673         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1674
1675         if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1676                 vmode->mtmdsclock /= 2;
1677
1678         /* Set up HDMI_FC_INVIDCONF */
1679         inv_val = (hdmi->hdmi_data.hdcp_enable ||
1680                    (dw_hdmi_support_scdc(hdmi) &&
1681                     (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
1682                      hdmi_info->scdc.scrambling.low_rates)) ?
1683                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1684                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1685
1686         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1687                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1688                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1689
1690         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1691                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1692                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1693
1694         inv_val |= (vmode->mdataenablepolarity ?
1695                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1696                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1697
1698         if (hdmi->vic == 39)
1699                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1700         else
1701                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1702                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1703                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1704
1705         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1706                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1707                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1708
1709         inv_val |= hdmi->sink_is_hdmi ?
1710                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1711                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1712
1713         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1714
1715         hdisplay = mode->hdisplay;
1716         hblank = mode->htotal - mode->hdisplay;
1717         h_de_hs = mode->hsync_start - mode->hdisplay;
1718         hsync_len = mode->hsync_end - mode->hsync_start;
1719
1720         /*
1721          * When we're setting a YCbCr420 mode, we need
1722          * to adjust the horizontal timing to suit.
1723          */
1724         if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1725                 hdisplay /= 2;
1726                 hblank /= 2;
1727                 h_de_hs /= 2;
1728                 hsync_len /= 2;
1729         }
1730
1731         vdisplay = mode->vdisplay;
1732         vblank = mode->vtotal - mode->vdisplay;
1733         v_de_vs = mode->vsync_start - mode->vdisplay;
1734         vsync_len = mode->vsync_end - mode->vsync_start;
1735
1736         /*
1737          * When we're setting an interlaced mode, we need
1738          * to adjust the vertical timing to suit.
1739          */
1740         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1741                 vdisplay /= 2;
1742                 vblank /= 2;
1743                 v_de_vs /= 2;
1744                 vsync_len /= 2;
1745         }
1746
1747         /* Scrambling Control */
1748         if (dw_hdmi_support_scdc(hdmi)) {
1749                 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
1750                     hdmi_info->scdc.scrambling.low_rates) {
1751                         /*
1752                          * HDMI2.0 Specifies the following procedure:
1753                          * After the Source Device has determined that
1754                          * SCDC_Present is set (=1), the Source Device should
1755                          * write the accurate Version of the Source Device
1756                          * to the Source Version field in the SCDCS.
1757                          * Source Devices compliant shall set the
1758                          * Source Version = 1.
1759                          */
1760                         drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION,
1761                                        &bytes);
1762                         drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION,
1763                                 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
1764
1765                         /* Enabled Scrambling in the Sink */
1766                         drm_scdc_set_scrambling(hdmi->ddc, 1);
1767
1768                         /*
1769                          * To activate the scrambler feature, you must ensure
1770                          * that the quasi-static configuration bit
1771                          * fc_invidconf.HDCP_keepout is set at configuration
1772                          * time, before the required mc_swrstzreq.tmdsswrst_req
1773                          * reset request is issued.
1774                          */
1775                         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1776                                     HDMI_MC_SWRSTZ);
1777                         hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1778                 } else {
1779                         hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1780                         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1781                                     HDMI_MC_SWRSTZ);
1782                         drm_scdc_set_scrambling(hdmi->ddc, 0);
1783                 }
1784         }
1785
1786         /* Set up horizontal active pixel width */
1787         hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
1788         hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
1789
1790         /* Set up vertical active lines */
1791         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1792         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1793
1794         /* Set up horizontal blanking pixel region width */
1795         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1796         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1797
1798         /* Set up vertical blanking pixel region width */
1799         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1800
1801         /* Set up HSYNC active edge delay width (in pixel clks) */
1802         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1803         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1804
1805         /* Set up VSYNC active edge delay (in lines) */
1806         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1807
1808         /* Set up HSYNC active pulse width (in pixel clks) */
1809         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1810         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1811
1812         /* Set up VSYNC active edge delay (in lines) */
1813         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1814 }
1815
1816 /* HDMI Initialization Step B.4 */
1817 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1818 {
1819         /* control period minimum duration */
1820         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1821         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1822         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1823
1824         /* Set to fill TMDS data channels */
1825         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1826         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1827         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1828
1829         /* Enable pixel clock and tmds data path */
1830         hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
1831                            HDMI_MC_CLKDIS_CSCCLK_DISABLE |
1832                            HDMI_MC_CLKDIS_AUDCLK_DISABLE |
1833                            HDMI_MC_CLKDIS_PREPCLK_DISABLE |
1834                            HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1835         hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1836         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1837
1838         hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1839         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1840
1841         /* Enable csc path */
1842         if (is_color_space_conversion(hdmi)) {
1843                 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1844                 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
1845         }
1846
1847         /* Enable color space conversion if needed */
1848         if (is_color_space_conversion(hdmi))
1849                 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
1850                             HDMI_MC_FLOWCTRL);
1851         else
1852                 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
1853                             HDMI_MC_FLOWCTRL);
1854 }
1855
1856 /* Workaround to clear the overflow condition */
1857 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1858 {
1859         unsigned int count;
1860         unsigned int i;
1861         u8 val;
1862
1863         /*
1864          * Under some circumstances the Frame Composer arithmetic unit can miss
1865          * an FC register write due to being busy processing the previous one.
1866          * The issue can be worked around by issuing a TMDS software reset and
1867          * then write one of the FC registers several times.
1868          *
1869          * The number of iterations matters and depends on the HDMI TX revision
1870          * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL
1871          * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified
1872          * as needing the workaround, with 4 iterations for v1.30a and 1
1873          * iteration for others.
1874          * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing
1875          * the workaround with a single iteration.
1876          * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have
1877          * been identified as needing the workaround with a single iteration.
1878          */
1879
1880         switch (hdmi->version) {
1881         case 0x130a:
1882                 count = 4;
1883                 break;
1884         case 0x131a:
1885         case 0x132a:
1886         case 0x200a:
1887         case 0x201a:
1888         case 0x211a:
1889         case 0x212a:
1890                 count = 1;
1891                 break;
1892         default:
1893                 return;
1894         }
1895
1896         /* TMDS software reset */
1897         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1898
1899         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1900         for (i = 0; i < count; i++)
1901                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1902 }
1903
1904 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1905 {
1906         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1907                     HDMI_IH_MUTE_FC_STAT2);
1908 }
1909
1910 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1911 {
1912         int ret;
1913
1914         hdmi_disable_overflow_interrupts(hdmi);
1915
1916         hdmi->vic = drm_match_cea_mode(mode);
1917
1918         if (!hdmi->vic) {
1919                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1920         } else {
1921                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1922         }
1923
1924         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1925             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1926             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1927             (hdmi->vic == 17) || (hdmi->vic == 18))
1928                 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
1929         else
1930                 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
1931
1932         hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1933         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1934
1935         /* TOFIX: Get input format from plat data or fallback to RGB888 */
1936         if (hdmi->plat_data->input_bus_format)
1937                 hdmi->hdmi_data.enc_in_bus_format =
1938                         hdmi->plat_data->input_bus_format;
1939         else
1940                 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1941
1942         /* TOFIX: Get input encoding from plat data or fallback to none */
1943         if (hdmi->plat_data->input_bus_encoding)
1944                 hdmi->hdmi_data.enc_in_encoding =
1945                         hdmi->plat_data->input_bus_encoding;
1946         else
1947                 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
1948
1949         /* TOFIX: Default to RGB888 output format */
1950         hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1951
1952         hdmi->hdmi_data.pix_repet_factor = 0;
1953         hdmi->hdmi_data.hdcp_enable = 0;
1954         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1955
1956         /* HDMI Initialization Step B.1 */
1957         hdmi_av_composer(hdmi, mode);
1958
1959         /* HDMI Initializateion Step B.2 */
1960         ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode);
1961         if (ret)
1962                 return ret;
1963         hdmi->phy.enabled = true;
1964
1965         /* HDMI Initialization Step B.3 */
1966         dw_hdmi_enable_video_path(hdmi);
1967
1968         if (hdmi->sink_has_audio) {
1969                 dev_dbg(hdmi->dev, "sink has audio support\n");
1970
1971                 /* HDMI Initialization Step E - Configure audio */
1972                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1973                 hdmi_enable_audio_clk(hdmi, true);
1974         }
1975
1976         /* not for DVI mode */
1977         if (hdmi->sink_is_hdmi) {
1978                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1979
1980                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1981                 hdmi_config_AVI(hdmi, mode);
1982                 hdmi_config_vendor_specific_infoframe(hdmi, mode);
1983         } else {
1984                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1985         }
1986
1987         hdmi_video_packetize(hdmi);
1988         hdmi_video_csc(hdmi);
1989         hdmi_video_sample(hdmi);
1990         hdmi_tx_hdcp_config(hdmi);
1991
1992         dw_hdmi_clear_overflow(hdmi);
1993
1994         return 0;
1995 }
1996
1997 static void dw_hdmi_setup_i2c(struct dw_hdmi *hdmi)
1998 {
1999         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2000                     HDMI_PHY_I2CM_INT_ADDR);
2001
2002         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2003                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2004                     HDMI_PHY_I2CM_CTLINT_ADDR);
2005 }
2006
2007 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
2008 {
2009         u8 ih_mute;
2010
2011         /*
2012          * Boot up defaults are:
2013          * HDMI_IH_MUTE   = 0x03 (disabled)
2014          * HDMI_IH_MUTE_* = 0x00 (enabled)
2015          *
2016          * Disable top level interrupt bits in HDMI block
2017          */
2018         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
2019                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2020                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
2021
2022         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2023
2024         /* by default mask all interrupts */
2025         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
2026         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
2027         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
2028         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
2029         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
2030         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
2031         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
2032         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
2033         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
2034         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
2035         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
2036         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
2037         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
2038         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
2039
2040         /* Disable interrupts in the IH_MUTE_* registers */
2041         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
2042         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
2043         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
2044         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
2045         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
2046         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
2047         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
2048         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
2049         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
2050         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
2051
2052         /* Enable top level interrupt bits in HDMI block */
2053         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2054                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
2055         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2056 }
2057
2058 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
2059 {
2060         hdmi->bridge_is_on = true;
2061         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
2062 }
2063
2064 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
2065 {
2066         if (hdmi->phy.enabled) {
2067                 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
2068                 hdmi->phy.enabled = false;
2069         }
2070
2071         hdmi->bridge_is_on = false;
2072 }
2073
2074 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
2075 {
2076         int force = hdmi->force;
2077
2078         if (hdmi->disabled) {
2079                 force = DRM_FORCE_OFF;
2080         } else if (force == DRM_FORCE_UNSPECIFIED) {
2081                 if (hdmi->rxsense)
2082                         force = DRM_FORCE_ON;
2083                 else
2084                         force = DRM_FORCE_OFF;
2085         }
2086
2087         if (force == DRM_FORCE_OFF) {
2088                 if (hdmi->bridge_is_on)
2089                         dw_hdmi_poweroff(hdmi);
2090         } else {
2091                 if (!hdmi->bridge_is_on)
2092                         dw_hdmi_poweron(hdmi);
2093         }
2094 }
2095
2096 /*
2097  * Adjust the detection of RXSENSE according to whether we have a forced
2098  * connection mode enabled, or whether we have been disabled.  There is
2099  * no point processing RXSENSE interrupts if we have a forced connection
2100  * state, or DRM has us disabled.
2101  *
2102  * We also disable rxsense interrupts when we think we're disconnected
2103  * to avoid floating TDMS signals giving false rxsense interrupts.
2104  *
2105  * Note: we still need to listen for HPD interrupts even when DRM has us
2106  * disabled so that we can detect a connect event.
2107  */
2108 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
2109 {
2110         if (hdmi->phy.ops->update_hpd)
2111                 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
2112                                           hdmi->force, hdmi->disabled,
2113                                           hdmi->rxsense);
2114 }
2115
2116 static enum drm_connector_status
2117 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
2118 {
2119         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2120                                              connector);
2121
2122         mutex_lock(&hdmi->mutex);
2123         hdmi->force = DRM_FORCE_UNSPECIFIED;
2124         dw_hdmi_update_power(hdmi);
2125         dw_hdmi_update_phy_mask(hdmi);
2126         mutex_unlock(&hdmi->mutex);
2127
2128         return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
2129 }
2130
2131 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
2132 {
2133         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2134                                              connector);
2135         struct edid *edid;
2136         int ret = 0;
2137
2138         if (!hdmi->ddc)
2139                 return 0;
2140
2141         edid = drm_get_edid(connector, hdmi->ddc);
2142         if (edid) {
2143                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
2144                         edid->width_cm, edid->height_cm);
2145
2146                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
2147                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
2148                 drm_connector_update_edid_property(connector, edid);
2149                 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
2150                 ret = drm_add_edid_modes(connector, edid);
2151                 kfree(edid);
2152         } else {
2153                 dev_dbg(hdmi->dev, "failed to get edid\n");
2154         }
2155
2156         return ret;
2157 }
2158
2159 static void dw_hdmi_connector_force(struct drm_connector *connector)
2160 {
2161         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2162                                              connector);
2163
2164         mutex_lock(&hdmi->mutex);
2165         hdmi->force = connector->force;
2166         dw_hdmi_update_power(hdmi);
2167         dw_hdmi_update_phy_mask(hdmi);
2168         mutex_unlock(&hdmi->mutex);
2169 }
2170
2171 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
2172         .fill_modes = drm_helper_probe_single_connector_modes,
2173         .detect = dw_hdmi_connector_detect,
2174         .destroy = drm_connector_cleanup,
2175         .force = dw_hdmi_connector_force,
2176         .reset = drm_atomic_helper_connector_reset,
2177         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2178         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2179 };
2180
2181 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
2182         .get_modes = dw_hdmi_connector_get_modes,
2183 };
2184
2185 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge)
2186 {
2187         struct dw_hdmi *hdmi = bridge->driver_private;
2188         struct drm_encoder *encoder = bridge->encoder;
2189         struct drm_connector *connector = &hdmi->connector;
2190
2191         connector->interlace_allowed = 1;
2192         connector->polled = DRM_CONNECTOR_POLL_HPD;
2193
2194         drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
2195
2196         drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs,
2197                            DRM_MODE_CONNECTOR_HDMIA);
2198
2199         drm_connector_attach_encoder(connector, encoder);
2200
2201         return 0;
2202 }
2203
2204 static enum drm_mode_status
2205 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
2206                           const struct drm_display_mode *mode)
2207 {
2208         struct dw_hdmi *hdmi = bridge->driver_private;
2209         struct drm_connector *connector = &hdmi->connector;
2210         enum drm_mode_status mode_status = MODE_OK;
2211
2212         /* We don't support double-clocked modes */
2213         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2214                 return MODE_BAD;
2215
2216         if (hdmi->plat_data->mode_valid)
2217                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
2218
2219         return mode_status;
2220 }
2221
2222 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
2223                                     const struct drm_display_mode *orig_mode,
2224                                     const struct drm_display_mode *mode)
2225 {
2226         struct dw_hdmi *hdmi = bridge->driver_private;
2227
2228         mutex_lock(&hdmi->mutex);
2229
2230         /* Store the display mode for plugin/DKMS poweron events */
2231         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
2232
2233         mutex_unlock(&hdmi->mutex);
2234 }
2235
2236 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
2237 {
2238         struct dw_hdmi *hdmi = bridge->driver_private;
2239
2240         mutex_lock(&hdmi->mutex);
2241         hdmi->disabled = true;
2242         dw_hdmi_update_power(hdmi);
2243         dw_hdmi_update_phy_mask(hdmi);
2244         mutex_unlock(&hdmi->mutex);
2245 }
2246
2247 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
2248 {
2249         struct dw_hdmi *hdmi = bridge->driver_private;
2250
2251         mutex_lock(&hdmi->mutex);
2252         hdmi->disabled = false;
2253         dw_hdmi_update_power(hdmi);
2254         dw_hdmi_update_phy_mask(hdmi);
2255         mutex_unlock(&hdmi->mutex);
2256 }
2257
2258 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2259         .attach = dw_hdmi_bridge_attach,
2260         .enable = dw_hdmi_bridge_enable,
2261         .disable = dw_hdmi_bridge_disable,
2262         .mode_set = dw_hdmi_bridge_mode_set,
2263         .mode_valid = dw_hdmi_bridge_mode_valid,
2264 };
2265
2266 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2267 {
2268         struct dw_hdmi_i2c *i2c = hdmi->i2c;
2269         unsigned int stat;
2270
2271         stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2272         if (!stat)
2273                 return IRQ_NONE;
2274
2275         hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2276
2277         i2c->stat = stat;
2278
2279         complete(&i2c->cmp);
2280
2281         return IRQ_HANDLED;
2282 }
2283
2284 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
2285 {
2286         struct dw_hdmi *hdmi = dev_id;
2287         u8 intr_stat;
2288         irqreturn_t ret = IRQ_NONE;
2289
2290         if (hdmi->i2c)
2291                 ret = dw_hdmi_i2c_irq(hdmi);
2292
2293         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2294         if (intr_stat) {
2295                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2296                 return IRQ_WAKE_THREAD;
2297         }
2298
2299         return ret;
2300 }
2301
2302 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
2303 {
2304         mutex_lock(&hdmi->mutex);
2305
2306         if (!hdmi->force) {
2307                 /*
2308                  * If the RX sense status indicates we're disconnected,
2309                  * clear the software rxsense status.
2310                  */
2311                 if (!rx_sense)
2312                         hdmi->rxsense = false;
2313
2314                 /*
2315                  * Only set the software rxsense status when both
2316                  * rxsense and hpd indicates we're connected.
2317                  * This avoids what seems to be bad behaviour in
2318                  * at least iMX6S versions of the phy.
2319                  */
2320                 if (hpd)
2321                         hdmi->rxsense = true;
2322
2323                 dw_hdmi_update_power(hdmi);
2324                 dw_hdmi_update_phy_mask(hdmi);
2325         }
2326         mutex_unlock(&hdmi->mutex);
2327 }
2328 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);
2329
2330 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
2331 {
2332         struct dw_hdmi *hdmi = dev_id;
2333         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
2334
2335         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2336         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
2337         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2338
2339         phy_pol_mask = 0;
2340         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2341                 phy_pol_mask |= HDMI_PHY_HPD;
2342         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2343                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2344         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2345                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2346         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2347                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2348         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2349                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2350
2351         if (phy_pol_mask)
2352                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2353
2354         /*
2355          * RX sense tells us whether the TDMS transmitters are detecting
2356          * load - in other words, there's something listening on the
2357          * other end of the link.  Use this to decide whether we should
2358          * power on the phy as HPD may be toggled by the sink to merely
2359          * ask the source to re-read the EDID.
2360          */
2361         if (intr_stat &
2362             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
2363                 dw_hdmi_setup_rx_sense(hdmi,
2364                                        phy_stat & HDMI_PHY_HPD,
2365                                        phy_stat & HDMI_PHY_RX_SENSE);
2366
2367                 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0)
2368                         cec_notifier_set_phys_addr(hdmi->cec_notifier,
2369                                                    CEC_PHYS_ADDR_INVALID);
2370         }
2371
2372         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2373                 dev_dbg(hdmi->dev, "EVENT=%s\n",
2374                         phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
2375                 if (hdmi->bridge.dev)
2376                         drm_helper_hpd_irq_event(hdmi->bridge.dev);
2377         }
2378
2379         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
2380         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2381                     HDMI_IH_MUTE_PHY_STAT0);
2382
2383         return IRQ_HANDLED;
2384 }
2385
2386 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
2387         {
2388                 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
2389                 .name = "DWC HDMI TX PHY",
2390                 .gen = 1,
2391         }, {
2392                 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
2393                 .name = "DWC MHL PHY + HEAC PHY",
2394                 .gen = 2,
2395                 .has_svsret = true,
2396                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2397         }, {
2398                 .type = DW_HDMI_PHY_DWC_MHL_PHY,
2399                 .name = "DWC MHL PHY",
2400                 .gen = 2,
2401                 .has_svsret = true,
2402                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2403         }, {
2404                 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
2405                 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
2406                 .gen = 2,
2407                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2408         }, {
2409                 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
2410                 .name = "DWC HDMI 3D TX PHY",
2411                 .gen = 2,
2412                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2413         }, {
2414                 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
2415                 .name = "DWC HDMI 2.0 TX PHY",
2416                 .gen = 2,
2417                 .has_svsret = true,
2418                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2419         }, {
2420                 .type = DW_HDMI_PHY_VENDOR_PHY,
2421                 .name = "Vendor PHY",
2422         }
2423 };
2424
2425 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
2426 {
2427         unsigned int i;
2428         u8 phy_type;
2429
2430         phy_type = hdmi->plat_data->phy_force_vendor ?
2431                                 DW_HDMI_PHY_VENDOR_PHY :
2432                                 hdmi_readb(hdmi, HDMI_CONFIG2_ID);
2433
2434         if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
2435                 /* Vendor PHYs require support from the glue layer. */
2436                 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
2437                         dev_err(hdmi->dev,
2438                                 "Vendor HDMI PHY not supported by glue layer\n");
2439                         return -ENODEV;
2440                 }
2441
2442                 hdmi->phy.ops = hdmi->plat_data->phy_ops;
2443                 hdmi->phy.data = hdmi->plat_data->phy_data;
2444                 hdmi->phy.name = hdmi->plat_data->phy_name;
2445                 return 0;
2446         }
2447
2448         /* Synopsys PHYs are handled internally. */
2449         for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
2450                 if (dw_hdmi_phys[i].type == phy_type) {
2451                         hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
2452                         hdmi->phy.name = dw_hdmi_phys[i].name;
2453                         hdmi->phy.data = (void *)&dw_hdmi_phys[i];
2454
2455                         if (!dw_hdmi_phys[i].configure &&
2456                             !hdmi->plat_data->configure_phy) {
2457                                 dev_err(hdmi->dev, "%s requires platform support\n",
2458                                         hdmi->phy.name);
2459                                 return -ENODEV;
2460                         }
2461
2462                         return 0;
2463                 }
2464         }
2465
2466         dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
2467         return -ENODEV;
2468 }
2469
2470 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)
2471 {
2472         mutex_lock(&hdmi->mutex);
2473         hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
2474         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2475         mutex_unlock(&hdmi->mutex);
2476 }
2477
2478 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)
2479 {
2480         mutex_lock(&hdmi->mutex);
2481         hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
2482         hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2483         mutex_unlock(&hdmi->mutex);
2484 }
2485
2486 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {
2487         .write = hdmi_writeb,
2488         .read = hdmi_readb,
2489         .enable = dw_hdmi_cec_enable,
2490         .disable = dw_hdmi_cec_disable,
2491 };
2492
2493 static const struct regmap_config hdmi_regmap_8bit_config = {
2494         .reg_bits       = 32,
2495         .val_bits       = 8,
2496         .reg_stride     = 1,
2497         .max_register   = HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
2498 };
2499
2500 static const struct regmap_config hdmi_regmap_32bit_config = {
2501         .reg_bits       = 32,
2502         .val_bits       = 32,
2503         .reg_stride     = 4,
2504         .max_register   = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
2505 };
2506
2507 static struct dw_hdmi *
2508 __dw_hdmi_probe(struct platform_device *pdev,
2509                 const struct dw_hdmi_plat_data *plat_data)
2510 {
2511         struct device *dev = &pdev->dev;
2512         struct device_node *np = dev->of_node;
2513         struct platform_device_info pdevinfo;
2514         struct device_node *ddc_node;
2515         struct dw_hdmi_cec_data cec;
2516         struct dw_hdmi *hdmi;
2517         struct resource *iores = NULL;
2518         int irq;
2519         int ret;
2520         u32 val = 1;
2521         u8 prod_id0;
2522         u8 prod_id1;
2523         u8 config0;
2524         u8 config3;
2525
2526         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2527         if (!hdmi)
2528                 return ERR_PTR(-ENOMEM);
2529
2530         hdmi->plat_data = plat_data;
2531         hdmi->dev = dev;
2532         hdmi->sample_rate = 48000;
2533         hdmi->disabled = true;
2534         hdmi->rxsense = true;
2535         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2536         hdmi->mc_clkdis = 0x7f;
2537
2538         mutex_init(&hdmi->mutex);
2539         mutex_init(&hdmi->audio_mutex);
2540         spin_lock_init(&hdmi->audio_lock);
2541
2542         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2543         if (ddc_node) {
2544                 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
2545                 of_node_put(ddc_node);
2546                 if (!hdmi->ddc) {
2547                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
2548                         return ERR_PTR(-EPROBE_DEFER);
2549                 }
2550
2551         } else {
2552                 dev_dbg(hdmi->dev, "no ddc property found\n");
2553         }
2554
2555         if (!plat_data->regm) {
2556                 const struct regmap_config *reg_config;
2557
2558                 of_property_read_u32(np, "reg-io-width", &val);
2559                 switch (val) {
2560                 case 4:
2561                         reg_config = &hdmi_regmap_32bit_config;
2562                         hdmi->reg_shift = 2;
2563                         break;
2564                 case 1:
2565                         reg_config = &hdmi_regmap_8bit_config;
2566                         break;
2567                 default:
2568                         dev_err(dev, "reg-io-width must be 1 or 4\n");
2569                         return ERR_PTR(-EINVAL);
2570                 }
2571
2572                 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2573                 hdmi->regs = devm_ioremap_resource(dev, iores);
2574                 if (IS_ERR(hdmi->regs)) {
2575                         ret = PTR_ERR(hdmi->regs);
2576                         goto err_res;
2577                 }
2578
2579                 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
2580                 if (IS_ERR(hdmi->regm)) {
2581                         dev_err(dev, "Failed to configure regmap\n");
2582                         ret = PTR_ERR(hdmi->regm);
2583                         goto err_res;
2584                 }
2585         } else {
2586                 hdmi->regm = plat_data->regm;
2587         }
2588
2589         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2590         if (IS_ERR(hdmi->isfr_clk)) {
2591                 ret = PTR_ERR(hdmi->isfr_clk);
2592                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2593                 goto err_res;
2594         }
2595
2596         ret = clk_prepare_enable(hdmi->isfr_clk);
2597         if (ret) {
2598                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2599                 goto err_res;
2600         }
2601
2602         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2603         if (IS_ERR(hdmi->iahb_clk)) {
2604                 ret = PTR_ERR(hdmi->iahb_clk);
2605                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2606                 goto err_isfr;
2607         }
2608
2609         ret = clk_prepare_enable(hdmi->iahb_clk);
2610         if (ret) {
2611                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2612                 goto err_isfr;
2613         }
2614
2615         hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec");
2616         if (PTR_ERR(hdmi->cec_clk) == -ENOENT) {
2617                 hdmi->cec_clk = NULL;
2618         } else if (IS_ERR(hdmi->cec_clk)) {
2619                 ret = PTR_ERR(hdmi->cec_clk);
2620                 if (ret != -EPROBE_DEFER)
2621                         dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
2622                                 ret);
2623
2624                 hdmi->cec_clk = NULL;
2625                 goto err_iahb;
2626         } else {
2627                 ret = clk_prepare_enable(hdmi->cec_clk);
2628                 if (ret) {
2629                         dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n",
2630                                 ret);
2631                         goto err_iahb;
2632                 }
2633         }
2634
2635         /* Product and revision IDs */
2636         hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
2637                       | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
2638         prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
2639         prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
2640
2641         if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
2642             (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
2643                 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
2644                         hdmi->version, prod_id0, prod_id1);
2645                 ret = -ENODEV;
2646                 goto err_iahb;
2647         }
2648
2649         ret = dw_hdmi_detect_phy(hdmi);
2650         if (ret < 0)
2651                 goto err_iahb;
2652
2653         dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
2654                  hdmi->version >> 12, hdmi->version & 0xfff,
2655                  prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
2656                  hdmi->phy.name);
2657
2658         initialize_hdmi_ih_mutes(hdmi);
2659
2660         irq = platform_get_irq(pdev, 0);
2661         if (irq < 0) {
2662                 ret = irq;
2663                 goto err_iahb;
2664         }
2665
2666         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2667                                         dw_hdmi_irq, IRQF_SHARED,
2668                                         dev_name(dev), hdmi);
2669         if (ret)
2670                 goto err_iahb;
2671
2672         hdmi->cec_notifier = cec_notifier_get(dev);
2673         if (!hdmi->cec_notifier) {
2674                 ret = -ENOMEM;
2675                 goto err_iahb;
2676         }
2677
2678         /*
2679          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2680          * N and cts values before enabling phy
2681          */
2682         hdmi_init_clk_regenerator(hdmi);
2683
2684         /* If DDC bus is not specified, try to register HDMI I2C bus */
2685         if (!hdmi->ddc) {
2686                 /* Look for (optional) stuff related to unwedging */
2687                 hdmi->pinctrl = devm_pinctrl_get(dev);
2688                 if (!IS_ERR(hdmi->pinctrl)) {
2689                         hdmi->unwedge_state =
2690                                 pinctrl_lookup_state(hdmi->pinctrl, "unwedge");
2691                         hdmi->default_state =
2692                                 pinctrl_lookup_state(hdmi->pinctrl, "default");
2693
2694                         if (IS_ERR(hdmi->default_state) &&
2695                             !IS_ERR(hdmi->unwedge_state)) {
2696                                 dev_warn(dev,
2697                                          "Unwedge requires default pinctrl\n");
2698                                 hdmi->unwedge_state = ERR_PTR(-ENODEV);
2699                         }
2700                 }
2701
2702                 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2703                 if (IS_ERR(hdmi->ddc))
2704                         hdmi->ddc = NULL;
2705         }
2706
2707         hdmi->bridge.driver_private = hdmi;
2708         hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
2709 #ifdef CONFIG_OF
2710         hdmi->bridge.of_node = pdev->dev.of_node;
2711 #endif
2712
2713         dw_hdmi_setup_i2c(hdmi);
2714         if (hdmi->phy.ops->setup_hpd)
2715                 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
2716
2717         memset(&pdevinfo, 0, sizeof(pdevinfo));
2718         pdevinfo.parent = dev;
2719         pdevinfo.id = PLATFORM_DEVID_AUTO;
2720
2721         config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2722         config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
2723
2724         if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) {
2725                 struct dw_hdmi_audio_data audio;
2726
2727                 audio.phys = iores->start;
2728                 audio.base = hdmi->regs;
2729                 audio.irq = irq;
2730                 audio.hdmi = hdmi;
2731                 audio.eld = hdmi->connector.eld;
2732                 hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
2733                 hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
2734
2735                 pdevinfo.name = "dw-hdmi-ahb-audio";
2736                 pdevinfo.data = &audio;
2737                 pdevinfo.size_data = sizeof(audio);
2738                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2739                 hdmi->audio = platform_device_register_full(&pdevinfo);
2740         } else if (config0 & HDMI_CONFIG0_I2S) {
2741                 struct dw_hdmi_i2s_audio_data audio;
2742
2743                 audio.hdmi      = hdmi;
2744                 audio.write     = hdmi_writeb;
2745                 audio.read      = hdmi_readb;
2746                 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
2747                 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
2748
2749                 pdevinfo.name = "dw-hdmi-i2s-audio";
2750                 pdevinfo.data = &audio;
2751                 pdevinfo.size_data = sizeof(audio);
2752                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2753                 hdmi->audio = platform_device_register_full(&pdevinfo);
2754         }
2755
2756         if (config0 & HDMI_CONFIG0_CEC) {
2757                 cec.hdmi = hdmi;
2758                 cec.ops = &dw_hdmi_cec_ops;
2759                 cec.irq = irq;
2760
2761                 pdevinfo.name = "dw-hdmi-cec";
2762                 pdevinfo.data = &cec;
2763                 pdevinfo.size_data = sizeof(cec);
2764                 pdevinfo.dma_mask = 0;
2765
2766                 hdmi->cec = platform_device_register_full(&pdevinfo);
2767         }
2768
2769         /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */
2770         if (hdmi->i2c)
2771                 dw_hdmi_i2c_init(hdmi);
2772
2773         return hdmi;
2774
2775 err_iahb:
2776         if (hdmi->i2c) {
2777                 i2c_del_adapter(&hdmi->i2c->adap);
2778                 hdmi->ddc = NULL;
2779         }
2780
2781         if (hdmi->cec_notifier)
2782                 cec_notifier_put(hdmi->cec_notifier);
2783
2784         clk_disable_unprepare(hdmi->iahb_clk);
2785         if (hdmi->cec_clk)
2786                 clk_disable_unprepare(hdmi->cec_clk);
2787 err_isfr:
2788         clk_disable_unprepare(hdmi->isfr_clk);
2789 err_res:
2790         i2c_put_adapter(hdmi->ddc);
2791
2792         return ERR_PTR(ret);
2793 }
2794
2795 static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
2796 {
2797         if (hdmi->audio && !IS_ERR(hdmi->audio))
2798                 platform_device_unregister(hdmi->audio);
2799         if (!IS_ERR(hdmi->cec))
2800                 platform_device_unregister(hdmi->cec);
2801
2802         /* Disable all interrupts */
2803         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2804
2805         if (hdmi->cec_notifier)
2806                 cec_notifier_put(hdmi->cec_notifier);
2807
2808         clk_disable_unprepare(hdmi->iahb_clk);
2809         clk_disable_unprepare(hdmi->isfr_clk);
2810         if (hdmi->cec_clk)
2811                 clk_disable_unprepare(hdmi->cec_clk);
2812
2813         if (hdmi->i2c)
2814                 i2c_del_adapter(&hdmi->i2c->adap);
2815         else
2816                 i2c_put_adapter(hdmi->ddc);
2817 }
2818
2819 /* -----------------------------------------------------------------------------
2820  * Probe/remove API, used from platforms based on the DRM bridge API.
2821  */
2822 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
2823                               const struct dw_hdmi_plat_data *plat_data)
2824 {
2825         struct dw_hdmi *hdmi;
2826
2827         hdmi = __dw_hdmi_probe(pdev, plat_data);
2828         if (IS_ERR(hdmi))
2829                 return hdmi;
2830
2831         drm_bridge_add(&hdmi->bridge);
2832
2833         return hdmi;
2834 }
2835 EXPORT_SYMBOL_GPL(dw_hdmi_probe);
2836
2837 void dw_hdmi_remove(struct dw_hdmi *hdmi)
2838 {
2839         drm_bridge_remove(&hdmi->bridge);
2840
2841         __dw_hdmi_remove(hdmi);
2842 }
2843 EXPORT_SYMBOL_GPL(dw_hdmi_remove);
2844
2845 /* -----------------------------------------------------------------------------
2846  * Bind/unbind API, used from platforms based on the component framework.
2847  */
2848 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
2849                              struct drm_encoder *encoder,
2850                              const struct dw_hdmi_plat_data *plat_data)
2851 {
2852         struct dw_hdmi *hdmi;
2853         int ret;
2854
2855         hdmi = __dw_hdmi_probe(pdev, plat_data);
2856         if (IS_ERR(hdmi))
2857                 return hdmi;
2858
2859         ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL);
2860         if (ret) {
2861                 dw_hdmi_remove(hdmi);
2862                 DRM_ERROR("Failed to initialize bridge with drm\n");
2863                 return ERR_PTR(ret);
2864         }
2865
2866         return hdmi;
2867 }
2868 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2869
2870 void dw_hdmi_unbind(struct dw_hdmi *hdmi)
2871 {
2872         __dw_hdmi_remove(hdmi);
2873 }
2874 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2875
2876 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2877 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2878 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2879 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2880 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2881 MODULE_LICENSE("GPL");
2882 MODULE_ALIAS("platform:dw-hdmi");