drivers/gpu/drm/bridge/samsung-dsim.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Samsung MIPI DSIM bridge driver.
   4  *
   5  * Copyright (C) 2021 Amarula Solutions(India)
   6  * Copyright (c) 2014 Samsung Electronics Co., Ltd
   7  * Author: Jagan Teki <jagan@amarulasolutions.com>
   8  *
   9  * Based on exynos_drm_dsi from
  10  * Tomasz Figa <t.figa@samsung.com>
  11  */
  12
  13 #include <asm/unaligned.h>
  14
  15 #include <linux/clk.h>
  16 #include <linux/delay.h>
  17 #include <linux/irq.h>
  18 #include <linux/media-bus-format.h>
  19 #include <linux/of_device.h>
  20 #include <linux/phy/phy.h>
  21
  22 #include <video/mipi_display.h>
  23
  24 #include <drm/bridge/samsung-dsim.h>
  25 #include <drm/drm_panel.h>
  26 #include <drm/drm_print.h>
  27
  28 /* returns true iff both arguments logically differs */
  29 #define NEQV(a, b) (!(a) ^ !(b))
  30
  31 /* DSIM_STATUS */
  32 #define DSIM_STOP_STATE_DAT(x)          (((x) & 0xf) << 0)
  33 #define DSIM_STOP_STATE_CLK             BIT(8)
  34 #define DSIM_TX_READY_HS_CLK            BIT(10)
  35 #define DSIM_PLL_STABLE                 BIT(31)
  36
  37 /* DSIM_SWRST */
  38 #define DSIM_FUNCRST                    BIT(16)
  39 #define DSIM_SWRST                      BIT(0)
  40
  41 /* DSIM_TIMEOUT */
  42 #define DSIM_LPDR_TIMEOUT(x)            ((x) << 0)
  43 #define DSIM_BTA_TIMEOUT(x)             ((x) << 16)
  44
  45 /* DSIM_CLKCTRL */
  46 #define DSIM_ESC_PRESCALER(x)           (((x) & 0xffff) << 0)
  47 #define DSIM_ESC_PRESCALER_MASK         (0xffff << 0)
  48 #define DSIM_LANE_ESC_CLK_EN_CLK        BIT(19)
  49 #define DSIM_LANE_ESC_CLK_EN_DATA(x)    (((x) & 0xf) << 20)
  50 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK  (0xf << 20)
  51 #define DSIM_BYTE_CLKEN                 BIT(24)
  52 #define DSIM_BYTE_CLK_SRC(x)            (((x) & 0x3) << 25)
  53 #define DSIM_BYTE_CLK_SRC_MASK          (0x3 << 25)
  54 #define DSIM_PLL_BYPASS                 BIT(27)
  55 #define DSIM_ESC_CLKEN                  BIT(28)
  56 #define DSIM_TX_REQUEST_HSCLK           BIT(31)
  57
  58 /* DSIM_CONFIG */
  59 #define DSIM_LANE_EN_CLK                BIT(0)
  60 #define DSIM_LANE_EN(x)                 (((x) & 0xf) << 1)
  61 #define DSIM_NUM_OF_DATA_LANE(x)        (((x) & 0x3) << 5)
  62 #define DSIM_SUB_PIX_FORMAT(x)          (((x) & 0x7) << 8)
  63 #define DSIM_MAIN_PIX_FORMAT_MASK       (0x7 << 12)
  64 #define DSIM_MAIN_PIX_FORMAT_RGB888     (0x7 << 12)
  65 #define DSIM_MAIN_PIX_FORMAT_RGB666     (0x6 << 12)
  66 #define DSIM_MAIN_PIX_FORMAT_RGB666_P   (0x5 << 12)
  67 #define DSIM_MAIN_PIX_FORMAT_RGB565     (0x4 << 12)
  68 #define DSIM_SUB_VC                     (((x) & 0x3) << 16)
  69 #define DSIM_MAIN_VC                    (((x) & 0x3) << 18)
  70 #define DSIM_HSA_DISABLE_MODE           BIT(20)
  71 #define DSIM_HBP_DISABLE_MODE           BIT(21)
  72 #define DSIM_HFP_DISABLE_MODE           BIT(22)
  73 /*
  74  * The i.MX 8M Mini Applications Processor Reference Manual,
  75  * Rev. 3, 11/2020 Page 4091
  76  * The i.MX 8M Nano Applications Processor Reference Manual,
  77  * Rev. 2, 07/2022 Page 3058
  78  * The i.MX 8M Plus Applications Processor Reference Manual,
  79  * Rev. 1, 06/2021 Page 5436
  80  * all claims this bit is 'HseDisableMode' with the definition
  81  * 0 = Disables transfer
  82  * 1 = Enables transfer
  83  *
  84  * This clearly states that HSE is not a disabled bit.
  85  *
  86  * The naming convention follows as per the manual and the
  87  * driver logic is based on the MIPI_DSI_MODE_VIDEO_HSE flag.
  88  */
  89 #define DSIM_HSE_DISABLE_MODE           BIT(23)
  90 #define DSIM_AUTO_MODE                  BIT(24)
  91 #define DSIM_VIDEO_MODE                 BIT(25)
  92 #define DSIM_BURST_MODE                 BIT(26)
  93 #define DSIM_SYNC_INFORM                BIT(27)
  94 #define DSIM_EOT_DISABLE                BIT(28)
  95 #define DSIM_MFLUSH_VS                  BIT(29)
  96 /* This flag is valid only for exynos3250/3472/5260/5430 */
  97 #define DSIM_CLKLANE_STOP               BIT(30)
  98
  99 /* DSIM_ESCMODE */
 100 #define DSIM_TX_TRIGGER_RST             BIT(4)
 101 #define DSIM_TX_LPDT_LP                 BIT(6)
 102 #define DSIM_CMD_LPDT_LP                BIT(7)
 103 #define DSIM_FORCE_BTA                  BIT(16)
 104 #define DSIM_FORCE_STOP_STATE           BIT(20)
 105 #define DSIM_STOP_STATE_CNT(x)          (((x) & 0x7ff) << 21)
 106 #define DSIM_STOP_STATE_CNT_MASK        (0x7ff << 21)
 107
 108 /* DSIM_MDRESOL */
 109 #define DSIM_MAIN_STAND_BY              BIT(31)
 110 #define DSIM_MAIN_VRESOL(x, num_bits)   (((x) & ((1 << (num_bits)) - 1)) << 16)
 111 #define DSIM_MAIN_HRESOL(x, num_bits)   (((x) & ((1 << (num_bits)) - 1)) << 0)
 112
 113 /* DSIM_MVPORCH */
 114 #define DSIM_CMD_ALLOW(x)               ((x) << 28)
 115 #define DSIM_STABLE_VFP(x)              ((x) << 16)
 116 #define DSIM_MAIN_VBP(x)                ((x) << 0)
 117 #define DSIM_CMD_ALLOW_MASK             (0xf << 28)
 118 #define DSIM_STABLE_VFP_MASK            (0x7ff << 16)
 119 #define DSIM_MAIN_VBP_MASK              (0x7ff << 0)
 120
 121 /* DSIM_MHPORCH */
 122 #define DSIM_MAIN_HFP(x)                ((x) << 16)
 123 #define DSIM_MAIN_HBP(x)                ((x) << 0)
 124 #define DSIM_MAIN_HFP_MASK              ((0xffff) << 16)
 125 #define DSIM_MAIN_HBP_MASK              ((0xffff) << 0)
 126
 127 /* DSIM_MSYNC */
 128 #define DSIM_MAIN_VSA(x)                ((x) << 22)
 129 #define DSIM_MAIN_HSA(x)                ((x) << 0)
 130 #define DSIM_MAIN_VSA_MASK              ((0x3ff) << 22)
 131 #define DSIM_MAIN_HSA_MASK              ((0xffff) << 0)
 132
 133 /* DSIM_SDRESOL */
 134 #define DSIM_SUB_STANDY(x)              ((x) << 31)
 135 #define DSIM_SUB_VRESOL(x)              ((x) << 16)
 136 #define DSIM_SUB_HRESOL(x)              ((x) << 0)
 137 #define DSIM_SUB_STANDY_MASK            ((0x1) << 31)
 138 #define DSIM_SUB_VRESOL_MASK            ((0x7ff) << 16)
 139 #define DSIM_SUB_HRESOL_MASK            ((0x7ff) << 0)
 140
 141 /* DSIM_INTSRC */
 142 #define DSIM_INT_PLL_STABLE             BIT(31)
 143 #define DSIM_INT_SW_RST_RELEASE         BIT(30)
 144 #define DSIM_INT_SFR_FIFO_EMPTY         BIT(29)
 145 #define DSIM_INT_SFR_HDR_FIFO_EMPTY     BIT(28)
 146 #define DSIM_INT_BTA                    BIT(25)
 147 #define DSIM_INT_FRAME_DONE             BIT(24)
 148 #define DSIM_INT_RX_TIMEOUT             BIT(21)
 149 #define DSIM_INT_BTA_TIMEOUT            BIT(20)
 150 #define DSIM_INT_RX_DONE                BIT(18)
 151 #define DSIM_INT_RX_TE                  BIT(17)
 152 #define DSIM_INT_RX_ACK                 BIT(16)
 153 #define DSIM_INT_RX_ECC_ERR             BIT(15)
 154 #define DSIM_INT_RX_CRC_ERR             BIT(14)
 155
 156 /* DSIM_FIFOCTRL */
 157 #define DSIM_RX_DATA_FULL               BIT(25)
 158 #define DSIM_RX_DATA_EMPTY              BIT(24)
 159 #define DSIM_SFR_HEADER_FULL            BIT(23)
 160 #define DSIM_SFR_HEADER_EMPTY           BIT(22)
 161 #define DSIM_SFR_PAYLOAD_FULL           BIT(21)
 162 #define DSIM_SFR_PAYLOAD_EMPTY          BIT(20)
 163 #define DSIM_I80_HEADER_FULL            BIT(19)
 164 #define DSIM_I80_HEADER_EMPTY           BIT(18)
 165 #define DSIM_I80_PAYLOAD_FULL           BIT(17)
 166 #define DSIM_I80_PAYLOAD_EMPTY          BIT(16)
 167 #define DSIM_SD_HEADER_FULL             BIT(15)
 168 #define DSIM_SD_HEADER_EMPTY            BIT(14)
 169 #define DSIM_SD_PAYLOAD_FULL            BIT(13)
 170 #define DSIM_SD_PAYLOAD_EMPTY           BIT(12)
 171 #define DSIM_MD_HEADER_FULL             BIT(11)
 172 #define DSIM_MD_HEADER_EMPTY            BIT(10)
 173 #define DSIM_MD_PAYLOAD_FULL            BIT(9)
 174 #define DSIM_MD_PAYLOAD_EMPTY           BIT(8)
 175 #define DSIM_RX_FIFO                    BIT(4)
 176 #define DSIM_SFR_FIFO                   BIT(3)
 177 #define DSIM_I80_FIFO                   BIT(2)
 178 #define DSIM_SD_FIFO                    BIT(1)
 179 #define DSIM_MD_FIFO                    BIT(0)
 180
 181 /* DSIM_PHYACCHR */
 182 #define DSIM_AFC_EN                     BIT(14)
 183 #define DSIM_AFC_CTL(x)                 (((x) & 0x7) << 5)
 184
 185 /* DSIM_PLLCTRL */
 186 #define DSIM_PLL_DPDNSWAP_CLK           (1 << 25)
 187 #define DSIM_PLL_DPDNSWAP_DAT           (1 << 24)
 188 #define DSIM_FREQ_BAND(x)               ((x) << 24)
 189 #define DSIM_PLL_EN                     BIT(23)
 190 #define DSIM_PLL_P(x, offset)           ((x) << (offset))
 191 #define DSIM_PLL_M(x)                   ((x) << 4)
 192 #define DSIM_PLL_S(x)                   ((x) << 1)
 193
 194 /* DSIM_PHYCTRL */
 195 #define DSIM_PHYCTRL_ULPS_EXIT(x)       (((x) & 0x1ff) << 0)
 196 #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP  BIT(30)
 197 #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP  BIT(14)
 198
 199 /* DSIM_PHYTIMING */
 200 #define DSIM_PHYTIMING_LPX(x)           ((x) << 8)
 201 #define DSIM_PHYTIMING_HS_EXIT(x)       ((x) << 0)
 202
 203 /* DSIM_PHYTIMING1 */
 204 #define DSIM_PHYTIMING1_CLK_PREPARE(x)  ((x) << 24)
 205 #define DSIM_PHYTIMING1_CLK_ZERO(x)     ((x) << 16)
 206 #define DSIM_PHYTIMING1_CLK_POST(x)     ((x) << 8)
 207 #define DSIM_PHYTIMING1_CLK_TRAIL(x)    ((x) << 0)
 208
 209 /* DSIM_PHYTIMING2 */
 210 #define DSIM_PHYTIMING2_HS_PREPARE(x)   ((x) << 16)
 211 #define DSIM_PHYTIMING2_HS_ZERO(x)      ((x) << 8)
 212 #define DSIM_PHYTIMING2_HS_TRAIL(x)     ((x) << 0)
 213
 214 #define DSI_MAX_BUS_WIDTH               4
 215 #define DSI_NUM_VIRTUAL_CHANNELS        4
 216 #define DSI_TX_FIFO_SIZE                2048
 217 #define DSI_RX_FIFO_SIZE                256
 218 #define DSI_XFER_TIMEOUT_MS             100
 219 #define DSI_RX_FIFO_EMPTY               0x30800002
 220
 221 #define OLD_SCLK_MIPI_CLK_NAME          "pll_clk"
 222
 223 static const char *const clk_names[5] = {
 224         "bus_clk",
 225         "sclk_mipi",
 226         "phyclk_mipidphy0_bitclkdiv8",
 227         "phyclk_mipidphy0_rxclkesc0",
 228         "sclk_rgb_vclk_to_dsim0"
 229 };
 230
 231 enum samsung_dsim_transfer_type {
 232         EXYNOS_DSI_TX,
 233         EXYNOS_DSI_RX,
 234 };
 235
 236 enum reg_idx {
 237         DSIM_STATUS_REG,        /* Status register */
 238         DSIM_SWRST_REG,         /* Software reset register */
 239         DSIM_CLKCTRL_REG,       /* Clock control register */
 240         DSIM_TIMEOUT_REG,       /* Time out register */
 241         DSIM_CONFIG_REG,        /* Configuration register */
 242         DSIM_ESCMODE_REG,       /* Escape mode register */
 243         DSIM_MDRESOL_REG,
 244         DSIM_MVPORCH_REG,       /* Main display Vporch register */
 245         DSIM_MHPORCH_REG,       /* Main display Hporch register */
 246         DSIM_MSYNC_REG,         /* Main display sync area register */
 247         DSIM_INTSRC_REG,        /* Interrupt source register */
 248         DSIM_INTMSK_REG,        /* Interrupt mask register */
 249         DSIM_PKTHDR_REG,        /* Packet Header FIFO register */
 250         DSIM_PAYLOAD_REG,       /* Payload FIFO register */
 251         DSIM_RXFIFO_REG,        /* Read FIFO register */
 252         DSIM_FIFOCTRL_REG,      /* FIFO status and control register */
 253         DSIM_PLLCTRL_REG,       /* PLL control register */
 254         DSIM_PHYCTRL_REG,
 255         DSIM_PHYTIMING_REG,
 256         DSIM_PHYTIMING1_REG,
 257         DSIM_PHYTIMING2_REG,
 258         NUM_REGS
 259 };
 260
 261 static const unsigned int exynos_reg_ofs[] = {
 262         [DSIM_STATUS_REG] =  0x00,
 263         [DSIM_SWRST_REG] =  0x04,
 264         [DSIM_CLKCTRL_REG] =  0x08,
 265         [DSIM_TIMEOUT_REG] =  0x0c,
 266         [DSIM_CONFIG_REG] =  0x10,
 267         [DSIM_ESCMODE_REG] =  0x14,
 268         [DSIM_MDRESOL_REG] =  0x18,
 269         [DSIM_MVPORCH_REG] =  0x1c,
 270         [DSIM_MHPORCH_REG] =  0x20,
 271         [DSIM_MSYNC_REG] =  0x24,
 272         [DSIM_INTSRC_REG] =  0x2c,
 273         [DSIM_INTMSK_REG] =  0x30,
 274         [DSIM_PKTHDR_REG] =  0x34,
 275         [DSIM_PAYLOAD_REG] =  0x38,
 276         [DSIM_RXFIFO_REG] =  0x3c,
 277         [DSIM_FIFOCTRL_REG] =  0x44,
 278         [DSIM_PLLCTRL_REG] =  0x4c,
 279         [DSIM_PHYCTRL_REG] =  0x5c,
 280         [DSIM_PHYTIMING_REG] =  0x64,
 281         [DSIM_PHYTIMING1_REG] =  0x68,
 282         [DSIM_PHYTIMING2_REG] =  0x6c,
 283 };
 284
 285 static const unsigned int exynos5433_reg_ofs[] = {
 286         [DSIM_STATUS_REG] = 0x04,
 287         [DSIM_SWRST_REG] = 0x0C,
 288         [DSIM_CLKCTRL_REG] = 0x10,
 289         [DSIM_TIMEOUT_REG] = 0x14,
 290         [DSIM_CONFIG_REG] = 0x18,
 291         [DSIM_ESCMODE_REG] = 0x1C,
 292         [DSIM_MDRESOL_REG] = 0x20,
 293         [DSIM_MVPORCH_REG] = 0x24,
 294         [DSIM_MHPORCH_REG] = 0x28,
 295         [DSIM_MSYNC_REG] = 0x2C,
 296         [DSIM_INTSRC_REG] = 0x34,
 297         [DSIM_INTMSK_REG] = 0x38,
 298         [DSIM_PKTHDR_REG] = 0x3C,
 299         [DSIM_PAYLOAD_REG] = 0x40,
 300         [DSIM_RXFIFO_REG] = 0x44,
 301         [DSIM_FIFOCTRL_REG] = 0x4C,
 302         [DSIM_PLLCTRL_REG] = 0x94,
 303         [DSIM_PHYCTRL_REG] = 0xA4,
 304         [DSIM_PHYTIMING_REG] = 0xB4,
 305         [DSIM_PHYTIMING1_REG] = 0xB8,
 306         [DSIM_PHYTIMING2_REG] = 0xBC,
 307 };
 308
 309 enum reg_value_idx {
 310         RESET_TYPE,
 311         PLL_TIMER,
 312         STOP_STATE_CNT,
 313         PHYCTRL_ULPS_EXIT,
 314         PHYCTRL_VREG_LP,
 315         PHYCTRL_SLEW_UP,
 316         PHYTIMING_LPX,
 317         PHYTIMING_HS_EXIT,
 318         PHYTIMING_CLK_PREPARE,
 319         PHYTIMING_CLK_ZERO,
 320         PHYTIMING_CLK_POST,
 321         PHYTIMING_CLK_TRAIL,
 322         PHYTIMING_HS_PREPARE,
 323         PHYTIMING_HS_ZERO,
 324         PHYTIMING_HS_TRAIL
 325 };
 326
 327 static const unsigned int reg_values[] = {
 328         [RESET_TYPE] = DSIM_SWRST,
 329         [PLL_TIMER] = 500,
 330         [STOP_STATE_CNT] = 0xf,
 331         [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af),
 332         [PHYCTRL_VREG_LP] = 0,
 333         [PHYCTRL_SLEW_UP] = 0,
 334         [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
 335         [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
 336         [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
 337         [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27),
 338         [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
 339         [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
 340         [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
 341         [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
 342         [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
 343 };
 344
 345 static const unsigned int exynos5422_reg_values[] = {
 346         [RESET_TYPE] = DSIM_SWRST,
 347         [PLL_TIMER] = 500,
 348         [STOP_STATE_CNT] = 0xf,
 349         [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
 350         [PHYCTRL_VREG_LP] = 0,
 351         [PHYCTRL_SLEW_UP] = 0,
 352         [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08),
 353         [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d),
 354         [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
 355         [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30),
 356         [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
 357         [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a),
 358         [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c),
 359         [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11),
 360         [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d),
 361 };
 362
 363 static const unsigned int exynos5433_reg_values[] = {
 364         [RESET_TYPE] = DSIM_FUNCRST,
 365         [PLL_TIMER] = 22200,
 366         [STOP_STATE_CNT] = 0xa,
 367         [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190),
 368         [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP,
 369         [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP,
 370         [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
 371         [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
 372         [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
 373         [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d),
 374         [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
 375         [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
 376         [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b),
 377         [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10),
 378         [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
 379 };
 380
 381 static const unsigned int imx8mm_dsim_reg_values[] = {
 382         [RESET_TYPE] = DSIM_SWRST,
 383         [PLL_TIMER] = 500,
 384         [STOP_STATE_CNT] = 0xf,
 385         [PHYCTRL_ULPS_EXIT] = 0,
 386         [PHYCTRL_VREG_LP] = 0,
 387         [PHYCTRL_SLEW_UP] = 0,
 388         [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
 389         [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
 390         [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
 391         [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x26),
 392         [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
 393         [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
 394         [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x08),
 395         [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
 396         [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
 397 };
 398
 399 static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = {
 400         .reg_ofs = exynos_reg_ofs,
 401         .plltmr_reg = 0x50,
 402         .has_freqband = 1,
 403         .has_clklane_stop = 1,
 404         .num_clks = 2,
 405         .max_freq = 1000,
 406         .wait_for_reset = 1,
 407         .num_bits_resol = 11,
 408         .pll_p_offset = 13,
 409         .reg_values = reg_values,
 410 };
 411
 412 static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = {
 413         .reg_ofs = exynos_reg_ofs,
 414         .plltmr_reg = 0x50,
 415         .has_freqband = 1,
 416         .has_clklane_stop = 1,
 417         .num_clks = 2,
 418         .max_freq = 1000,
 419         .wait_for_reset = 1,
 420         .num_bits_resol = 11,
 421         .pll_p_offset = 13,
 422         .reg_values = reg_values,
 423 };
 424
 425 static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = {
 426         .reg_ofs = exynos_reg_ofs,
 427         .plltmr_reg = 0x58,
 428         .num_clks = 2,
 429         .max_freq = 1000,
 430         .wait_for_reset = 1,
 431         .num_bits_resol = 11,
 432         .pll_p_offset = 13,
 433         .reg_values = reg_values,
 434 };
 435
 436 static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = {
 437         .reg_ofs = exynos5433_reg_ofs,
 438         .plltmr_reg = 0xa0,
 439         .has_clklane_stop = 1,
 440         .num_clks = 5,
 441         .max_freq = 1500,
 442         .wait_for_reset = 0,
 443         .num_bits_resol = 12,
 444         .pll_p_offset = 13,
 445         .reg_values = exynos5433_reg_values,
 446 };
 447
 448 static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = {
 449         .reg_ofs = exynos5433_reg_ofs,
 450         .plltmr_reg = 0xa0,
 451         .has_clklane_stop = 1,
 452         .num_clks = 2,
 453         .max_freq = 1500,
 454         .wait_for_reset = 1,
 455         .num_bits_resol = 12,
 456         .pll_p_offset = 13,
 457         .reg_values = exynos5422_reg_values,
 458 };
 459
 460 static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = {
 461         .reg_ofs = exynos5433_reg_ofs,
 462         .plltmr_reg = 0xa0,
 463         .has_clklane_stop = 1,
 464         .num_clks = 2,
 465         .max_freq = 2100,
 466         .wait_for_reset = 0,
 467         .num_bits_resol = 12,
 468         /*
 469          * Unlike Exynos, PLL_P(PMS_P) offset 14 is used in i.MX8M Mini/Nano/Plus
 470          * downstream driver - drivers/gpu/drm/bridge/sec-dsim.c
 471          */
 472         .pll_p_offset = 14,
 473         .reg_values = imx8mm_dsim_reg_values,
 474 };
 475
 476 static const struct samsung_dsim_driver_data *
 477 samsung_dsim_types[DSIM_TYPE_COUNT] = {
 478         [DSIM_TYPE_EXYNOS3250] = &exynos3_dsi_driver_data,
 479         [DSIM_TYPE_EXYNOS4210] = &exynos4_dsi_driver_data,
 480         [DSIM_TYPE_EXYNOS5410] = &exynos5_dsi_driver_data,
 481         [DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data,
 482         [DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data,
 483         [DSIM_TYPE_IMX8MM] = &imx8mm_dsi_driver_data,
 484         [DSIM_TYPE_IMX8MP] = &imx8mm_dsi_driver_data,
 485 };
 486
 487 static inline struct samsung_dsim *host_to_dsi(struct mipi_dsi_host *h)
 488 {
 489         return container_of(h, struct samsung_dsim, dsi_host);
 490 }
 491
 492 static inline struct samsung_dsim *bridge_to_dsi(struct drm_bridge *b)
 493 {
 494         return container_of(b, struct samsung_dsim, bridge);
 495 }
 496
 497 static inline void samsung_dsim_write(struct samsung_dsim *dsi,
 498                                       enum reg_idx idx, u32 val)
 499 {
 500         writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
 501 }
 502
 503 static inline u32 samsung_dsim_read(struct samsung_dsim *dsi, enum reg_idx idx)
 504 {
 505         return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
 506 }
 507
 508 static void samsung_dsim_wait_for_reset(struct samsung_dsim *dsi)
 509 {
 510         if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
 511                 return;
 512
 513         dev_err(dsi->dev, "timeout waiting for reset\n");
 514 }
 515
 516 static void samsung_dsim_reset(struct samsung_dsim *dsi)
 517 {
 518         u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];
 519
 520         reinit_completion(&dsi->completed);
 521         samsung_dsim_write(dsi, DSIM_SWRST_REG, reset_val);
 522 }
 523
 524 #ifndef MHZ
 525 #define MHZ     (1000 * 1000)
 526 #endif
 527
 528 static unsigned long samsung_dsim_pll_find_pms(struct samsung_dsim *dsi,
 529                                                unsigned long fin,
 530                                                unsigned long fout,
 531                                                u8 *p, u16 *m, u8 *s)
 532 {
 533         const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
 534         unsigned long best_freq = 0;
 535         u32 min_delta = 0xffffffff;
 536         u8 p_min, p_max;
 537         u8 _p, best_p;
 538         u16 _m, best_m;
 539         u8 _s, best_s;
 540
 541         p_min = DIV_ROUND_UP(fin, (12 * MHZ));
 542         p_max = fin / (6 * MHZ);
 543
 544         for (_p = p_min; _p <= p_max; ++_p) {
 545                 for (_s = 0; _s <= 5; ++_s) {
 546                         u64 tmp;
 547                         u32 delta;
 548
 549                         tmp = (u64)fout * (_p << _s);
 550                         do_div(tmp, fin);
 551                         _m = tmp;
 552                         if (_m < 41 || _m > 125)
 553                                 continue;
 554
 555                         tmp = (u64)_m * fin;
 556                         do_div(tmp, _p);
 557                         if (tmp < 500 * MHZ ||
 558                             tmp > driver_data->max_freq * MHZ)
 559                                 continue;
 560
 561                         tmp = (u64)_m * fin;
 562                         do_div(tmp, _p << _s);
 563
 564                         delta = abs(fout - tmp);
 565                         if (delta < min_delta) {
 566                                 best_p = _p;
 567                                 best_m = _m;
 568                                 best_s = _s;
 569                                 min_delta = delta;
 570                                 best_freq = tmp;
 571                         }
 572                 }
 573         }
 574
 575         if (best_freq) {
 576                 *p = best_p;
 577                 *m = best_m;
 578                 *s = best_s;
 579         }
 580
 581         return best_freq;
 582 }
 583
 584 static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
 585                                           unsigned long freq)
 586 {
 587         const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
 588         unsigned long fin, fout;
 589         int timeout;
 590         u8 p, s;
 591         u16 m;
 592         u32 reg;
 593
 594         fin = dsi->pll_clk_rate;
 595         fout = samsung_dsim_pll_find_pms(dsi, fin, freq, &p, &m, &s);
 596         if (!fout) {
 597                 dev_err(dsi->dev,
 598                         "failed to find PLL PMS for requested frequency\n");
 599                 return 0;
 600         }
 601         dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
 602
 603         writel(driver_data->reg_values[PLL_TIMER],
 604                dsi->reg_base + driver_data->plltmr_reg);
 605
 606         reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) |
 607               DSIM_PLL_M(m) | DSIM_PLL_S(s);
 608
 609         if (driver_data->has_freqband) {
 610                 static const unsigned long freq_bands[] = {
 611                         100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
 612                         270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
 613                         510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
 614                         770 * MHZ, 870 * MHZ, 950 * MHZ,
 615                 };
 616                 int band;
 617
 618                 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
 619                         if (fout < freq_bands[band])
 620                                 break;
 621
 622                 dev_dbg(dsi->dev, "band %d\n", band);
 623
 624                 reg |= DSIM_FREQ_BAND(band);
 625         }
 626
 627         if (dsi->swap_dn_dp_clk)
 628                 reg |= DSIM_PLL_DPDNSWAP_CLK;
 629         if (dsi->swap_dn_dp_data)
 630                 reg |= DSIM_PLL_DPDNSWAP_DAT;
 631
 632         samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
 633
 634         timeout = 1000;
 635         do {
 636                 if (timeout-- == 0) {
 637                         dev_err(dsi->dev, "PLL failed to stabilize\n");
 638                         return 0;
 639                 }
 640                 reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
 641         } while ((reg & DSIM_PLL_STABLE) == 0);
 642
 643         return fout;
 644 }
 645
 646 static int samsung_dsim_enable_clock(struct samsung_dsim *dsi)
 647 {
 648         unsigned long hs_clk, byte_clk, esc_clk;
 649         unsigned long esc_div;
 650         u32 reg;
 651
 652         hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate);
 653         if (!hs_clk) {
 654                 dev_err(dsi->dev, "failed to configure DSI PLL\n");
 655                 return -EFAULT;
 656         }
 657
 658         byte_clk = hs_clk / 8;
 659         esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
 660         esc_clk = byte_clk / esc_div;
 661
 662         if (esc_clk > 20 * MHZ) {
 663                 ++esc_div;
 664                 esc_clk = byte_clk / esc_div;
 665         }
 666
 667         dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
 668                 hs_clk, byte_clk, esc_clk);
 669
 670         reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG);
 671         reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
 672                         | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
 673                         | DSIM_BYTE_CLK_SRC_MASK);
 674         reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
 675                         | DSIM_ESC_PRESCALER(esc_div)
 676                         | DSIM_LANE_ESC_CLK_EN_CLK
 677                         | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
 678                         | DSIM_BYTE_CLK_SRC(0)
 679                         | DSIM_TX_REQUEST_HSCLK;
 680         samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg);
 681
 682         return 0;
 683 }
 684
 685 static void samsung_dsim_set_phy_ctrl(struct samsung_dsim *dsi)
 686 {
 687         const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
 688         const unsigned int *reg_values = driver_data->reg_values;
 689         u32 reg;
 690
 691         if (driver_data->has_freqband)
 692                 return;
 693
 694         /* B D-PHY: D-PHY Master & Slave Analog Block control */
 695         reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
 696                 reg_values[PHYCTRL_SLEW_UP];
 697         samsung_dsim_write(dsi, DSIM_PHYCTRL_REG, reg);
 698
 699         /*
 700          * T LPX: Transmitted length of any Low-Power state period
 701          * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
 702          *      burst
 703          */
 704         reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT];
 705         samsung_dsim_write(dsi, DSIM_PHYTIMING_REG, reg);
 706
 707         /*
 708          * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
 709          *      Line state immediately before the HS-0 Line state starting the
 710          *      HS transmission
 711          * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
 712          *      transmitting the Clock.
 713          * T CLK_POST: Time that the transmitter continues to send HS clock
 714          *      after the last associated Data Lane has transitioned to LP Mode
 715          *      Interval is defined as the period from the end of T HS-TRAIL to
 716          *      the beginning of T CLK-TRAIL
 717          * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
 718          *      the last payload clock bit of a HS transmission burst
 719          */
 720         reg = reg_values[PHYTIMING_CLK_PREPARE] |
 721                 reg_values[PHYTIMING_CLK_ZERO] |
 722                 reg_values[PHYTIMING_CLK_POST] |
 723                 reg_values[PHYTIMING_CLK_TRAIL];
 724
 725         samsung_dsim_write(dsi, DSIM_PHYTIMING1_REG, reg);
 726
 727         /*
 728          * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
 729          *      Line state immediately before the HS-0 Line state starting the
 730          *      HS transmission
 731          * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
 732          *      transmitting the Sync sequence.
 733          * T HS-TRAIL: Time that the transmitter drives the flipped differential
 734          *      state after last payload data bit of a HS transmission burst
 735          */
 736         reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] |
 737                 reg_values[PHYTIMING_HS_TRAIL];
 738         samsung_dsim_write(dsi, DSIM_PHYTIMING2_REG, reg);
 739 }
 740
 741 static void samsung_dsim_disable_clock(struct samsung_dsim *dsi)
 742 {
 743         u32 reg;
 744
 745         reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG);
 746         reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
 747                         | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
 748         samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg);
 749
 750         reg = samsung_dsim_read(dsi, DSIM_PLLCTRL_REG);
 751         reg &= ~DSIM_PLL_EN;
 752         samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
 753 }
 754
 755 static void samsung_dsim_enable_lane(struct samsung_dsim *dsi, u32 lane)
 756 {
 757         u32 reg = samsung_dsim_read(dsi, DSIM_CONFIG_REG);
 758
 759         reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK |
 760                         DSIM_LANE_EN(lane));
 761         samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg);
 762 }
 763
 764 static int samsung_dsim_init_link(struct samsung_dsim *dsi)
 765 {
 766         const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
 767         int timeout;
 768         u32 reg;
 769         u32 lanes_mask;
 770
 771         /* Initialize FIFO pointers */
 772         reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG);
 773         reg &= ~0x1f;
 774         samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg);
 775
 776         usleep_range(9000, 11000);
 777
 778         reg |= 0x1f;
 779         samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg);
 780         usleep_range(9000, 11000);
 781
 782         /* DSI configuration */
 783         reg = 0;
 784
 785         /*
 786          * The first bit of mode_flags specifies display configuration.
 787          * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
 788          * mode, otherwise it will support command mode.
 789          */
 790         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
 791                 reg |= DSIM_VIDEO_MODE;
 792
 793                 /*
 794                  * The user manual describes that following bits are ignored in
 795                  * command mode.
 796                  */
 797                 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
 798                         reg |= DSIM_MFLUSH_VS;
 799                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 800                         reg |= DSIM_SYNC_INFORM;
 801                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 802                         reg |= DSIM_BURST_MODE;
 803                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
 804                         reg |= DSIM_AUTO_MODE;
 805                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
 806                         reg |= DSIM_HSE_DISABLE_MODE;
 807                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP)
 808                         reg |= DSIM_HFP_DISABLE_MODE;
 809                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP)
 810                         reg |= DSIM_HBP_DISABLE_MODE;
 811                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA)
 812                         reg |= DSIM_HSA_DISABLE_MODE;
 813         }
 814
 815         if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
 816                 reg |= DSIM_EOT_DISABLE;
 817
 818         switch (dsi->format) {
 819         case MIPI_DSI_FMT_RGB888:
 820                 reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
 821                 break;
 822         case MIPI_DSI_FMT_RGB666:
 823                 reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
 824                 break;
 825         case MIPI_DSI_FMT_RGB666_PACKED:
 826                 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
 827                 break;
 828         case MIPI_DSI_FMT_RGB565:
 829                 reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
 830                 break;
 831         default:
 832                 dev_err(dsi->dev, "invalid pixel format\n");
 833                 return -EINVAL;
 834         }
 835
 836         /*
 837          * Use non-continuous clock mode if the periparal wants and
 838          * host controller supports
 839          *
 840          * In non-continous clock mode, host controller will turn off
 841          * the HS clock between high-speed transmissions to reduce
 842          * power consumption.
 843          */
 844         if (driver_data->has_clklane_stop &&
 845             dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
 846                 reg |= DSIM_CLKLANE_STOP;
 847         samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg);
 848
 849         lanes_mask = BIT(dsi->lanes) - 1;
 850         samsung_dsim_enable_lane(dsi, lanes_mask);
 851
 852         /* Check clock and data lane state are stop state */
 853         timeout = 100;
 854         do {
 855                 if (timeout-- == 0) {
 856                         dev_err(dsi->dev, "waiting for bus lanes timed out\n");
 857                         return -EFAULT;
 858                 }
 859
 860                 reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
 861                 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
 862                     != DSIM_STOP_STATE_DAT(lanes_mask))
 863                         continue;
 864         } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
 865
 866         reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
 867         reg &= ~DSIM_STOP_STATE_CNT_MASK;
 868         reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
 869
 870         if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type))
 871                 reg |= DSIM_FORCE_STOP_STATE;
 872
 873         samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg);
 874
 875         reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
 876         samsung_dsim_write(dsi, DSIM_TIMEOUT_REG, reg);
 877
 878         return 0;
 879 }
 880
 881 static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi)
 882 {
 883         struct drm_display_mode *m = &dsi->mode;
 884         unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
 885         u32 reg;
 886
 887         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
 888                 reg = DSIM_CMD_ALLOW(0xf)
 889                         | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay)
 890                         | DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
 891                 samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg);
 892
 893                 reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay)
 894                         | DSIM_MAIN_HBP(m->htotal - m->hsync_end);
 895                 samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg);
 896
 897                 reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
 898                         | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start);
 899                 samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg);
 900         }
 901         reg =  DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |
 902                 DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol);
 903
 904         samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg);
 905
 906         dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay);
 907 }
 908
 909 static void samsung_dsim_set_display_enable(struct samsung_dsim *dsi, bool enable)
 910 {
 911         u32 reg;
 912
 913         reg = samsung_dsim_read(dsi, DSIM_MDRESOL_REG);
 914         if (enable)
 915                 reg |= DSIM_MAIN_STAND_BY;
 916         else
 917                 reg &= ~DSIM_MAIN_STAND_BY;
 918         samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg);
 919 }
 920
 921 static int samsung_dsim_wait_for_hdr_fifo(struct samsung_dsim *dsi)
 922 {
 923         int timeout = 2000;
 924
 925         do {
 926                 u32 reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG);
 927
 928                 if (!(reg & DSIM_SFR_HEADER_FULL))
 929                         return 0;
 930
 931                 if (!cond_resched())
 932                         usleep_range(950, 1050);
 933         } while (--timeout);
 934
 935         return -ETIMEDOUT;
 936 }
 937
 938 static void samsung_dsim_set_cmd_lpm(struct samsung_dsim *dsi, bool lpm)
 939 {
 940         u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
 941
 942         if (lpm)
 943                 v |= DSIM_CMD_LPDT_LP;
 944         else
 945                 v &= ~DSIM_CMD_LPDT_LP;
 946
 947         samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v);
 948 }
 949
 950 static void samsung_dsim_force_bta(struct samsung_dsim *dsi)
 951 {
 952         u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
 953
 954         v |= DSIM_FORCE_BTA;
 955         samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v);
 956 }
 957
 958 static void samsung_dsim_send_to_fifo(struct samsung_dsim *dsi,
 959                                       struct samsung_dsim_transfer *xfer)
 960 {
 961         struct device *dev = dsi->dev;
 962         struct mipi_dsi_packet *pkt = &xfer->packet;
 963         const u8 *payload = pkt->payload + xfer->tx_done;
 964         u16 length = pkt->payload_length - xfer->tx_done;
 965         bool first = !xfer->tx_done;
 966         u32 reg;
 967
 968         dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n",
 969                 xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done);
 970
 971         if (length > DSI_TX_FIFO_SIZE)
 972                 length = DSI_TX_FIFO_SIZE;
 973
 974         xfer->tx_done += length;
 975
 976         /* Send payload */
 977         while (length >= 4) {
 978                 reg = get_unaligned_le32(payload);
 979                 samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg);
 980                 payload += 4;
 981                 length -= 4;
 982         }
 983
 984         reg = 0;
 985         switch (length) {
 986         case 3:
 987                 reg |= payload[2] << 16;
 988                 fallthrough;
 989         case 2:
 990                 reg |= payload[1] << 8;
 991                 fallthrough;
 992         case 1:
 993                 reg |= payload[0];
 994                 samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg);
 995                 break;
 996         }
 997
 998         /* Send packet header */
 999         if (!first)
1000                 return;
1001
1002         reg = get_unaligned_le32(pkt->header);
1003         if (samsung_dsim_wait_for_hdr_fifo(dsi)) {
1004                 dev_err(dev, "waiting for header FIFO timed out\n");
1005                 return;
1006         }
1007
1008         if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
1009                  dsi->state & DSIM_STATE_CMD_LPM)) {
1010                 samsung_dsim_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
1011                 dsi->state ^= DSIM_STATE_CMD_LPM;
1012         }
1013
1014         samsung_dsim_write(dsi, DSIM_PKTHDR_REG, reg);
1015
1016         if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
1017                 samsung_dsim_force_bta(dsi);
1018 }
1019
1020 static void samsung_dsim_read_from_fifo(struct samsung_dsim *dsi,
1021                                         struct samsung_dsim_transfer *xfer)
1022 {
1023         u8 *payload = xfer->rx_payload + xfer->rx_done;
1024         bool first = !xfer->rx_done;
1025         struct device *dev = dsi->dev;
1026         u16 length;
1027         u32 reg;
1028
1029         if (first) {
1030                 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1031
1032                 switch (reg & 0x3f) {
1033                 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1034                 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1035                         if (xfer->rx_len >= 2) {
1036                                 payload[1] = reg >> 16;
1037                                 ++xfer->rx_done;
1038                         }
1039                         fallthrough;
1040                 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1041                 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1042                         payload[0] = reg >> 8;
1043                         ++xfer->rx_done;
1044                         xfer->rx_len = xfer->rx_done;
1045                         xfer->result = 0;
1046                         goto clear_fifo;
1047                 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1048                         dev_err(dev, "DSI Error Report: 0x%04x\n", (reg >> 8) & 0xffff);
1049                         xfer->result = 0;
1050                         goto clear_fifo;
1051                 }
1052
1053                 length = (reg >> 8) & 0xffff;
1054                 if (length > xfer->rx_len) {
1055                         dev_err(dev,
1056                                 "response too long (%u > %u bytes), stripping\n",
1057                                 xfer->rx_len, length);
1058                         length = xfer->rx_len;
1059                 } else if (length < xfer->rx_len) {
1060                         xfer->rx_len = length;
1061                 }
1062         }
1063
1064         length = xfer->rx_len - xfer->rx_done;
1065         xfer->rx_done += length;
1066
1067         /* Receive payload */
1068         while (length >= 4) {
1069                 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1070                 payload[0] = (reg >>  0) & 0xff;
1071                 payload[1] = (reg >>  8) & 0xff;
1072                 payload[2] = (reg >> 16) & 0xff;
1073                 payload[3] = (reg >> 24) & 0xff;
1074                 payload += 4;
1075                 length -= 4;
1076         }
1077
1078         if (length) {
1079                 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1080                 switch (length) {
1081                 case 3:
1082                         payload[2] = (reg >> 16) & 0xff;
1083                         fallthrough;
1084                 case 2:
1085                         payload[1] = (reg >> 8) & 0xff;
1086                         fallthrough;
1087                 case 1:
1088                         payload[0] = reg & 0xff;
1089                 }
1090         }
1091
1092         if (xfer->rx_done == xfer->rx_len)
1093                 xfer->result = 0;
1094
1095 clear_fifo:
1096         length = DSI_RX_FIFO_SIZE / 4;
1097         do {
1098                 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1099                 if (reg == DSI_RX_FIFO_EMPTY)
1100                         break;
1101         } while (--length);
1102 }
1103
1104 static void samsung_dsim_transfer_start(struct samsung_dsim *dsi)
1105 {
1106         unsigned long flags;
1107         struct samsung_dsim_transfer *xfer;
1108         bool start = false;
1109
1110 again:
1111         spin_lock_irqsave(&dsi->transfer_lock, flags);
1112
1113         if (list_empty(&dsi->transfer_list)) {
1114                 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1115                 return;
1116         }
1117
1118         xfer = list_first_entry(&dsi->transfer_list,
1119                                 struct samsung_dsim_transfer, list);
1120
1121         spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1122
1123         if (xfer->packet.payload_length &&
1124             xfer->tx_done == xfer->packet.payload_length)
1125                 /* waiting for RX */
1126                 return;
1127
1128         samsung_dsim_send_to_fifo(dsi, xfer);
1129
1130         if (xfer->packet.payload_length || xfer->rx_len)
1131                 return;
1132
1133         xfer->result = 0;
1134         complete(&xfer->completed);
1135
1136         spin_lock_irqsave(&dsi->transfer_lock, flags);
1137
1138         list_del_init(&xfer->list);
1139         start = !list_empty(&dsi->transfer_list);
1140
1141         spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1142
1143         if (start)
1144                 goto again;
1145 }
1146
1147 static bool samsung_dsim_transfer_finish(struct samsung_dsim *dsi)
1148 {
1149         struct samsung_dsim_transfer *xfer;
1150         unsigned long flags;
1151         bool start = true;
1152
1153         spin_lock_irqsave(&dsi->transfer_lock, flags);
1154
1155         if (list_empty(&dsi->transfer_list)) {
1156                 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1157                 return false;
1158         }
1159
1160         xfer = list_first_entry(&dsi->transfer_list,
1161                                 struct samsung_dsim_transfer, list);
1162
1163         spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1164
1165         dev_dbg(dsi->dev,
1166                 "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n",
1167                 xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len,
1168                 xfer->rx_done);
1169
1170         if (xfer->tx_done != xfer->packet.payload_length)
1171                 return true;
1172
1173         if (xfer->rx_done != xfer->rx_len)
1174                 samsung_dsim_read_from_fifo(dsi, xfer);
1175
1176         if (xfer->rx_done != xfer->rx_len)
1177                 return true;
1178
1179         spin_lock_irqsave(&dsi->transfer_lock, flags);
1180
1181         list_del_init(&xfer->list);
1182         start = !list_empty(&dsi->transfer_list);
1183
1184         spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1185
1186         if (!xfer->rx_len)
1187                 xfer->result = 0;
1188         complete(&xfer->completed);
1189
1190         return start;
1191 }
1192
1193 static void samsung_dsim_remove_transfer(struct samsung_dsim *dsi,
1194                                          struct samsung_dsim_transfer *xfer)
1195 {
1196         unsigned long flags;
1197         bool start;
1198
1199         spin_lock_irqsave(&dsi->transfer_lock, flags);
1200
1201         if (!list_empty(&dsi->transfer_list) &&
1202             xfer == list_first_entry(&dsi->transfer_list,
1203                                      struct samsung_dsim_transfer, list)) {
1204                 list_del_init(&xfer->list);
1205                 start = !list_empty(&dsi->transfer_list);
1206                 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1207                 if (start)
1208                         samsung_dsim_transfer_start(dsi);
1209                 return;
1210         }
1211
1212         list_del_init(&xfer->list);
1213
1214         spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1215 }
1216
1217 static int samsung_dsim_transfer(struct samsung_dsim *dsi,
1218                                  struct samsung_dsim_transfer *xfer)
1219 {
1220         unsigned long flags;
1221         bool stopped;
1222
1223         xfer->tx_done = 0;
1224         xfer->rx_done = 0;
1225         xfer->result = -ETIMEDOUT;
1226         init_completion(&xfer->completed);
1227
1228         spin_lock_irqsave(&dsi->transfer_lock, flags);
1229
1230         stopped = list_empty(&dsi->transfer_list);
1231         list_add_tail(&xfer->list, &dsi->transfer_list);
1232
1233         spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1234
1235         if (stopped)
1236                 samsung_dsim_transfer_start(dsi);
1237
1238         wait_for_completion_timeout(&xfer->completed,
1239                                     msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
1240         if (xfer->result == -ETIMEDOUT) {
1241                 struct mipi_dsi_packet *pkt = &xfer->packet;
1242
1243                 samsung_dsim_remove_transfer(dsi, xfer);
1244                 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header,
1245                         (int)pkt->payload_length, pkt->payload);
1246                 return -ETIMEDOUT;
1247         }
1248
1249         /* Also covers hardware timeout condition */
1250         return xfer->result;
1251 }
1252
1253 static irqreturn_t samsung_dsim_irq(int irq, void *dev_id)
1254 {
1255         struct samsung_dsim *dsi = dev_id;
1256         u32 status;
1257
1258         status = samsung_dsim_read(dsi, DSIM_INTSRC_REG);
1259         if (!status) {
1260                 static unsigned long j;
1261
1262                 if (printk_timed_ratelimit(&j, 500))
1263                         dev_warn(dsi->dev, "spurious interrupt\n");
1264                 return IRQ_HANDLED;
1265         }
1266         samsung_dsim_write(dsi, DSIM_INTSRC_REG, status);
1267
1268         if (status & DSIM_INT_SW_RST_RELEASE) {
1269                 unsigned long mask = ~(DSIM_INT_RX_DONE |
1270                                        DSIM_INT_SFR_FIFO_EMPTY |
1271                                        DSIM_INT_SFR_HDR_FIFO_EMPTY |
1272                                        DSIM_INT_RX_ECC_ERR |
1273                                        DSIM_INT_SW_RST_RELEASE);
1274                 samsung_dsim_write(dsi, DSIM_INTMSK_REG, mask);
1275                 complete(&dsi->completed);
1276                 return IRQ_HANDLED;
1277         }
1278
1279         if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1280                         DSIM_INT_PLL_STABLE)))
1281                 return IRQ_HANDLED;
1282
1283         if (samsung_dsim_transfer_finish(dsi))
1284                 samsung_dsim_transfer_start(dsi);
1285
1286         return IRQ_HANDLED;
1287 }
1288
1289 static void samsung_dsim_enable_irq(struct samsung_dsim *dsi)
1290 {
1291         enable_irq(dsi->irq);
1292
1293         if (dsi->te_gpio)
1294                 enable_irq(gpiod_to_irq(dsi->te_gpio));
1295 }
1296
1297 static void samsung_dsim_disable_irq(struct samsung_dsim *dsi)
1298 {
1299         if (dsi->te_gpio)
1300                 disable_irq(gpiod_to_irq(dsi->te_gpio));
1301
1302         disable_irq(dsi->irq);
1303 }
1304
1305 static int samsung_dsim_init(struct samsung_dsim *dsi)
1306 {
1307         const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
1308
1309         if (dsi->state & DSIM_STATE_INITIALIZED)
1310                 return 0;
1311
1312         samsung_dsim_reset(dsi);
1313         samsung_dsim_enable_irq(dsi);
1314
1315         if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
1316                 samsung_dsim_enable_lane(dsi, BIT(dsi->lanes) - 1);
1317
1318         samsung_dsim_enable_clock(dsi);
1319         if (driver_data->wait_for_reset)
1320                 samsung_dsim_wait_for_reset(dsi);
1321         samsung_dsim_set_phy_ctrl(dsi);
1322         samsung_dsim_init_link(dsi);
1323
1324         dsi->state |= DSIM_STATE_INITIALIZED;
1325
1326         return 0;
1327 }
1328
1329 static void samsung_dsim_atomic_pre_enable(struct drm_bridge *bridge,
1330                                            struct drm_bridge_state *old_bridge_state)
1331 {
1332         struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1333         int ret;
1334
1335         if (dsi->state & DSIM_STATE_ENABLED)
1336                 return;
1337
1338         ret = pm_runtime_resume_and_get(dsi->dev);
1339         if (ret < 0) {
1340                 dev_err(dsi->dev, "failed to enable DSI device.\n");
1341                 return;
1342         }
1343
1344         dsi->state |= DSIM_STATE_ENABLED;
1345
1346         /*
1347          * For Exynos-DSIM the downstream bridge, or panel are expecting
1348          * the host initialization during DSI transfer.
1349          */
1350         if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) {
1351                 ret = samsung_dsim_init(dsi);
1352                 if (ret)
1353                         return;
1354
1355                 samsung_dsim_set_display_mode(dsi);
1356                 samsung_dsim_set_display_enable(dsi, true);
1357         }
1358 }
1359
1360 static void samsung_dsim_atomic_enable(struct drm_bridge *bridge,
1361                                        struct drm_bridge_state *old_bridge_state)
1362 {
1363         struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1364         u32 reg;
1365
1366         if (samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) {
1367                 samsung_dsim_set_display_mode(dsi);
1368                 samsung_dsim_set_display_enable(dsi, true);
1369         } else {
1370                 reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
1371                 reg &= ~DSIM_FORCE_STOP_STATE;
1372                 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg);
1373         }
1374
1375         dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
1376 }
1377
1378 static void samsung_dsim_atomic_disable(struct drm_bridge *bridge,
1379                                         struct drm_bridge_state *old_bridge_state)
1380 {
1381         struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1382         u32 reg;
1383
1384         if (!(dsi->state & DSIM_STATE_ENABLED))
1385                 return;
1386
1387         if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) {
1388                 reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
1389                 reg |= DSIM_FORCE_STOP_STATE;
1390                 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg);
1391         }
1392
1393         dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
1394 }
1395
1396 static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
1397                                              struct drm_bridge_state *old_bridge_state)
1398 {
1399         struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1400
1401         samsung_dsim_set_display_enable(dsi, false);
1402
1403         dsi->state &= ~DSIM_STATE_ENABLED;
1404         pm_runtime_put_sync(dsi->dev);
1405 }
1406
1407 /*
1408  * This pixel output formats list referenced from,
1409  * AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022
1410  * 3.7.4 Pixel formats
1411  * Table 14. DSI pixel packing formats
1412  */
1413 static const u32 samsung_dsim_pixel_output_fmts[] = {
1414         MEDIA_BUS_FMT_YUYV10_1X20,
1415         MEDIA_BUS_FMT_YUYV12_1X24,
1416         MEDIA_BUS_FMT_UYVY8_1X16,
1417         MEDIA_BUS_FMT_RGB101010_1X30,
1418         MEDIA_BUS_FMT_RGB121212_1X36,
1419         MEDIA_BUS_FMT_RGB565_1X16,
1420         MEDIA_BUS_FMT_RGB666_1X18,
1421         MEDIA_BUS_FMT_RGB888_1X24,
1422 };
1423
1424 static bool samsung_dsim_pixel_output_fmt_supported(u32 fmt)
1425 {
1426         int i;
1427
1428         if (fmt == MEDIA_BUS_FMT_FIXED)
1429                 return false;
1430
1431         for (i = 0; i < ARRAY_SIZE(samsung_dsim_pixel_output_fmts); i++) {
1432                 if (samsung_dsim_pixel_output_fmts[i] == fmt)
1433                         return true;
1434         }
1435
1436         return false;
1437 }
1438
1439 static u32 *
1440 samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
1441                                        struct drm_bridge_state *bridge_state,
1442                                        struct drm_crtc_state *crtc_state,
1443                                        struct drm_connector_state *conn_state,
1444                                        u32 output_fmt,
1445                                        unsigned int *num_input_fmts)
1446 {
1447         u32 *input_fmts;
1448
1449         input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
1450         if (!input_fmts)
1451                 return NULL;
1452
1453         if (!samsung_dsim_pixel_output_fmt_supported(output_fmt))
1454                 /*
1455                  * Some bridge/display drivers are still not able to pass the
1456                  * correct format, so handle those pipelines by falling back
1457                  * to the default format till the supported formats finalized.
1458                  */
1459                 output_fmt = MEDIA_BUS_FMT_RGB888_1X24;
1460
1461         input_fmts[0] = output_fmt;
1462         *num_input_fmts = 1;
1463
1464         return input_fmts;
1465 }
1466
1467 static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
1468                                      struct drm_bridge_state *bridge_state,
1469                                      struct drm_crtc_state *crtc_state,
1470                                      struct drm_connector_state *conn_state)
1471 {
1472         struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1473         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1474
1475         /*
1476          * The i.MX8M Mini/Nano glue logic between LCDIF and DSIM
1477          * inverts HS/VS/DE sync signals polarity, therefore, while
1478          * i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020
1479          * 13.6.3.5.2 RGB interface
1480          * i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022
1481          * 13.6.2.7.2 RGB interface
1482          * both claim "Vsync, Hsync, and VDEN are active high signals.", the
1483          * LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW.
1484          *
1485          * The i.MX8M Plus glue logic between LCDIFv3 and DSIM does not
1486          * implement the same behavior, therefore LCDIFv3 must generate
1487          * HS/VS/DE signals active HIGH.
1488          */
1489         if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) {
1490                 adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1491                 adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1492         } else if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MP) {
1493                 adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1494                 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1495         }
1496
1497         return 0;
1498 }
1499
1500 static void samsung_dsim_mode_set(struct drm_bridge *bridge,
1501                                   const struct drm_display_mode *mode,
1502                                   const struct drm_display_mode *adjusted_mode)
1503 {
1504         struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1505
1506         drm_mode_copy(&dsi->mode, adjusted_mode);
1507 }
1508
1509 static int samsung_dsim_attach(struct drm_bridge *bridge,
1510                                enum drm_bridge_attach_flags flags)
1511 {
1512         struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1513
1514         return drm_bridge_attach(bridge->encoder, dsi->out_bridge, bridge,
1515                                  flags);
1516 }
1517
1518 static const struct drm_bridge_funcs samsung_dsim_bridge_funcs = {
1519         .atomic_duplicate_state         = drm_atomic_helper_bridge_duplicate_state,
1520         .atomic_destroy_state           = drm_atomic_helper_bridge_destroy_state,
1521         .atomic_reset                   = drm_atomic_helper_bridge_reset,
1522         .atomic_get_input_bus_fmts      = samsung_dsim_atomic_get_input_bus_fmts,
1523         .atomic_check                   = samsung_dsim_atomic_check,
1524         .atomic_pre_enable              = samsung_dsim_atomic_pre_enable,
1525         .atomic_enable                  = samsung_dsim_atomic_enable,
1526         .atomic_disable                 = samsung_dsim_atomic_disable,
1527         .atomic_post_disable            = samsung_dsim_atomic_post_disable,
1528         .mode_set                       = samsung_dsim_mode_set,
1529         .attach                         = samsung_dsim_attach,
1530 };
1531
1532 static irqreturn_t samsung_dsim_te_irq_handler(int irq, void *dev_id)
1533 {
1534         struct samsung_dsim *dsi = (struct samsung_dsim *)dev_id;
1535         const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
1536
1537         if (pdata->host_ops && pdata->host_ops->te_irq_handler)
1538                 return pdata->host_ops->te_irq_handler(dsi);
1539
1540         return IRQ_HANDLED;
1541 }
1542
1543 static int samsung_dsim_register_te_irq(struct samsung_dsim *dsi, struct device *dev)
1544 {
1545         int te_gpio_irq;
1546         int ret;
1547
1548         dsi->te_gpio = devm_gpiod_get_optional(dev, "te", GPIOD_IN);
1549         if (!dsi->te_gpio)
1550                 return 0;
1551         else if (IS_ERR(dsi->te_gpio))
1552                 return dev_err_probe(dev, PTR_ERR(dsi->te_gpio), "failed to get te GPIO\n");
1553
1554         te_gpio_irq = gpiod_to_irq(dsi->te_gpio);
1555
1556         ret = request_threaded_irq(te_gpio_irq, samsung_dsim_te_irq_handler, NULL,
1557                                    IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, "TE", dsi);
1558         if (ret) {
1559                 dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1560                 gpiod_put(dsi->te_gpio);
1561                 return ret;
1562         }
1563
1564         return 0;
1565 }
1566
1567 static int samsung_dsim_host_attach(struct mipi_dsi_host *host,
1568                                     struct mipi_dsi_device *device)
1569 {
1570         struct samsung_dsim *dsi = host_to_dsi(host);
1571         const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
1572         struct device *dev = dsi->dev;
1573         struct device_node *np = dev->of_node;
1574         struct device_node *remote;
1575         struct drm_panel *panel;
1576         int ret;
1577
1578         /*
1579          * Devices can also be child nodes when we also control that device
1580          * through the upstream device (ie, MIPI-DCS for a MIPI-DSI device).
1581          *
1582          * Lookup for a child node of the given parent that isn't either port
1583          * or ports.
1584          */
1585         for_each_available_child_of_node(np, remote) {
1586                 if (of_node_name_eq(remote, "port") ||
1587                     of_node_name_eq(remote, "ports"))
1588                         continue;
1589
1590                 goto of_find_panel_or_bridge;
1591         }
1592
1593         /*
1594          * of_graph_get_remote_node() produces a noisy error message if port
1595          * node isn't found and the absence of the port is a legit case here,
1596          * so at first we silently check whether graph presents in the
1597          * device-tree node.
1598          */
1599         if (!of_graph_is_present(np))
1600                 return -ENODEV;
1601
1602         remote = of_graph_get_remote_node(np, 1, 0);
1603
1604 of_find_panel_or_bridge:
1605         if (!remote)
1606                 return -ENODEV;
1607
1608         panel = of_drm_find_panel(remote);
1609         if (!IS_ERR(panel)) {
1610                 dsi->out_bridge = devm_drm_panel_bridge_add(dev, panel);
1611         } else {
1612                 dsi->out_bridge = of_drm_find_bridge(remote);
1613                 if (!dsi->out_bridge)
1614                         dsi->out_bridge = ERR_PTR(-EINVAL);
1615         }
1616
1617         of_node_put(remote);
1618
1619         if (IS_ERR(dsi->out_bridge)) {
1620                 ret = PTR_ERR(dsi->out_bridge);
1621                 DRM_DEV_ERROR(dev, "failed to find the bridge: %d\n", ret);
1622                 return ret;
1623         }
1624
1625         DRM_DEV_INFO(dev, "Attached %s device\n", device->name);
1626
1627         drm_bridge_add(&dsi->bridge);
1628
1629         /*
1630          * This is a temporary solution and should be made by more generic way.
1631          *
1632          * If attached panel device is for command mode one, dsi should register
1633          * TE interrupt handler.
1634          */
1635         if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1636                 ret = samsung_dsim_register_te_irq(dsi, &device->dev);
1637                 if (ret)
1638                         return ret;
1639         }
1640
1641         if (pdata->host_ops && pdata->host_ops->attach) {
1642                 ret = pdata->host_ops->attach(dsi, device);
1643                 if (ret)
1644                         return ret;
1645         }
1646
1647         dsi->lanes = device->lanes;
1648         dsi->format = device->format;
1649         dsi->mode_flags = device->mode_flags;
1650
1651         return 0;
1652 }
1653
1654 static void samsung_dsim_unregister_te_irq(struct samsung_dsim *dsi)
1655 {
1656         if (dsi->te_gpio) {
1657                 free_irq(gpiod_to_irq(dsi->te_gpio), dsi);
1658                 gpiod_put(dsi->te_gpio);
1659         }
1660 }
1661
1662 static int samsung_dsim_host_detach(struct mipi_dsi_host *host,
1663                                     struct mipi_dsi_device *device)
1664 {
1665         struct samsung_dsim *dsi = host_to_dsi(host);
1666         const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
1667
1668         dsi->out_bridge = NULL;
1669
1670         if (pdata->host_ops && pdata->host_ops->detach)
1671                 pdata->host_ops->detach(dsi, device);
1672
1673         samsung_dsim_unregister_te_irq(dsi);
1674
1675         drm_bridge_remove(&dsi->bridge);
1676
1677         return 0;
1678 }
1679
1680 static ssize_t samsung_dsim_host_transfer(struct mipi_dsi_host *host,
1681                                           const struct mipi_dsi_msg *msg)
1682 {
1683         struct samsung_dsim *dsi = host_to_dsi(host);
1684         struct samsung_dsim_transfer xfer;
1685         int ret;
1686
1687         if (!(dsi->state & DSIM_STATE_ENABLED))
1688                 return -EINVAL;
1689
1690         ret = samsung_dsim_init(dsi);
1691         if (ret)
1692                 return ret;
1693
1694         ret = mipi_dsi_create_packet(&xfer.packet, msg);
1695         if (ret < 0)
1696                 return ret;
1697
1698         xfer.rx_len = msg->rx_len;
1699         xfer.rx_payload = msg->rx_buf;
1700         xfer.flags = msg->flags;
1701
1702         ret = samsung_dsim_transfer(dsi, &xfer);
1703         return (ret < 0) ? ret : xfer.rx_done;
1704 }
1705
1706 static const struct mipi_dsi_host_ops samsung_dsim_ops = {
1707         .attach = samsung_dsim_host_attach,
1708         .detach = samsung_dsim_host_detach,
1709         .transfer = samsung_dsim_host_transfer,
1710 };
1711
1712 static int samsung_dsim_of_read_u32(const struct device_node *np,
1713                                     const char *propname, u32 *out_value)
1714 {
1715         int ret = of_property_read_u32(np, propname, out_value);
1716
1717         if (ret < 0)
1718                 pr_err("%pOF: failed to get '%s' property\n", np, propname);
1719
1720         return ret;
1721 }
1722
1723 static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
1724 {
1725         struct device *dev = dsi->dev;
1726         struct device_node *node = dev->of_node;
1727         u32 lane_polarities[5] = { 0 };
1728         struct device_node *endpoint;
1729         int i, nr_lanes, ret;
1730
1731         ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
1732                                        &dsi->pll_clk_rate);
1733         if (ret < 0)
1734                 return ret;
1735
1736         ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency",
1737                                        &dsi->burst_clk_rate);
1738         if (ret < 0)
1739                 return ret;
1740
1741         ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency",
1742                                        &dsi->esc_clk_rate);
1743         if (ret < 0)
1744                 return ret;
1745
1746         endpoint = of_graph_get_endpoint_by_regs(node, 1, -1);
1747         nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
1748         if (nr_lanes > 0 && nr_lanes <= 4) {
1749                 /* Polarity 0 is clock lane, 1..4 are data lanes. */
1750                 of_property_read_u32_array(endpoint, "lane-polarities",
1751                                            lane_polarities, nr_lanes + 1);
1752                 for (i = 1; i <= nr_lanes; i++) {
1753                         if (lane_polarities[1] != lane_polarities[i])
1754                                 DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match");
1755                 }
1756                 if (lane_polarities[0])
1757                         dsi->swap_dn_dp_clk = true;
1758                 if (lane_polarities[1])
1759                         dsi->swap_dn_dp_data = true;
1760         }
1761
1762         return 0;
1763 }
1764
1765 static int generic_dsim_register_host(struct samsung_dsim *dsi)
1766 {
1767         return mipi_dsi_host_register(&dsi->dsi_host);
1768 }
1769
1770 static void generic_dsim_unregister_host(struct samsung_dsim *dsi)
1771 {
1772         mipi_dsi_host_unregister(&dsi->dsi_host);
1773 }
1774
1775 static const struct samsung_dsim_host_ops generic_dsim_host_ops = {
1776         .register_host = generic_dsim_register_host,
1777         .unregister_host = generic_dsim_unregister_host,
1778 };
1779
1780 static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_high = {
1781         .input_bus_flags = DRM_BUS_FLAG_DE_HIGH,
1782 };
1783
1784 static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_low = {
1785         .input_bus_flags = DRM_BUS_FLAG_DE_LOW,
1786 };
1787
1788 int samsung_dsim_probe(struct platform_device *pdev)
1789 {
1790         struct device *dev = &pdev->dev;
1791         struct samsung_dsim *dsi;
1792         int ret, i;
1793
1794         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1795         if (!dsi)
1796                 return -ENOMEM;
1797
1798         init_completion(&dsi->completed);
1799         spin_lock_init(&dsi->transfer_lock);
1800         INIT_LIST_HEAD(&dsi->transfer_list);
1801
1802         dsi->dsi_host.ops = &samsung_dsim_ops;
1803         dsi->dsi_host.dev = dev;
1804
1805         dsi->dev = dev;
1806         dsi->plat_data = of_device_get_match_data(dev);
1807         dsi->driver_data = samsung_dsim_types[dsi->plat_data->hw_type];
1808
1809         dsi->supplies[0].supply = "vddcore";
1810         dsi->supplies[1].supply = "vddio";
1811         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
1812                                       dsi->supplies);
1813         if (ret)
1814                 return dev_err_probe(dev, ret, "failed to get regulators\n");
1815
1816         dsi->clks = devm_kcalloc(dev, dsi->driver_data->num_clks,
1817                                  sizeof(*dsi->clks), GFP_KERNEL);
1818         if (!dsi->clks)
1819                 return -ENOMEM;
1820
1821         for (i = 0; i < dsi->driver_data->num_clks; i++) {
1822                 dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
1823                 if (IS_ERR(dsi->clks[i])) {
1824                         if (strcmp(clk_names[i], "sclk_mipi") == 0) {
1825                                 dsi->clks[i] = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME);
1826                                 if (!IS_ERR(dsi->clks[i]))
1827                                         continue;
1828                         }
1829
1830                         dev_info(dev, "failed to get the clock: %s\n", clk_names[i]);
1831                         return PTR_ERR(dsi->clks[i]);
1832                 }
1833         }
1834
1835         dsi->reg_base = devm_platform_ioremap_resource(pdev, 0);
1836         if (IS_ERR(dsi->reg_base))
1837                 return PTR_ERR(dsi->reg_base);
1838
1839         dsi->phy = devm_phy_optional_get(dev, "dsim");
1840         if (IS_ERR(dsi->phy)) {
1841                 dev_info(dev, "failed to get dsim phy\n");
1842                 return PTR_ERR(dsi->phy);
1843         }
1844
1845         dsi->irq = platform_get_irq(pdev, 0);
1846         if (dsi->irq < 0)
1847                 return dsi->irq;
1848
1849         ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
1850                                         samsung_dsim_irq,
1851                                         IRQF_ONESHOT | IRQF_NO_AUTOEN,
1852                                         dev_name(dev), dsi);
1853         if (ret) {
1854                 dev_err(dev, "failed to request dsi irq\n");
1855                 return ret;
1856         }
1857
1858         ret = samsung_dsim_parse_dt(dsi);
1859         if (ret)
1860                 return ret;
1861
1862         platform_set_drvdata(pdev, dsi);
1863
1864         pm_runtime_enable(dev);
1865
1866         dsi->bridge.funcs = &samsung_dsim_bridge_funcs;
1867         dsi->bridge.of_node = dev->of_node;
1868         dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
1869
1870         /* DE_LOW: i.MX8M Mini/Nano LCDIF-DSIM glue logic inverts HS/VS/DE */
1871         if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM)
1872                 dsi->bridge.timings = &samsung_dsim_bridge_timings_de_low;
1873         else
1874                 dsi->bridge.timings = &samsung_dsim_bridge_timings_de_high;
1875
1876         if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->register_host)
1877                 ret = dsi->plat_data->host_ops->register_host(dsi);
1878
1879         if (ret)
1880                 goto err_disable_runtime;
1881
1882         return 0;
1883
1884 err_disable_runtime:
1885         pm_runtime_disable(dev);
1886
1887         return ret;
1888 }
1889 EXPORT_SYMBOL_GPL(samsung_dsim_probe);
1890
1891 int samsung_dsim_remove(struct platform_device *pdev)
1892 {
1893         struct samsung_dsim *dsi = platform_get_drvdata(pdev);
1894
1895         pm_runtime_disable(&pdev->dev);
1896
1897         if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->unregister_host)
1898                 dsi->plat_data->host_ops->unregister_host(dsi);
1899
1900         return 0;
1901 }
1902 EXPORT_SYMBOL_GPL(samsung_dsim_remove);
1903
1904 static int __maybe_unused samsung_dsim_suspend(struct device *dev)
1905 {
1906         struct samsung_dsim *dsi = dev_get_drvdata(dev);
1907         const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
1908         int ret, i;
1909
1910         usleep_range(10000, 20000);
1911
1912         if (dsi->state & DSIM_STATE_INITIALIZED) {
1913                 dsi->state &= ~DSIM_STATE_INITIALIZED;
1914
1915                 samsung_dsim_disable_clock(dsi);
1916
1917                 samsung_dsim_disable_irq(dsi);
1918         }
1919
1920         dsi->state &= ~DSIM_STATE_CMD_LPM;
1921
1922         phy_power_off(dsi->phy);
1923
1924         for (i = driver_data->num_clks - 1; i > -1; i--)
1925                 clk_disable_unprepare(dsi->clks[i]);
1926
1927         ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1928         if (ret < 0)
1929                 dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
1930
1931         return 0;
1932 }
1933
1934 static int __maybe_unused samsung_dsim_resume(struct device *dev)
1935 {
1936         struct samsung_dsim *dsi = dev_get_drvdata(dev);
1937         const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
1938         int ret, i;
1939
1940         ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1941         if (ret < 0) {
1942                 dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
1943                 return ret;
1944         }
1945
1946         for (i = 0; i < driver_data->num_clks; i++) {
1947                 ret = clk_prepare_enable(dsi->clks[i]);
1948                 if (ret < 0)
1949                         goto err_clk;
1950         }
1951
1952         ret = phy_power_on(dsi->phy);
1953         if (ret < 0) {
1954                 dev_err(dsi->dev, "cannot enable phy %d\n", ret);
1955                 goto err_clk;
1956         }
1957
1958         return 0;
1959
1960 err_clk:
1961         while (--i > -1)
1962                 clk_disable_unprepare(dsi->clks[i]);
1963         regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1964
1965         return ret;
1966 }
1967
1968 const struct dev_pm_ops samsung_dsim_pm_ops = {
1969         SET_RUNTIME_PM_OPS(samsung_dsim_suspend, samsung_dsim_resume, NULL)
1970         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1971                                 pm_runtime_force_resume)
1972 };
1973 EXPORT_SYMBOL_GPL(samsung_dsim_pm_ops);
1974
1975 static const struct samsung_dsim_plat_data samsung_dsim_imx8mm_pdata = {
1976         .hw_type = DSIM_TYPE_IMX8MM,
1977         .host_ops = &generic_dsim_host_ops,
1978 };
1979
1980 static const struct samsung_dsim_plat_data samsung_dsim_imx8mp_pdata = {
1981         .hw_type = DSIM_TYPE_IMX8MP,
1982         .host_ops = &generic_dsim_host_ops,
1983 };
1984
1985 static const struct of_device_id samsung_dsim_of_match[] = {
1986         {
1987                 .compatible = "fsl,imx8mm-mipi-dsim",
1988                 .data = &samsung_dsim_imx8mm_pdata,
1989         },
1990         {
1991                 .compatible = "fsl,imx8mp-mipi-dsim",
1992                 .data = &samsung_dsim_imx8mp_pdata,
1993         },
1994         { /* sentinel. */ }
1995 };
1996 MODULE_DEVICE_TABLE(of, samsung_dsim_of_match);
1997
1998 static struct platform_driver samsung_dsim_driver = {
1999         .probe = samsung_dsim_probe,
2000         .remove = samsung_dsim_remove,
2001         .driver = {
2002                    .name = "samsung-dsim",
2003                    .pm = &samsung_dsim_pm_ops,
2004                    .of_match_table = samsung_dsim_of_match,
2005         },
2006 };
2007
2008 module_platform_driver(samsung_dsim_driver);
2009
2010 MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
2011 MODULE_DESCRIPTION("Samsung MIPI DSIM controller bridge");
2012 MODULE_LICENSE("GPL");