drivers/gpu/drm/bridge/nwl-dsi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * i.MX8 NWL MIPI DSI host driver
   4  *
   5  * Copyright (C) 2017 NXP
   6  * Copyright (C) 2020 Purism SPC
   7  */
   8
   9 #include <linux/bitfield.h>
  10 #include <linux/bits.h>
  11 #include <linux/clk.h>
  12 #include <linux/irq.h>
  13 #include <linux/math64.h>
  14 #include <linux/mfd/syscon.h>
  15 #include <linux/module.h>
  16 #include <linux/mux/consumer.h>
  17 #include <linux/of.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/phy/phy.h>
  20 #include <linux/regmap.h>
  21 #include <linux/reset.h>
  22 #include <linux/sys_soc.h>
  23 #include <linux/time64.h>
  24
  25 #include <drm/drm_atomic_state_helper.h>
  26 #include <drm/drm_bridge.h>
  27 #include <drm/drm_mipi_dsi.h>
  28 #include <drm/drm_of.h>
  29 #include <drm/drm_print.h>
  30
  31 #include <video/mipi_display.h>
  32
  33 #include "nwl-dsi.h"
  34
  35 #define DRV_NAME "nwl-dsi"
  36
  37 /* i.MX8 NWL quirks */
  38 /* i.MX8MQ errata E11418 */
  39 #define E11418_HS_MODE_QUIRK    BIT(0)
  40
  41 #define NWL_DSI_MIPI_FIFO_TIMEOUT msecs_to_jiffies(500)
  42
  43 enum transfer_direction {
  44         DSI_PACKET_SEND,
  45         DSI_PACKET_RECEIVE,
  46 };
  47
  48 #define NWL_DSI_ENDPOINT_LCDIF 0
  49 #define NWL_DSI_ENDPOINT_DCSS 1
  50
  51 struct nwl_dsi_transfer {
  52         const struct mipi_dsi_msg *msg;
  53         struct mipi_dsi_packet packet;
  54         struct completion completed;
  55
  56         int status; /* status of transmission */
  57         enum transfer_direction direction;
  58         bool need_bta;
  59         u8 cmd;
  60         u16 rx_word_count;
  61         size_t tx_len; /* in bytes */
  62         size_t rx_len; /* in bytes */
  63 };
  64
  65 struct nwl_dsi {
  66         struct drm_bridge bridge;
  67         struct mipi_dsi_host dsi_host;
  68         struct device *dev;
  69         struct phy *phy;
  70         union phy_configure_opts phy_cfg;
  71         unsigned int quirks;
  72
  73         struct regmap *regmap;
  74         int irq;
  75         /*
  76          * The DSI host controller needs this reset sequence according to NWL:
  77          * 1. Deassert pclk reset to get access to DSI regs
  78          * 2. Configure DSI Host and DPHY and enable DPHY
  79          * 3. Deassert ESC and BYTE resets to allow host TX operations)
  80          * 4. Send DSI cmds to configure peripheral (handled by panel drv)
  81          * 5. Deassert DPI reset so DPI receives pixels and starts sending
  82          *    DSI data
  83          *
  84          * TODO: Since panel_bridges do their DSI setup in enable we
  85          * currently have 4. and 5. swapped.
  86          */
  87         struct reset_control *rst_byte;
  88         struct reset_control *rst_esc;
  89         struct reset_control *rst_dpi;
  90         struct reset_control *rst_pclk;
  91         struct mux_control *mux;
  92
  93         /* DSI clocks */
  94         struct clk *phy_ref_clk;
  95         struct clk *rx_esc_clk;
  96         struct clk *tx_esc_clk;
  97         struct clk *core_clk;
  98         /*
  99          * hardware bug: the i.MX8MQ needs this clock on during reset
 100          * even when not using LCDIF.
 101          */
 102         struct clk *lcdif_clk;
 103
 104         /* dsi lanes */
 105         u32 lanes;
 106         enum mipi_dsi_pixel_format format;
 107         struct drm_display_mode mode;
 108         unsigned long dsi_mode_flags;
 109         int error;
 110
 111         struct nwl_dsi_transfer *xfer;
 112 };
 113
 114 static const struct regmap_config nwl_dsi_regmap_config = {
 115         .reg_bits = 16,
 116         .val_bits = 32,
 117         .reg_stride = 4,
 118         .max_register = NWL_DSI_IRQ_MASK2,
 119         .name = DRV_NAME,
 120 };
 121
 122 static inline struct nwl_dsi *bridge_to_dsi(struct drm_bridge *bridge)
 123 {
 124         return container_of(bridge, struct nwl_dsi, bridge);
 125 }
 126
 127 static int nwl_dsi_clear_error(struct nwl_dsi *dsi)
 128 {
 129         int ret = dsi->error;
 130
 131         dsi->error = 0;
 132         return ret;
 133 }
 134
 135 static void nwl_dsi_write(struct nwl_dsi *dsi, unsigned int reg, u32 val)
 136 {
 137         int ret;
 138
 139         if (dsi->error)
 140                 return;
 141
 142         ret = regmap_write(dsi->regmap, reg, val);
 143         if (ret < 0) {
 144                 DRM_DEV_ERROR(dsi->dev,
 145                               "Failed to write NWL DSI reg 0x%x: %d\n", reg,
 146                               ret);
 147                 dsi->error = ret;
 148         }
 149 }
 150
 151 static u32 nwl_dsi_read(struct nwl_dsi *dsi, u32 reg)
 152 {
 153         unsigned int val;
 154         int ret;
 155
 156         if (dsi->error)
 157                 return 0;
 158
 159         ret = regmap_read(dsi->regmap, reg, &val);
 160         if (ret < 0) {
 161                 DRM_DEV_ERROR(dsi->dev, "Failed to read NWL DSI reg 0x%x: %d\n",
 162                               reg, ret);
 163                 dsi->error = ret;
 164         }
 165         return val;
 166 }
 167
 168 static int nwl_dsi_get_dpi_pixel_format(enum mipi_dsi_pixel_format format)
 169 {
 170         switch (format) {
 171         case MIPI_DSI_FMT_RGB565:
 172                 return NWL_DSI_PIXEL_FORMAT_16;
 173         case MIPI_DSI_FMT_RGB666:
 174                 return NWL_DSI_PIXEL_FORMAT_18L;
 175         case MIPI_DSI_FMT_RGB666_PACKED:
 176                 return NWL_DSI_PIXEL_FORMAT_18;
 177         case MIPI_DSI_FMT_RGB888:
 178                 return NWL_DSI_PIXEL_FORMAT_24;
 179         default:
 180                 return -EINVAL;
 181         }
 182 }
 183
 184 /*
 185  * ps2bc - Picoseconds to byte clock cycles
 186  */
 187 static u32 ps2bc(struct nwl_dsi *dsi, unsigned long long ps)
 188 {
 189         u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 190
 191         return DIV64_U64_ROUND_UP(ps * dsi->mode.clock * bpp,
 192                                   dsi->lanes * 8ULL * NSEC_PER_SEC);
 193 }
 194
 195 /*
 196  * ui2bc - UI time periods to byte clock cycles
 197  */
 198 static u32 ui2bc(unsigned int ui)
 199 {
 200         return DIV_ROUND_UP(ui, BITS_PER_BYTE);
 201 }
 202
 203 /*
 204  * us2bc - micro seconds to lp clock cycles
 205  */
 206 static u32 us2lp(u32 lp_clk_rate, unsigned long us)
 207 {
 208         return DIV_ROUND_UP(us * lp_clk_rate, USEC_PER_SEC);
 209 }
 210
 211 static int nwl_dsi_config_host(struct nwl_dsi *dsi)
 212 {
 213         u32 cycles;
 214         struct phy_configure_opts_mipi_dphy *cfg = &dsi->phy_cfg.mipi_dphy;
 215
 216         if (dsi->lanes < 1 || dsi->lanes > 4)
 217                 return -EINVAL;
 218
 219         DRM_DEV_DEBUG_DRIVER(dsi->dev, "DSI Lanes %d\n", dsi->lanes);
 220         nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1);
 221
 222         if (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
 223                 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x01);
 224                 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x01);
 225         } else {
 226                 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x00);
 227                 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x00);
 228         }
 229
 230         /* values in byte clock cycles */
 231         cycles = ui2bc(cfg->clk_pre);
 232         DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_pre: 0x%x\n", cycles);
 233         nwl_dsi_write(dsi, NWL_DSI_CFG_T_PRE, cycles);
 234         cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero);
 235         DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap (pre): 0x%x\n", cycles);
 236         cycles += ui2bc(cfg->clk_pre);
 237         DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_post: 0x%x\n", cycles);
 238         nwl_dsi_write(dsi, NWL_DSI_CFG_T_POST, cycles);
 239         cycles = ps2bc(dsi, cfg->hs_exit);
 240         DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap: 0x%x\n", cycles);
 241         nwl_dsi_write(dsi, NWL_DSI_CFG_TX_GAP, cycles);
 242
 243         nwl_dsi_write(dsi, NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP, 0x01);
 244         nwl_dsi_write(dsi, NWL_DSI_CFG_HTX_TO_COUNT, 0x00);
 245         nwl_dsi_write(dsi, NWL_DSI_CFG_LRX_H_TO_COUNT, 0x00);
 246         nwl_dsi_write(dsi, NWL_DSI_CFG_BTA_H_TO_COUNT, 0x00);
 247         /* In LP clock cycles */
 248         cycles = us2lp(cfg->lp_clk_rate, cfg->wakeup);
 249         DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_twakeup: 0x%x\n", cycles);
 250         nwl_dsi_write(dsi, NWL_DSI_CFG_TWAKEUP, cycles);
 251
 252         return nwl_dsi_clear_error(dsi);
 253 }
 254
 255 static int nwl_dsi_config_dpi(struct nwl_dsi *dsi)
 256 {
 257         u32 mode;
 258         int color_format;
 259         bool burst_mode;
 260         int hfront_porch, hback_porch, vfront_porch, vback_porch;
 261         int hsync_len, vsync_len;
 262
 263         hfront_porch = dsi->mode.hsync_start - dsi->mode.hdisplay;
 264         hsync_len = dsi->mode.hsync_end - dsi->mode.hsync_start;
 265         hback_porch = dsi->mode.htotal - dsi->mode.hsync_end;
 266
 267         vfront_porch = dsi->mode.vsync_start - dsi->mode.vdisplay;
 268         vsync_len = dsi->mode.vsync_end - dsi->mode.vsync_start;
 269         vback_porch = dsi->mode.vtotal - dsi->mode.vsync_end;
 270
 271         DRM_DEV_DEBUG_DRIVER(dsi->dev, "hfront_porch = %d\n", hfront_porch);
 272         DRM_DEV_DEBUG_DRIVER(dsi->dev, "hback_porch = %d\n", hback_porch);
 273         DRM_DEV_DEBUG_DRIVER(dsi->dev, "hsync_len = %d\n", hsync_len);
 274         DRM_DEV_DEBUG_DRIVER(dsi->dev, "hdisplay = %d\n", dsi->mode.hdisplay);
 275         DRM_DEV_DEBUG_DRIVER(dsi->dev, "vfront_porch = %d\n", vfront_porch);
 276         DRM_DEV_DEBUG_DRIVER(dsi->dev, "vback_porch = %d\n", vback_porch);
 277         DRM_DEV_DEBUG_DRIVER(dsi->dev, "vsync_len = %d\n", vsync_len);
 278         DRM_DEV_DEBUG_DRIVER(dsi->dev, "vactive = %d\n", dsi->mode.vdisplay);
 279         DRM_DEV_DEBUG_DRIVER(dsi->dev, "clock = %d kHz\n", dsi->mode.clock);
 280
 281         color_format = nwl_dsi_get_dpi_pixel_format(dsi->format);
 282         if (color_format < 0) {
 283                 DRM_DEV_ERROR(dsi->dev, "Invalid color format 0x%x\n",
 284                               dsi->format);
 285                 return color_format;
 286         }
 287         DRM_DEV_DEBUG_DRIVER(dsi->dev, "pixel fmt = %d\n", dsi->format);
 288
 289         nwl_dsi_write(dsi, NWL_DSI_INTERFACE_COLOR_CODING, NWL_DSI_DPI_24_BIT);
 290         nwl_dsi_write(dsi, NWL_DSI_PIXEL_FORMAT, color_format);
 291         /*
 292          * Adjusting input polarity based on the video mode results in
 293          * a black screen so always pick active low:
 294          */
 295         nwl_dsi_write(dsi, NWL_DSI_VSYNC_POLARITY,
 296                       NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW);
 297         nwl_dsi_write(dsi, NWL_DSI_HSYNC_POLARITY,
 298                       NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW);
 299
 300         burst_mode = (dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_BURST) &&
 301                      !(dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE);
 302
 303         if (burst_mode) {
 304                 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, NWL_DSI_VM_BURST_MODE);
 305                 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, 256);
 306         } else {
 307                 mode = ((dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) ?
 308                                 NWL_DSI_VM_BURST_MODE_WITH_SYNC_PULSES :
 309                                 NWL_DSI_VM_NON_BURST_MODE_WITH_SYNC_EVENTS);
 310                 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, mode);
 311                 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL,
 312                               dsi->mode.hdisplay);
 313         }
 314
 315         nwl_dsi_write(dsi, NWL_DSI_HFP, hfront_porch);
 316         nwl_dsi_write(dsi, NWL_DSI_HBP, hback_porch);
 317         nwl_dsi_write(dsi, NWL_DSI_HSA, hsync_len);
 318
 319         nwl_dsi_write(dsi, NWL_DSI_ENABLE_MULT_PKTS, 0x0);
 320         nwl_dsi_write(dsi, NWL_DSI_BLLP_MODE, 0x1);
 321         nwl_dsi_write(dsi, NWL_DSI_USE_NULL_PKT_BLLP, 0x0);
 322         nwl_dsi_write(dsi, NWL_DSI_VC, 0x0);
 323
 324         nwl_dsi_write(dsi, NWL_DSI_PIXEL_PAYLOAD_SIZE, dsi->mode.hdisplay);
 325         nwl_dsi_write(dsi, NWL_DSI_VACTIVE, dsi->mode.vdisplay - 1);
 326         nwl_dsi_write(dsi, NWL_DSI_VBP, vback_porch);
 327         nwl_dsi_write(dsi, NWL_DSI_VFP, vfront_porch);
 328
 329         return nwl_dsi_clear_error(dsi);
 330 }
 331
 332 static int nwl_dsi_init_interrupts(struct nwl_dsi *dsi)
 333 {
 334         u32 irq_enable = ~(u32)(NWL_DSI_TX_PKT_DONE_MASK |
 335                                 NWL_DSI_RX_PKT_HDR_RCVD_MASK |
 336                                 NWL_DSI_TX_FIFO_OVFLW_MASK |
 337                                 NWL_DSI_HS_TX_TIMEOUT_MASK);
 338
 339         nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, irq_enable);
 340         nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK2, 0x7);
 341
 342         return nwl_dsi_clear_error(dsi);
 343 }
 344
 345 static int nwl_dsi_host_attach(struct mipi_dsi_host *dsi_host,
 346                                struct mipi_dsi_device *device)
 347 {
 348         struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host);
 349         struct device *dev = dsi->dev;
 350
 351         DRM_DEV_INFO(dev, "lanes=%u, format=0x%x flags=0x%lx\n", device->lanes,
 352                      device->format, device->mode_flags);
 353
 354         if (device->lanes < 1 || device->lanes > 4)
 355                 return -EINVAL;
 356
 357         dsi->lanes = device->lanes;
 358         dsi->format = device->format;
 359         dsi->dsi_mode_flags = device->mode_flags;
 360
 361         return 0;
 362 }
 363
 364 static bool nwl_dsi_read_packet(struct nwl_dsi *dsi, u32 status)
 365 {
 366         struct device *dev = dsi->dev;
 367         struct nwl_dsi_transfer *xfer = dsi->xfer;
 368         int err;
 369         u8 *payload = xfer->msg->rx_buf;
 370         u32 val;
 371         u16 word_count;
 372         u8 channel;
 373         u8 data_type;
 374
 375         xfer->status = 0;
 376
 377         if (xfer->rx_word_count == 0) {
 378                 if (!(status & NWL_DSI_RX_PKT_HDR_RCVD))
 379                         return false;
 380                 /* Get the RX header and parse it */
 381                 val = nwl_dsi_read(dsi, NWL_DSI_RX_PKT_HEADER);
 382                 err = nwl_dsi_clear_error(dsi);
 383                 if (err)
 384                         xfer->status = err;
 385                 word_count = NWL_DSI_WC(val);
 386                 channel = NWL_DSI_RX_VC(val);
 387                 data_type = NWL_DSI_RX_DT(val);
 388
 389                 if (channel != xfer->msg->channel) {
 390                         DRM_DEV_ERROR(dev,
 391                                       "[%02X] Channel mismatch (%u != %u)\n",
 392                                       xfer->cmd, channel, xfer->msg->channel);
 393                         xfer->status = -EINVAL;
 394                         return true;
 395                 }
 396
 397                 switch (data_type) {
 398                 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
 399                 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
 400                         if (xfer->msg->rx_len > 1) {
 401                                 /* read second byte */
 402                                 payload[1] = word_count >> 8;
 403                                 ++xfer->rx_len;
 404                         }
 405                         fallthrough;
 406                 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
 407                 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
 408                         if (xfer->msg->rx_len > 0) {
 409                                 /* read first byte */
 410                                 payload[0] = word_count & 0xff;
 411                                 ++xfer->rx_len;
 412                         }
 413                         xfer->status = xfer->rx_len;
 414                         return true;
 415                 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
 416                         word_count &= 0xff;
 417                         DRM_DEV_ERROR(dev, "[%02X] DSI error report: 0x%02x\n",
 418                                       xfer->cmd, word_count);
 419                         xfer->status = -EPROTO;
 420                         return true;
 421                 }
 422
 423                 if (word_count > xfer->msg->rx_len) {
 424                         DRM_DEV_ERROR(dev,
 425                                 "[%02X] Receive buffer too small: %zu (< %u)\n",
 426                                 xfer->cmd, xfer->msg->rx_len, word_count);
 427                         xfer->status = -EINVAL;
 428                         return true;
 429                 }
 430
 431                 xfer->rx_word_count = word_count;
 432         } else {
 433                 /* Set word_count from previous header read */
 434                 word_count = xfer->rx_word_count;
 435         }
 436
 437         /* If RX payload is not yet received, wait for it */
 438         if (!(status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD))
 439                 return false;
 440
 441         /* Read the RX payload */
 442         while (word_count >= 4) {
 443                 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD);
 444                 payload[0] = (val >> 0) & 0xff;
 445                 payload[1] = (val >> 8) & 0xff;
 446                 payload[2] = (val >> 16) & 0xff;
 447                 payload[3] = (val >> 24) & 0xff;
 448                 payload += 4;
 449                 xfer->rx_len += 4;
 450                 word_count -= 4;
 451         }
 452
 453         if (word_count > 0) {
 454                 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD);
 455                 switch (word_count) {
 456                 case 3:
 457                         payload[2] = (val >> 16) & 0xff;
 458                         ++xfer->rx_len;
 459                         fallthrough;
 460                 case 2:
 461                         payload[1] = (val >> 8) & 0xff;
 462                         ++xfer->rx_len;
 463                         fallthrough;
 464                 case 1:
 465                         payload[0] = (val >> 0) & 0xff;
 466                         ++xfer->rx_len;
 467                         break;
 468                 }
 469         }
 470
 471         xfer->status = xfer->rx_len;
 472         err = nwl_dsi_clear_error(dsi);
 473         if (err)
 474                 xfer->status = err;
 475
 476         return true;
 477 }
 478
 479 static void nwl_dsi_finish_transmission(struct nwl_dsi *dsi, u32 status)
 480 {
 481         struct nwl_dsi_transfer *xfer = dsi->xfer;
 482         bool end_packet = false;
 483
 484         if (!xfer)
 485                 return;
 486
 487         if (xfer->direction == DSI_PACKET_SEND &&
 488             status & NWL_DSI_TX_PKT_DONE) {
 489                 xfer->status = xfer->tx_len;
 490                 end_packet = true;
 491         } else if (status & NWL_DSI_DPHY_DIRECTION &&
 492                    ((status & (NWL_DSI_RX_PKT_HDR_RCVD |
 493                                NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)))) {
 494                 end_packet = nwl_dsi_read_packet(dsi, status);
 495         }
 496
 497         if (end_packet)
 498                 complete(&xfer->completed);
 499 }
 500
 501 static void nwl_dsi_begin_transmission(struct nwl_dsi *dsi)
 502 {
 503         struct nwl_dsi_transfer *xfer = dsi->xfer;
 504         struct mipi_dsi_packet *pkt = &xfer->packet;
 505         const u8 *payload;
 506         size_t length;
 507         u16 word_count;
 508         u8 hs_mode;
 509         u32 val;
 510         u32 hs_workaround = 0;
 511
 512         /* Send the payload, if any */
 513         length = pkt->payload_length;
 514         payload = pkt->payload;
 515
 516         while (length >= 4) {
 517                 val = *(u32 *)payload;
 518                 hs_workaround |= !(val & 0xFFFF00);
 519                 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
 520                 payload += 4;
 521                 length -= 4;
 522         }
 523         /* Send the rest of the payload */
 524         val = 0;
 525         switch (length) {
 526         case 3:
 527                 val |= payload[2] << 16;
 528                 fallthrough;
 529         case 2:
 530                 val |= payload[1] << 8;
 531                 hs_workaround |= !(val & 0xFFFF00);
 532                 fallthrough;
 533         case 1:
 534                 val |= payload[0];
 535                 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
 536                 break;
 537         }
 538         xfer->tx_len = pkt->payload_length;
 539
 540         /*
 541          * Send the header
 542          * header[0] = Virtual Channel + Data Type
 543          * header[1] = Word Count LSB (LP) or first param (SP)
 544          * header[2] = Word Count MSB (LP) or second param (SP)
 545          */
 546         word_count = pkt->header[1] | (pkt->header[2] << 8);
 547         if (hs_workaround && (dsi->quirks & E11418_HS_MODE_QUIRK)) {
 548                 DRM_DEV_DEBUG_DRIVER(dsi->dev,
 549                                      "Using hs mode workaround for cmd 0x%x\n",
 550                                      xfer->cmd);
 551                 hs_mode = 1;
 552         } else {
 553                 hs_mode = (xfer->msg->flags & MIPI_DSI_MSG_USE_LPM) ? 0 : 1;
 554         }
 555         val = NWL_DSI_WC(word_count) | NWL_DSI_TX_VC(xfer->msg->channel) |
 556               NWL_DSI_TX_DT(xfer->msg->type) | NWL_DSI_HS_SEL(hs_mode) |
 557               NWL_DSI_BTA_TX(xfer->need_bta);
 558         nwl_dsi_write(dsi, NWL_DSI_PKT_CONTROL, val);
 559
 560         /* Send packet command */
 561         nwl_dsi_write(dsi, NWL_DSI_SEND_PACKET, 0x1);
 562 }
 563
 564 static ssize_t nwl_dsi_host_transfer(struct mipi_dsi_host *dsi_host,
 565                                      const struct mipi_dsi_msg *msg)
 566 {
 567         struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host);
 568         struct nwl_dsi_transfer xfer;
 569         ssize_t ret = 0;
 570
 571         /* Create packet to be sent */
 572         dsi->xfer = &xfer;
 573         ret = mipi_dsi_create_packet(&xfer.packet, msg);
 574         if (ret < 0) {
 575                 dsi->xfer = NULL;
 576                 return ret;
 577         }
 578
 579         if ((msg->type & MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM ||
 580              msg->type & MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM ||
 581              msg->type & MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM ||
 582              msg->type & MIPI_DSI_DCS_READ) &&
 583             msg->rx_len > 0 && msg->rx_buf)
 584                 xfer.direction = DSI_PACKET_RECEIVE;
 585         else
 586                 xfer.direction = DSI_PACKET_SEND;
 587
 588         xfer.need_bta = (xfer.direction == DSI_PACKET_RECEIVE);
 589         xfer.need_bta |= (msg->flags & MIPI_DSI_MSG_REQ_ACK) ? 1 : 0;
 590         xfer.msg = msg;
 591         xfer.status = -ETIMEDOUT;
 592         xfer.rx_word_count = 0;
 593         xfer.rx_len = 0;
 594         xfer.cmd = 0x00;
 595         if (msg->tx_len > 0)
 596                 xfer.cmd = ((u8 *)(msg->tx_buf))[0];
 597         init_completion(&xfer.completed);
 598
 599         ret = clk_prepare_enable(dsi->rx_esc_clk);
 600         if (ret < 0) {
 601                 DRM_DEV_ERROR(dsi->dev, "Failed to enable rx_esc clk: %zd\n",
 602                               ret);
 603                 return ret;
 604         }
 605         DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled rx_esc clk @%lu Hz\n",
 606                              clk_get_rate(dsi->rx_esc_clk));
 607
 608         /* Initiate the DSI packet transmision */
 609         nwl_dsi_begin_transmission(dsi);
 610
 611         if (!wait_for_completion_timeout(&xfer.completed,
 612                                          NWL_DSI_MIPI_FIFO_TIMEOUT)) {
 613                 DRM_DEV_ERROR(dsi_host->dev, "[%02X] DSI transfer timed out\n",
 614                               xfer.cmd);
 615                 ret = -ETIMEDOUT;
 616         } else {
 617                 ret = xfer.status;
 618         }
 619
 620         clk_disable_unprepare(dsi->rx_esc_clk);
 621
 622         return ret;
 623 }
 624
 625 static const struct mipi_dsi_host_ops nwl_dsi_host_ops = {
 626         .attach = nwl_dsi_host_attach,
 627         .transfer = nwl_dsi_host_transfer,
 628 };
 629
 630 static irqreturn_t nwl_dsi_irq_handler(int irq, void *data)
 631 {
 632         u32 irq_status;
 633         struct nwl_dsi *dsi = data;
 634
 635         irq_status = nwl_dsi_read(dsi, NWL_DSI_IRQ_STATUS);
 636
 637         if (irq_status & NWL_DSI_TX_FIFO_OVFLW)
 638                 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "tx fifo overflow\n");
 639
 640         if (irq_status & NWL_DSI_HS_TX_TIMEOUT)
 641                 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "HS tx timeout\n");
 642
 643         if (irq_status & NWL_DSI_TX_PKT_DONE ||
 644             irq_status & NWL_DSI_RX_PKT_HDR_RCVD ||
 645             irq_status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)
 646                 nwl_dsi_finish_transmission(dsi, irq_status);
 647
 648         return IRQ_HANDLED;
 649 }
 650
 651 static int nwl_dsi_mode_set(struct nwl_dsi *dsi)
 652 {
 653         struct device *dev = dsi->dev;
 654         union phy_configure_opts *phy_cfg = &dsi->phy_cfg;
 655         int ret;
 656
 657         if (!dsi->lanes) {
 658                 DRM_DEV_ERROR(dev, "Need DSI lanes: %d\n", dsi->lanes);
 659                 return -EINVAL;
 660         }
 661
 662         ret = phy_init(dsi->phy);
 663         if (ret < 0) {
 664                 DRM_DEV_ERROR(dev, "Failed to init DSI phy: %d\n", ret);
 665                 return ret;
 666         }
 667
 668         ret = phy_configure(dsi->phy, phy_cfg);
 669         if (ret < 0) {
 670                 DRM_DEV_ERROR(dev, "Failed to configure DSI phy: %d\n", ret);
 671                 goto uninit_phy;
 672         }
 673
 674         ret = clk_prepare_enable(dsi->tx_esc_clk);
 675         if (ret < 0) {
 676                 DRM_DEV_ERROR(dsi->dev, "Failed to enable tx_esc clk: %d\n",
 677                               ret);
 678                 goto uninit_phy;
 679         }
 680         DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled tx_esc clk @%lu Hz\n",
 681                              clk_get_rate(dsi->tx_esc_clk));
 682
 683         ret = nwl_dsi_config_host(dsi);
 684         if (ret < 0) {
 685                 DRM_DEV_ERROR(dev, "Failed to set up DSI: %d", ret);
 686                 goto disable_clock;
 687         }
 688
 689         ret = nwl_dsi_config_dpi(dsi);
 690         if (ret < 0) {
 691                 DRM_DEV_ERROR(dev, "Failed to set up DPI: %d", ret);
 692                 goto disable_clock;
 693         }
 694
 695         ret = phy_power_on(dsi->phy);
 696         if (ret < 0) {
 697                 DRM_DEV_ERROR(dev, "Failed to power on DPHY (%d)\n", ret);
 698                 goto disable_clock;
 699         }
 700
 701         ret = nwl_dsi_init_interrupts(dsi);
 702         if (ret < 0)
 703                 goto power_off_phy;
 704
 705         return ret;
 706
 707 power_off_phy:
 708         phy_power_off(dsi->phy);
 709 disable_clock:
 710         clk_disable_unprepare(dsi->tx_esc_clk);
 711 uninit_phy:
 712         phy_exit(dsi->phy);
 713
 714         return ret;
 715 }
 716
 717 static int nwl_dsi_disable(struct nwl_dsi *dsi)
 718 {
 719         struct device *dev = dsi->dev;
 720
 721         DRM_DEV_DEBUG_DRIVER(dev, "Disabling clocks and phy\n");
 722
 723         phy_power_off(dsi->phy);
 724         phy_exit(dsi->phy);
 725
 726         /* Disabling the clock before the phy breaks enabling dsi again */
 727         clk_disable_unprepare(dsi->tx_esc_clk);
 728
 729         return 0;
 730 }
 731
 732 static void
 733 nwl_dsi_bridge_atomic_disable(struct drm_bridge *bridge,
 734                               struct drm_bridge_state *old_bridge_state)
 735 {
 736         struct nwl_dsi *dsi = bridge_to_dsi(bridge);
 737         int ret;
 738
 739         nwl_dsi_disable(dsi);
 740
 741         ret = reset_control_assert(dsi->rst_dpi);
 742         if (ret < 0) {
 743                 DRM_DEV_ERROR(dsi->dev, "Failed to assert DPI: %d\n", ret);
 744                 return;
 745         }
 746         ret = reset_control_assert(dsi->rst_byte);
 747         if (ret < 0) {
 748                 DRM_DEV_ERROR(dsi->dev, "Failed to assert ESC: %d\n", ret);
 749                 return;
 750         }
 751         ret = reset_control_assert(dsi->rst_esc);
 752         if (ret < 0) {
 753                 DRM_DEV_ERROR(dsi->dev, "Failed to assert BYTE: %d\n", ret);
 754                 return;
 755         }
 756         ret = reset_control_assert(dsi->rst_pclk);
 757         if (ret < 0) {
 758                 DRM_DEV_ERROR(dsi->dev, "Failed to assert PCLK: %d\n", ret);
 759                 return;
 760         }
 761
 762         clk_disable_unprepare(dsi->core_clk);
 763         clk_disable_unprepare(dsi->lcdif_clk);
 764
 765         pm_runtime_put(dsi->dev);
 766 }
 767
 768 static int nwl_dsi_get_dphy_params(struct nwl_dsi *dsi,
 769                                    const struct drm_display_mode *mode,
 770                                    union phy_configure_opts *phy_opts)
 771 {
 772         unsigned long rate;
 773         int ret;
 774
 775         if (dsi->lanes < 1 || dsi->lanes > 4)
 776                 return -EINVAL;
 777
 778         /*
 779          * So far the DPHY spec minimal timings work for both mixel
 780          * dphy and nwl dsi host
 781          */
 782         ret = phy_mipi_dphy_get_default_config(mode->clock * 1000,
 783                 mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes,
 784                 &phy_opts->mipi_dphy);
 785         if (ret < 0)
 786                 return ret;
 787
 788         rate = clk_get_rate(dsi->tx_esc_clk);
 789         DRM_DEV_DEBUG_DRIVER(dsi->dev, "LP clk is @%lu Hz\n", rate);
 790         phy_opts->mipi_dphy.lp_clk_rate = rate;
 791
 792         return 0;
 793 }
 794
 795 static enum drm_mode_status
 796 nwl_dsi_bridge_mode_valid(struct drm_bridge *bridge,
 797                           const struct drm_display_info *info,
 798                           const struct drm_display_mode *mode)
 799 {
 800         struct nwl_dsi *dsi = bridge_to_dsi(bridge);
 801         int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
 802
 803         if (mode->clock * bpp > 15000000 * dsi->lanes)
 804                 return MODE_CLOCK_HIGH;
 805
 806         if (mode->clock * bpp < 80000 * dsi->lanes)
 807                 return MODE_CLOCK_LOW;
 808
 809         return MODE_OK;
 810 }
 811
 812 static int nwl_dsi_bridge_atomic_check(struct drm_bridge *bridge,
 813                                        struct drm_bridge_state *bridge_state,
 814                                        struct drm_crtc_state *crtc_state,
 815                                        struct drm_connector_state *conn_state)
 816 {
 817         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
 818
 819         /* At least LCDIF + NWL needs active high sync */
 820         adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
 821         adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
 822
 823         /*
 824          * Do a full modeset if crtc_state->active is changed to be true.
 825          * This ensures our ->mode_set() is called to get the DSI controller
 826          * and the PHY ready to send DCS commands, when only the connector's
 827          * DPMS is brought out of "Off" status.
 828          */
 829         if (crtc_state->active_changed && crtc_state->active)
 830                 crtc_state->mode_changed = true;
 831
 832         return 0;
 833 }
 834
 835 static void
 836 nwl_dsi_bridge_mode_set(struct drm_bridge *bridge,
 837                         const struct drm_display_mode *mode,
 838                         const struct drm_display_mode *adjusted_mode)
 839 {
 840         struct nwl_dsi *dsi = bridge_to_dsi(bridge);
 841         struct device *dev = dsi->dev;
 842         union phy_configure_opts new_cfg;
 843         unsigned long phy_ref_rate;
 844         int ret;
 845
 846         ret = nwl_dsi_get_dphy_params(dsi, adjusted_mode, &new_cfg);
 847         if (ret < 0)
 848                 return;
 849
 850         phy_ref_rate = clk_get_rate(dsi->phy_ref_clk);
 851         DRM_DEV_DEBUG_DRIVER(dev, "PHY at ref rate: %lu\n", phy_ref_rate);
 852         /* Save the new desired phy config */
 853         memcpy(&dsi->phy_cfg, &new_cfg, sizeof(new_cfg));
 854
 855         drm_mode_copy(&dsi->mode, adjusted_mode);
 856         drm_mode_debug_printmodeline(adjusted_mode);
 857
 858         if (pm_runtime_resume_and_get(dev) < 0)
 859                 return;
 860
 861         if (clk_prepare_enable(dsi->lcdif_clk) < 0)
 862                 goto runtime_put;
 863         if (clk_prepare_enable(dsi->core_clk) < 0)
 864                 goto runtime_put;
 865
 866         /* Step 1 from DSI reset-out instructions */
 867         ret = reset_control_deassert(dsi->rst_pclk);
 868         if (ret < 0) {
 869                 DRM_DEV_ERROR(dev, "Failed to deassert PCLK: %d\n", ret);
 870                 goto runtime_put;
 871         }
 872
 873         /* Step 2 from DSI reset-out instructions */
 874         nwl_dsi_mode_set(dsi);
 875
 876         /* Step 3 from DSI reset-out instructions */
 877         ret = reset_control_deassert(dsi->rst_esc);
 878         if (ret < 0) {
 879                 DRM_DEV_ERROR(dev, "Failed to deassert ESC: %d\n", ret);
 880                 goto runtime_put;
 881         }
 882         ret = reset_control_deassert(dsi->rst_byte);
 883         if (ret < 0) {
 884                 DRM_DEV_ERROR(dev, "Failed to deassert BYTE: %d\n", ret);
 885                 goto runtime_put;
 886         }
 887
 888         return;
 889
 890 runtime_put:
 891         pm_runtime_put_sync(dev);
 892 }
 893
 894 static void
 895 nwl_dsi_bridge_atomic_enable(struct drm_bridge *bridge,
 896                              struct drm_bridge_state *old_bridge_state)
 897 {
 898         struct nwl_dsi *dsi = bridge_to_dsi(bridge);
 899         int ret;
 900
 901         /* Step 5 from DSI reset-out instructions */
 902         ret = reset_control_deassert(dsi->rst_dpi);
 903         if (ret < 0)
 904                 DRM_DEV_ERROR(dsi->dev, "Failed to deassert DPI: %d\n", ret);
 905 }
 906
 907 static int nwl_dsi_bridge_attach(struct drm_bridge *bridge,
 908                                  enum drm_bridge_attach_flags flags)
 909 {
 910         struct nwl_dsi *dsi = bridge_to_dsi(bridge);
 911         struct drm_bridge *panel_bridge;
 912
 913         panel_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node, 1, 0);
 914         if (IS_ERR(panel_bridge))
 915                 return PTR_ERR(panel_bridge);
 916
 917         return drm_bridge_attach(bridge->encoder, panel_bridge, bridge, flags);
 918 }
 919
 920 static u32 *nwl_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
 921                                                  struct drm_bridge_state *bridge_state,
 922                                                  struct drm_crtc_state *crtc_state,
 923                                                  struct drm_connector_state *conn_state,
 924                                                  u32 output_fmt,
 925                                                  unsigned int *num_input_fmts)
 926 {
 927         u32 *input_fmts, input_fmt;
 928
 929         *num_input_fmts = 0;
 930
 931         switch (output_fmt) {
 932         /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */
 933         case MEDIA_BUS_FMT_FIXED:
 934                 input_fmt = MEDIA_BUS_FMT_RGB888_1X24;
 935                 break;
 936         case MEDIA_BUS_FMT_RGB888_1X24:
 937         case MEDIA_BUS_FMT_RGB666_1X18:
 938         case MEDIA_BUS_FMT_RGB565_1X16:
 939                 input_fmt = output_fmt;
 940                 break;
 941         default:
 942                 return NULL;
 943         }
 944
 945         input_fmts = kcalloc(1, sizeof(*input_fmts), GFP_KERNEL);
 946         if (!input_fmts)
 947                 return NULL;
 948         input_fmts[0] = input_fmt;
 949         *num_input_fmts = 1;
 950
 951         return input_fmts;
 952 }
 953
 954 static const struct drm_bridge_funcs nwl_dsi_bridge_funcs = {
 955         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
 956         .atomic_destroy_state   = drm_atomic_helper_bridge_destroy_state,
 957         .atomic_reset           = drm_atomic_helper_bridge_reset,
 958         .atomic_check           = nwl_dsi_bridge_atomic_check,
 959         .atomic_enable          = nwl_dsi_bridge_atomic_enable,
 960         .atomic_disable         = nwl_dsi_bridge_atomic_disable,
 961         .atomic_get_input_bus_fmts = nwl_bridge_atomic_get_input_bus_fmts,
 962         .mode_set               = nwl_dsi_bridge_mode_set,
 963         .mode_valid             = nwl_dsi_bridge_mode_valid,
 964         .attach                 = nwl_dsi_bridge_attach,
 965 };
 966
 967 static int nwl_dsi_parse_dt(struct nwl_dsi *dsi)
 968 {
 969         struct platform_device *pdev = to_platform_device(dsi->dev);
 970         struct clk *clk;
 971         void __iomem *base;
 972         int ret;
 973
 974         dsi->phy = devm_phy_get(dsi->dev, "dphy");
 975         if (IS_ERR(dsi->phy)) {
 976                 ret = PTR_ERR(dsi->phy);
 977                 if (ret != -EPROBE_DEFER)
 978                         DRM_DEV_ERROR(dsi->dev, "Could not get PHY: %d\n", ret);
 979                 return ret;
 980         }
 981
 982         clk = devm_clk_get(dsi->dev, "lcdif");
 983         if (IS_ERR(clk)) {
 984                 ret = PTR_ERR(clk);
 985                 DRM_DEV_ERROR(dsi->dev, "Failed to get lcdif clock: %d\n",
 986                               ret);
 987                 return ret;
 988         }
 989         dsi->lcdif_clk = clk;
 990
 991         clk = devm_clk_get(dsi->dev, "core");
 992         if (IS_ERR(clk)) {
 993                 ret = PTR_ERR(clk);
 994                 DRM_DEV_ERROR(dsi->dev, "Failed to get core clock: %d\n",
 995                               ret);
 996                 return ret;
 997         }
 998         dsi->core_clk = clk;
 999
1000         clk = devm_clk_get(dsi->dev, "phy_ref");
1001         if (IS_ERR(clk)) {
1002                 ret = PTR_ERR(clk);
1003                 DRM_DEV_ERROR(dsi->dev, "Failed to get phy_ref clock: %d\n",
1004                               ret);
1005                 return ret;
1006         }
1007         dsi->phy_ref_clk = clk;
1008
1009         clk = devm_clk_get(dsi->dev, "rx_esc");
1010         if (IS_ERR(clk)) {
1011                 ret = PTR_ERR(clk);
1012                 DRM_DEV_ERROR(dsi->dev, "Failed to get rx_esc clock: %d\n",
1013                               ret);
1014                 return ret;
1015         }
1016         dsi->rx_esc_clk = clk;
1017
1018         clk = devm_clk_get(dsi->dev, "tx_esc");
1019         if (IS_ERR(clk)) {
1020                 ret = PTR_ERR(clk);
1021                 DRM_DEV_ERROR(dsi->dev, "Failed to get tx_esc clock: %d\n",
1022                               ret);
1023                 return ret;
1024         }
1025         dsi->tx_esc_clk = clk;
1026
1027         dsi->mux = devm_mux_control_get(dsi->dev, NULL);
1028         if (IS_ERR(dsi->mux)) {
1029                 ret = PTR_ERR(dsi->mux);
1030                 if (ret != -EPROBE_DEFER)
1031                         DRM_DEV_ERROR(dsi->dev, "Failed to get mux: %d\n", ret);
1032                 return ret;
1033         }
1034
1035         base = devm_platform_ioremap_resource(pdev, 0);
1036         if (IS_ERR(base))
1037                 return PTR_ERR(base);
1038
1039         dsi->regmap =
1040                 devm_regmap_init_mmio(dsi->dev, base, &nwl_dsi_regmap_config);
1041         if (IS_ERR(dsi->regmap)) {
1042                 ret = PTR_ERR(dsi->regmap);
1043                 DRM_DEV_ERROR(dsi->dev, "Failed to create NWL DSI regmap: %d\n",
1044                               ret);
1045                 return ret;
1046         }
1047
1048         dsi->irq = platform_get_irq(pdev, 0);
1049         if (dsi->irq < 0) {
1050                 DRM_DEV_ERROR(dsi->dev, "Failed to get device IRQ: %d\n",
1051                               dsi->irq);
1052                 return dsi->irq;
1053         }
1054
1055         dsi->rst_pclk = devm_reset_control_get_exclusive(dsi->dev, "pclk");
1056         if (IS_ERR(dsi->rst_pclk)) {
1057                 DRM_DEV_ERROR(dsi->dev, "Failed to get pclk reset: %ld\n",
1058                               PTR_ERR(dsi->rst_pclk));
1059                 return PTR_ERR(dsi->rst_pclk);
1060         }
1061         dsi->rst_byte = devm_reset_control_get_exclusive(dsi->dev, "byte");
1062         if (IS_ERR(dsi->rst_byte)) {
1063                 DRM_DEV_ERROR(dsi->dev, "Failed to get byte reset: %ld\n",
1064                               PTR_ERR(dsi->rst_byte));
1065                 return PTR_ERR(dsi->rst_byte);
1066         }
1067         dsi->rst_esc = devm_reset_control_get_exclusive(dsi->dev, "esc");
1068         if (IS_ERR(dsi->rst_esc)) {
1069                 DRM_DEV_ERROR(dsi->dev, "Failed to get esc reset: %ld\n",
1070                               PTR_ERR(dsi->rst_esc));
1071                 return PTR_ERR(dsi->rst_esc);
1072         }
1073         dsi->rst_dpi = devm_reset_control_get_exclusive(dsi->dev, "dpi");
1074         if (IS_ERR(dsi->rst_dpi)) {
1075                 DRM_DEV_ERROR(dsi->dev, "Failed to get dpi reset: %ld\n",
1076                               PTR_ERR(dsi->rst_dpi));
1077                 return PTR_ERR(dsi->rst_dpi);
1078         }
1079         return 0;
1080 }
1081
1082 static int nwl_dsi_select_input(struct nwl_dsi *dsi)
1083 {
1084         struct device_node *remote;
1085         u32 use_dcss = 1;
1086         int ret;
1087
1088         remote = of_graph_get_remote_node(dsi->dev->of_node, 0,
1089                                           NWL_DSI_ENDPOINT_LCDIF);
1090         if (remote) {
1091                 use_dcss = 0;
1092         } else {
1093                 remote = of_graph_get_remote_node(dsi->dev->of_node, 0,
1094                                                   NWL_DSI_ENDPOINT_DCSS);
1095                 if (!remote) {
1096                         DRM_DEV_ERROR(dsi->dev,
1097                                       "No valid input endpoint found\n");
1098                         return -EINVAL;
1099                 }
1100         }
1101
1102         DRM_DEV_INFO(dsi->dev, "Using %s as input source\n",
1103                      (use_dcss) ? "DCSS" : "LCDIF");
1104         ret = mux_control_try_select(dsi->mux, use_dcss);
1105         if (ret < 0)
1106                 DRM_DEV_ERROR(dsi->dev, "Failed to select input: %d\n", ret);
1107
1108         of_node_put(remote);
1109         return ret;
1110 }
1111
1112 static int nwl_dsi_deselect_input(struct nwl_dsi *dsi)
1113 {
1114         int ret;
1115
1116         ret = mux_control_deselect(dsi->mux);
1117         if (ret < 0)
1118                 DRM_DEV_ERROR(dsi->dev, "Failed to deselect input: %d\n", ret);
1119
1120         return ret;
1121 }
1122
1123 static const struct drm_bridge_timings nwl_dsi_timings = {
1124         .input_bus_flags = DRM_BUS_FLAG_DE_LOW,
1125 };
1126
1127 static const struct of_device_id nwl_dsi_dt_ids[] = {
1128         { .compatible = "fsl,imx8mq-nwl-dsi", },
1129         { /* sentinel */ }
1130 };
1131 MODULE_DEVICE_TABLE(of, nwl_dsi_dt_ids);
1132
1133 static const struct soc_device_attribute nwl_dsi_quirks_match[] = {
1134         { .soc_id = "i.MX8MQ", .revision = "2.0",
1135           .data = (void *)E11418_HS_MODE_QUIRK },
1136         { /* sentinel. */ }
1137 };
1138
1139 static int nwl_dsi_probe(struct platform_device *pdev)
1140 {
1141         struct device *dev = &pdev->dev;
1142         const struct soc_device_attribute *attr;
1143         struct nwl_dsi *dsi;
1144         int ret;
1145
1146         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1147         if (!dsi)
1148                 return -ENOMEM;
1149
1150         dsi->dev = dev;
1151
1152         ret = nwl_dsi_parse_dt(dsi);
1153         if (ret)
1154                 return ret;
1155
1156         ret = devm_request_irq(dev, dsi->irq, nwl_dsi_irq_handler, 0,
1157                                dev_name(dev), dsi);
1158         if (ret < 0) {
1159                 DRM_DEV_ERROR(dev, "Failed to request IRQ %d: %d\n", dsi->irq,
1160                               ret);
1161                 return ret;
1162         }
1163
1164         dsi->dsi_host.ops = &nwl_dsi_host_ops;
1165         dsi->dsi_host.dev = dev;
1166         ret = mipi_dsi_host_register(&dsi->dsi_host);
1167         if (ret) {
1168                 DRM_DEV_ERROR(dev, "Failed to register MIPI host: %d\n", ret);
1169                 return ret;
1170         }
1171
1172         attr = soc_device_match(nwl_dsi_quirks_match);
1173         if (attr)
1174                 dsi->quirks = (uintptr_t)attr->data;
1175
1176         dsi->bridge.driver_private = dsi;
1177         dsi->bridge.funcs = &nwl_dsi_bridge_funcs;
1178         dsi->bridge.of_node = dev->of_node;
1179         dsi->bridge.timings = &nwl_dsi_timings;
1180
1181         dev_set_drvdata(dev, dsi);
1182         pm_runtime_enable(dev);
1183
1184         ret = nwl_dsi_select_input(dsi);
1185         if (ret < 0) {
1186                 pm_runtime_disable(dev);
1187                 mipi_dsi_host_unregister(&dsi->dsi_host);
1188                 return ret;
1189         }
1190
1191         drm_bridge_add(&dsi->bridge);
1192         return 0;
1193 }
1194
1195 static int nwl_dsi_remove(struct platform_device *pdev)
1196 {
1197         struct nwl_dsi *dsi = platform_get_drvdata(pdev);
1198
1199         nwl_dsi_deselect_input(dsi);
1200         mipi_dsi_host_unregister(&dsi->dsi_host);
1201         drm_bridge_remove(&dsi->bridge);
1202         pm_runtime_disable(&pdev->dev);
1203         return 0;
1204 }
1205
1206 static struct platform_driver nwl_dsi_driver = {
1207         .probe          = nwl_dsi_probe,
1208         .remove         = nwl_dsi_remove,
1209         .driver         = {
1210                 .of_match_table = nwl_dsi_dt_ids,
1211                 .name   = DRV_NAME,
1212         },
1213 };
1214
1215 module_platform_driver(nwl_dsi_driver);
1216
1217 MODULE_AUTHOR("NXP Semiconductor");
1218 MODULE_AUTHOR("Purism SPC");
1219 MODULE_DESCRIPTION("Northwest Logic MIPI-DSI driver");
1220 MODULE_LICENSE("GPL"); /* GPLv2 or later */