1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved.
7 #include <linux/gpio/consumer.h>
9 #include <linux/interrupt.h>
10 #include <linux/iopoll.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/mutex.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/slab.h>
17 #include <linux/types.h>
18 #include <linux/workqueue.h>
20 #include <linux/of_gpio.h>
21 #include <linux/of_graph.h>
22 #include <linux/of_platform.h>
24 #include <drm/display/drm_dp_aux_bus.h>
25 #include <drm/display/drm_dp_helper.h>
26 #include <drm/display/drm_hdcp_helper.h>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_bridge.h>
29 #include <drm/drm_crtc_helper.h>
30 #include <drm/drm_edid.h>
31 #include <drm/drm_mipi_dsi.h>
32 #include <drm/drm_of.h>
33 #include <drm/drm_panel.h>
34 #include <drm/drm_print.h>
35 #include <drm/drm_probe_helper.h>
37 #include <media/v4l2-fwnode.h>
38 #include <sound/hdmi-codec.h>
39 #include <video/display_timing.h>
44 * There is a sync issue while access I2C register between AP(CPU) and
45 * internal firmware(OCM), to avoid the race condition, AP should access
46 * the reserved slave address before slave address occurs changes.
48 static int i2c_access_workaround(struct anx7625_data *ctx,
49 struct i2c_client *client)
52 struct device *dev = &client->dev;
55 if (client == ctx->last_client)
58 ctx->last_client = client;
60 if (client == ctx->i2c.tcpc_client)
61 offset = RSVD_00_ADDR;
62 else if (client == ctx->i2c.tx_p0_client)
63 offset = RSVD_D1_ADDR;
64 else if (client == ctx->i2c.tx_p1_client)
65 offset = RSVD_60_ADDR;
66 else if (client == ctx->i2c.rx_p0_client)
67 offset = RSVD_39_ADDR;
68 else if (client == ctx->i2c.rx_p1_client)
69 offset = RSVD_7F_ADDR;
71 offset = RSVD_00_ADDR;
73 ret = i2c_smbus_write_byte_data(client, offset, 0x00);
76 "fail to access i2c id=%x\n:%x",
77 client->addr, offset);
82 static int anx7625_reg_read(struct anx7625_data *ctx,
83 struct i2c_client *client, u8 reg_addr)
86 struct device *dev = &client->dev;
88 i2c_access_workaround(ctx, client);
90 ret = i2c_smbus_read_byte_data(client, reg_addr);
92 DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n",
93 client->addr, reg_addr);
98 static int anx7625_reg_block_read(struct anx7625_data *ctx,
99 struct i2c_client *client,
100 u8 reg_addr, u8 len, u8 *buf)
103 struct device *dev = &client->dev;
105 i2c_access_workaround(ctx, client);
107 ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf);
109 DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n",
110 client->addr, reg_addr);
115 static int anx7625_reg_write(struct anx7625_data *ctx,
116 struct i2c_client *client,
117 u8 reg_addr, u8 reg_val)
120 struct device *dev = &client->dev;
122 i2c_access_workaround(ctx, client);
124 ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val);
127 DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x",
128 client->addr, reg_addr);
133 static int anx7625_reg_block_write(struct anx7625_data *ctx,
134 struct i2c_client *client,
135 u8 reg_addr, u8 len, u8 *buf)
138 struct device *dev = &client->dev;
140 i2c_access_workaround(ctx, client);
142 ret = i2c_smbus_write_i2c_block_data(client, reg_addr, len, buf);
144 dev_err(dev, "write i2c block failed id=%x\n:%x",
145 client->addr, reg_addr);
150 static int anx7625_write_or(struct anx7625_data *ctx,
151 struct i2c_client *client,
156 val = anx7625_reg_read(ctx, client, offset);
160 return anx7625_reg_write(ctx, client, offset, (val | (mask)));
163 static int anx7625_write_and(struct anx7625_data *ctx,
164 struct i2c_client *client,
169 val = anx7625_reg_read(ctx, client, offset);
173 return anx7625_reg_write(ctx, client, offset, (val & (mask)));
176 static int anx7625_write_and_or(struct anx7625_data *ctx,
177 struct i2c_client *client,
178 u8 offset, u8 and_mask, u8 or_mask)
182 val = anx7625_reg_read(ctx, client, offset);
186 return anx7625_reg_write(ctx, client,
187 offset, (val & and_mask) | (or_mask));
190 static int anx7625_config_bit_matrix(struct anx7625_data *ctx)
194 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client,
195 AUDIO_CONTROL_REGISTER, 0x80);
196 for (i = 0; i < 13; i++)
197 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
198 VIDEO_BIT_MATRIX_12 + i,
204 static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx)
206 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS);
209 static int wait_aux_op_finish(struct anx7625_data *ctx)
211 struct device *dev = &ctx->client->dev;
215 ret = readx_poll_timeout(anx7625_read_ctrl_status_p0,
217 (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)),
221 DRM_DEV_ERROR(dev, "aux operation fail!\n");
225 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
227 if (val < 0 || (val & 0x0F)) {
228 DRM_DEV_ERROR(dev, "aux status %02x\n", val);
235 static int anx7625_aux_trans(struct anx7625_data *ctx, u8 op, u32 address,
238 struct device *dev = &ctx->client->dev;
240 u8 addrh, addrm, addrl;
242 bool is_write = !(op & DP_AUX_I2C_READ);
244 if (len > DP_AUX_MAX_PAYLOAD_BYTES) {
245 dev_err(dev, "exceed aux buffer len.\n");
252 addrl = address & 0xFF;
253 addrm = (address >> 8) & 0xFF;
254 addrh = (address >> 16) & 0xFF;
257 op &= ~DP_AUX_I2C_MOT;
258 cmd = DPCD_CMD(len, op);
260 /* Set command and length */
261 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
262 AP_AUX_COMMAND, cmd);
264 /* Set aux access address */
265 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
266 AP_AUX_ADDR_7_0, addrl);
267 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
268 AP_AUX_ADDR_15_8, addrm);
269 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
270 AP_AUX_ADDR_19_16, addrh);
273 ret |= anx7625_reg_block_write(ctx, ctx->i2c.rx_p0_client,
274 AP_AUX_BUFF_START, len, buf);
275 /* Enable aux access */
276 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
277 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
280 dev_err(dev, "cannot access aux related register.\n");
284 ret = wait_aux_op_finish(ctx);
286 dev_err(dev, "aux IO error: wait aux op finish.\n");
294 /* Read done, read out dpcd data */
295 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
296 AP_AUX_BUFF_START, len, buf);
298 dev_err(dev, "read dpcd register failed\n");
305 static int anx7625_video_mute_control(struct anx7625_data *ctx,
311 /* Set mute on flag */
312 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
313 AP_AV_STATUS, AP_MIPI_MUTE);
314 /* Clear mipi RX en */
315 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
316 AP_AV_STATUS, (u8)~AP_MIPI_RX_EN);
319 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
320 AP_AV_STATUS, (u8)~AP_MIPI_MUTE);
322 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
323 AP_AV_STATUS, AP_MIPI_RX_EN);
329 /* Reduction of fraction a/b */
330 static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b)
332 unsigned long gcd_num;
333 unsigned long tmp_a, tmp_b;
336 gcd_num = gcd(*a, *b);
343 while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) {
350 * In the end, make a, b larger to have higher ODFC PLL
351 * output frequency accuracy
353 while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) {
362 static int anx7625_calculate_m_n(u32 pixelclock,
367 if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) {
368 /* Pixel clock frequency is too high */
369 DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n",
371 PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN);
375 if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) {
376 /* Pixel clock frequency is too low */
377 DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n",
379 PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX);
383 for (*post_divider = 1;
384 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));)
387 if (*post_divider > POST_DIVIDER_MAX) {
388 for (*post_divider = 1;
390 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));)
393 if (*post_divider > POST_DIVIDER_MAX) {
394 DRM_ERROR("cannot find property post_divider(%d)\n",
400 /* Patch to improve the accuracy */
401 if (*post_divider == 7) {
402 /* 27,000,000 is not divisible by 7 */
404 } else if (*post_divider == 11) {
405 /* 27,000,000 is not divisible by 11 */
407 } else if ((*post_divider == 13) || (*post_divider == 14)) {
408 /* 27,000,000 is not divisible by 13 or 14 */
412 if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) {
413 DRM_ERROR("act clock(%u) large than maximum(%lu)\n",
414 pixelclock * (*post_divider),
415 PLL_OUT_FREQ_ABS_MAX);
420 *n = XTAL_FRQ / (*post_divider);
422 anx7625_reduction_of_a_fraction(m, n);
427 static int anx7625_odfc_config(struct anx7625_data *ctx,
431 struct device *dev = &ctx->client->dev;
433 /* Config input reference clock frequency 27MHz/19.2MHz */
434 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16,
435 ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND));
436 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16,
437 (REF_CLK_27000KHZ << MIPI_FREF_D_IND));
439 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client,
440 MIPI_DIGITAL_PLL_8, 0x0f);
441 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8,
444 /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */
445 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
446 ~MIPI_PLL_VCO_TUNE_REG_VAL);
449 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
451 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
455 DRM_DEV_ERROR(dev, "IO error.\n");
461 * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz),
462 * anx7625 defined K ratio for matching MIPI input video clock and
463 * DP output video clock. Increase K value can match bigger video data
464 * variation. IVO panel has small variation than DP CTS spec, need
465 * decrease the K value.
467 static int anx7625_set_k_value(struct anx7625_data *ctx)
469 struct edid *edid = (struct edid *)ctx->slimport_edid_p.edid_raw_data;
471 if (edid->mfg_id[0] == IVO_MID0 && edid->mfg_id[1] == IVO_MID1)
472 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
473 MIPI_DIGITAL_ADJ_1, 0x3B);
475 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
476 MIPI_DIGITAL_ADJ_1, 0x3D);
479 static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx)
481 struct device *dev = &ctx->client->dev;
487 ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000,
488 &m, &n, &post_divider);
491 DRM_DEV_ERROR(dev, "cannot get property m n value.\n");
495 DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n",
498 /* Configure pixel clock */
499 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L,
500 (ctx->dt.pixelclock.min / 1000) & 0xFF);
501 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H,
502 (ctx->dt.pixelclock.min / 1000) >> 8);
504 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client,
505 MIPI_LANE_CTRL_0, 0xfc);
506 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client,
507 MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1);
510 htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min +
511 ctx->dt.hback_porch.min + ctx->dt.hsync_len.min;
512 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
513 HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF);
514 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
515 HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8);
517 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
518 HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF);
519 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
520 HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8);
522 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
523 HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min);
524 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
525 HORIZONTAL_FRONT_PORCH_H,
526 ctx->dt.hfront_porch.min >> 8);
528 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
529 HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min);
530 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
531 HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8);
533 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
534 HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min);
535 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
536 HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8);
538 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L,
539 ctx->dt.vactive.min);
540 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H,
541 ctx->dt.vactive.min >> 8);
543 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
544 VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min);
546 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
547 VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min);
549 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
550 VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min);
552 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
553 MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff);
554 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
555 MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff);
556 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
557 MIPI_PLL_M_NUM_7_0, (m & 0xff));
559 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
560 MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff);
561 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
562 MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff);
563 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0,
566 anx7625_set_k_value(ctx);
568 ret |= anx7625_odfc_config(ctx, post_divider - 1);
571 DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n");
576 static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx)
579 struct device *dev = &ctx->client->dev;
581 /* Swap MIPI-DSI data lane 3 P and N */
582 val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP);
584 DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n");
588 val |= (1 << MIPI_SWAP_CH3);
589 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val);
592 static int anx7625_api_dsi_config(struct anx7625_data *ctx)
596 struct device *dev = &ctx->client->dev;
598 /* Swap MIPI-DSI data lane 3 P and N */
599 ret = anx7625_swap_dsi_lane3(ctx);
601 DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n");
605 /* DSI clock settings */
606 val = (0 << MIPI_HS_PWD_CLK) |
607 (0 << MIPI_HS_RT_CLK) |
609 (1 << MIPI_CLK_RT_MANUAL_PD_EN) |
610 (1 << MIPI_CLK_HS_MANUAL_PD_EN) |
611 (0 << MIPI_CLK_DET_DET_BYPASS) |
612 (0 << MIPI_CLK_MISS_CTRL) |
613 (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN);
614 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
615 MIPI_PHY_CONTROL_3, val);
618 * Decreased HS prepare timing delay from 160ns to 80ns work with
619 * a) Dragon board 810 series (Qualcomm AP)
620 * b) Moving Pixel DSI source (PG3A pattern generator +
621 * P332 D-PHY Probe) default D-PHY timing
624 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
625 MIPI_TIME_HS_PRPR, 0x10);
628 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18,
629 SELECT_DSI << MIPI_DPI_SELECT);
631 ret |= anx7625_dsi_video_timing_config(ctx);
633 DRM_DEV_ERROR(dev, "dsi video timing config fail\n");
637 /* Toggle m, n ready */
638 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6,
639 ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY));
640 usleep_range(1000, 1100);
641 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6,
642 MIPI_M_NUM_READY | MIPI_N_NUM_READY);
644 /* Configure integer stable register */
645 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
646 MIPI_VIDEO_STABLE_CNT, 0x02);
647 /* Power on MIPI RX */
648 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
649 MIPI_LANE_CTRL_10, 0x00);
650 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
651 MIPI_LANE_CTRL_10, 0x80);
654 DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n");
659 static int anx7625_dsi_config(struct anx7625_data *ctx)
661 struct device *dev = &ctx->client->dev;
664 DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n");
667 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
668 R_DSC_CTRL_0, ~DSC_EN);
670 ret |= anx7625_api_dsi_config(ctx);
673 DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n");
678 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
679 AP_AV_STATUS, AP_MIPI_RX_EN);
680 /* Clear mute flag */
681 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
682 AP_AV_STATUS, (u8)~AP_MIPI_MUTE);
684 DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n");
686 DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n");
691 static int anx7625_api_dpi_config(struct anx7625_data *ctx)
693 struct device *dev = &ctx->client->dev;
694 u16 freq = ctx->dt.pixelclock.min / 1000;
697 /* configure pixel clock */
698 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
699 PIXEL_CLOCK_L, freq & 0xFF);
700 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
701 PIXEL_CLOCK_H, (freq >> 8));
704 /* set to DPI PLL module sel */
705 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
706 MIPI_DIGITAL_PLL_9, 0x20);
707 /* power down MIPI */
708 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
709 MIPI_LANE_CTRL_10, 0x08);
710 /* enable DPI mode */
711 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
712 MIPI_DIGITAL_PLL_18, 0x1C);
714 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
715 VIDEO_CONTROL_0, 0x06);
717 DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n");
722 static int anx7625_dpi_config(struct anx7625_data *ctx)
724 struct device *dev = &ctx->client->dev;
727 DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n");
730 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
731 R_DSC_CTRL_0, ~DSC_EN);
733 DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n");
737 ret = anx7625_config_bit_matrix(ctx);
739 DRM_DEV_ERROR(dev, "config bit matrix failed.\n");
743 ret = anx7625_api_dpi_config(ctx);
745 DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n");
750 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
751 AP_AV_STATUS, AP_MIPI_RX_EN);
752 /* clear mute flag */
753 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
754 AP_AV_STATUS, (u8)~AP_MIPI_MUTE);
756 DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n");
761 static int anx7625_read_flash_status(struct anx7625_data *ctx)
763 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL);
766 static int anx7625_hdcp_key_probe(struct anx7625_data *ctx)
769 struct device *dev = &ctx->client->dev;
770 u8 ident[FLASH_BUF_LEN];
772 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
773 FLASH_ADDR_HIGH, 0x91);
774 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
775 FLASH_ADDR_LOW, 0xA0);
777 dev_err(dev, "IO error : set key flash address.\n");
781 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
782 FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8);
783 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
784 FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF);
786 dev_err(dev, "IO error : set key flash len.\n");
790 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
791 R_FLASH_RW_CTRL, FLASH_READ);
792 ret |= readx_poll_timeout(anx7625_read_flash_status,
794 ((val & FLASH_DONE) || (val < 0)),
798 dev_err(dev, "flash read access fail!\n");
802 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
804 FLASH_BUF_LEN, ident);
806 dev_err(dev, "read flash data fail!\n");
810 if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xFF)
816 static int anx7625_hdcp_key_load(struct anx7625_data *ctx)
819 struct device *dev = &ctx->client->dev;
821 /* Select HDCP 1.4 KEY */
822 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
824 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
825 FLASH_ADDR_HIGH, HDCP14KEY_START_ADDR >> 8);
826 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
827 FLASH_ADDR_LOW, HDCP14KEY_START_ADDR & 0xFF);
828 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
829 R_RAM_LEN_H, HDCP14KEY_SIZE >> 12);
830 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
831 R_RAM_LEN_L, HDCP14KEY_SIZE >> 4);
833 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
835 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
837 /* Enable HDCP 1.4 KEY load */
838 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
839 R_RAM_CTRL, DECRYPT_EN | LOAD_START);
840 dev_dbg(dev, "load HDCP 1.4 key done\n");
844 static int anx7625_hdcp_disable(struct anx7625_data *ctx)
847 struct device *dev = &ctx->client->dev;
849 dev_dbg(dev, "disable HDCP 1.4\n");
852 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
854 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
855 /* Interrupt for DRM */
856 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
858 dev_err(dev, "fail to disable HDCP\n");
860 return anx7625_write_and(ctx, ctx->i2c.tx_p0_client,
861 TX_HDCP_CTRL0, ~HARD_AUTH_EN & 0xFF);
864 static int anx7625_hdcp_enable(struct anx7625_data *ctx)
868 struct device *dev = &ctx->client->dev;
870 ret = anx7625_hdcp_key_probe(ctx);
872 dev_dbg(dev, "no key found, not to do hdcp\n");
876 /* Read downstream capability */
877 ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_READ, 0x68028, 1, &bcap);
881 if (!(bcap & 0x01)) {
882 pr_warn("downstream not support HDCP 1.4, cap(%x).\n", bcap);
886 dev_dbg(dev, "enable HDCP 1.4\n");
888 /* First clear HDCP state */
889 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
891 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN);
892 usleep_range(1000, 1100);
893 /* Second clear HDCP state */
894 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
896 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN);
898 /* Set time for waiting KSVR */
899 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
900 SP_TX_WAIT_KSVR_TIME, 0xc8);
901 /* Set time for waiting R0 */
902 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
903 SP_TX_WAIT_R0_TIME, 0xb0);
904 ret |= anx7625_hdcp_key_load(ctx);
906 pr_warn("prepare HDCP key failed.\n");
910 ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20);
913 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
914 /* Interrupt for DRM */
915 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
917 dev_err(dev, "fail to enable HDCP\n");
919 return anx7625_write_or(ctx, ctx->i2c.tx_p0_client,
920 TX_HDCP_CTRL0, HARD_AUTH_EN);
923 static void anx7625_dp_start(struct anx7625_data *ctx)
926 struct device *dev = &ctx->client->dev;
929 if (!ctx->display_timing_valid) {
930 DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n");
934 dev_dbg(dev, "set downstream sink into normal\n");
935 /* Downstream sink enter into normal mode */
937 ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, 0x000600, 1, &data);
939 dev_err(dev, "IO error : set sink into normal mode fail\n");
942 anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
944 if (ctx->pdata.is_dpi)
945 ret = anx7625_dpi_config(ctx);
947 ret = anx7625_dsi_config(ctx);
950 DRM_DEV_ERROR(dev, "MIPI phy setup error.\n");
952 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
957 static void anx7625_dp_stop(struct anx7625_data *ctx)
959 struct device *dev = &ctx->client->dev;
963 DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n");
966 * Video disable: 0x72:08 bit 7 = 0;
967 * Audio disable: 0x70:87 bit 0 = 0;
969 ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe);
970 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f);
972 ret |= anx7625_video_mute_control(ctx, 1);
974 dev_dbg(dev, "notify downstream enter into standby\n");
975 /* Downstream monitor enter into standby mode */
977 ret |= anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, 0x000600, 1, &data);
979 DRM_DEV_ERROR(dev, "IO error : mute video fail\n");
981 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
986 static int sp_tx_rst_aux(struct anx7625_data *ctx)
990 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2,
992 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2,
997 static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset)
1001 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1002 AP_AUX_BUFF_START, offset);
1003 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1004 AP_AUX_COMMAND, 0x04);
1005 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
1006 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
1007 return (ret | wait_aux_op_finish(ctx));
1010 static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd)
1014 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1015 AP_AUX_COMMAND, len_cmd);
1016 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
1017 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
1018 return (ret | wait_aux_op_finish(ctx));
1021 static int sp_tx_get_edid_block(struct anx7625_data *ctx)
1024 struct device *dev = &ctx->client->dev;
1026 sp_tx_aux_wr(ctx, 0x7e);
1027 sp_tx_aux_rd(ctx, 0x01);
1028 c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START);
1030 DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n");
1034 DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1);
1036 if (c > MAX_EDID_BLOCK)
1042 static int edid_read(struct anx7625_data *ctx,
1043 u8 offset, u8 *pblock_buf)
1046 struct device *dev = &ctx->client->dev;
1048 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) {
1049 sp_tx_aux_wr(ctx, offset);
1050 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */
1051 ret = sp_tx_aux_rd(ctx, 0xf1);
1054 ret = sp_tx_rst_aux(ctx);
1055 DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n");
1057 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
1059 MAX_DPCD_BUFFER_SIZE,
1066 if (cnt > EDID_TRY_CNT)
1072 static int segments_edid_read(struct anx7625_data *ctx,
1073 u8 segment, u8 *buf, u8 offset)
1077 struct device *dev = &ctx->client->dev;
1079 /* Write address only */
1080 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1081 AP_AUX_ADDR_7_0, 0x30);
1082 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1083 AP_AUX_COMMAND, 0x04);
1084 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1086 AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN);
1088 ret |= wait_aux_op_finish(ctx);
1089 /* Write segment address */
1090 ret |= sp_tx_aux_wr(ctx, segment);
1092 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1093 AP_AUX_ADDR_7_0, 0x50);
1095 DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n");
1099 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) {
1100 sp_tx_aux_wr(ctx, offset);
1101 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */
1102 ret = sp_tx_aux_rd(ctx, 0xf1);
1105 ret = sp_tx_rst_aux(ctx);
1106 DRM_DEV_ERROR(dev, "segment read fail, reset!\n");
1108 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
1110 MAX_DPCD_BUFFER_SIZE, buf);
1116 if (cnt > EDID_TRY_CNT)
1122 static int sp_tx_edid_read(struct anx7625_data *ctx,
1123 u8 *pedid_blocks_buf)
1127 int count, blocks_num;
1128 u8 pblock_buf[MAX_DPCD_BUFFER_SIZE];
1130 int g_edid_break = 0;
1132 struct device *dev = &ctx->client->dev;
1134 /* Address initial */
1135 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1136 AP_AUX_ADDR_7_0, 0x50);
1137 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1138 AP_AUX_ADDR_15_8, 0);
1139 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
1140 AP_AUX_ADDR_19_16, 0xf0);
1142 DRM_DEV_ERROR(dev, "access aux channel IO error.\n");
1146 blocks_num = sp_tx_get_edid_block(ctx);
1156 for (i = 0; i < 8; i++) {
1157 offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE;
1158 g_edid_break = edid_read(ctx, offset,
1161 if (g_edid_break < 0)
1164 memcpy(&pedid_blocks_buf[offset],
1166 MAX_DPCD_BUFFER_SIZE);
1173 for (j = 0; j < 8; j++) {
1174 edid_pos = (j + count * 8) *
1175 MAX_DPCD_BUFFER_SIZE;
1177 if (g_edid_break == 1)
1180 ret = segments_edid_read(ctx, count / 2,
1181 pblock_buf, offset);
1185 memcpy(&pedid_blocks_buf[edid_pos],
1187 MAX_DPCD_BUFFER_SIZE);
1188 offset = offset + 0x10;
1195 for (j = 0; j < 8; j++) {
1196 edid_pos = (j + count * 8) *
1197 MAX_DPCD_BUFFER_SIZE;
1198 if (g_edid_break == 1)
1201 ret = segments_edid_read(ctx, count / 2,
1202 pblock_buf, offset);
1206 memcpy(&pedid_blocks_buf[edid_pos],
1208 MAX_DPCD_BUFFER_SIZE);
1209 offset = offset + 0x10;
1219 } while (blocks_num >= count);
1221 /* Check edid data */
1222 if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) {
1223 DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n");
1227 /* Reset aux channel */
1228 ret = sp_tx_rst_aux(ctx);
1230 DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n");
1234 return (blocks_num + 1);
1237 static void anx7625_power_on(struct anx7625_data *ctx)
1239 struct device *dev = &ctx->client->dev;
1242 if (!ctx->pdata.low_power_mode) {
1243 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n");
1247 for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) {
1248 ret = regulator_enable(ctx->pdata.supplies[i].consumer);
1250 DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n",
1254 usleep_range(2000, 2100);
1257 usleep_range(11000, 12000);
1259 /* Power on pin enable */
1260 gpiod_set_value(ctx->pdata.gpio_p_on, 1);
1261 usleep_range(10000, 11000);
1262 /* Power reset pin enable */
1263 gpiod_set_value(ctx->pdata.gpio_reset, 1);
1264 usleep_range(10000, 11000);
1266 DRM_DEV_DEBUG_DRIVER(dev, "power on !\n");
1269 for (--i; i >= 0; i--)
1270 regulator_disable(ctx->pdata.supplies[i].consumer);
1273 static void anx7625_power_standby(struct anx7625_data *ctx)
1275 struct device *dev = &ctx->client->dev;
1278 if (!ctx->pdata.low_power_mode) {
1279 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n");
1283 gpiod_set_value(ctx->pdata.gpio_reset, 0);
1284 usleep_range(1000, 1100);
1285 gpiod_set_value(ctx->pdata.gpio_p_on, 0);
1286 usleep_range(1000, 1100);
1288 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies),
1289 ctx->pdata.supplies);
1291 DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret);
1293 DRM_DEV_DEBUG_DRIVER(dev, "power down\n");
1296 /* Basic configurations of ANX7625 */
1297 static void anx7625_config(struct anx7625_data *ctx)
1299 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1300 XTAL_FRQ_SEL, XTAL_FRQ_27M);
1303 static void anx7625_disable_pd_protocol(struct anx7625_data *ctx)
1305 struct device *dev = &ctx->client->dev;
1308 /* Reset main ocm */
1309 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40);
1311 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1312 AP_AV_STATUS, AP_DISABLE_PD);
1313 /* Release main ocm */
1314 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00);
1317 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n");
1319 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n");
1322 static int anx7625_ocm_loading_check(struct anx7625_data *ctx)
1325 struct device *dev = &ctx->client->dev;
1327 /* Check interface workable */
1328 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
1331 DRM_DEV_ERROR(dev, "IO error : access flash load.\n");
1334 if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK)
1337 anx7625_disable_pd_protocol(ctx);
1339 DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,",
1340 anx7625_reg_read(ctx,
1341 ctx->i2c.rx_p0_client,
1343 anx7625_reg_read(ctx,
1344 ctx->i2c.rx_p0_client,
1346 DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n",
1347 ANX7625_DRV_VERSION);
1352 static void anx7625_power_on_init(struct anx7625_data *ctx)
1356 for (retry_count = 0; retry_count < 3; retry_count++) {
1357 anx7625_power_on(ctx);
1358 anx7625_config(ctx);
1360 for (i = 0; i < OCM_LOADING_TIME; i++) {
1361 if (!anx7625_ocm_loading_check(ctx))
1363 usleep_range(1000, 1100);
1365 anx7625_power_standby(ctx);
1369 static void anx7625_init_gpio(struct anx7625_data *platform)
1371 struct device *dev = &platform->client->dev;
1373 DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n");
1375 /* Gpio for chip power enable */
1376 platform->pdata.gpio_p_on =
1377 devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW);
1378 if (IS_ERR_OR_NULL(platform->pdata.gpio_p_on)) {
1379 DRM_DEV_DEBUG_DRIVER(dev, "no enable gpio found\n");
1380 platform->pdata.gpio_p_on = NULL;
1383 /* Gpio for chip reset */
1384 platform->pdata.gpio_reset =
1385 devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1386 if (IS_ERR_OR_NULL(platform->pdata.gpio_reset)) {
1387 DRM_DEV_DEBUG_DRIVER(dev, "no reset gpio found\n");
1388 platform->pdata.gpio_reset = NULL;
1391 if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) {
1392 platform->pdata.low_power_mode = 1;
1393 DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n",
1394 desc_to_gpio(platform->pdata.gpio_p_on),
1395 desc_to_gpio(platform->pdata.gpio_reset));
1397 platform->pdata.low_power_mode = 0;
1398 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n");
1402 static void anx7625_stop_dp_work(struct anx7625_data *ctx)
1404 ctx->hpd_status = 0;
1405 ctx->hpd_high_cnt = 0;
1406 ctx->display_timing_valid = 0;
1409 static void anx7625_start_dp_work(struct anx7625_data *ctx)
1412 struct device *dev = &ctx->client->dev;
1414 if (ctx->hpd_high_cnt >= 2) {
1415 DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n");
1419 ctx->hpd_status = 1;
1420 ctx->hpd_high_cnt++;
1422 /* Not support HDCP */
1423 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
1426 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
1427 /* Interrupt for DRM */
1428 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
1430 DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n");
1434 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86);
1438 DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret);
1441 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx)
1443 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS);
1446 static void anx7625_hpd_polling(struct anx7625_data *ctx)
1449 struct device *dev = &ctx->client->dev;
1451 /* Interrupt mode, no need poll HPD status, just return */
1452 if (ctx->pdata.intp_irq)
1455 ret = readx_poll_timeout(anx7625_read_hpd_status_p0,
1457 ((val & HPD_STATUS) || (val < 0)),
1461 DRM_DEV_ERROR(dev, "no hpd.\n");
1465 DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val);
1466 anx7625_reg_write(ctx, ctx->i2c.tcpc_client,
1467 INTR_ALERT_1, 0xFF);
1468 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1469 INTERFACE_CHANGE_INT, 0);
1471 anx7625_start_dp_work(ctx);
1473 if (!ctx->pdata.panel_bridge && ctx->bridge_attached)
1474 drm_helper_hpd_irq_event(ctx->bridge.dev);
1477 static void anx7625_remove_edid(struct anx7625_data *ctx)
1479 ctx->slimport_edid_p.edid_block_num = -1;
1482 static void anx7625_dp_adjust_swing(struct anx7625_data *ctx)
1486 for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++)
1487 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client,
1488 DP_TX_LANE0_SWING_REG0 + i,
1489 ctx->pdata.lane0_reg_data[i]);
1491 for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++)
1492 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client,
1493 DP_TX_LANE1_SWING_REG0 + i,
1494 ctx->pdata.lane1_reg_data[i]);
1497 static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on)
1499 struct device *dev = &ctx->client->dev;
1502 DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n",
1506 DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n");
1507 anx7625_remove_edid(ctx);
1508 anx7625_stop_dp_work(ctx);
1510 DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n");
1511 anx7625_start_dp_work(ctx);
1512 anx7625_dp_adjust_swing(ctx);
1516 static int anx7625_hpd_change_detect(struct anx7625_data *ctx)
1518 int intr_vector, status;
1519 struct device *dev = &ctx->client->dev;
1521 status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client,
1522 INTR_ALERT_1, 0xFF);
1524 DRM_DEV_ERROR(dev, "cannot clear alert reg.\n");
1528 intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
1529 INTERFACE_CHANGE_INT);
1530 if (intr_vector < 0) {
1531 DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n");
1534 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector);
1535 status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1536 INTERFACE_CHANGE_INT,
1537 intr_vector & (~intr_vector));
1539 DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n");
1543 if (!(intr_vector & HPD_STATUS_CHANGE))
1546 status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
1549 DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n");
1553 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status);
1554 dp_hpd_change_handler(ctx, status & HPD_STATUS);
1559 static void anx7625_work_func(struct work_struct *work)
1562 struct anx7625_data *ctx = container_of(work,
1563 struct anx7625_data, work);
1565 mutex_lock(&ctx->lock);
1567 if (pm_runtime_suspended(&ctx->client->dev))
1570 event = anx7625_hpd_change_detect(ctx);
1574 if (ctx->bridge_attached)
1575 drm_helper_hpd_irq_event(ctx->bridge.dev);
1578 mutex_unlock(&ctx->lock);
1581 static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data)
1583 struct anx7625_data *ctx = (struct anx7625_data *)data;
1585 queue_work(ctx->workqueue, &ctx->work);
1590 static int anx7625_get_swing_setting(struct device *dev,
1591 struct anx7625_platform_data *pdata)
1595 if (of_get_property(dev->of_node,
1596 "analogix,lane0-swing", &num_regs)) {
1597 if (num_regs > DP_TX_SWING_REG_CNT)
1598 num_regs = DP_TX_SWING_REG_CNT;
1600 pdata->dp_lane0_swing_reg_cnt = num_regs;
1601 of_property_read_u8_array(dev->of_node, "analogix,lane0-swing",
1602 pdata->lane0_reg_data, num_regs);
1605 if (of_get_property(dev->of_node,
1606 "analogix,lane1-swing", &num_regs)) {
1607 if (num_regs > DP_TX_SWING_REG_CNT)
1608 num_regs = DP_TX_SWING_REG_CNT;
1610 pdata->dp_lane1_swing_reg_cnt = num_regs;
1611 of_property_read_u8_array(dev->of_node, "analogix,lane1-swing",
1612 pdata->lane1_reg_data, num_regs);
1618 static int anx7625_parse_dt(struct device *dev,
1619 struct anx7625_platform_data *pdata)
1621 struct device_node *np = dev->of_node, *ep0;
1622 int bus_type, mipi_lanes;
1624 anx7625_get_swing_setting(dev, pdata);
1626 pdata->is_dpi = 1; /* default dpi mode */
1627 pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0);
1628 if (!pdata->mipi_host_node) {
1629 DRM_DEV_ERROR(dev, "fail to get internal panel.\n");
1633 bus_type = V4L2_FWNODE_BUS_TYPE_PARALLEL;
1634 mipi_lanes = MAX_LANES_SUPPORT;
1635 ep0 = of_graph_get_endpoint_by_regs(np, 0, 0);
1637 if (of_property_read_u32(ep0, "bus-type", &bus_type))
1640 mipi_lanes = of_property_count_u32_elems(ep0, "data-lanes");
1643 if (bus_type == V4L2_FWNODE_BUS_TYPE_PARALLEL) /* bus type is Parallel(DSI) */
1646 pdata->mipi_lanes = mipi_lanes;
1647 if (pdata->mipi_lanes > MAX_LANES_SUPPORT || pdata->mipi_lanes <= 0)
1648 pdata->mipi_lanes = MAX_LANES_SUPPORT;
1651 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DPI host node.\n");
1653 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DSI host node.\n");
1655 if (of_property_read_bool(np, "analogix,audio-enable"))
1656 pdata->audio_en = 1;
1658 pdata->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0);
1659 if (IS_ERR(pdata->panel_bridge)) {
1660 if (PTR_ERR(pdata->panel_bridge) == -ENODEV)
1663 return PTR_ERR(pdata->panel_bridge);
1666 DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n");
1671 static bool anx7625_of_panel_on_aux_bus(struct device *dev)
1673 struct device_node *bus, *panel;
1675 bus = of_get_child_by_name(dev->of_node, "aux-bus");
1679 panel = of_get_child_by_name(bus, "panel");
1688 static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge)
1690 return container_of(bridge, struct anx7625_data, bridge);
1693 static ssize_t anx7625_aux_transfer(struct drm_dp_aux *aux,
1694 struct drm_dp_aux_msg *msg)
1696 struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux);
1697 struct device *dev = &ctx->client->dev;
1698 u8 request = msg->request & ~DP_AUX_I2C_MOT;
1701 pm_runtime_get_sync(dev);
1704 case DP_AUX_NATIVE_WRITE:
1705 case DP_AUX_I2C_WRITE:
1706 case DP_AUX_NATIVE_READ:
1707 case DP_AUX_I2C_READ:
1713 ret = anx7625_aux_trans(ctx, msg->request, msg->address,
1714 msg->size, msg->buffer);
1715 pm_runtime_mark_last_busy(dev);
1716 pm_runtime_put_autosuspend(dev);
1721 static struct edid *anx7625_get_edid(struct anx7625_data *ctx)
1723 struct device *dev = &ctx->client->dev;
1724 struct s_edid_data *p_edid = &ctx->slimport_edid_p;
1728 edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL);
1730 DRM_DEV_ERROR(dev, "Fail to allocate buffer\n");
1734 if (ctx->slimport_edid_p.edid_block_num > 0) {
1735 memcpy(edid, ctx->slimport_edid_p.edid_raw_data,
1737 return (struct edid *)edid;
1740 pm_runtime_get_sync(dev);
1741 edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data);
1742 pm_runtime_put_sync(dev);
1745 DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num);
1750 p_edid->edid_block_num = edid_num;
1752 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE);
1753 return (struct edid *)edid;
1756 static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx)
1758 struct device *dev = &ctx->client->dev;
1760 DRM_DEV_DEBUG_DRIVER(dev, "sink detect\n");
1762 if (ctx->pdata.panel_bridge)
1763 return connector_status_connected;
1765 return ctx->hpd_status ? connector_status_connected :
1766 connector_status_disconnected;
1769 static int anx7625_audio_hw_params(struct device *dev, void *data,
1770 struct hdmi_codec_daifmt *fmt,
1771 struct hdmi_codec_params *params)
1773 struct anx7625_data *ctx = dev_get_drvdata(dev);
1777 if (fmt->fmt != HDMI_DSP_A) {
1778 DRM_DEV_ERROR(dev, "only supports DSP_A\n");
1782 DRM_DEV_DEBUG_DRIVER(dev, "setting %d Hz, %d bit, %d channels\n",
1783 params->sample_rate, params->sample_width,
1784 params->cea.channels);
1786 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1787 AUDIO_CHANNEL_STATUS_6,
1792 switch (params->sample_width) {
1794 wl = AUDIO_W_LEN_16_20MAX;
1797 wl = AUDIO_W_LEN_18_20MAX;
1800 wl = AUDIO_W_LEN_20_20MAX;
1803 wl = AUDIO_W_LEN_24_24MAX;
1806 DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support",
1807 params->sample_width);
1810 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1811 AUDIO_CHANNEL_STATUS_5,
1815 switch (params->cea.channels) {
1829 DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support",
1830 params->cea.channels);
1833 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1834 AUDIO_CHANNEL_STATUS_6, 0x1f, ch << 5);
1836 ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client,
1837 AUDIO_CHANNEL_STATUS_6, AUDIO_LAYOUT);
1839 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client,
1840 AUDIO_CHANNEL_STATUS_6, ~AUDIO_LAYOUT);
1843 switch (params->sample_rate) {
1845 rate = AUDIO_FS_32K;
1848 rate = AUDIO_FS_441K;
1851 rate = AUDIO_FS_48K;
1854 rate = AUDIO_FS_882K;
1857 rate = AUDIO_FS_96K;
1860 rate = AUDIO_FS_1764K;
1863 rate = AUDIO_FS_192K;
1866 DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d not support",
1867 params->sample_rate);
1870 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1871 AUDIO_CHANNEL_STATUS_4,
1873 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
1874 AP_AV_STATUS, AP_AUDIO_CHG);
1876 DRM_DEV_ERROR(dev, "IO error : config audio.\n");
1883 static void anx7625_audio_shutdown(struct device *dev, void *data)
1885 DRM_DEV_DEBUG_DRIVER(dev, "stop audio\n");
1888 static int anx7625_hdmi_i2s_get_dai_id(struct snd_soc_component *component,
1889 struct device_node *endpoint)
1891 struct of_endpoint of_ep;
1894 ret = of_graph_parse_endpoint(endpoint, &of_ep);
1899 * HDMI sound should be located at external DPI port
1900 * Didn't have good way to check where is internal(DSI)
1901 * or external(DPI) bridge
1907 anx7625_audio_update_connector_status(struct anx7625_data *ctx,
1908 enum drm_connector_status status)
1910 if (ctx->plugged_cb && ctx->codec_dev) {
1911 ctx->plugged_cb(ctx->codec_dev,
1912 status == connector_status_connected);
1916 static int anx7625_audio_hook_plugged_cb(struct device *dev, void *data,
1917 hdmi_codec_plugged_cb fn,
1918 struct device *codec_dev)
1920 struct anx7625_data *ctx = data;
1922 ctx->plugged_cb = fn;
1923 ctx->codec_dev = codec_dev;
1924 anx7625_audio_update_connector_status(ctx, anx7625_sink_detect(ctx));
1929 static int anx7625_audio_get_eld(struct device *dev, void *data,
1930 u8 *buf, size_t len)
1932 struct anx7625_data *ctx = dev_get_drvdata(dev);
1934 if (!ctx->connector) {
1935 /* Pass en empty ELD if connector not available */
1936 memset(buf, 0, len);
1938 dev_dbg(dev, "audio copy eld\n");
1939 memcpy(buf, ctx->connector->eld,
1940 min(sizeof(ctx->connector->eld), len));
1946 static const struct hdmi_codec_ops anx7625_codec_ops = {
1947 .hw_params = anx7625_audio_hw_params,
1948 .audio_shutdown = anx7625_audio_shutdown,
1949 .get_eld = anx7625_audio_get_eld,
1950 .get_dai_id = anx7625_hdmi_i2s_get_dai_id,
1951 .hook_plugged_cb = anx7625_audio_hook_plugged_cb,
1954 static void anx7625_unregister_audio(struct anx7625_data *ctx)
1956 struct device *dev = &ctx->client->dev;
1958 if (ctx->audio_pdev) {
1959 platform_device_unregister(ctx->audio_pdev);
1960 ctx->audio_pdev = NULL;
1963 DRM_DEV_DEBUG_DRIVER(dev, "unbound to %s", HDMI_CODEC_DRV_NAME);
1966 static int anx7625_register_audio(struct device *dev, struct anx7625_data *ctx)
1968 struct hdmi_codec_pdata codec_data = {
1969 .ops = &anx7625_codec_ops,
1970 .max_i2s_channels = 8,
1975 ctx->audio_pdev = platform_device_register_data(dev,
1976 HDMI_CODEC_DRV_NAME,
1977 PLATFORM_DEVID_AUTO,
1979 sizeof(codec_data));
1981 if (IS_ERR(ctx->audio_pdev))
1982 return PTR_ERR(ctx->audio_pdev);
1984 DRM_DEV_DEBUG_DRIVER(dev, "bound to %s", HDMI_CODEC_DRV_NAME);
1989 static int anx7625_attach_dsi(struct anx7625_data *ctx)
1991 struct mipi_dsi_device *dsi;
1992 struct device *dev = &ctx->client->dev;
1993 struct mipi_dsi_host *host;
1994 const struct mipi_dsi_device_info info = {
2001 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n");
2003 host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node);
2005 DRM_DEV_ERROR(dev, "fail to find dsi host.\n");
2006 return -EPROBE_DEFER;
2009 dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
2011 DRM_DEV_ERROR(dev, "fail to create dsi device.\n");
2015 dsi->lanes = ctx->pdata.mipi_lanes;
2016 dsi->format = MIPI_DSI_FMT_RGB888;
2017 dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
2018 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
2019 MIPI_DSI_MODE_VIDEO_HSE |
2020 MIPI_DSI_HS_PKT_END_ALIGNED;
2022 ret = devm_mipi_dsi_attach(dev, dsi);
2024 DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n");
2030 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n");
2035 static void hdcp_check_work_func(struct work_struct *work)
2038 struct delayed_work *dwork;
2039 struct anx7625_data *ctx;
2041 struct drm_device *drm_dev;
2043 dwork = to_delayed_work(work);
2044 ctx = container_of(dwork, struct anx7625_data, hdcp_work);
2045 dev = &ctx->client->dev;
2047 if (!ctx->connector) {
2048 dev_err(dev, "HDCP connector is null!");
2052 drm_dev = ctx->connector->dev;
2053 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2054 mutex_lock(&ctx->hdcp_wq_lock);
2056 status = anx7625_reg_read(ctx, ctx->i2c.tx_p0_client, 0);
2057 dev_dbg(dev, "sink HDCP status check: %.02x\n", status);
2058 if (status & BIT(1)) {
2059 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED;
2060 drm_hdcp_update_content_protection(ctx->connector,
2062 dev_dbg(dev, "update CP to ENABLE\n");
2065 mutex_unlock(&ctx->hdcp_wq_lock);
2066 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2069 static int anx7625_connector_atomic_check(struct anx7625_data *ctx,
2070 struct drm_connector_state *state)
2072 struct device *dev = &ctx->client->dev;
2075 dev_dbg(dev, "hdcp state check\n");
2076 cp = state->content_protection;
2078 if (cp == ctx->hdcp_cp)
2081 if (cp == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
2083 dev_dbg(dev, "enable HDCP\n");
2084 anx7625_hdcp_enable(ctx);
2086 queue_delayed_work(ctx->hdcp_workqueue,
2088 msecs_to_jiffies(2000));
2092 if (cp == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
2093 if (ctx->hdcp_cp != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
2094 dev_err(dev, "current CP is not ENABLED\n");
2097 anx7625_hdcp_disable(ctx);
2098 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
2099 drm_hdcp_update_content_protection(ctx->connector,
2101 dev_dbg(dev, "update CP to UNDESIRE\n");
2104 if (cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
2105 dev_err(dev, "Userspace illegal set to PROTECTION ENABLE\n");
2112 static int anx7625_bridge_attach(struct drm_bridge *bridge,
2113 enum drm_bridge_attach_flags flags)
2115 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2117 struct device *dev = &ctx->client->dev;
2119 DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n");
2120 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
2123 if (!bridge->encoder) {
2124 DRM_DEV_ERROR(dev, "Parent encoder object not found");
2128 ctx->aux.drm_dev = bridge->dev;
2129 err = drm_dp_aux_register(&ctx->aux);
2131 dev_err(dev, "failed to register aux channel: %d\n", err);
2135 if (ctx->pdata.panel_bridge) {
2136 err = drm_bridge_attach(bridge->encoder,
2137 ctx->pdata.panel_bridge,
2138 &ctx->bridge, flags);
2143 ctx->bridge_attached = 1;
2148 static void anx7625_bridge_detach(struct drm_bridge *bridge)
2150 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2152 drm_dp_aux_unregister(&ctx->aux);
2155 static enum drm_mode_status
2156 anx7625_bridge_mode_valid(struct drm_bridge *bridge,
2157 const struct drm_display_info *info,
2158 const struct drm_display_mode *mode)
2160 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2161 struct device *dev = &ctx->client->dev;
2163 DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n");
2165 /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */
2166 if (mode->clock > SUPPORT_PIXEL_CLOCK) {
2167 DRM_DEV_DEBUG_DRIVER(dev,
2168 "drm mode invalid, pixelclock too high.\n");
2169 return MODE_CLOCK_HIGH;
2172 DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n");
2177 static void anx7625_bridge_mode_set(struct drm_bridge *bridge,
2178 const struct drm_display_mode *old_mode,
2179 const struct drm_display_mode *mode)
2181 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2182 struct device *dev = &ctx->client->dev;
2184 DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n");
2186 ctx->dt.pixelclock.min = mode->clock;
2187 ctx->dt.hactive.min = mode->hdisplay;
2188 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start;
2189 ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay;
2190 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end;
2191 ctx->dt.vactive.min = mode->vdisplay;
2192 ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start;
2193 ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay;
2194 ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end;
2196 ctx->display_timing_valid = 1;
2198 DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min);
2199 DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n",
2200 ctx->dt.hactive.min,
2201 ctx->dt.hsync_len.min,
2202 ctx->dt.hfront_porch.min,
2203 ctx->dt.hback_porch.min);
2204 DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n",
2205 ctx->dt.vactive.min,
2206 ctx->dt.vsync_len.min,
2207 ctx->dt.vfront_porch.min,
2208 ctx->dt.vback_porch.min);
2209 DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n",
2212 DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n",
2215 DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n",
2218 DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n",
2223 static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge,
2224 const struct drm_display_mode *mode,
2225 struct drm_display_mode *adj)
2227 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2228 struct device *dev = &ctx->client->dev;
2229 u32 hsync, hfp, hbp, hblanking;
2230 u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj;
2231 u32 vref, adj_clock;
2233 DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n");
2235 /* No need fixup for external monitor */
2236 if (!ctx->pdata.panel_bridge)
2239 hsync = mode->hsync_end - mode->hsync_start;
2240 hfp = mode->hsync_start - mode->hdisplay;
2241 hbp = mode->htotal - mode->hsync_end;
2242 hblanking = mode->htotal - mode->hdisplay;
2244 DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n");
2245 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n",
2246 hsync, hfp, hbp, adj->clock);
2247 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n",
2248 adj->hsync_start, adj->hsync_end, adj->htotal);
2253 adj_hblanking = hblanking;
2255 /* HFP needs to be even */
2261 /* HBP needs to be even */
2267 /* HSYNC needs to be even */
2269 if (adj_hblanking < hblanking)
2276 * Once illegal timing detected, use default HFP, HSYNC, HBP
2277 * This adjusting made for built-in eDP panel, for the externel
2278 * DP monitor, may need return false.
2280 if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) {
2281 adj_hsync = SYNC_LEN_DEF;
2282 adj_hfp = HFP_HBP_DEF;
2283 adj_hbp = HFP_HBP_DEF;
2284 vref = adj->clock * 1000 / (adj->htotal * adj->vtotal);
2285 if (hblanking < HBLANKING_MIN) {
2286 delta_adj = HBLANKING_MIN - hblanking;
2287 adj_clock = vref * delta_adj * adj->vtotal;
2288 adj->clock += DIV_ROUND_UP(adj_clock, 1000);
2290 delta_adj = hblanking - HBLANKING_MIN;
2291 adj_clock = vref * delta_adj * adj->vtotal;
2292 adj->clock -= DIV_ROUND_UP(adj_clock, 1000);
2295 DRM_WARN("illegal hblanking timing, use default.\n");
2296 DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync);
2297 } else if (adj_hfp < HP_MIN) {
2298 /* Adjust hfp if hfp less than HP_MIN */
2299 delta_adj = HP_MIN - adj_hfp;
2303 * Balance total HBlanking pixel, if HBP does not have enough
2304 * space, adjust HSYNC length, otherwise adjust HBP
2306 if ((adj_hbp - delta_adj) < HP_MIN)
2307 /* HBP not enough space */
2308 adj_hsync -= delta_adj;
2310 adj_hbp -= delta_adj;
2311 } else if (adj_hbp < HP_MIN) {
2312 delta_adj = HP_MIN - adj_hbp;
2316 * Balance total HBlanking pixel, if HBP hasn't enough space,
2317 * adjust HSYNC length, otherwize adjust HBP
2319 if ((adj_hfp - delta_adj) < HP_MIN)
2320 /* HFP not enough space */
2321 adj_hsync -= delta_adj;
2323 adj_hfp -= delta_adj;
2326 DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n");
2327 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n",
2328 adj_hsync, adj_hfp, adj_hbp, adj->clock);
2330 /* Reconstruct timing */
2331 adj->hsync_start = adj->hdisplay + adj_hfp;
2332 adj->hsync_end = adj->hsync_start + adj_hsync;
2333 adj->htotal = adj->hsync_end + adj_hbp;
2334 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n",
2335 adj->hsync_start, adj->hsync_end, adj->htotal);
2340 static int anx7625_bridge_atomic_check(struct drm_bridge *bridge,
2341 struct drm_bridge_state *bridge_state,
2342 struct drm_crtc_state *crtc_state,
2343 struct drm_connector_state *conn_state)
2345 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2346 struct device *dev = &ctx->client->dev;
2348 dev_dbg(dev, "drm bridge atomic check\n");
2350 anx7625_bridge_mode_fixup(bridge, &crtc_state->mode,
2351 &crtc_state->adjusted_mode);
2353 return anx7625_connector_atomic_check(ctx, conn_state);
2356 static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge,
2357 struct drm_bridge_state *state)
2359 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2360 struct device *dev = &ctx->client->dev;
2361 struct drm_connector *connector;
2363 dev_dbg(dev, "drm atomic enable\n");
2365 if (!bridge->encoder) {
2366 dev_err(dev, "Parent encoder object not found");
2370 connector = drm_atomic_get_new_connector_for_encoder(state->base.state,
2375 ctx->connector = connector;
2377 pm_runtime_get_sync(dev);
2379 anx7625_dp_start(ctx);
2382 static void anx7625_bridge_atomic_disable(struct drm_bridge *bridge,
2383 struct drm_bridge_state *old)
2385 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2386 struct device *dev = &ctx->client->dev;
2388 dev_dbg(dev, "drm atomic disable\n");
2390 ctx->connector = NULL;
2391 anx7625_dp_stop(ctx);
2393 pm_runtime_put_sync(dev);
2396 static enum drm_connector_status
2397 anx7625_bridge_detect(struct drm_bridge *bridge)
2399 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2400 struct device *dev = &ctx->client->dev;
2402 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n");
2404 return anx7625_sink_detect(ctx);
2407 static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge,
2408 struct drm_connector *connector)
2410 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
2411 struct device *dev = &ctx->client->dev;
2413 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n");
2415 return anx7625_get_edid(ctx);
2418 static const struct drm_bridge_funcs anx7625_bridge_funcs = {
2419 .attach = anx7625_bridge_attach,
2420 .detach = anx7625_bridge_detach,
2421 .mode_valid = anx7625_bridge_mode_valid,
2422 .mode_set = anx7625_bridge_mode_set,
2423 .atomic_check = anx7625_bridge_atomic_check,
2424 .atomic_enable = anx7625_bridge_atomic_enable,
2425 .atomic_disable = anx7625_bridge_atomic_disable,
2426 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
2427 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
2428 .atomic_reset = drm_atomic_helper_bridge_reset,
2429 .detect = anx7625_bridge_detect,
2430 .get_edid = anx7625_bridge_get_edid,
2433 static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx,
2434 struct i2c_client *client)
2438 ctx->i2c.tx_p0_client = i2c_new_dummy_device(client->adapter,
2440 if (IS_ERR(ctx->i2c.tx_p0_client))
2441 return PTR_ERR(ctx->i2c.tx_p0_client);
2443 ctx->i2c.tx_p1_client = i2c_new_dummy_device(client->adapter,
2445 if (IS_ERR(ctx->i2c.tx_p1_client)) {
2446 err = PTR_ERR(ctx->i2c.tx_p1_client);
2450 ctx->i2c.tx_p2_client = i2c_new_dummy_device(client->adapter,
2452 if (IS_ERR(ctx->i2c.tx_p2_client)) {
2453 err = PTR_ERR(ctx->i2c.tx_p2_client);
2457 ctx->i2c.rx_p0_client = i2c_new_dummy_device(client->adapter,
2459 if (IS_ERR(ctx->i2c.rx_p0_client)) {
2460 err = PTR_ERR(ctx->i2c.rx_p0_client);
2464 ctx->i2c.rx_p1_client = i2c_new_dummy_device(client->adapter,
2466 if (IS_ERR(ctx->i2c.rx_p1_client)) {
2467 err = PTR_ERR(ctx->i2c.rx_p1_client);
2471 ctx->i2c.rx_p2_client = i2c_new_dummy_device(client->adapter,
2473 if (IS_ERR(ctx->i2c.rx_p2_client)) {
2474 err = PTR_ERR(ctx->i2c.rx_p2_client);
2478 ctx->i2c.tcpc_client = i2c_new_dummy_device(client->adapter,
2479 TCPC_INTERFACE_ADDR >> 1);
2480 if (IS_ERR(ctx->i2c.tcpc_client)) {
2481 err = PTR_ERR(ctx->i2c.tcpc_client);
2488 i2c_unregister_device(ctx->i2c.rx_p2_client);
2490 i2c_unregister_device(ctx->i2c.rx_p1_client);
2492 i2c_unregister_device(ctx->i2c.rx_p0_client);
2494 i2c_unregister_device(ctx->i2c.tx_p2_client);
2496 i2c_unregister_device(ctx->i2c.tx_p1_client);
2498 i2c_unregister_device(ctx->i2c.tx_p0_client);
2503 static void anx7625_unregister_i2c_dummy_clients(struct anx7625_data *ctx)
2505 i2c_unregister_device(ctx->i2c.tx_p0_client);
2506 i2c_unregister_device(ctx->i2c.tx_p1_client);
2507 i2c_unregister_device(ctx->i2c.tx_p2_client);
2508 i2c_unregister_device(ctx->i2c.rx_p0_client);
2509 i2c_unregister_device(ctx->i2c.rx_p1_client);
2510 i2c_unregister_device(ctx->i2c.rx_p2_client);
2511 i2c_unregister_device(ctx->i2c.tcpc_client);
2514 static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev)
2516 struct anx7625_data *ctx = dev_get_drvdata(dev);
2518 mutex_lock(&ctx->lock);
2520 anx7625_stop_dp_work(ctx);
2521 anx7625_power_standby(ctx);
2523 mutex_unlock(&ctx->lock);
2528 static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev)
2530 struct anx7625_data *ctx = dev_get_drvdata(dev);
2532 mutex_lock(&ctx->lock);
2534 anx7625_power_on_init(ctx);
2535 anx7625_hpd_polling(ctx);
2537 mutex_unlock(&ctx->lock);
2542 static int __maybe_unused anx7625_resume(struct device *dev)
2544 struct anx7625_data *ctx = dev_get_drvdata(dev);
2546 if (!ctx->pdata.intp_irq)
2549 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) {
2550 enable_irq(ctx->pdata.intp_irq);
2551 anx7625_runtime_pm_resume(dev);
2557 static int __maybe_unused anx7625_suspend(struct device *dev)
2559 struct anx7625_data *ctx = dev_get_drvdata(dev);
2561 if (!ctx->pdata.intp_irq)
2564 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) {
2565 anx7625_runtime_pm_suspend(dev);
2566 disable_irq(ctx->pdata.intp_irq);
2572 static const struct dev_pm_ops anx7625_pm_ops = {
2573 SET_SYSTEM_SLEEP_PM_OPS(anx7625_suspend, anx7625_resume)
2574 SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend,
2575 anx7625_runtime_pm_resume, NULL)
2578 static void anx7625_runtime_disable(void *data)
2580 pm_runtime_dont_use_autosuspend(data);
2581 pm_runtime_disable(data);
2584 static int anx7625_i2c_probe(struct i2c_client *client,
2585 const struct i2c_device_id *id)
2587 struct anx7625_data *platform;
2588 struct anx7625_platform_data *pdata;
2590 struct device *dev = &client->dev;
2592 if (!i2c_check_functionality(client->adapter,
2593 I2C_FUNC_SMBUS_I2C_BLOCK)) {
2594 DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n");
2598 platform = devm_kzalloc(dev, sizeof(*platform), GFP_KERNEL);
2600 DRM_DEV_ERROR(dev, "fail to allocate driver data\n");
2604 pdata = &platform->pdata;
2606 platform->client = client;
2607 i2c_set_clientdata(client, platform);
2609 pdata->supplies[0].supply = "vdd10";
2610 pdata->supplies[1].supply = "vdd18";
2611 pdata->supplies[2].supply = "vdd33";
2612 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies),
2615 DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret);
2618 anx7625_init_gpio(platform);
2620 mutex_init(&platform->lock);
2621 mutex_init(&platform->hdcp_wq_lock);
2623 INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func);
2624 platform->hdcp_workqueue = create_workqueue("hdcp workqueue");
2625 if (!platform->hdcp_workqueue) {
2626 dev_err(dev, "fail to create work queue\n");
2631 platform->pdata.intp_irq = client->irq;
2632 if (platform->pdata.intp_irq) {
2633 INIT_WORK(&platform->work, anx7625_work_func);
2634 platform->workqueue = alloc_workqueue("anx7625_work",
2635 WQ_FREEZABLE | WQ_MEM_RECLAIM, 1);
2636 if (!platform->workqueue) {
2637 DRM_DEV_ERROR(dev, "fail to create work queue\n");
2642 ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq,
2643 NULL, anx7625_intr_hpd_isr,
2644 IRQF_TRIGGER_FALLING |
2646 "anx7625-intp", platform);
2648 DRM_DEV_ERROR(dev, "fail to request irq\n");
2653 platform->aux.name = "anx7625-aux";
2654 platform->aux.dev = dev;
2655 platform->aux.transfer = anx7625_aux_transfer;
2656 drm_dp_aux_init(&platform->aux);
2657 devm_of_dp_aux_populate_ep_devices(&platform->aux);
2659 ret = anx7625_parse_dt(dev, pdata);
2661 if (ret != -EPROBE_DEFER)
2662 DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret);
2666 if (anx7625_register_i2c_dummy_clients(platform, client) != 0) {
2668 DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n");
2672 pm_runtime_enable(dev);
2673 pm_runtime_set_autosuspend_delay(dev, 1000);
2674 pm_runtime_use_autosuspend(dev);
2675 pm_suspend_ignore_children(dev, true);
2676 ret = devm_add_action_or_reset(dev, anx7625_runtime_disable, dev);
2680 if (!platform->pdata.low_power_mode) {
2681 anx7625_disable_pd_protocol(platform);
2682 pm_runtime_get_sync(dev);
2685 /* Add work function */
2686 if (platform->pdata.intp_irq)
2687 queue_work(platform->workqueue, &platform->work);
2689 platform->bridge.funcs = &anx7625_bridge_funcs;
2690 platform->bridge.of_node = client->dev.of_node;
2691 if (!anx7625_of_panel_on_aux_bus(&client->dev))
2692 platform->bridge.ops |= DRM_BRIDGE_OP_EDID;
2693 if (!platform->pdata.panel_bridge)
2694 platform->bridge.ops |= DRM_BRIDGE_OP_HPD |
2695 DRM_BRIDGE_OP_DETECT;
2696 platform->bridge.type = platform->pdata.panel_bridge ?
2697 DRM_MODE_CONNECTOR_eDP :
2698 DRM_MODE_CONNECTOR_DisplayPort;
2700 drm_bridge_add(&platform->bridge);
2702 if (!platform->pdata.is_dpi) {
2703 ret = anx7625_attach_dsi(platform);
2705 DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", ret);
2706 goto unregister_bridge;
2710 if (platform->pdata.audio_en)
2711 anx7625_register_audio(dev, platform);
2713 DRM_DEV_DEBUG_DRIVER(dev, "probe done\n");
2718 drm_bridge_remove(&platform->bridge);
2720 if (!platform->pdata.low_power_mode)
2721 pm_runtime_put_sync_suspend(&client->dev);
2723 anx7625_unregister_i2c_dummy_clients(platform);
2726 if (platform->workqueue)
2727 destroy_workqueue(platform->workqueue);
2730 if (platform->hdcp_workqueue)
2731 destroy_workqueue(platform->hdcp_workqueue);
2736 static int anx7625_i2c_remove(struct i2c_client *client)
2738 struct anx7625_data *platform = i2c_get_clientdata(client);
2740 drm_bridge_remove(&platform->bridge);
2742 if (platform->pdata.intp_irq)
2743 destroy_workqueue(platform->workqueue);
2745 if (platform->hdcp_workqueue) {
2746 cancel_delayed_work(&platform->hdcp_work);
2747 flush_workqueue(platform->hdcp_workqueue);
2748 destroy_workqueue(platform->hdcp_workqueue);
2751 if (!platform->pdata.low_power_mode)
2752 pm_runtime_put_sync_suspend(&client->dev);
2754 anx7625_unregister_i2c_dummy_clients(platform);
2756 if (platform->pdata.audio_en)
2757 anx7625_unregister_audio(platform);
2762 static const struct i2c_device_id anx7625_id[] = {
2767 MODULE_DEVICE_TABLE(i2c, anx7625_id);
2769 static const struct of_device_id anx_match_table[] = {
2770 {.compatible = "analogix,anx7625",},
2773 MODULE_DEVICE_TABLE(of, anx_match_table);
2775 static struct i2c_driver anx7625_driver = {
2778 .of_match_table = anx_match_table,
2779 .pm = &anx7625_pm_ops,
2781 .probe = anx7625_i2c_probe,
2782 .remove = anx7625_i2c_remove,
2784 .id_table = anx7625_id,
2787 module_i2c_driver(anx7625_driver);
2789 MODULE_DESCRIPTION("MIPI2DP anx7625 driver");
2790 MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>");
2791 MODULE_LICENSE("GPL v2");
2792 MODULE_VERSION(ANX7625_DRV_VERSION);