1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Register definition file for Analogix DP core driver
5 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
6 * Author: Jingoo Han <jg1.han@samsung.com>
9 #ifndef _ANALOGIX_DP_REG_H
10 #define _ANALOGIX_DP_REG_H
12 #define ANALOGIX_DP_TX_SW_RESET 0x14
13 #define ANALOGIX_DP_FUNC_EN_1 0x18
14 #define ANALOGIX_DP_FUNC_EN_2 0x1C
15 #define ANALOGIX_DP_VIDEO_CTL_1 0x20
16 #define ANALOGIX_DP_VIDEO_CTL_2 0x24
17 #define ANALOGIX_DP_VIDEO_CTL_3 0x28
19 #define ANALOGIX_DP_VIDEO_CTL_8 0x3C
20 #define ANALOGIX_DP_VIDEO_CTL_10 0x44
22 #define ANALOGIX_DP_SPDIF_AUDIO_CTL_0 0xD8
24 #define ANALOGIX_DP_PLL_REG_1 0xfc
25 #define ANALOGIX_DP_PLL_REG_2 0x9e4
26 #define ANALOGIX_DP_PLL_REG_3 0x9e8
27 #define ANALOGIX_DP_PLL_REG_4 0x9ec
28 #define ANALOGIX_DP_PLL_REG_5 0xa00
30 #define ANALOGIX_DP_PD 0x12c
32 #define ANALOGIX_DP_IF_TYPE 0x244
33 #define ANALOGIX_DP_IF_PKT_DB1 0x254
34 #define ANALOGIX_DP_IF_PKT_DB2 0x258
35 #define ANALOGIX_DP_SPD_HB0 0x2F8
36 #define ANALOGIX_DP_SPD_HB1 0x2FC
37 #define ANALOGIX_DP_SPD_HB2 0x300
38 #define ANALOGIX_DP_SPD_HB3 0x304
39 #define ANALOGIX_DP_SPD_PB0 0x308
40 #define ANALOGIX_DP_SPD_PB1 0x30C
41 #define ANALOGIX_DP_SPD_PB2 0x310
42 #define ANALOGIX_DP_SPD_PB3 0x314
43 #define ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL 0x318
44 #define ANALOGIX_DP_VSC_SHADOW_DB0 0x31C
45 #define ANALOGIX_DP_VSC_SHADOW_DB1 0x320
47 #define ANALOGIX_DP_LANE_MAP 0x35C
49 #define ANALOGIX_DP_ANALOG_CTL_1 0x370
50 #define ANALOGIX_DP_ANALOG_CTL_2 0x374
51 #define ANALOGIX_DP_ANALOG_CTL_3 0x378
52 #define ANALOGIX_DP_PLL_FILTER_CTL_1 0x37C
53 #define ANALOGIX_DP_TX_AMP_TUNING_CTL 0x380
55 #define ANALOGIX_DP_AUX_HW_RETRY_CTL 0x390
57 #define ANALOGIX_DP_COMMON_INT_STA_1 0x3C4
58 #define ANALOGIX_DP_COMMON_INT_STA_2 0x3C8
59 #define ANALOGIX_DP_COMMON_INT_STA_3 0x3CC
60 #define ANALOGIX_DP_COMMON_INT_STA_4 0x3D0
61 #define ANALOGIX_DP_INT_STA 0x3DC
62 #define ANALOGIX_DP_COMMON_INT_MASK_1 0x3E0
63 #define ANALOGIX_DP_COMMON_INT_MASK_2 0x3E4
64 #define ANALOGIX_DP_COMMON_INT_MASK_3 0x3E8
65 #define ANALOGIX_DP_COMMON_INT_MASK_4 0x3EC
66 #define ANALOGIX_DP_INT_STA_MASK 0x3F8
67 #define ANALOGIX_DP_INT_CTL 0x3FC
69 #define ANALOGIX_DP_SYS_CTL_1 0x600
70 #define ANALOGIX_DP_SYS_CTL_2 0x604
71 #define ANALOGIX_DP_SYS_CTL_3 0x608
72 #define ANALOGIX_DP_SYS_CTL_4 0x60C
74 #define ANALOGIX_DP_PKT_SEND_CTL 0x640
75 #define ANALOGIX_DP_HDCP_CTL 0x648
77 #define ANALOGIX_DP_LINK_BW_SET 0x680
78 #define ANALOGIX_DP_LANE_COUNT_SET 0x684
79 #define ANALOGIX_DP_TRAINING_PTN_SET 0x688
80 #define ANALOGIX_DP_LN0_LINK_TRAINING_CTL 0x68C
81 #define ANALOGIX_DP_LN1_LINK_TRAINING_CTL 0x690
82 #define ANALOGIX_DP_LN2_LINK_TRAINING_CTL 0x694
83 #define ANALOGIX_DP_LN3_LINK_TRAINING_CTL 0x698
85 #define ANALOGIX_DP_DEBUG_CTL 0x6C0
86 #define ANALOGIX_DP_HPD_DEGLITCH_L 0x6C4
87 #define ANALOGIX_DP_HPD_DEGLITCH_H 0x6C8
88 #define ANALOGIX_DP_LINK_DEBUG_CTL 0x6E0
90 #define ANALOGIX_DP_M_VID_0 0x700
91 #define ANALOGIX_DP_M_VID_1 0x704
92 #define ANALOGIX_DP_M_VID_2 0x708
93 #define ANALOGIX_DP_N_VID_0 0x70C
94 #define ANALOGIX_DP_N_VID_1 0x710
95 #define ANALOGIX_DP_N_VID_2 0x714
97 #define ANALOGIX_DP_PLL_CTL 0x71C
98 #define ANALOGIX_DP_PHY_PD 0x720
99 #define ANALOGIX_DP_PHY_TEST 0x724
101 #define ANALOGIX_DP_VIDEO_FIFO_THRD 0x730
102 #define ANALOGIX_DP_AUDIO_MARGIN 0x73C
104 #define ANALOGIX_DP_M_VID_GEN_FILTER_TH 0x764
105 #define ANALOGIX_DP_M_AUD_GEN_FILTER_TH 0x778
106 #define ANALOGIX_DP_AUX_CH_STA 0x780
107 #define ANALOGIX_DP_AUX_CH_DEFER_CTL 0x788
108 #define ANALOGIX_DP_AUX_RX_COMM 0x78C
109 #define ANALOGIX_DP_BUFFER_DATA_CTL 0x790
110 #define ANALOGIX_DP_AUX_CH_CTL_1 0x794
111 #define ANALOGIX_DP_AUX_ADDR_7_0 0x798
112 #define ANALOGIX_DP_AUX_ADDR_15_8 0x79C
113 #define ANALOGIX_DP_AUX_ADDR_19_16 0x7A0
114 #define ANALOGIX_DP_AUX_CH_CTL_2 0x7A4
116 #define ANALOGIX_DP_BUF_DATA_0 0x7C0
118 #define ANALOGIX_DP_SOC_GENERAL_CTL 0x800
120 #define ANALOGIX_DP_CRC_CON 0x890
122 /* ANALOGIX_DP_TX_SW_RESET */
123 #define RESET_DP_TX (0x1 << 0)
125 /* ANALOGIX_DP_FUNC_EN_1 */
126 #define MASTER_VID_FUNC_EN_N (0x1 << 7)
127 #define RK_VID_CAP_FUNC_EN_N (0x1 << 6)
128 #define SLAVE_VID_FUNC_EN_N (0x1 << 5)
129 #define RK_VID_FIFO_FUNC_EN_N (0x1 << 5)
130 #define AUD_FIFO_FUNC_EN_N (0x1 << 4)
131 #define AUD_FUNC_EN_N (0x1 << 3)
132 #define HDCP_FUNC_EN_N (0x1 << 2)
133 #define CRC_FUNC_EN_N (0x1 << 1)
134 #define SW_FUNC_EN_N (0x1 << 0)
136 /* ANALOGIX_DP_FUNC_EN_2 */
137 #define SSC_FUNC_EN_N (0x1 << 7)
138 #define AUX_FUNC_EN_N (0x1 << 2)
139 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
140 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
142 /* ANALOGIX_DP_VIDEO_CTL_1 */
143 #define VIDEO_EN (0x1 << 7)
144 #define HDCP_VIDEO_MUTE (0x1 << 6)
146 /* ANALOGIX_DP_VIDEO_CTL_1 */
147 #define IN_D_RANGE_MASK (0x1 << 7)
148 #define IN_D_RANGE_SHIFT (7)
149 #define IN_D_RANGE_CEA (0x1 << 7)
150 #define IN_D_RANGE_VESA (0x0 << 7)
151 #define IN_BPC_MASK (0x7 << 4)
152 #define IN_BPC_SHIFT (4)
153 #define IN_BPC_12_BITS (0x3 << 4)
154 #define IN_BPC_10_BITS (0x2 << 4)
155 #define IN_BPC_8_BITS (0x1 << 4)
156 #define IN_BPC_6_BITS (0x0 << 4)
157 #define IN_COLOR_F_MASK (0x3 << 0)
158 #define IN_COLOR_F_SHIFT (0)
159 #define IN_COLOR_F_YCBCR444 (0x2 << 0)
160 #define IN_COLOR_F_YCBCR422 (0x1 << 0)
161 #define IN_COLOR_F_RGB (0x0 << 0)
163 /* ANALOGIX_DP_VIDEO_CTL_3 */
164 #define IN_YC_COEFFI_MASK (0x1 << 7)
165 #define IN_YC_COEFFI_SHIFT (7)
166 #define IN_YC_COEFFI_ITU709 (0x1 << 7)
167 #define IN_YC_COEFFI_ITU601 (0x0 << 7)
168 #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4)
169 #define VID_CHK_UPDATE_TYPE_SHIFT (4)
170 #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4)
171 #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4)
172 #define REUSE_SPD_EN (0x1 << 3)
174 /* ANALOGIX_DP_VIDEO_CTL_8 */
175 #define VID_HRES_TH(x) (((x) & 0xf) << 4)
176 #define VID_VRES_TH(x) (((x) & 0xf) << 0)
178 /* ANALOGIX_DP_VIDEO_CTL_10 */
179 #define FORMAT_SEL (0x1 << 4)
180 #define INTERACE_SCAN_CFG (0x1 << 2)
181 #define VSYNC_POLARITY_CFG (0x1 << 1)
182 #define HSYNC_POLARITY_CFG (0x1 << 0)
184 /* ANALOGIX_DP_PLL_REG_1 */
185 #define REF_CLK_24M (0x1 << 0)
186 #define REF_CLK_27M (0x0 << 0)
187 #define REF_CLK_MASK (0x1 << 0)
189 /* ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL */
190 #define PSR_FRAME_UP_TYPE_BURST (0x1 << 0)
191 #define PSR_FRAME_UP_TYPE_SINGLE (0x0 << 0)
192 #define PSR_CRC_SEL_HARDWARE (0x1 << 1)
193 #define PSR_CRC_SEL_MANUALLY (0x0 << 1)
195 /* ANALOGIX_DP_LANE_MAP */
196 #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)
197 #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6)
198 #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6)
199 #define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6)
200 #define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4)
201 #define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4)
202 #define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4)
203 #define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4)
204 #define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2)
205 #define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2)
206 #define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2)
207 #define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2)
208 #define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0)
209 #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0)
210 #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0)
211 #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0)
213 /* ANALOGIX_DP_ANALOG_CTL_1 */
214 #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4)
216 /* ANALOGIX_DP_ANALOG_CTL_2 */
217 #define SEL_24M (0x1 << 3)
218 #define TX_DVDD_BIT_1_0625V (0x4 << 0)
220 /* ANALOGIX_DP_ANALOG_CTL_3 */
221 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5)
222 #define VCO_BIT_600_MICRO (0x5 << 0)
224 /* ANALOGIX_DP_PLL_FILTER_CTL_1 */
225 #define PD_RING_OSC (0x1 << 6)
226 #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4)
227 #define TX_CUR1_2X (0x1 << 2)
228 #define TX_CUR_16_MA (0x3 << 0)
230 /* ANALOGIX_DP_TX_AMP_TUNING_CTL */
231 #define CH3_AMP_400_MV (0x0 << 24)
232 #define CH2_AMP_400_MV (0x0 << 16)
233 #define CH1_AMP_400_MV (0x0 << 8)
234 #define CH0_AMP_400_MV (0x0 << 0)
236 /* ANALOGIX_DP_AUX_HW_RETRY_CTL */
237 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8)
238 #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3)
239 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3)
240 #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3)
241 #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3)
242 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3)
243 #define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0)
245 /* ANALOGIX_DP_COMMON_INT_STA_1 */
246 #define VSYNC_DET (0x1 << 7)
247 #define PLL_LOCK_CHG (0x1 << 6)
248 #define SPDIF_ERR (0x1 << 5)
249 #define SPDIF_UNSTBL (0x1 << 4)
250 #define VID_FORMAT_CHG (0x1 << 3)
251 #define AUD_CLK_CHG (0x1 << 2)
252 #define VID_CLK_CHG (0x1 << 1)
253 #define SW_INT (0x1 << 0)
255 /* ANALOGIX_DP_COMMON_INT_STA_2 */
256 #define ENC_EN_CHG (0x1 << 6)
257 #define HW_BKSV_RDY (0x1 << 3)
258 #define HW_SHA_DONE (0x1 << 2)
259 #define HW_AUTH_STATE_CHG (0x1 << 1)
260 #define HW_AUTH_DONE (0x1 << 0)
262 /* ANALOGIX_DP_COMMON_INT_STA_3 */
263 #define AFIFO_UNDER (0x1 << 7)
264 #define AFIFO_OVER (0x1 << 6)
265 #define R0_CHK_FLAG (0x1 << 5)
267 /* ANALOGIX_DP_COMMON_INT_STA_4 */
268 #define PSR_ACTIVE (0x1 << 7)
269 #define PSR_INACTIVE (0x1 << 6)
270 #define SPDIF_BI_PHASE_ERR (0x1 << 5)
271 #define HOTPLUG_CHG (0x1 << 2)
272 #define HPD_LOST (0x1 << 1)
273 #define PLUG (0x1 << 0)
275 /* ANALOGIX_DP_INT_STA */
276 #define INT_HPD (0x1 << 6)
277 #define HW_TRAINING_FINISH (0x1 << 5)
278 #define RPLY_RECEIV (0x1 << 1)
279 #define AUX_ERR (0x1 << 0)
281 /* ANALOGIX_DP_INT_CTL */
282 #define SOFT_INT_CTRL (0x1 << 2)
283 #define INT_POL1 (0x1 << 1)
284 #define INT_POL0 (0x1 << 0)
286 /* ANALOGIX_DP_SYS_CTL_1 */
287 #define DET_STA (0x1 << 2)
288 #define FORCE_DET (0x1 << 1)
289 #define DET_CTRL (0x1 << 0)
291 /* ANALOGIX_DP_SYS_CTL_2 */
292 #define CHA_CRI(x) (((x) & 0xf) << 4)
293 #define CHA_STA (0x1 << 2)
294 #define FORCE_CHA (0x1 << 1)
295 #define CHA_CTRL (0x1 << 0)
297 /* ANALOGIX_DP_SYS_CTL_3 */
298 #define HPD_STATUS (0x1 << 6)
299 #define F_HPD (0x1 << 5)
300 #define HPD_CTRL (0x1 << 4)
301 #define HDCP_RDY (0x1 << 3)
302 #define STRM_VALID (0x1 << 2)
303 #define F_VALID (0x1 << 1)
304 #define VALID_CTRL (0x1 << 0)
306 /* ANALOGIX_DP_SYS_CTL_4 */
307 #define FIX_M_AUD (0x1 << 4)
308 #define ENHANCED (0x1 << 3)
309 #define FIX_M_VID (0x1 << 2)
310 #define M_VID_UPDATE_CTRL (0x3 << 0)
312 /* ANALOGIX_DP_TRAINING_PTN_SET */
313 #define SCRAMBLER_TYPE (0x1 << 9)
314 #define HW_LINK_TRAINING_PATTERN (0x1 << 8)
315 #define SCRAMBLING_DISABLE (0x1 << 5)
316 #define SCRAMBLING_ENABLE (0x0 << 5)
317 #define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2)
318 #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2)
319 #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2)
320 #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2)
321 #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0)
322 #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0)
323 #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0)
324 #define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0)
326 /* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */
327 #define PRE_EMPHASIS_SET_MASK (0x3 << 3)
328 #define PRE_EMPHASIS_SET_SHIFT (3)
330 /* ANALOGIX_DP_DEBUG_CTL */
331 #define PLL_LOCK (0x1 << 4)
332 #define F_PLL_LOCK (0x1 << 3)
333 #define PLL_LOCK_CTRL (0x1 << 2)
334 #define PN_INV (0x1 << 0)
336 /* ANALOGIX_DP_PLL_CTL */
337 #define DP_PLL_PD (0x1 << 7)
338 #define DP_PLL_RESET (0x1 << 6)
339 #define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4)
340 #define DP_PLL_REF_BIT_1_1250V (0x5 << 0)
341 #define DP_PLL_REF_BIT_1_2500V (0x7 << 0)
343 /* ANALOGIX_DP_PHY_PD */
344 #define DP_INC_BG (0x1 << 7)
345 #define DP_EXP_BG (0x1 << 6)
346 #define DP_PHY_PD (0x1 << 5)
347 #define RK_AUX_PD (0x1 << 5)
348 #define AUX_PD (0x1 << 4)
349 #define RK_PLL_PD (0x1 << 4)
350 #define CH3_PD (0x1 << 3)
351 #define CH2_PD (0x1 << 2)
352 #define CH1_PD (0x1 << 1)
353 #define CH0_PD (0x1 << 0)
354 #define DP_ALL_PD (0xff)
356 /* ANALOGIX_DP_PHY_TEST */
357 #define MACRO_RST (0x1 << 5)
358 #define CH1_TEST (0x1 << 1)
359 #define CH0_TEST (0x1 << 0)
361 /* ANALOGIX_DP_AUX_CH_STA */
362 #define AUX_BUSY (0x1 << 4)
363 #define AUX_STATUS_MASK (0xf << 0)
365 /* ANALOGIX_DP_AUX_CH_DEFER_CTL */
366 #define DEFER_CTRL_EN (0x1 << 7)
367 #define DEFER_COUNT(x) (((x) & 0x7f) << 0)
369 /* ANALOGIX_DP_AUX_RX_COMM */
370 #define AUX_RX_COMM_I2C_DEFER (0x2 << 2)
371 #define AUX_RX_COMM_AUX_DEFER (0x2 << 0)
373 /* ANALOGIX_DP_BUFFER_DATA_CTL */
374 #define BUF_CLR (0x1 << 7)
375 #define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0)
377 /* ANALOGIX_DP_AUX_CH_CTL_1 */
378 #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4)
379 #define AUX_TX_COMM_MASK (0xf << 0)
380 #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3)
381 #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3)
382 #define AUX_TX_COMM_MOT (0x1 << 2)
383 #define AUX_TX_COMM_WRITE (0x0 << 0)
384 #define AUX_TX_COMM_READ (0x1 << 0)
386 /* ANALOGIX_DP_AUX_ADDR_7_0 */
387 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
389 /* ANALOGIX_DP_AUX_ADDR_15_8 */
390 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
392 /* ANALOGIX_DP_AUX_ADDR_19_16 */
393 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f)
395 /* ANALOGIX_DP_AUX_CH_CTL_2 */
396 #define ADDR_ONLY (0x1 << 1)
397 #define AUX_EN (0x1 << 0)
399 /* ANALOGIX_DP_SOC_GENERAL_CTL */
400 #define AUDIO_MODE_SPDIF_MODE (0x1 << 8)
401 #define AUDIO_MODE_MASTER_MODE (0x0 << 8)
402 #define MASTER_VIDEO_INTERLACE_EN (0x1 << 4)
403 #define VIDEO_MASTER_CLK_SEL (0x1 << 2)
404 #define VIDEO_MASTER_MODE_EN (0x1 << 1)
405 #define VIDEO_MODE_MASK (0x1 << 0)
406 #define VIDEO_MODE_SLAVE_MODE (0x1 << 0)
407 #define VIDEO_MODE_MASTER_MODE (0x0 << 0)
409 /* ANALOGIX_DP_PKT_SEND_CTL */
410 #define IF_UP (0x1 << 4)
411 #define IF_EN (0x1 << 0)
413 /* ANALOGIX_DP_CRC_CON */
414 #define PSR_VID_CRC_FLUSH (0x1 << 2)
415 #define PSR_VID_CRC_ENABLE (0x1 << 0)
417 #endif /* _ANALOGIX_DP_REG_H */
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