1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Free Electrons
4 * Copyright (C) 2014 Atmel
6 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
9 #include <linux/dmapool.h>
10 #include <linux/mfd/atmel-hlcdc.h>
12 #include <drm/drm_atomic.h>
13 #include <drm/drm_atomic_helper.h>
14 #include <drm/drm_fb_cma_helper.h>
15 #include <drm/drm_fourcc.h>
16 #include <drm/drm_gem_cma_helper.h>
17 #include <drm/drm_plane_helper.h>
19 #include "atmel_hlcdc_dc.h"
22 * Atmel HLCDC Plane state structure.
24 * @base: DRM plane state
25 * @crtc_x: x position of the plane relative to the CRTC
26 * @crtc_y: y position of the plane relative to the CRTC
27 * @crtc_w: visible width of the plane
28 * @crtc_h: visible height of the plane
29 * @src_x: x buffer position
30 * @src_y: y buffer position
31 * @src_w: buffer width
32 * @src_h: buffer height
33 * @disc_x: x discard position
34 * @disc_y: y discard position
35 * @disc_w: discard width
36 * @disc_h: discard height
37 * @bpp: bytes per pixel deduced from pixel_format
38 * @offsets: offsets to apply to the GEM buffers
39 * @xstride: value to add to the pixel pointer between each line
40 * @pstride: value to add to the pixel pointer between each pixel
41 * @nplanes: number of planes (deduced from pixel_format)
42 * @dscrs: DMA descriptors
44 struct atmel_hlcdc_plane_state {
45 struct drm_plane_state base;
62 /* These fields are private and should not be touched */
63 int bpp[ATMEL_HLCDC_LAYER_MAX_PLANES];
64 unsigned int offsets[ATMEL_HLCDC_LAYER_MAX_PLANES];
65 int xstride[ATMEL_HLCDC_LAYER_MAX_PLANES];
66 int pstride[ATMEL_HLCDC_LAYER_MAX_PLANES];
69 /* DMA descriptors. */
70 struct atmel_hlcdc_dma_channel_dscr *dscrs[ATMEL_HLCDC_LAYER_MAX_PLANES];
73 static inline struct atmel_hlcdc_plane_state *
74 drm_plane_state_to_atmel_hlcdc_plane_state(struct drm_plane_state *s)
76 return container_of(s, struct atmel_hlcdc_plane_state, base);
79 #define SUBPIXEL_MASK 0xffff
81 static uint32_t rgb_formats[] = {
94 struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats = {
95 .formats = rgb_formats,
96 .nformats = ARRAY_SIZE(rgb_formats),
99 static uint32_t rgb_and_yuv_formats[] = {
121 struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_and_yuv_formats = {
122 .formats = rgb_and_yuv_formats,
123 .nformats = ARRAY_SIZE(rgb_and_yuv_formats),
126 static int atmel_hlcdc_format_to_plane_mode(u32 format, u32 *mode)
130 *mode = ATMEL_HLCDC_C8_MODE;
132 case DRM_FORMAT_XRGB4444:
133 *mode = ATMEL_HLCDC_XRGB4444_MODE;
135 case DRM_FORMAT_ARGB4444:
136 *mode = ATMEL_HLCDC_ARGB4444_MODE;
138 case DRM_FORMAT_RGBA4444:
139 *mode = ATMEL_HLCDC_RGBA4444_MODE;
141 case DRM_FORMAT_RGB565:
142 *mode = ATMEL_HLCDC_RGB565_MODE;
144 case DRM_FORMAT_RGB888:
145 *mode = ATMEL_HLCDC_RGB888_MODE;
147 case DRM_FORMAT_ARGB1555:
148 *mode = ATMEL_HLCDC_ARGB1555_MODE;
150 case DRM_FORMAT_XRGB8888:
151 *mode = ATMEL_HLCDC_XRGB8888_MODE;
153 case DRM_FORMAT_ARGB8888:
154 *mode = ATMEL_HLCDC_ARGB8888_MODE;
156 case DRM_FORMAT_RGBA8888:
157 *mode = ATMEL_HLCDC_RGBA8888_MODE;
159 case DRM_FORMAT_AYUV:
160 *mode = ATMEL_HLCDC_AYUV_MODE;
162 case DRM_FORMAT_YUYV:
163 *mode = ATMEL_HLCDC_YUYV_MODE;
165 case DRM_FORMAT_UYVY:
166 *mode = ATMEL_HLCDC_UYVY_MODE;
168 case DRM_FORMAT_YVYU:
169 *mode = ATMEL_HLCDC_YVYU_MODE;
171 case DRM_FORMAT_VYUY:
172 *mode = ATMEL_HLCDC_VYUY_MODE;
174 case DRM_FORMAT_NV21:
175 *mode = ATMEL_HLCDC_NV21_MODE;
177 case DRM_FORMAT_NV61:
178 *mode = ATMEL_HLCDC_NV61_MODE;
180 case DRM_FORMAT_YUV420:
181 *mode = ATMEL_HLCDC_YUV420_MODE;
183 case DRM_FORMAT_YUV422:
184 *mode = ATMEL_HLCDC_YUV422_MODE;
193 static u32 heo_downscaling_xcoef[] = {
212 static u32 heo_downscaling_ycoef[] = {
223 static u32 heo_upscaling_xcoef[] = {
242 static u32 heo_upscaling_ycoef[] = {
253 #define ATMEL_HLCDC_XPHIDEF 4
254 #define ATMEL_HLCDC_YPHIDEF 4
256 static u32 atmel_hlcdc_plane_phiscaler_get_factor(u32 srcsize,
260 u32 factor, max_memsize;
262 factor = (256 * ((8 * (srcsize - 1)) - phidef)) / (dstsize - 1);
263 max_memsize = ((factor * (dstsize - 1)) + (256 * phidef)) / 2048;
265 if (max_memsize > srcsize - 1)
272 atmel_hlcdc_plane_scaler_set_phicoeff(struct atmel_hlcdc_plane *plane,
273 const u32 *coeff_tab, int size,
274 unsigned int cfg_offs)
278 for (i = 0; i < size; i++)
279 atmel_hlcdc_layer_write_cfg(&plane->layer, cfg_offs + i,
283 void atmel_hlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane,
284 struct atmel_hlcdc_plane_state *state)
286 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
287 u32 xfactor, yfactor;
289 if (!desc->layout.scaler_config)
292 if (state->crtc_w == state->src_w && state->crtc_h == state->src_h) {
293 atmel_hlcdc_layer_write_cfg(&plane->layer,
294 desc->layout.scaler_config, 0);
298 if (desc->layout.phicoeffs.x) {
299 xfactor = atmel_hlcdc_plane_phiscaler_get_factor(state->src_w,
301 ATMEL_HLCDC_XPHIDEF);
303 yfactor = atmel_hlcdc_plane_phiscaler_get_factor(state->src_h,
305 ATMEL_HLCDC_YPHIDEF);
307 atmel_hlcdc_plane_scaler_set_phicoeff(plane,
308 state->crtc_w < state->src_w ?
309 heo_downscaling_xcoef :
311 ARRAY_SIZE(heo_upscaling_xcoef),
312 desc->layout.phicoeffs.x);
314 atmel_hlcdc_plane_scaler_set_phicoeff(plane,
315 state->crtc_h < state->src_h ?
316 heo_downscaling_ycoef :
318 ARRAY_SIZE(heo_upscaling_ycoef),
319 desc->layout.phicoeffs.y);
321 xfactor = (1024 * state->src_w) / state->crtc_w;
322 yfactor = (1024 * state->src_h) / state->crtc_h;
325 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config,
326 ATMEL_HLCDC_LAYER_SCALER_ENABLE |
327 ATMEL_HLCDC_LAYER_SCALER_FACTORS(xfactor,
332 atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane,
333 struct atmel_hlcdc_plane_state *state)
335 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
337 if (desc->layout.size)
338 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.size,
339 ATMEL_HLCDC_LAYER_SIZE(state->crtc_w,
342 if (desc->layout.memsize)
343 atmel_hlcdc_layer_write_cfg(&plane->layer,
344 desc->layout.memsize,
345 ATMEL_HLCDC_LAYER_SIZE(state->src_w,
348 if (desc->layout.pos)
349 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.pos,
350 ATMEL_HLCDC_LAYER_POS(state->crtc_x,
353 atmel_hlcdc_plane_setup_scaler(plane, state);
357 atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane,
358 struct atmel_hlcdc_plane_state *state)
360 unsigned int cfg = ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 | state->ahb_id;
361 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
362 const struct drm_format_info *format = state->base.fb->format;
365 * Rotation optimization is not working on RGB888 (rotation is still
366 * working but without any optimization).
368 if (format->format == DRM_FORMAT_RGB888)
369 cfg |= ATMEL_HLCDC_LAYER_DMA_ROTDIS;
371 atmel_hlcdc_layer_write_cfg(&plane->layer, ATMEL_HLCDC_LAYER_DMA_CFG,
374 cfg = ATMEL_HLCDC_LAYER_DMA | ATMEL_HLCDC_LAYER_REP;
376 if (plane->base.type != DRM_PLANE_TYPE_PRIMARY) {
377 cfg |= ATMEL_HLCDC_LAYER_OVR | ATMEL_HLCDC_LAYER_ITER2BL |
378 ATMEL_HLCDC_LAYER_ITER;
380 if (format->has_alpha)
381 cfg |= ATMEL_HLCDC_LAYER_LAEN;
383 cfg |= ATMEL_HLCDC_LAYER_GAEN |
384 ATMEL_HLCDC_LAYER_GA(state->base.alpha);
387 if (state->disc_h && state->disc_w)
388 cfg |= ATMEL_HLCDC_LAYER_DISCEN;
390 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.general_config,
394 static void atmel_hlcdc_plane_update_format(struct atmel_hlcdc_plane *plane,
395 struct atmel_hlcdc_plane_state *state)
400 ret = atmel_hlcdc_format_to_plane_mode(state->base.fb->format->format,
405 if ((state->base.fb->format->format == DRM_FORMAT_YUV422 ||
406 state->base.fb->format->format == DRM_FORMAT_NV61) &&
407 drm_rotation_90_or_270(state->base.rotation))
408 cfg |= ATMEL_HLCDC_YUV422ROT;
410 atmel_hlcdc_layer_write_cfg(&plane->layer,
411 ATMEL_HLCDC_LAYER_FORMAT_CFG, cfg);
414 static void atmel_hlcdc_plane_update_clut(struct atmel_hlcdc_plane *plane,
415 struct atmel_hlcdc_plane_state *state)
417 struct drm_crtc *crtc = state->base.crtc;
418 struct drm_color_lut *lut;
421 if (!crtc || !crtc->state)
424 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut)
427 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data;
429 for (idx = 0; idx < ATMEL_HLCDC_CLUT_SIZE; idx++, lut++) {
430 u32 val = ((lut->red << 8) & 0xff0000) |
431 (lut->green & 0xff00) |
434 atmel_hlcdc_layer_write_clut(&plane->layer, idx, val);
438 static void atmel_hlcdc_plane_update_buffers(struct atmel_hlcdc_plane *plane,
439 struct atmel_hlcdc_plane_state *state)
441 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
442 struct drm_framebuffer *fb = state->base.fb;
446 sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR);
448 for (i = 0; i < state->nplanes; i++) {
449 struct drm_gem_cma_object *gem = drm_fb_cma_get_gem_obj(fb, i);
451 state->dscrs[i]->addr = gem->paddr + state->offsets[i];
453 atmel_hlcdc_layer_write_reg(&plane->layer,
454 ATMEL_HLCDC_LAYER_PLANE_HEAD(i),
455 state->dscrs[i]->self);
457 if (!(sr & ATMEL_HLCDC_LAYER_EN)) {
458 atmel_hlcdc_layer_write_reg(&plane->layer,
459 ATMEL_HLCDC_LAYER_PLANE_ADDR(i),
460 state->dscrs[i]->addr);
461 atmel_hlcdc_layer_write_reg(&plane->layer,
462 ATMEL_HLCDC_LAYER_PLANE_CTRL(i),
463 state->dscrs[i]->ctrl);
464 atmel_hlcdc_layer_write_reg(&plane->layer,
465 ATMEL_HLCDC_LAYER_PLANE_NEXT(i),
466 state->dscrs[i]->self);
469 if (desc->layout.xstride[i])
470 atmel_hlcdc_layer_write_cfg(&plane->layer,
471 desc->layout.xstride[i],
474 if (desc->layout.pstride[i])
475 atmel_hlcdc_layer_write_cfg(&plane->layer,
476 desc->layout.pstride[i],
481 int atmel_hlcdc_plane_prepare_ahb_routing(struct drm_crtc_state *c_state)
483 unsigned int ahb_load[2] = { };
484 struct drm_plane *plane;
486 drm_atomic_crtc_state_for_each_plane(plane, c_state) {
487 struct atmel_hlcdc_plane_state *plane_state;
488 struct drm_plane_state *plane_s;
489 unsigned int pixels, load = 0;
492 plane_s = drm_atomic_get_plane_state(c_state->state, plane);
494 return PTR_ERR(plane_s);
497 drm_plane_state_to_atmel_hlcdc_plane_state(plane_s);
499 pixels = (plane_state->src_w * plane_state->src_h) -
500 (plane_state->disc_w * plane_state->disc_h);
502 for (i = 0; i < plane_state->nplanes; i++)
503 load += pixels * plane_state->bpp[i];
505 if (ahb_load[0] <= ahb_load[1])
506 plane_state->ahb_id = 0;
508 plane_state->ahb_id = 1;
510 ahb_load[plane_state->ahb_id] += load;
517 atmel_hlcdc_plane_prepare_disc_area(struct drm_crtc_state *c_state)
519 int disc_x = 0, disc_y = 0, disc_w = 0, disc_h = 0;
520 const struct atmel_hlcdc_layer_cfg_layout *layout;
521 struct atmel_hlcdc_plane_state *primary_state;
522 struct drm_plane_state *primary_s;
523 struct atmel_hlcdc_plane *primary;
524 struct drm_plane *ovl;
526 primary = drm_plane_to_atmel_hlcdc_plane(c_state->crtc->primary);
527 layout = &primary->layer.desc->layout;
528 if (!layout->disc_pos || !layout->disc_size)
531 primary_s = drm_atomic_get_plane_state(c_state->state,
533 if (IS_ERR(primary_s))
534 return PTR_ERR(primary_s);
536 primary_state = drm_plane_state_to_atmel_hlcdc_plane_state(primary_s);
538 drm_atomic_crtc_state_for_each_plane(ovl, c_state) {
539 struct atmel_hlcdc_plane_state *ovl_state;
540 struct drm_plane_state *ovl_s;
542 if (ovl == c_state->crtc->primary)
545 ovl_s = drm_atomic_get_plane_state(c_state->state, ovl);
547 return PTR_ERR(ovl_s);
549 ovl_state = drm_plane_state_to_atmel_hlcdc_plane_state(ovl_s);
551 if (!ovl_s->visible ||
553 ovl_s->fb->format->has_alpha ||
554 ovl_s->alpha != DRM_BLEND_ALPHA_OPAQUE)
557 /* TODO: implement a smarter hidden area detection */
558 if (ovl_state->crtc_h * ovl_state->crtc_w < disc_h * disc_w)
561 disc_x = ovl_state->crtc_x;
562 disc_y = ovl_state->crtc_y;
563 disc_h = ovl_state->crtc_h;
564 disc_w = ovl_state->crtc_w;
567 primary_state->disc_x = disc_x;
568 primary_state->disc_y = disc_y;
569 primary_state->disc_w = disc_w;
570 primary_state->disc_h = disc_h;
576 atmel_hlcdc_plane_update_disc_area(struct atmel_hlcdc_plane *plane,
577 struct atmel_hlcdc_plane_state *state)
579 const struct atmel_hlcdc_layer_cfg_layout *layout;
581 layout = &plane->layer.desc->layout;
582 if (!layout->disc_pos || !layout->disc_size)
585 atmel_hlcdc_layer_write_cfg(&plane->layer, layout->disc_pos,
586 ATMEL_HLCDC_LAYER_DISC_POS(state->disc_x,
589 atmel_hlcdc_layer_write_cfg(&plane->layer, layout->disc_size,
590 ATMEL_HLCDC_LAYER_DISC_SIZE(state->disc_w,
594 static int atmel_hlcdc_plane_atomic_check(struct drm_plane *p,
595 struct drm_plane_state *s)
597 struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
598 struct atmel_hlcdc_plane_state *state =
599 drm_plane_state_to_atmel_hlcdc_plane_state(s);
600 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
601 struct drm_framebuffer *fb = state->base.fb;
602 const struct drm_display_mode *mode;
603 struct drm_crtc_state *crtc_state;
607 if (!state->base.crtc || !fb)
610 crtc_state = drm_atomic_get_existing_crtc_state(s->state, s->crtc);
611 mode = &crtc_state->adjusted_mode;
613 ret = drm_atomic_helper_check_plane_state(s, crtc_state,
615 INT_MAX, true, true);
616 if (ret || !s->visible)
619 state->src_x = s->src.x1;
620 state->src_y = s->src.y1;
621 state->src_w = drm_rect_width(&s->src);
622 state->src_h = drm_rect_height(&s->src);
623 state->crtc_x = s->dst.x1;
624 state->crtc_y = s->dst.y1;
625 state->crtc_w = drm_rect_width(&s->dst);
626 state->crtc_h = drm_rect_height(&s->dst);
628 if ((state->src_x | state->src_y | state->src_w | state->src_h) &
637 state->nplanes = fb->format->num_planes;
638 if (state->nplanes > ATMEL_HLCDC_LAYER_MAX_PLANES)
641 for (i = 0; i < state->nplanes; i++) {
642 unsigned int offset = 0;
643 int xdiv = i ? fb->format->hsub : 1;
644 int ydiv = i ? fb->format->vsub : 1;
646 state->bpp[i] = fb->format->cpp[i];
650 switch (state->base.rotation & DRM_MODE_ROTATE_MASK) {
651 case DRM_MODE_ROTATE_90:
652 offset = (state->src_y / ydiv) *
654 offset += ((state->src_x + state->src_w - 1) /
655 xdiv) * state->bpp[i];
656 state->xstride[i] = -(((state->src_h - 1) / ydiv) *
659 state->pstride[i] = fb->pitches[i] - state->bpp[i];
661 case DRM_MODE_ROTATE_180:
662 offset = ((state->src_y + state->src_h - 1) /
663 ydiv) * fb->pitches[i];
664 offset += ((state->src_x + state->src_w - 1) /
665 xdiv) * state->bpp[i];
666 state->xstride[i] = ((((state->src_w - 1) / xdiv) - 1) *
667 state->bpp[i]) - fb->pitches[i];
668 state->pstride[i] = -2 * state->bpp[i];
670 case DRM_MODE_ROTATE_270:
671 offset = ((state->src_y + state->src_h - 1) /
672 ydiv) * fb->pitches[i];
673 offset += (state->src_x / xdiv) * state->bpp[i];
674 state->xstride[i] = ((state->src_h - 1) / ydiv) *
676 state->pstride[i] = -fb->pitches[i] - state->bpp[i];
678 case DRM_MODE_ROTATE_0:
680 offset = (state->src_y / ydiv) * fb->pitches[i];
681 offset += (state->src_x / xdiv) * state->bpp[i];
682 state->xstride[i] = fb->pitches[i] -
683 ((state->src_w / xdiv) *
685 state->pstride[i] = 0;
689 state->offsets[i] = offset + fb->offsets[i];
693 * Swap width and size in case of 90 or 270 degrees rotation
695 if (drm_rotation_90_or_270(state->base.rotation)) {
696 swap(state->src_w, state->src_h);
699 if (!desc->layout.size &&
700 (mode->hdisplay != state->crtc_w ||
701 mode->vdisplay != state->crtc_h))
704 if ((state->crtc_h != state->src_h || state->crtc_w != state->src_w) &&
705 (!desc->layout.memsize ||
706 state->base.fb->format->has_alpha))
712 static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p,
713 struct drm_plane_state *old_state)
715 struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
717 /* Disable interrupts */
718 atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IDR,
721 /* Disable the layer */
722 atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHDR,
723 ATMEL_HLCDC_LAYER_RST |
724 ATMEL_HLCDC_LAYER_A2Q |
725 ATMEL_HLCDC_LAYER_UPDATE);
727 /* Clear all pending interrupts */
728 atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR);
731 static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p,
732 struct drm_plane_state *old_s)
734 struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
735 struct atmel_hlcdc_plane_state *state =
736 drm_plane_state_to_atmel_hlcdc_plane_state(p->state);
739 if (!p->state->crtc || !p->state->fb)
742 if (!state->base.visible) {
743 atmel_hlcdc_plane_atomic_disable(p, old_s);
747 atmel_hlcdc_plane_update_pos_and_size(plane, state);
748 atmel_hlcdc_plane_update_general_settings(plane, state);
749 atmel_hlcdc_plane_update_format(plane, state);
750 atmel_hlcdc_plane_update_clut(plane, state);
751 atmel_hlcdc_plane_update_buffers(plane, state);
752 atmel_hlcdc_plane_update_disc_area(plane, state);
754 /* Enable the overrun interrupts. */
755 atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IER,
756 ATMEL_HLCDC_LAYER_OVR_IRQ(0) |
757 ATMEL_HLCDC_LAYER_OVR_IRQ(1) |
758 ATMEL_HLCDC_LAYER_OVR_IRQ(2));
760 /* Apply the new config at the next SOF event. */
761 sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR);
762 atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHER,
763 ATMEL_HLCDC_LAYER_UPDATE |
764 (sr & ATMEL_HLCDC_LAYER_EN ?
765 ATMEL_HLCDC_LAYER_A2Q : ATMEL_HLCDC_LAYER_EN));
768 static int atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane)
770 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
772 if (desc->type == ATMEL_HLCDC_OVERLAY_LAYER ||
773 desc->type == ATMEL_HLCDC_CURSOR_LAYER) {
776 ret = drm_plane_create_alpha_property(&plane->base);
781 if (desc->layout.xstride[0] && desc->layout.pstride[0]) {
784 ret = drm_plane_create_rotation_property(&plane->base,
788 DRM_MODE_ROTATE_180 |
789 DRM_MODE_ROTATE_270);
794 if (desc->layout.csc) {
796 * TODO: decare a "yuv-to-rgb-conv-factors" property to let
797 * userspace modify these factors (using a BLOB property ?).
799 atmel_hlcdc_layer_write_cfg(&plane->layer,
802 atmel_hlcdc_layer_write_cfg(&plane->layer,
803 desc->layout.csc + 1,
805 atmel_hlcdc_layer_write_cfg(&plane->layer,
806 desc->layout.csc + 2,
813 void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane)
815 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc;
818 isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR);
821 * There's not much we can do in case of overrun except informing
822 * the user. However, we are in interrupt context here, hence the
826 (ATMEL_HLCDC_LAYER_OVR_IRQ(0) | ATMEL_HLCDC_LAYER_OVR_IRQ(1) |
827 ATMEL_HLCDC_LAYER_OVR_IRQ(2)))
828 dev_dbg(plane->base.dev->dev, "overrun on plane %s\n",
832 static const struct drm_plane_helper_funcs atmel_hlcdc_layer_plane_helper_funcs = {
833 .atomic_check = atmel_hlcdc_plane_atomic_check,
834 .atomic_update = atmel_hlcdc_plane_atomic_update,
835 .atomic_disable = atmel_hlcdc_plane_atomic_disable,
838 static int atmel_hlcdc_plane_alloc_dscrs(struct drm_plane *p,
839 struct atmel_hlcdc_plane_state *state)
841 struct atmel_hlcdc_dc *dc = p->dev->dev_private;
844 for (i = 0; i < ARRAY_SIZE(state->dscrs); i++) {
845 struct atmel_hlcdc_dma_channel_dscr *dscr;
848 dscr = dma_pool_alloc(dc->dscrpool, GFP_KERNEL, &dscr_dma);
853 dscr->next = dscr_dma;
854 dscr->self = dscr_dma;
855 dscr->ctrl = ATMEL_HLCDC_LAYER_DFETCH;
857 state->dscrs[i] = dscr;
863 for (i--; i >= 0; i--) {
864 dma_pool_free(dc->dscrpool, state->dscrs[i],
865 state->dscrs[i]->self);
871 static void atmel_hlcdc_plane_reset(struct drm_plane *p)
873 struct atmel_hlcdc_plane_state *state;
876 state = drm_plane_state_to_atmel_hlcdc_plane_state(p->state);
879 drm_framebuffer_put(state->base.fb);
885 state = kzalloc(sizeof(*state), GFP_KERNEL);
887 if (atmel_hlcdc_plane_alloc_dscrs(p, state)) {
890 "Failed to allocate initial plane state\n");
893 __drm_atomic_helper_plane_reset(p, &state->base);
897 static struct drm_plane_state *
898 atmel_hlcdc_plane_atomic_duplicate_state(struct drm_plane *p)
900 struct atmel_hlcdc_plane_state *state =
901 drm_plane_state_to_atmel_hlcdc_plane_state(p->state);
902 struct atmel_hlcdc_plane_state *copy;
904 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
908 if (atmel_hlcdc_plane_alloc_dscrs(p, copy)) {
914 drm_framebuffer_get(copy->base.fb);
919 static void atmel_hlcdc_plane_atomic_destroy_state(struct drm_plane *p,
920 struct drm_plane_state *s)
922 struct atmel_hlcdc_plane_state *state =
923 drm_plane_state_to_atmel_hlcdc_plane_state(s);
924 struct atmel_hlcdc_dc *dc = p->dev->dev_private;
927 for (i = 0; i < ARRAY_SIZE(state->dscrs); i++) {
928 dma_pool_free(dc->dscrpool, state->dscrs[i],
929 state->dscrs[i]->self);
933 drm_framebuffer_put(s->fb);
938 static const struct drm_plane_funcs layer_plane_funcs = {
939 .update_plane = drm_atomic_helper_update_plane,
940 .disable_plane = drm_atomic_helper_disable_plane,
941 .destroy = drm_plane_cleanup,
942 .reset = atmel_hlcdc_plane_reset,
943 .atomic_duplicate_state = atmel_hlcdc_plane_atomic_duplicate_state,
944 .atomic_destroy_state = atmel_hlcdc_plane_atomic_destroy_state,
947 static int atmel_hlcdc_plane_create(struct drm_device *dev,
948 const struct atmel_hlcdc_layer_desc *desc)
950 struct atmel_hlcdc_dc *dc = dev->dev_private;
951 struct atmel_hlcdc_plane *plane;
952 enum drm_plane_type type;
955 plane = devm_kzalloc(dev->dev, sizeof(*plane), GFP_KERNEL);
959 atmel_hlcdc_layer_init(&plane->layer, desc, dc->hlcdc->regmap);
961 if (desc->type == ATMEL_HLCDC_BASE_LAYER)
962 type = DRM_PLANE_TYPE_PRIMARY;
963 else if (desc->type == ATMEL_HLCDC_CURSOR_LAYER)
964 type = DRM_PLANE_TYPE_CURSOR;
966 type = DRM_PLANE_TYPE_OVERLAY;
968 ret = drm_universal_plane_init(dev, &plane->base, 0,
970 desc->formats->formats,
971 desc->formats->nformats,
976 drm_plane_helper_add(&plane->base,
977 &atmel_hlcdc_layer_plane_helper_funcs);
979 /* Set default property values*/
980 ret = atmel_hlcdc_plane_init_properties(plane);
984 dc->layers[desc->id] = &plane->layer;
989 int atmel_hlcdc_create_planes(struct drm_device *dev)
991 struct atmel_hlcdc_dc *dc = dev->dev_private;
992 const struct atmel_hlcdc_layer_desc *descs = dc->desc->layers;
993 int nlayers = dc->desc->nlayers;
996 dc->dscrpool = dmam_pool_create("atmel-hlcdc-dscr", dev->dev,
997 sizeof(struct atmel_hlcdc_dma_channel_dscr),
1002 for (i = 0; i < nlayers; i++) {
1003 if (descs[i].type != ATMEL_HLCDC_BASE_LAYER &&
1004 descs[i].type != ATMEL_HLCDC_OVERLAY_LAYER &&
1005 descs[i].type != ATMEL_HLCDC_CURSOR_LAYER)
1008 ret = atmel_hlcdc_plane_create(dev, &descs[i]);