1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Russell King
4 * Rewritten from the dovefb driver, and Armada510 manuals.
7 #include <drm/armada_drm.h>
8 #include <drm/drm_atomic.h>
9 #include <drm/drm_atomic_helper.h>
10 #include <drm/drm_atomic_uapi.h>
11 #include <drm/drm_fourcc.h>
12 #include <drm/drm_plane_helper.h>
14 #include "armada_crtc.h"
15 #include "armada_drm.h"
16 #include "armada_fb.h"
17 #include "armada_gem.h"
18 #include "armada_hw.h"
19 #include "armada_ioctlP.h"
20 #include "armada_plane.h"
21 #include "armada_trace.h"
23 #define DEFAULT_BRIGHTNESS 0
24 #define DEFAULT_CONTRAST 0x4000
25 #define DEFAULT_SATURATION 0x4000
26 #define DEFAULT_ENCODING DRM_COLOR_YCBCR_BT601
28 struct armada_overlay_state {
29 struct armada_plane_state base;
39 #define drm_to_overlay_state(s) \
40 container_of(s, struct armada_overlay_state, base.base)
42 static inline u32 armada_spu_contrast(struct drm_plane_state *state)
44 return drm_to_overlay_state(state)->brightness << 16 |
45 drm_to_overlay_state(state)->contrast;
48 static inline u32 armada_spu_saturation(struct drm_plane_state *state)
50 /* Docs say 15:0, but it seems to actually be 31:16 on Armada 510 */
51 return drm_to_overlay_state(state)->saturation << 16;
54 static inline u32 armada_csc(struct drm_plane_state *state)
57 * The CFG_CSC_RGB_* settings control the output of the colour space
58 * converter, setting the range of output values it produces. Since
59 * we will be blending with the full-range graphics, we need to
60 * produce full-range RGB output from the conversion.
62 return CFG_CSC_RGB_COMPUTER |
63 (state->color_encoding == DRM_COLOR_YCBCR_BT709 ?
64 CFG_CSC_YUV_CCIR709 : CFG_CSC_YUV_CCIR601);
67 /* === Plane support === */
68 static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane,
69 struct drm_atomic_state *state)
71 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
73 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
75 struct armada_crtc *dcrtc;
76 struct armada_regs *regs;
78 u32 cfg, cfg_mask, val;
80 DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
82 if (!new_state->fb || WARN_ON(!new_state->crtc))
85 DRM_DEBUG_KMS("[PLANE:%d:%s] is on [CRTC:%d:%s] with [FB:%d] visible %u->%u\n",
86 plane->base.id, plane->name,
87 new_state->crtc->base.id, new_state->crtc->name,
88 new_state->fb->base.id,
89 old_state->visible, new_state->visible);
91 dcrtc = drm_to_armada_crtc(new_state->crtc);
92 regs = dcrtc->regs + dcrtc->regs_idx;
95 if (!old_state->visible && new_state->visible)
96 armada_reg_queue_mod(regs, idx,
97 0, CFG_PDWN16x66 | CFG_PDWN32x66,
99 val = armada_src_hw(new_state);
100 if (armada_src_hw(old_state) != val)
101 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_HPXL_VLN);
102 val = armada_dst_yx(new_state);
103 if (armada_dst_yx(old_state) != val)
104 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN);
105 val = armada_dst_hw(new_state);
106 if (armada_dst_hw(old_state) != val)
107 armada_reg_queue_set(regs, idx, val, LCD_SPU_DZM_HPXL_VLN);
108 /* FIXME: overlay on an interlaced display */
109 if (old_state->src.x1 != new_state->src.x1 ||
110 old_state->src.y1 != new_state->src.y1 ||
111 old_state->fb != new_state->fb ||
112 new_state->crtc->state->mode_changed) {
113 const struct drm_format_info *format;
116 armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 0),
117 LCD_SPU_DMA_START_ADDR_Y0);
118 armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 1),
119 LCD_SPU_DMA_START_ADDR_U0);
120 armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 2),
121 LCD_SPU_DMA_START_ADDR_V0);
122 armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 0),
123 LCD_SPU_DMA_START_ADDR_Y1);
124 armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 1),
125 LCD_SPU_DMA_START_ADDR_U1);
126 armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 2),
127 LCD_SPU_DMA_START_ADDR_V1);
129 val = armada_pitch(new_state, 0) << 16 | armada_pitch(new_state,
131 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_YC);
132 val = armada_pitch(new_state, 1) << 16 | armada_pitch(new_state,
134 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_UV);
136 cfg = CFG_DMA_FMT(drm_fb_to_armada_fb(new_state->fb)->fmt) |
137 CFG_DMA_MOD(drm_fb_to_armada_fb(new_state->fb)->mod) |
139 if (new_state->visible)
143 * Shifting a YUV packed format image by one pixel causes the
144 * U/V planes to swap. Compensate for it by also toggling
147 format = new_state->fb->format;
148 src_x = new_state->src.x1 >> 16;
149 if (format->num_planes == 1 && src_x & (format->hsub - 1))
150 cfg ^= CFG_DMA_MOD(CFG_SWAPUV);
151 if (to_armada_plane_state(new_state)->interlace)
152 cfg |= CFG_DMA_FTOGGLE;
153 cfg_mask = CFG_CBSH_ENA | CFG_DMAFORMAT |
154 CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV |
155 CFG_SWAPYU | CFG_YUV2RGB) |
156 CFG_DMA_FTOGGLE | CFG_DMA_TSTMODE |
158 } else if (old_state->visible != new_state->visible) {
159 cfg = new_state->visible ? CFG_DMA_ENA : 0;
160 cfg_mask = CFG_DMA_ENA;
164 if (drm_rect_width(&old_state->src) != drm_rect_width(&new_state->src) ||
165 drm_rect_width(&old_state->dst) != drm_rect_width(&new_state->dst)) {
166 cfg_mask |= CFG_DMA_HSMOOTH;
167 if (drm_rect_width(&new_state->src) >> 16 !=
168 drm_rect_width(&new_state->dst))
169 cfg |= CFG_DMA_HSMOOTH;
173 armada_reg_queue_mod(regs, idx, cfg, cfg_mask,
176 val = armada_spu_contrast(new_state);
177 if ((!old_state->visible && new_state->visible) ||
178 armada_spu_contrast(old_state) != val)
179 armada_reg_queue_set(regs, idx, val, LCD_SPU_CONTRAST);
180 val = armada_spu_saturation(new_state);
181 if ((!old_state->visible && new_state->visible) ||
182 armada_spu_saturation(old_state) != val)
183 armada_reg_queue_set(regs, idx, val, LCD_SPU_SATURATION);
184 if (!old_state->visible && new_state->visible)
185 armada_reg_queue_set(regs, idx, 0x00002000, LCD_SPU_CBSH_HUE);
186 val = armada_csc(new_state);
187 if ((!old_state->visible && new_state->visible) ||
188 armada_csc(old_state) != val)
189 armada_reg_queue_mod(regs, idx, val, CFG_CSC_MASK,
190 LCD_SPU_IOPAD_CONTROL);
191 val = drm_to_overlay_state(new_state)->colorkey_yr;
192 if ((!old_state->visible && new_state->visible) ||
193 drm_to_overlay_state(old_state)->colorkey_yr != val)
194 armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_Y);
195 val = drm_to_overlay_state(new_state)->colorkey_ug;
196 if ((!old_state->visible && new_state->visible) ||
197 drm_to_overlay_state(old_state)->colorkey_ug != val)
198 armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_U);
199 val = drm_to_overlay_state(new_state)->colorkey_vb;
200 if ((!old_state->visible && new_state->visible) ||
201 drm_to_overlay_state(old_state)->colorkey_vb != val)
202 armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_V);
203 val = drm_to_overlay_state(new_state)->colorkey_mode;
204 if ((!old_state->visible && new_state->visible) ||
205 drm_to_overlay_state(old_state)->colorkey_mode != val)
206 armada_reg_queue_mod(regs, idx, val, CFG_CKMODE_MASK |
207 CFG_ALPHAM_MASK | CFG_ALPHA_MASK,
209 val = drm_to_overlay_state(new_state)->colorkey_enable;
210 if (((!old_state->visible && new_state->visible) ||
211 drm_to_overlay_state(old_state)->colorkey_enable != val) &&
212 dcrtc->variant->has_spu_adv_reg)
213 armada_reg_queue_mod(regs, idx, val, ADV_GRACOLORKEY |
214 ADV_VIDCOLORKEY, LCD_SPU_ADV_REG);
216 dcrtc->regs_idx += idx;
219 static void armada_drm_overlay_plane_atomic_disable(struct drm_plane *plane,
220 struct drm_atomic_state *state)
222 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
224 struct armada_crtc *dcrtc;
225 struct armada_regs *regs;
226 unsigned int idx = 0;
228 DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
230 if (!old_state->crtc)
233 DRM_DEBUG_KMS("[PLANE:%d:%s] was on [CRTC:%d:%s] with [FB:%d]\n",
234 plane->base.id, plane->name,
235 old_state->crtc->base.id, old_state->crtc->name,
236 old_state->fb->base.id);
238 dcrtc = drm_to_armada_crtc(old_state->crtc);
239 regs = dcrtc->regs + dcrtc->regs_idx;
241 /* Disable plane and power down the YUV FIFOs */
242 armada_reg_queue_mod(regs, idx, 0, CFG_DMA_ENA, LCD_SPU_DMA_CTRL0);
243 armada_reg_queue_mod(regs, idx, CFG_PDWN16x66 | CFG_PDWN32x66, 0,
246 dcrtc->regs_idx += idx;
249 static const struct drm_plane_helper_funcs armada_overlay_plane_helper_funcs = {
250 .atomic_check = armada_drm_plane_atomic_check,
251 .atomic_update = armada_drm_overlay_plane_atomic_update,
252 .atomic_disable = armada_drm_overlay_plane_atomic_disable,
256 armada_overlay_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
257 struct drm_framebuffer *fb,
258 int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h,
259 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h,
260 struct drm_modeset_acquire_ctx *ctx)
262 struct drm_atomic_state *state;
263 struct drm_plane_state *plane_state;
266 trace_armada_ovl_plane_update(plane, crtc, fb,
267 crtc_x, crtc_y, crtc_w, crtc_h,
268 src_x, src_y, src_w, src_h);
270 state = drm_atomic_state_alloc(plane->dev);
274 state->acquire_ctx = ctx;
275 plane_state = drm_atomic_get_plane_state(state, plane);
276 if (IS_ERR(plane_state)) {
277 ret = PTR_ERR(plane_state);
281 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
285 drm_atomic_set_fb_for_plane(plane_state, fb);
286 plane_state->crtc_x = crtc_x;
287 plane_state->crtc_y = crtc_y;
288 plane_state->crtc_h = crtc_h;
289 plane_state->crtc_w = crtc_w;
290 plane_state->src_x = src_x;
291 plane_state->src_y = src_y;
292 plane_state->src_h = src_h;
293 plane_state->src_w = src_w;
295 ret = drm_atomic_nonblocking_commit(state);
297 drm_atomic_state_put(state);
301 static void armada_overlay_reset(struct drm_plane *plane)
303 struct armada_overlay_state *state;
306 __drm_atomic_helper_plane_destroy_state(plane->state);
310 state = kzalloc(sizeof(*state), GFP_KERNEL);
312 state->colorkey_yr = 0xfefefe00;
313 state->colorkey_ug = 0x01010100;
314 state->colorkey_vb = 0x01010100;
315 state->colorkey_mode = CFG_CKMODE(CKMODE_RGB) |
316 CFG_ALPHAM_GRA | CFG_ALPHA(0);
317 state->colorkey_enable = ADV_GRACOLORKEY;
318 state->brightness = DEFAULT_BRIGHTNESS;
319 state->contrast = DEFAULT_CONTRAST;
320 state->saturation = DEFAULT_SATURATION;
321 __drm_atomic_helper_plane_reset(plane, &state->base.base);
322 state->base.base.color_encoding = DEFAULT_ENCODING;
323 state->base.base.color_range = DRM_COLOR_YCBCR_LIMITED_RANGE;
327 static struct drm_plane_state *
328 armada_overlay_duplicate_state(struct drm_plane *plane)
330 struct armada_overlay_state *state;
332 if (WARN_ON(!plane->state))
335 state = kmemdup(plane->state, sizeof(*state), GFP_KERNEL);
337 __drm_atomic_helper_plane_duplicate_state(plane,
339 return &state->base.base;
342 static int armada_overlay_set_property(struct drm_plane *plane,
343 struct drm_plane_state *state, struct drm_property *property,
346 struct armada_private *priv = drm_to_armada_dev(plane->dev);
348 #define K2R(val) (((val) >> 0) & 0xff)
349 #define K2G(val) (((val) >> 8) & 0xff)
350 #define K2B(val) (((val) >> 16) & 0xff)
351 if (property == priv->colorkey_prop) {
352 #define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8)
353 drm_to_overlay_state(state)->colorkey_yr = CCC(K2R(val));
354 drm_to_overlay_state(state)->colorkey_ug = CCC(K2G(val));
355 drm_to_overlay_state(state)->colorkey_vb = CCC(K2B(val));
357 } else if (property == priv->colorkey_min_prop) {
358 drm_to_overlay_state(state)->colorkey_yr &= ~0x00ff0000;
359 drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 16;
360 drm_to_overlay_state(state)->colorkey_ug &= ~0x00ff0000;
361 drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 16;
362 drm_to_overlay_state(state)->colorkey_vb &= ~0x00ff0000;
363 drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 16;
364 } else if (property == priv->colorkey_max_prop) {
365 drm_to_overlay_state(state)->colorkey_yr &= ~0xff000000;
366 drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 24;
367 drm_to_overlay_state(state)->colorkey_ug &= ~0xff000000;
368 drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 24;
369 drm_to_overlay_state(state)->colorkey_vb &= ~0xff000000;
370 drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 24;
371 } else if (property == priv->colorkey_val_prop) {
372 drm_to_overlay_state(state)->colorkey_yr &= ~0x0000ff00;
373 drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 8;
374 drm_to_overlay_state(state)->colorkey_ug &= ~0x0000ff00;
375 drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 8;
376 drm_to_overlay_state(state)->colorkey_vb &= ~0x0000ff00;
377 drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 8;
378 } else if (property == priv->colorkey_alpha_prop) {
379 drm_to_overlay_state(state)->colorkey_yr &= ~0x000000ff;
380 drm_to_overlay_state(state)->colorkey_yr |= K2R(val);
381 drm_to_overlay_state(state)->colorkey_ug &= ~0x000000ff;
382 drm_to_overlay_state(state)->colorkey_ug |= K2G(val);
383 drm_to_overlay_state(state)->colorkey_vb &= ~0x000000ff;
384 drm_to_overlay_state(state)->colorkey_vb |= K2B(val);
385 } else if (property == priv->colorkey_mode_prop) {
386 if (val == CKMODE_DISABLE) {
387 drm_to_overlay_state(state)->colorkey_mode =
388 CFG_CKMODE(CKMODE_DISABLE) |
389 CFG_ALPHAM_CFG | CFG_ALPHA(255);
390 drm_to_overlay_state(state)->colorkey_enable = 0;
392 drm_to_overlay_state(state)->colorkey_mode =
394 CFG_ALPHAM_GRA | CFG_ALPHA(0);
395 drm_to_overlay_state(state)->colorkey_enable =
398 } else if (property == priv->brightness_prop) {
399 drm_to_overlay_state(state)->brightness = val - 256;
400 } else if (property == priv->contrast_prop) {
401 drm_to_overlay_state(state)->contrast = val;
402 } else if (property == priv->saturation_prop) {
403 drm_to_overlay_state(state)->saturation = val;
410 static int armada_overlay_get_property(struct drm_plane *plane,
411 const struct drm_plane_state *state, struct drm_property *property,
414 struct armada_private *priv = drm_to_armada_dev(plane->dev);
416 #define C2K(c,s) (((c) >> (s)) & 0xff)
417 #define R2BGR(r,g,b,s) (C2K(r,s) << 0 | C2K(g,s) << 8 | C2K(b,s) << 16)
418 if (property == priv->colorkey_prop) {
419 /* Do best-efforts here for this property */
420 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
421 drm_to_overlay_state(state)->colorkey_ug,
422 drm_to_overlay_state(state)->colorkey_vb, 16);
423 /* If min != max, or min != val, error out */
424 if (*val != R2BGR(drm_to_overlay_state(state)->colorkey_yr,
425 drm_to_overlay_state(state)->colorkey_ug,
426 drm_to_overlay_state(state)->colorkey_vb, 24) ||
427 *val != R2BGR(drm_to_overlay_state(state)->colorkey_yr,
428 drm_to_overlay_state(state)->colorkey_ug,
429 drm_to_overlay_state(state)->colorkey_vb, 8))
431 } else if (property == priv->colorkey_min_prop) {
432 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
433 drm_to_overlay_state(state)->colorkey_ug,
434 drm_to_overlay_state(state)->colorkey_vb, 16);
435 } else if (property == priv->colorkey_max_prop) {
436 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
437 drm_to_overlay_state(state)->colorkey_ug,
438 drm_to_overlay_state(state)->colorkey_vb, 24);
439 } else if (property == priv->colorkey_val_prop) {
440 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
441 drm_to_overlay_state(state)->colorkey_ug,
442 drm_to_overlay_state(state)->colorkey_vb, 8);
443 } else if (property == priv->colorkey_alpha_prop) {
444 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
445 drm_to_overlay_state(state)->colorkey_ug,
446 drm_to_overlay_state(state)->colorkey_vb, 0);
447 } else if (property == priv->colorkey_mode_prop) {
448 *val = (drm_to_overlay_state(state)->colorkey_mode &
449 CFG_CKMODE_MASK) >> ffs(CFG_CKMODE_MASK);
450 } else if (property == priv->brightness_prop) {
451 *val = drm_to_overlay_state(state)->brightness + 256;
452 } else if (property == priv->contrast_prop) {
453 *val = drm_to_overlay_state(state)->contrast;
454 } else if (property == priv->saturation_prop) {
455 *val = drm_to_overlay_state(state)->saturation;
462 static const struct drm_plane_funcs armada_ovl_plane_funcs = {
463 .update_plane = armada_overlay_plane_update,
464 .disable_plane = drm_atomic_helper_disable_plane,
465 .destroy = drm_plane_helper_destroy,
466 .reset = armada_overlay_reset,
467 .atomic_duplicate_state = armada_overlay_duplicate_state,
468 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
469 .atomic_set_property = armada_overlay_set_property,
470 .atomic_get_property = armada_overlay_get_property,
473 static const uint32_t armada_ovl_formats[] = {
494 static const struct drm_prop_enum_list armada_drm_colorkey_enum_list[] = {
495 { CKMODE_DISABLE, "disabled" },
496 { CKMODE_Y, "Y component" },
497 { CKMODE_U, "U component" },
498 { CKMODE_V, "V component" },
499 { CKMODE_RGB, "RGB" },
500 { CKMODE_R, "R component" },
501 { CKMODE_G, "G component" },
502 { CKMODE_B, "B component" },
505 static int armada_overlay_create_properties(struct drm_device *dev)
507 struct armada_private *priv = drm_to_armada_dev(dev);
509 if (priv->colorkey_prop)
512 priv->colorkey_prop = drm_property_create_range(dev, 0,
513 "colorkey", 0, 0xffffff);
514 priv->colorkey_min_prop = drm_property_create_range(dev, 0,
515 "colorkey_min", 0, 0xffffff);
516 priv->colorkey_max_prop = drm_property_create_range(dev, 0,
517 "colorkey_max", 0, 0xffffff);
518 priv->colorkey_val_prop = drm_property_create_range(dev, 0,
519 "colorkey_val", 0, 0xffffff);
520 priv->colorkey_alpha_prop = drm_property_create_range(dev, 0,
521 "colorkey_alpha", 0, 0xffffff);
522 priv->colorkey_mode_prop = drm_property_create_enum(dev, 0,
524 armada_drm_colorkey_enum_list,
525 ARRAY_SIZE(armada_drm_colorkey_enum_list));
526 priv->brightness_prop = drm_property_create_range(dev, 0,
527 "brightness", 0, 256 + 255);
528 priv->contrast_prop = drm_property_create_range(dev, 0,
529 "contrast", 0, 0x7fff);
530 priv->saturation_prop = drm_property_create_range(dev, 0,
531 "saturation", 0, 0x7fff);
533 if (!priv->colorkey_prop)
539 int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs)
541 struct armada_private *priv = drm_to_armada_dev(dev);
542 struct drm_mode_object *mobj;
543 struct drm_plane *overlay;
546 ret = armada_overlay_create_properties(dev);
550 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
554 drm_plane_helper_add(overlay, &armada_overlay_plane_helper_funcs);
556 ret = drm_universal_plane_init(dev, overlay, crtcs,
557 &armada_ovl_plane_funcs,
559 ARRAY_SIZE(armada_ovl_formats),
561 DRM_PLANE_TYPE_OVERLAY, NULL);
567 mobj = &overlay->base;
568 drm_object_attach_property(mobj, priv->colorkey_prop,
570 drm_object_attach_property(mobj, priv->colorkey_min_prop,
572 drm_object_attach_property(mobj, priv->colorkey_max_prop,
574 drm_object_attach_property(mobj, priv->colorkey_val_prop,
576 drm_object_attach_property(mobj, priv->colorkey_alpha_prop,
578 drm_object_attach_property(mobj, priv->colorkey_mode_prop,
580 drm_object_attach_property(mobj, priv->brightness_prop,
581 256 + DEFAULT_BRIGHTNESS);
582 drm_object_attach_property(mobj, priv->contrast_prop,
584 drm_object_attach_property(mobj, priv->saturation_prop,
587 ret = drm_plane_create_color_properties(overlay,
588 BIT(DRM_COLOR_YCBCR_BT601) |
589 BIT(DRM_COLOR_YCBCR_BT709),
590 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE),
592 DRM_COLOR_YCBCR_LIMITED_RANGE);