drivers/gpu/drm/armada/armada_overlay.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012 Russell King
   4  *  Rewritten from the dovefb driver, and Armada510 manuals.
   5  */
   6
   7 #include <drm/armada_drm.h>
   8 #include <drm/drm_atomic.h>
   9 #include <drm/drm_atomic_helper.h>
  10 #include <drm/drm_atomic_uapi.h>
  11 #include <drm/drm_fourcc.h>
  12 #include <drm/drm_plane_helper.h>
  13
  14 #include "armada_crtc.h"
  15 #include "armada_drm.h"
  16 #include "armada_fb.h"
  17 #include "armada_gem.h"
  18 #include "armada_hw.h"
  19 #include "armada_ioctlP.h"
  20 #include "armada_plane.h"
  21 #include "armada_trace.h"
  22
  23 #define DEFAULT_BRIGHTNESS      0
  24 #define DEFAULT_CONTRAST        0x4000
  25 #define DEFAULT_SATURATION      0x4000
  26 #define DEFAULT_ENCODING        DRM_COLOR_YCBCR_BT601
  27
  28 struct armada_overlay_state {
  29         struct armada_plane_state base;
  30         u32 colorkey_yr;
  31         u32 colorkey_ug;
  32         u32 colorkey_vb;
  33         u32 colorkey_mode;
  34         u32 colorkey_enable;
  35         s16 brightness;
  36         u16 contrast;
  37         u16 saturation;
  38 };
  39 #define drm_to_overlay_state(s) \
  40         container_of(s, struct armada_overlay_state, base.base)
  41
  42 static inline u32 armada_spu_contrast(struct drm_plane_state *state)
  43 {
  44         return drm_to_overlay_state(state)->brightness << 16 |
  45                drm_to_overlay_state(state)->contrast;
  46 }
  47
  48 static inline u32 armada_spu_saturation(struct drm_plane_state *state)
  49 {
  50         /* Docs say 15:0, but it seems to actually be 31:16 on Armada 510 */
  51         return drm_to_overlay_state(state)->saturation << 16;
  52 }
  53
  54 static inline u32 armada_csc(struct drm_plane_state *state)
  55 {
  56         /*
  57          * The CFG_CSC_RGB_* settings control the output of the colour space
  58          * converter, setting the range of output values it produces.  Since
  59          * we will be blending with the full-range graphics, we need to
  60          * produce full-range RGB output from the conversion.
  61          */
  62         return CFG_CSC_RGB_COMPUTER |
  63                (state->color_encoding == DRM_COLOR_YCBCR_BT709 ?
  64                         CFG_CSC_YUV_CCIR709 : CFG_CSC_YUV_CCIR601);
  65 }
  66
  67 /* === Plane support === */
  68 static void armada_drm_overlay_plane_atomic_update(struct drm_plane *plane,
  69         struct drm_atomic_state *state)
  70 {
  71         struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
  72                                                                            plane);
  73         struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
  74                                                                            plane);
  75         struct armada_crtc *dcrtc;
  76         struct armada_regs *regs;
  77         unsigned int idx;
  78         u32 cfg, cfg_mask, val;
  79
  80         DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
  81
  82         if (!new_state->fb || WARN_ON(!new_state->crtc))
  83                 return;
  84
  85         DRM_DEBUG_KMS("[PLANE:%d:%s] is on [CRTC:%d:%s] with [FB:%d] visible %u->%u\n",
  86                 plane->base.id, plane->name,
  87                 new_state->crtc->base.id, new_state->crtc->name,
  88                 new_state->fb->base.id,
  89                 old_state->visible, new_state->visible);
  90
  91         dcrtc = drm_to_armada_crtc(new_state->crtc);
  92         regs = dcrtc->regs + dcrtc->regs_idx;
  93
  94         idx = 0;
  95         if (!old_state->visible && new_state->visible)
  96                 armada_reg_queue_mod(regs, idx,
  97                                      0, CFG_PDWN16x66 | CFG_PDWN32x66,
  98                                      LCD_SPU_SRAM_PARA1);
  99         val = armada_src_hw(new_state);
 100         if (armada_src_hw(old_state) != val)
 101                 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_HPXL_VLN);
 102         val = armada_dst_yx(new_state);
 103         if (armada_dst_yx(old_state) != val)
 104                 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN);
 105         val = armada_dst_hw(new_state);
 106         if (armada_dst_hw(old_state) != val)
 107                 armada_reg_queue_set(regs, idx, val, LCD_SPU_DZM_HPXL_VLN);
 108         /* FIXME: overlay on an interlaced display */
 109         if (old_state->src.x1 != new_state->src.x1 ||
 110             old_state->src.y1 != new_state->src.y1 ||
 111             old_state->fb != new_state->fb ||
 112             new_state->crtc->state->mode_changed) {
 113                 const struct drm_format_info *format;
 114                 u16 src_x;
 115
 116                 armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 0),
 117                                      LCD_SPU_DMA_START_ADDR_Y0);
 118                 armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 1),
 119                                      LCD_SPU_DMA_START_ADDR_U0);
 120                 armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 2),
 121                                      LCD_SPU_DMA_START_ADDR_V0);
 122                 armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 0),
 123                                      LCD_SPU_DMA_START_ADDR_Y1);
 124                 armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 1),
 125                                      LCD_SPU_DMA_START_ADDR_U1);
 126                 armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 2),
 127                                      LCD_SPU_DMA_START_ADDR_V1);
 128
 129                 val = armada_pitch(new_state, 0) << 16 | armada_pitch(new_state,
 130                                                                       0);
 131                 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_YC);
 132                 val = armada_pitch(new_state, 1) << 16 | armada_pitch(new_state,
 133                                                                       2);
 134                 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_UV);
 135
 136                 cfg = CFG_DMA_FMT(drm_fb_to_armada_fb(new_state->fb)->fmt) |
 137                       CFG_DMA_MOD(drm_fb_to_armada_fb(new_state->fb)->mod) |
 138                       CFG_CBSH_ENA;
 139                 if (new_state->visible)
 140                         cfg |= CFG_DMA_ENA;
 141
 142                 /*
 143                  * Shifting a YUV packed format image by one pixel causes the
 144                  * U/V planes to swap.  Compensate for it by also toggling
 145                  * the UV swap.
 146                  */
 147                 format = new_state->fb->format;
 148                 src_x = new_state->src.x1 >> 16;
 149                 if (format->num_planes == 1 && src_x & (format->hsub - 1))
 150                         cfg ^= CFG_DMA_MOD(CFG_SWAPUV);
 151                 if (to_armada_plane_state(new_state)->interlace)
 152                         cfg |= CFG_DMA_FTOGGLE;
 153                 cfg_mask = CFG_CBSH_ENA | CFG_DMAFORMAT |
 154                            CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV |
 155                                        CFG_SWAPYU | CFG_YUV2RGB) |
 156                            CFG_DMA_FTOGGLE | CFG_DMA_TSTMODE |
 157                            CFG_DMA_ENA;
 158         } else if (old_state->visible != new_state->visible) {
 159                 cfg = new_state->visible ? CFG_DMA_ENA : 0;
 160                 cfg_mask = CFG_DMA_ENA;
 161         } else {
 162                 cfg = cfg_mask = 0;
 163         }
 164         if (drm_rect_width(&old_state->src) != drm_rect_width(&new_state->src) ||
 165             drm_rect_width(&old_state->dst) != drm_rect_width(&new_state->dst)) {
 166                 cfg_mask |= CFG_DMA_HSMOOTH;
 167                 if (drm_rect_width(&new_state->src) >> 16 !=
 168                     drm_rect_width(&new_state->dst))
 169                         cfg |= CFG_DMA_HSMOOTH;
 170         }
 171
 172         if (cfg_mask)
 173                 armada_reg_queue_mod(regs, idx, cfg, cfg_mask,
 174                                      LCD_SPU_DMA_CTRL0);
 175
 176         val = armada_spu_contrast(new_state);
 177         if ((!old_state->visible && new_state->visible) ||
 178             armada_spu_contrast(old_state) != val)
 179                 armada_reg_queue_set(regs, idx, val, LCD_SPU_CONTRAST);
 180         val = armada_spu_saturation(new_state);
 181         if ((!old_state->visible && new_state->visible) ||
 182             armada_spu_saturation(old_state) != val)
 183                 armada_reg_queue_set(regs, idx, val, LCD_SPU_SATURATION);
 184         if (!old_state->visible && new_state->visible)
 185                 armada_reg_queue_set(regs, idx, 0x00002000, LCD_SPU_CBSH_HUE);
 186         val = armada_csc(new_state);
 187         if ((!old_state->visible && new_state->visible) ||
 188             armada_csc(old_state) != val)
 189                 armada_reg_queue_mod(regs, idx, val, CFG_CSC_MASK,
 190                                      LCD_SPU_IOPAD_CONTROL);
 191         val = drm_to_overlay_state(new_state)->colorkey_yr;
 192         if ((!old_state->visible && new_state->visible) ||
 193             drm_to_overlay_state(old_state)->colorkey_yr != val)
 194                 armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_Y);
 195         val = drm_to_overlay_state(new_state)->colorkey_ug;
 196         if ((!old_state->visible && new_state->visible) ||
 197             drm_to_overlay_state(old_state)->colorkey_ug != val)
 198                 armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_U);
 199         val = drm_to_overlay_state(new_state)->colorkey_vb;
 200         if ((!old_state->visible && new_state->visible) ||
 201             drm_to_overlay_state(old_state)->colorkey_vb != val)
 202                 armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_V);
 203         val = drm_to_overlay_state(new_state)->colorkey_mode;
 204         if ((!old_state->visible && new_state->visible) ||
 205             drm_to_overlay_state(old_state)->colorkey_mode != val)
 206                 armada_reg_queue_mod(regs, idx, val, CFG_CKMODE_MASK |
 207                                      CFG_ALPHAM_MASK | CFG_ALPHA_MASK,
 208                                      LCD_SPU_DMA_CTRL1);
 209         val = drm_to_overlay_state(new_state)->colorkey_enable;
 210         if (((!old_state->visible && new_state->visible) ||
 211              drm_to_overlay_state(old_state)->colorkey_enable != val) &&
 212             dcrtc->variant->has_spu_adv_reg)
 213                 armada_reg_queue_mod(regs, idx, val, ADV_GRACOLORKEY |
 214                                      ADV_VIDCOLORKEY, LCD_SPU_ADV_REG);
 215
 216         dcrtc->regs_idx += idx;
 217 }
 218
 219 static void armada_drm_overlay_plane_atomic_disable(struct drm_plane *plane,
 220         struct drm_atomic_state *state)
 221 {
 222         struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
 223                                                                            plane);
 224         struct armada_crtc *dcrtc;
 225         struct armada_regs *regs;
 226         unsigned int idx = 0;
 227
 228         DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
 229
 230         if (!old_state->crtc)
 231                 return;
 232
 233         DRM_DEBUG_KMS("[PLANE:%d:%s] was on [CRTC:%d:%s] with [FB:%d]\n",
 234                 plane->base.id, plane->name,
 235                 old_state->crtc->base.id, old_state->crtc->name,
 236                 old_state->fb->base.id);
 237
 238         dcrtc = drm_to_armada_crtc(old_state->crtc);
 239         regs = dcrtc->regs + dcrtc->regs_idx;
 240
 241         /* Disable plane and power down the YUV FIFOs */
 242         armada_reg_queue_mod(regs, idx, 0, CFG_DMA_ENA, LCD_SPU_DMA_CTRL0);
 243         armada_reg_queue_mod(regs, idx, CFG_PDWN16x66 | CFG_PDWN32x66, 0,
 244                              LCD_SPU_SRAM_PARA1);
 245
 246         dcrtc->regs_idx += idx;
 247 }
 248
 249 static const struct drm_plane_helper_funcs armada_overlay_plane_helper_funcs = {
 250         .prepare_fb     = armada_drm_plane_prepare_fb,
 251         .cleanup_fb     = armada_drm_plane_cleanup_fb,
 252         .atomic_check   = armada_drm_plane_atomic_check,
 253         .atomic_update  = armada_drm_overlay_plane_atomic_update,
 254         .atomic_disable = armada_drm_overlay_plane_atomic_disable,
 255 };
 256
 257 static int
 258 armada_overlay_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
 259         struct drm_framebuffer *fb,
 260         int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h,
 261         uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h,
 262         struct drm_modeset_acquire_ctx *ctx)
 263 {
 264         struct drm_atomic_state *state;
 265         struct drm_plane_state *plane_state;
 266         int ret = 0;
 267
 268         trace_armada_ovl_plane_update(plane, crtc, fb,
 269                                  crtc_x, crtc_y, crtc_w, crtc_h,
 270                                  src_x, src_y, src_w, src_h);
 271
 272         state = drm_atomic_state_alloc(plane->dev);
 273         if (!state)
 274                 return -ENOMEM;
 275
 276         state->acquire_ctx = ctx;
 277         plane_state = drm_atomic_get_plane_state(state, plane);
 278         if (IS_ERR(plane_state)) {
 279                 ret = PTR_ERR(plane_state);
 280                 goto fail;
 281         }
 282
 283         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
 284         if (ret != 0)
 285                 goto fail;
 286
 287         drm_atomic_set_fb_for_plane(plane_state, fb);
 288         plane_state->crtc_x = crtc_x;
 289         plane_state->crtc_y = crtc_y;
 290         plane_state->crtc_h = crtc_h;
 291         plane_state->crtc_w = crtc_w;
 292         plane_state->src_x = src_x;
 293         plane_state->src_y = src_y;
 294         plane_state->src_h = src_h;
 295         plane_state->src_w = src_w;
 296
 297         ret = drm_atomic_nonblocking_commit(state);
 298 fail:
 299         drm_atomic_state_put(state);
 300         return ret;
 301 }
 302
 303 static void armada_ovl_plane_destroy(struct drm_plane *plane)
 304 {
 305         drm_plane_cleanup(plane);
 306         kfree(plane);
 307 }
 308
 309 static void armada_overlay_reset(struct drm_plane *plane)
 310 {
 311         struct armada_overlay_state *state;
 312
 313         if (plane->state)
 314                 __drm_atomic_helper_plane_destroy_state(plane->state);
 315         kfree(plane->state);
 316         plane->state = NULL;
 317
 318         state = kzalloc(sizeof(*state), GFP_KERNEL);
 319         if (state) {
 320                 state->colorkey_yr = 0xfefefe00;
 321                 state->colorkey_ug = 0x01010100;
 322                 state->colorkey_vb = 0x01010100;
 323                 state->colorkey_mode = CFG_CKMODE(CKMODE_RGB) |
 324                                        CFG_ALPHAM_GRA | CFG_ALPHA(0);
 325                 state->colorkey_enable = ADV_GRACOLORKEY;
 326                 state->brightness = DEFAULT_BRIGHTNESS;
 327                 state->contrast = DEFAULT_CONTRAST;
 328                 state->saturation = DEFAULT_SATURATION;
 329                 __drm_atomic_helper_plane_reset(plane, &state->base.base);
 330                 state->base.base.color_encoding = DEFAULT_ENCODING;
 331                 state->base.base.color_range = DRM_COLOR_YCBCR_LIMITED_RANGE;
 332         }
 333 }
 334
 335 static struct drm_plane_state *
 336 armada_overlay_duplicate_state(struct drm_plane *plane)
 337 {
 338         struct armada_overlay_state *state;
 339
 340         if (WARN_ON(!plane->state))
 341                 return NULL;
 342
 343         state = kmemdup(plane->state, sizeof(*state), GFP_KERNEL);
 344         if (state)
 345                 __drm_atomic_helper_plane_duplicate_state(plane,
 346                                                           &state->base.base);
 347         return &state->base.base;
 348 }
 349
 350 static int armada_overlay_set_property(struct drm_plane *plane,
 351         struct drm_plane_state *state, struct drm_property *property,
 352         uint64_t val)
 353 {
 354         struct armada_private *priv = drm_to_armada_dev(plane->dev);
 355
 356 #define K2R(val) (((val) >> 0) & 0xff)
 357 #define K2G(val) (((val) >> 8) & 0xff)
 358 #define K2B(val) (((val) >> 16) & 0xff)
 359         if (property == priv->colorkey_prop) {
 360 #define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8)
 361                 drm_to_overlay_state(state)->colorkey_yr = CCC(K2R(val));
 362                 drm_to_overlay_state(state)->colorkey_ug = CCC(K2G(val));
 363                 drm_to_overlay_state(state)->colorkey_vb = CCC(K2B(val));
 364 #undef CCC
 365         } else if (property == priv->colorkey_min_prop) {
 366                 drm_to_overlay_state(state)->colorkey_yr &= ~0x00ff0000;
 367                 drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 16;
 368                 drm_to_overlay_state(state)->colorkey_ug &= ~0x00ff0000;
 369                 drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 16;
 370                 drm_to_overlay_state(state)->colorkey_vb &= ~0x00ff0000;
 371                 drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 16;
 372         } else if (property == priv->colorkey_max_prop) {
 373                 drm_to_overlay_state(state)->colorkey_yr &= ~0xff000000;
 374                 drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 24;
 375                 drm_to_overlay_state(state)->colorkey_ug &= ~0xff000000;
 376                 drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 24;
 377                 drm_to_overlay_state(state)->colorkey_vb &= ~0xff000000;
 378                 drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 24;
 379         } else if (property == priv->colorkey_val_prop) {
 380                 drm_to_overlay_state(state)->colorkey_yr &= ~0x0000ff00;
 381                 drm_to_overlay_state(state)->colorkey_yr |= K2R(val) << 8;
 382                 drm_to_overlay_state(state)->colorkey_ug &= ~0x0000ff00;
 383                 drm_to_overlay_state(state)->colorkey_ug |= K2G(val) << 8;
 384                 drm_to_overlay_state(state)->colorkey_vb &= ~0x0000ff00;
 385                 drm_to_overlay_state(state)->colorkey_vb |= K2B(val) << 8;
 386         } else if (property == priv->colorkey_alpha_prop) {
 387                 drm_to_overlay_state(state)->colorkey_yr &= ~0x000000ff;
 388                 drm_to_overlay_state(state)->colorkey_yr |= K2R(val);
 389                 drm_to_overlay_state(state)->colorkey_ug &= ~0x000000ff;
 390                 drm_to_overlay_state(state)->colorkey_ug |= K2G(val);
 391                 drm_to_overlay_state(state)->colorkey_vb &= ~0x000000ff;
 392                 drm_to_overlay_state(state)->colorkey_vb |= K2B(val);
 393         } else if (property == priv->colorkey_mode_prop) {
 394                 if (val == CKMODE_DISABLE) {
 395                         drm_to_overlay_state(state)->colorkey_mode =
 396                                 CFG_CKMODE(CKMODE_DISABLE) |
 397                                 CFG_ALPHAM_CFG | CFG_ALPHA(255);
 398                         drm_to_overlay_state(state)->colorkey_enable = 0;
 399                 } else {
 400                         drm_to_overlay_state(state)->colorkey_mode =
 401                                 CFG_CKMODE(val) |
 402                                 CFG_ALPHAM_GRA | CFG_ALPHA(0);
 403                         drm_to_overlay_state(state)->colorkey_enable =
 404                                 ADV_GRACOLORKEY;
 405                 }
 406         } else if (property == priv->brightness_prop) {
 407                 drm_to_overlay_state(state)->brightness = val - 256;
 408         } else if (property == priv->contrast_prop) {
 409                 drm_to_overlay_state(state)->contrast = val;
 410         } else if (property == priv->saturation_prop) {
 411                 drm_to_overlay_state(state)->saturation = val;
 412         } else {
 413                 return -EINVAL;
 414         }
 415         return 0;
 416 }
 417
 418 static int armada_overlay_get_property(struct drm_plane *plane,
 419         const struct drm_plane_state *state, struct drm_property *property,
 420         uint64_t *val)
 421 {
 422         struct armada_private *priv = drm_to_armada_dev(plane->dev);
 423
 424 #define C2K(c,s)        (((c) >> (s)) & 0xff)
 425 #define R2BGR(r,g,b,s)  (C2K(r,s) << 0 | C2K(g,s) << 8 | C2K(b,s) << 16)
 426         if (property == priv->colorkey_prop) {
 427                 /* Do best-efforts here for this property */
 428                 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
 429                              drm_to_overlay_state(state)->colorkey_ug,
 430                              drm_to_overlay_state(state)->colorkey_vb, 16);
 431                 /* If min != max, or min != val, error out */
 432                 if (*val != R2BGR(drm_to_overlay_state(state)->colorkey_yr,
 433                                   drm_to_overlay_state(state)->colorkey_ug,
 434                                   drm_to_overlay_state(state)->colorkey_vb, 24) ||
 435                     *val != R2BGR(drm_to_overlay_state(state)->colorkey_yr,
 436                                   drm_to_overlay_state(state)->colorkey_ug,
 437                                   drm_to_overlay_state(state)->colorkey_vb, 8))
 438                         return -EINVAL;
 439         } else if (property == priv->colorkey_min_prop) {
 440                 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
 441                              drm_to_overlay_state(state)->colorkey_ug,
 442                              drm_to_overlay_state(state)->colorkey_vb, 16);
 443         } else if (property == priv->colorkey_max_prop) {
 444                 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
 445                              drm_to_overlay_state(state)->colorkey_ug,
 446                              drm_to_overlay_state(state)->colorkey_vb, 24);
 447         } else if (property == priv->colorkey_val_prop) {
 448                 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
 449                              drm_to_overlay_state(state)->colorkey_ug,
 450                              drm_to_overlay_state(state)->colorkey_vb, 8);
 451         } else if (property == priv->colorkey_alpha_prop) {
 452                 *val = R2BGR(drm_to_overlay_state(state)->colorkey_yr,
 453                              drm_to_overlay_state(state)->colorkey_ug,
 454                              drm_to_overlay_state(state)->colorkey_vb, 0);
 455         } else if (property == priv->colorkey_mode_prop) {
 456                 *val = (drm_to_overlay_state(state)->colorkey_mode &
 457                         CFG_CKMODE_MASK) >> ffs(CFG_CKMODE_MASK);
 458         } else if (property == priv->brightness_prop) {
 459                 *val = drm_to_overlay_state(state)->brightness + 256;
 460         } else if (property == priv->contrast_prop) {
 461                 *val = drm_to_overlay_state(state)->contrast;
 462         } else if (property == priv->saturation_prop) {
 463                 *val = drm_to_overlay_state(state)->saturation;
 464         } else {
 465                 return -EINVAL;
 466         }
 467         return 0;
 468 }
 469
 470 static const struct drm_plane_funcs armada_ovl_plane_funcs = {
 471         .update_plane   = armada_overlay_plane_update,
 472         .disable_plane  = drm_atomic_helper_disable_plane,
 473         .destroy        = armada_ovl_plane_destroy,
 474         .reset          = armada_overlay_reset,
 475         .atomic_duplicate_state = armada_overlay_duplicate_state,
 476         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
 477         .atomic_set_property = armada_overlay_set_property,
 478         .atomic_get_property = armada_overlay_get_property,
 479 };
 480
 481 static const uint32_t armada_ovl_formats[] = {
 482         DRM_FORMAT_UYVY,
 483         DRM_FORMAT_YUYV,
 484         DRM_FORMAT_YUV420,
 485         DRM_FORMAT_YVU420,
 486         DRM_FORMAT_YUV422,
 487         DRM_FORMAT_YVU422,
 488         DRM_FORMAT_VYUY,
 489         DRM_FORMAT_YVYU,
 490         DRM_FORMAT_ARGB8888,
 491         DRM_FORMAT_ABGR8888,
 492         DRM_FORMAT_XRGB8888,
 493         DRM_FORMAT_XBGR8888,
 494         DRM_FORMAT_RGB888,
 495         DRM_FORMAT_BGR888,
 496         DRM_FORMAT_ARGB1555,
 497         DRM_FORMAT_ABGR1555,
 498         DRM_FORMAT_RGB565,
 499         DRM_FORMAT_BGR565,
 500 };
 501
 502 static const struct drm_prop_enum_list armada_drm_colorkey_enum_list[] = {
 503         { CKMODE_DISABLE, "disabled" },
 504         { CKMODE_Y,       "Y component" },
 505         { CKMODE_U,       "U component" },
 506         { CKMODE_V,       "V component" },
 507         { CKMODE_RGB,     "RGB" },
 508         { CKMODE_R,       "R component" },
 509         { CKMODE_G,       "G component" },
 510         { CKMODE_B,       "B component" },
 511 };
 512
 513 static int armada_overlay_create_properties(struct drm_device *dev)
 514 {
 515         struct armada_private *priv = drm_to_armada_dev(dev);
 516
 517         if (priv->colorkey_prop)
 518                 return 0;
 519
 520         priv->colorkey_prop = drm_property_create_range(dev, 0,
 521                                 "colorkey", 0, 0xffffff);
 522         priv->colorkey_min_prop = drm_property_create_range(dev, 0,
 523                                 "colorkey_min", 0, 0xffffff);
 524         priv->colorkey_max_prop = drm_property_create_range(dev, 0,
 525                                 "colorkey_max", 0, 0xffffff);
 526         priv->colorkey_val_prop = drm_property_create_range(dev, 0,
 527                                 "colorkey_val", 0, 0xffffff);
 528         priv->colorkey_alpha_prop = drm_property_create_range(dev, 0,
 529                                 "colorkey_alpha", 0, 0xffffff);
 530         priv->colorkey_mode_prop = drm_property_create_enum(dev, 0,
 531                                 "colorkey_mode",
 532                                 armada_drm_colorkey_enum_list,
 533                                 ARRAY_SIZE(armada_drm_colorkey_enum_list));
 534         priv->brightness_prop = drm_property_create_range(dev, 0,
 535                                 "brightness", 0, 256 + 255);
 536         priv->contrast_prop = drm_property_create_range(dev, 0,
 537                                 "contrast", 0, 0x7fff);
 538         priv->saturation_prop = drm_property_create_range(dev, 0,
 539                                 "saturation", 0, 0x7fff);
 540
 541         if (!priv->colorkey_prop)
 542                 return -ENOMEM;
 543
 544         return 0;
 545 }
 546
 547 int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs)
 548 {
 549         struct armada_private *priv = drm_to_armada_dev(dev);
 550         struct drm_mode_object *mobj;
 551         struct drm_plane *overlay;
 552         int ret;
 553
 554         ret = armada_overlay_create_properties(dev);
 555         if (ret)
 556                 return ret;
 557
 558         overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
 559         if (!overlay)
 560                 return -ENOMEM;
 561
 562         drm_plane_helper_add(overlay, &armada_overlay_plane_helper_funcs);
 563
 564         ret = drm_universal_plane_init(dev, overlay, crtcs,
 565                                        &armada_ovl_plane_funcs,
 566                                        armada_ovl_formats,
 567                                        ARRAY_SIZE(armada_ovl_formats),
 568                                        NULL,
 569                                        DRM_PLANE_TYPE_OVERLAY, NULL);
 570         if (ret) {
 571                 kfree(overlay);
 572                 return ret;
 573         }
 574
 575         mobj = &overlay->base;
 576         drm_object_attach_property(mobj, priv->colorkey_prop,
 577                                    0x0101fe);
 578         drm_object_attach_property(mobj, priv->colorkey_min_prop,
 579                                    0x0101fe);
 580         drm_object_attach_property(mobj, priv->colorkey_max_prop,
 581                                    0x0101fe);
 582         drm_object_attach_property(mobj, priv->colorkey_val_prop,
 583                                    0x0101fe);
 584         drm_object_attach_property(mobj, priv->colorkey_alpha_prop,
 585                                    0x000000);
 586         drm_object_attach_property(mobj, priv->colorkey_mode_prop,
 587                                    CKMODE_RGB);
 588         drm_object_attach_property(mobj, priv->brightness_prop,
 589                                    256 + DEFAULT_BRIGHTNESS);
 590         drm_object_attach_property(mobj, priv->contrast_prop,
 591                                    DEFAULT_CONTRAST);
 592         drm_object_attach_property(mobj, priv->saturation_prop,
 593                                    DEFAULT_SATURATION);
 594
 595         ret = drm_plane_create_color_properties(overlay,
 596                                                 BIT(DRM_COLOR_YCBCR_BT601) |
 597                                                 BIT(DRM_COLOR_YCBCR_BT709),
 598                                                 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE),
 599                                                 DEFAULT_ENCODING,
 600                                                 DRM_COLOR_YCBCR_LIMITED_RANGE);
 601
 602         return ret;
 603 }