drivers/gpu/drm/arm/malidp_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
   4  * Author: Liviu Dudau <Liviu.Dudau@arm.com>
   5  *
   6  * ARM Mali DP500/DP550/DP650 driver (crtc operations)
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/pm_runtime.h>
  11
  12 #include <video/videomode.h>
  13
  14 #include <drm/drm_atomic.h>
  15 #include <drm/drm_atomic_helper.h>
  16 #include <drm/drm_crtc.h>
  17 #include <drm/drm_print.h>
  18 #include <drm/drm_probe_helper.h>
  19 #include <drm/drm_vblank.h>
  20
  21 #include "malidp_drv.h"
  22 #include "malidp_hw.h"
  23
  24 static enum drm_mode_status malidp_crtc_mode_valid(struct drm_crtc *crtc,
  25                                                    const struct drm_display_mode *mode)
  26 {
  27         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  28         struct malidp_hw_device *hwdev = malidp->dev;
  29
  30         /*
  31          * check that the hardware can drive the required clock rate,
  32          * but skip the check if the clock is meant to be disabled (req_rate = 0)
  33          */
  34         long rate, req_rate = mode->crtc_clock * 1000;
  35
  36         if (req_rate) {
  37                 rate = clk_round_rate(hwdev->pxlclk, req_rate);
  38                 if (rate != req_rate) {
  39                         DRM_DEBUG_DRIVER("pxlclk doesn't support %ld Hz\n",
  40                                          req_rate);
  41                         return MODE_NOCLOCK;
  42                 }
  43         }
  44
  45         return MODE_OK;
  46 }
  47
  48 static void malidp_crtc_atomic_enable(struct drm_crtc *crtc,
  49                                       struct drm_crtc_state *old_state)
  50 {
  51         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  52         struct malidp_hw_device *hwdev = malidp->dev;
  53         struct videomode vm;
  54         int err = pm_runtime_get_sync(crtc->dev->dev);
  55
  56         if (err < 0) {
  57                 DRM_DEBUG_DRIVER("Failed to enable runtime power management: %d\n", err);
  58                 return;
  59         }
  60
  61         drm_display_mode_to_videomode(&crtc->state->adjusted_mode, &vm);
  62         clk_prepare_enable(hwdev->pxlclk);
  63
  64         /* We rely on firmware to set mclk to a sensible level. */
  65         clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000);
  66
  67         hwdev->hw->modeset(hwdev, &vm);
  68         hwdev->hw->leave_config_mode(hwdev);
  69         drm_crtc_vblank_on(crtc);
  70 }
  71
  72 static void malidp_crtc_atomic_disable(struct drm_crtc *crtc,
  73                                        struct drm_crtc_state *old_state)
  74 {
  75         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  76         struct malidp_hw_device *hwdev = malidp->dev;
  77         int err;
  78
  79         /* always disable planes on the CRTC that is being turned off */
  80         drm_atomic_helper_disable_planes_on_crtc(old_state, false);
  81
  82         drm_crtc_vblank_off(crtc);
  83         hwdev->hw->enter_config_mode(hwdev);
  84
  85         clk_disable_unprepare(hwdev->pxlclk);
  86
  87         err = pm_runtime_put(crtc->dev->dev);
  88         if (err < 0) {
  89                 DRM_DEBUG_DRIVER("Failed to disable runtime power management: %d\n", err);
  90         }
  91 }
  92
  93 static const struct gamma_curve_segment {
  94         u16 start;
  95         u16 end;
  96 } segments[MALIDP_COEFFTAB_NUM_COEFFS] = {
  97         /* sector 0 */
  98         {    0,    0 }, {    1,    1 }, {    2,    2 }, {    3,    3 },
  99         {    4,    4 }, {    5,    5 }, {    6,    6 }, {    7,    7 },
 100         {    8,    8 }, {    9,    9 }, {   10,   10 }, {   11,   11 },
 101         {   12,   12 }, {   13,   13 }, {   14,   14 }, {   15,   15 },
 102         /* sector 1 */
 103         {   16,   19 }, {   20,   23 }, {   24,   27 }, {   28,   31 },
 104         /* sector 2 */
 105         {   32,   39 }, {   40,   47 }, {   48,   55 }, {   56,   63 },
 106         /* sector 3 */
 107         {   64,   79 }, {   80,   95 }, {   96,  111 }, {  112,  127 },
 108         /* sector 4 */
 109         {  128,  159 }, {  160,  191 }, {  192,  223 }, {  224,  255 },
 110         /* sector 5 */
 111         {  256,  319 }, {  320,  383 }, {  384,  447 }, {  448,  511 },
 112         /* sector 6 */
 113         {  512,  639 }, {  640,  767 }, {  768,  895 }, {  896, 1023 },
 114         { 1024, 1151 }, { 1152, 1279 }, { 1280, 1407 }, { 1408, 1535 },
 115         { 1536, 1663 }, { 1664, 1791 }, { 1792, 1919 }, { 1920, 2047 },
 116         { 2048, 2175 }, { 2176, 2303 }, { 2304, 2431 }, { 2432, 2559 },
 117         { 2560, 2687 }, { 2688, 2815 }, { 2816, 2943 }, { 2944, 3071 },
 118         { 3072, 3199 }, { 3200, 3327 }, { 3328, 3455 }, { 3456, 3583 },
 119         { 3584, 3711 }, { 3712, 3839 }, { 3840, 3967 }, { 3968, 4095 },
 120 };
 121
 122 #define DE_COEFTAB_DATA(a, b) ((((a) & 0xfff) << 16) | (((b) & 0xfff)))
 123
 124 static void malidp_generate_gamma_table(struct drm_property_blob *lut_blob,
 125                                         u32 coeffs[MALIDP_COEFFTAB_NUM_COEFFS])
 126 {
 127         struct drm_color_lut *lut = (struct drm_color_lut *)lut_blob->data;
 128         int i;
 129
 130         for (i = 0; i < MALIDP_COEFFTAB_NUM_COEFFS; ++i) {
 131                 u32 a, b, delta_in, out_start, out_end;
 132
 133                 delta_in = segments[i].end - segments[i].start;
 134                 /* DP has 12-bit internal precision for its LUTs. */
 135                 out_start = drm_color_lut_extract(lut[segments[i].start].green,
 136                                                   12);
 137                 out_end = drm_color_lut_extract(lut[segments[i].end].green, 12);
 138                 a = (delta_in == 0) ? 0 : ((out_end - out_start) * 256) / delta_in;
 139                 b = out_start;
 140                 coeffs[i] = DE_COEFTAB_DATA(a, b);
 141         }
 142 }
 143
 144 /*
 145  * Check if there is a new gamma LUT and if it is of an acceptable size. Also,
 146  * reject any LUTs that use distinct red, green, and blue curves.
 147  */
 148 static int malidp_crtc_atomic_check_gamma(struct drm_crtc *crtc,
 149                                           struct drm_crtc_state *state)
 150 {
 151         struct malidp_crtc_state *mc = to_malidp_crtc_state(state);
 152         struct drm_color_lut *lut;
 153         size_t lut_size;
 154         int i;
 155
 156         if (!state->color_mgmt_changed || !state->gamma_lut)
 157                 return 0;
 158
 159         if (crtc->state->gamma_lut &&
 160             (crtc->state->gamma_lut->base.id == state->gamma_lut->base.id))
 161                 return 0;
 162
 163         if (state->gamma_lut->length % sizeof(struct drm_color_lut))
 164                 return -EINVAL;
 165
 166         lut_size = state->gamma_lut->length / sizeof(struct drm_color_lut);
 167         if (lut_size != MALIDP_GAMMA_LUT_SIZE)
 168                 return -EINVAL;
 169
 170         lut = (struct drm_color_lut *)state->gamma_lut->data;
 171         for (i = 0; i < lut_size; ++i)
 172                 if (!((lut[i].red == lut[i].green) &&
 173                       (lut[i].red == lut[i].blue)))
 174                         return -EINVAL;
 175
 176         if (!state->mode_changed) {
 177                 int ret;
 178
 179                 state->mode_changed = true;
 180                 /*
 181                  * Kerneldoc for drm_atomic_helper_check_modeset mandates that
 182                  * it be invoked when the driver sets ->mode_changed. Since
 183                  * changing the gamma LUT doesn't depend on any external
 184                  * resources, it is safe to call it only once.
 185                  */
 186                 ret = drm_atomic_helper_check_modeset(crtc->dev, state->state);
 187                 if (ret)
 188                         return ret;
 189         }
 190
 191         malidp_generate_gamma_table(state->gamma_lut, mc->gamma_coeffs);
 192         return 0;
 193 }
 194
 195 /*
 196  * Check if there is a new CTM and if it contains valid input. Valid here means
 197  * that the number is inside the representable range for a Q3.12 number,
 198  * excluding truncating the fractional part of the input data.
 199  *
 200  * The COLORADJ registers can be changed atomically.
 201  */
 202 static int malidp_crtc_atomic_check_ctm(struct drm_crtc *crtc,
 203                                         struct drm_crtc_state *state)
 204 {
 205         struct malidp_crtc_state *mc = to_malidp_crtc_state(state);
 206         struct drm_color_ctm *ctm;
 207         int i;
 208
 209         if (!state->color_mgmt_changed)
 210                 return 0;
 211
 212         if (!state->ctm)
 213                 return 0;
 214
 215         if (crtc->state->ctm && (crtc->state->ctm->base.id ==
 216                                  state->ctm->base.id))
 217                 return 0;
 218
 219         /*
 220          * The size of the ctm is checked in
 221          * drm_atomic_replace_property_blob_from_id.
 222          */
 223         ctm = (struct drm_color_ctm *)state->ctm->data;
 224         for (i = 0; i < ARRAY_SIZE(ctm->matrix); ++i) {
 225                 /* Convert from S31.32 to Q3.12. */
 226                 s64 val = ctm->matrix[i];
 227                 u32 mag = ((((u64)val) & ~BIT_ULL(63)) >> 20) &
 228                           GENMASK_ULL(14, 0);
 229
 230                 /*
 231                  * Convert to 2s complement and check the destination's top bit
 232                  * for overflow. NB: Can't check before converting or it'd
 233                  * incorrectly reject the case:
 234                  * sign == 1
 235                  * mag == 0x2000
 236                  */
 237                 if (val & BIT_ULL(63))
 238                         mag = ~mag + 1;
 239                 if (!!(val & BIT_ULL(63)) != !!(mag & BIT(14)))
 240                         return -EINVAL;
 241                 mc->coloradj_coeffs[i] = mag;
 242         }
 243
 244         return 0;
 245 }
 246
 247 static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc,
 248                                             struct drm_crtc_state *state)
 249 {
 250         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
 251         struct malidp_hw_device *hwdev = malidp->dev;
 252         struct malidp_crtc_state *cs = to_malidp_crtc_state(state);
 253         struct malidp_se_config *s = &cs->scaler_config;
 254         struct drm_plane *plane;
 255         struct videomode vm;
 256         const struct drm_plane_state *pstate;
 257         u32 h_upscale_factor = 0; /* U16.16 */
 258         u32 v_upscale_factor = 0; /* U16.16 */
 259         u8 scaling = cs->scaled_planes_mask;
 260         int ret;
 261
 262         if (!scaling) {
 263                 s->scale_enable = false;
 264                 goto mclk_calc;
 265         }
 266
 267         /* The scaling engine can only handle one plane at a time. */
 268         if (scaling & (scaling - 1))
 269                 return -EINVAL;
 270
 271         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
 272                 struct malidp_plane *mp = to_malidp_plane(plane);
 273                 u32 phase;
 274
 275                 if (!(mp->layer->id & scaling))
 276                         continue;
 277
 278                 /*
 279                  * Convert crtc_[w|h] to U32.32, then divide by U16.16 src_[w|h]
 280                  * to get the U16.16 result.
 281                  */
 282                 h_upscale_factor = div_u64((u64)pstate->crtc_w << 32,
 283                                            pstate->src_w);
 284                 v_upscale_factor = div_u64((u64)pstate->crtc_h << 32,
 285                                            pstate->src_h);
 286
 287                 s->enhancer_enable = ((h_upscale_factor >> 16) >= 2 ||
 288                                       (v_upscale_factor >> 16) >= 2);
 289
 290                 if (pstate->rotation & MALIDP_ROTATED_MASK) {
 291                         s->input_w = pstate->src_h >> 16;
 292                         s->input_h = pstate->src_w >> 16;
 293                 } else {
 294                         s->input_w = pstate->src_w >> 16;
 295                         s->input_h = pstate->src_h >> 16;
 296                 }
 297
 298                 s->output_w = pstate->crtc_w;
 299                 s->output_h = pstate->crtc_h;
 300
 301 #define SE_N_PHASE 4
 302 #define SE_SHIFT_N_PHASE 12
 303                 /* Calculate initial_phase and delta_phase for horizontal. */
 304                 phase = s->input_w;
 305                 s->h_init_phase =
 306                                 ((phase << SE_N_PHASE) / s->output_w + 1) / 2;
 307
 308                 phase = s->input_w;
 309                 phase <<= (SE_SHIFT_N_PHASE + SE_N_PHASE);
 310                 s->h_delta_phase = phase / s->output_w;
 311
 312                 /* Same for vertical. */
 313                 phase = s->input_h;
 314                 s->v_init_phase =
 315                                 ((phase << SE_N_PHASE) / s->output_h + 1) / 2;
 316
 317                 phase = s->input_h;
 318                 phase <<= (SE_SHIFT_N_PHASE + SE_N_PHASE);
 319                 s->v_delta_phase = phase / s->output_h;
 320 #undef SE_N_PHASE
 321 #undef SE_SHIFT_N_PHASE
 322                 s->plane_src_id = mp->layer->id;
 323         }
 324
 325         s->scale_enable = true;
 326         s->hcoeff = malidp_se_select_coeffs(h_upscale_factor);
 327         s->vcoeff = malidp_se_select_coeffs(v_upscale_factor);
 328
 329 mclk_calc:
 330         drm_display_mode_to_videomode(&state->adjusted_mode, &vm);
 331         ret = hwdev->hw->se_calc_mclk(hwdev, s, &vm);
 332         if (ret < 0)
 333                 return -EINVAL;
 334         return 0;
 335 }
 336
 337 static int malidp_crtc_atomic_check(struct drm_crtc *crtc,
 338                                     struct drm_crtc_state *state)
 339 {
 340         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
 341         struct malidp_hw_device *hwdev = malidp->dev;
 342         struct drm_plane *plane;
 343         const struct drm_plane_state *pstate;
 344         u32 rot_mem_free, rot_mem_usable;
 345         int rotated_planes = 0;
 346         int ret;
 347
 348         /*
 349          * check if there is enough rotation memory available for planes
 350          * that need 90° and 270° rotion or planes that are compressed.
 351          * Each plane has set its required memory size in the ->plane_check()
 352          * callback, here we only make sure that the sums are less that the
 353          * total usable memory.
 354          *
 355          * The rotation memory allocation algorithm (for each plane):
 356          *  a. If no more rotated or compressed planes exist, all remaining
 357          *     rotate memory in the bank is available for use by the plane.
 358          *  b. If other rotated or compressed planes exist, and plane's
 359          *     layer ID is DE_VIDEO1, it can use all the memory from first bank
 360          *     if secondary rotation memory bank is available, otherwise it can
 361          *     use up to half the bank's memory.
 362          *  c. If other rotated or compressed planes exist, and plane's layer ID
 363          *     is not DE_VIDEO1, it can use half of the available memory.
 364          *
 365          * Note: this algorithm assumes that the order in which the planes are
 366          * checked always has DE_VIDEO1 plane first in the list if it is
 367          * rotated. Because that is how we create the planes in the first
 368          * place, under current DRM version things work, but if ever the order
 369          * in which drm_atomic_crtc_state_for_each_plane() iterates over planes
 370          * changes, we need to pre-sort the planes before validation.
 371          */
 372
 373         /* first count the number of rotated planes */
 374         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
 375                 struct drm_framebuffer *fb = pstate->fb;
 376
 377                 if ((pstate->rotation & MALIDP_ROTATED_MASK) || fb->modifier)
 378                         rotated_planes++;
 379         }
 380
 381         rot_mem_free = hwdev->rotation_memory[0];
 382         /*
 383          * if we have more than 1 plane using rotation memory, use the second
 384          * block of rotation memory as well
 385          */
 386         if (rotated_planes > 1)
 387                 rot_mem_free += hwdev->rotation_memory[1];
 388
 389         /* now validate the rotation memory requirements */
 390         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
 391                 struct malidp_plane *mp = to_malidp_plane(plane);
 392                 struct malidp_plane_state *ms = to_malidp_plane_state(pstate);
 393                 struct drm_framebuffer *fb = pstate->fb;
 394
 395                 if ((pstate->rotation & MALIDP_ROTATED_MASK) || fb->modifier) {
 396                         /* process current plane */
 397                         rotated_planes--;
 398
 399                         if (!rotated_planes) {
 400                                 /* no more rotated planes, we can use what's left */
 401                                 rot_mem_usable = rot_mem_free;
 402                         } else {
 403                                 if ((mp->layer->id != DE_VIDEO1) ||
 404                                     (hwdev->rotation_memory[1] == 0))
 405                                         rot_mem_usable = rot_mem_free / 2;
 406                                 else
 407                                         rot_mem_usable = hwdev->rotation_memory[0];
 408                         }
 409
 410                         rot_mem_free -= rot_mem_usable;
 411
 412                         if (ms->rotmem_size > rot_mem_usable)
 413                                 return -EINVAL;
 414                 }
 415         }
 416
 417         /* If only the writeback routing has changed, we don't need a modeset */
 418         if (state->connectors_changed) {
 419                 u32 old_mask = crtc->state->connector_mask;
 420                 u32 new_mask = state->connector_mask;
 421
 422                 if ((old_mask ^ new_mask) ==
 423                     (1 << drm_connector_index(&malidp->mw_connector.base)))
 424                         state->connectors_changed = false;
 425         }
 426
 427         ret = malidp_crtc_atomic_check_gamma(crtc, state);
 428         ret = ret ? ret : malidp_crtc_atomic_check_ctm(crtc, state);
 429         ret = ret ? ret : malidp_crtc_atomic_check_scaling(crtc, state);
 430
 431         return ret;
 432 }
 433
 434 static const struct drm_crtc_helper_funcs malidp_crtc_helper_funcs = {
 435         .mode_valid = malidp_crtc_mode_valid,
 436         .atomic_check = malidp_crtc_atomic_check,
 437         .atomic_enable = malidp_crtc_atomic_enable,
 438         .atomic_disable = malidp_crtc_atomic_disable,
 439 };
 440
 441 static struct drm_crtc_state *malidp_crtc_duplicate_state(struct drm_crtc *crtc)
 442 {
 443         struct malidp_crtc_state *state, *old_state;
 444
 445         if (WARN_ON(!crtc->state))
 446                 return NULL;
 447
 448         old_state = to_malidp_crtc_state(crtc->state);
 449         state = kmalloc(sizeof(*state), GFP_KERNEL);
 450         if (!state)
 451                 return NULL;
 452
 453         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 454         memcpy(state->gamma_coeffs, old_state->gamma_coeffs,
 455                sizeof(state->gamma_coeffs));
 456         memcpy(state->coloradj_coeffs, old_state->coloradj_coeffs,
 457                sizeof(state->coloradj_coeffs));
 458         memcpy(&state->scaler_config, &old_state->scaler_config,
 459                sizeof(state->scaler_config));
 460         state->scaled_planes_mask = 0;
 461
 462         return &state->base;
 463 }
 464
 465 static void malidp_crtc_destroy_state(struct drm_crtc *crtc,
 466                                       struct drm_crtc_state *state)
 467 {
 468         struct malidp_crtc_state *mali_state = NULL;
 469
 470         if (state) {
 471                 mali_state = to_malidp_crtc_state(state);
 472                 __drm_atomic_helper_crtc_destroy_state(state);
 473         }
 474
 475         kfree(mali_state);
 476 }
 477
 478 static void malidp_crtc_reset(struct drm_crtc *crtc)
 479 {
 480         struct malidp_crtc_state *state =
 481                 kzalloc(sizeof(*state), GFP_KERNEL);
 482
 483         if (crtc->state)
 484                 malidp_crtc_destroy_state(crtc, crtc->state);
 485
 486         __drm_atomic_helper_crtc_reset(crtc, &state->base);
 487 }
 488
 489 static int malidp_crtc_enable_vblank(struct drm_crtc *crtc)
 490 {
 491         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
 492         struct malidp_hw_device *hwdev = malidp->dev;
 493
 494         malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
 495                              hwdev->hw->map.de_irq_map.vsync_irq);
 496         return 0;
 497 }
 498
 499 static void malidp_crtc_disable_vblank(struct drm_crtc *crtc)
 500 {
 501         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
 502         struct malidp_hw_device *hwdev = malidp->dev;
 503
 504         malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK,
 505                               hwdev->hw->map.de_irq_map.vsync_irq);
 506 }
 507
 508 static const struct drm_crtc_funcs malidp_crtc_funcs = {
 509         .gamma_set = drm_atomic_helper_legacy_gamma_set,
 510         .destroy = drm_crtc_cleanup,
 511         .set_config = drm_atomic_helper_set_config,
 512         .page_flip = drm_atomic_helper_page_flip,
 513         .reset = malidp_crtc_reset,
 514         .atomic_duplicate_state = malidp_crtc_duplicate_state,
 515         .atomic_destroy_state = malidp_crtc_destroy_state,
 516         .enable_vblank = malidp_crtc_enable_vblank,
 517         .disable_vblank = malidp_crtc_disable_vblank,
 518 };
 519
 520 int malidp_crtc_init(struct drm_device *drm)
 521 {
 522         struct malidp_drm *malidp = drm->dev_private;
 523         struct drm_plane *primary = NULL, *plane;
 524         int ret;
 525
 526         ret = malidp_de_planes_init(drm);
 527         if (ret < 0) {
 528                 DRM_ERROR("Failed to initialise planes\n");
 529                 return ret;
 530         }
 531
 532         drm_for_each_plane(plane, drm) {
 533                 if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
 534                         primary = plane;
 535                         break;
 536                 }
 537         }
 538
 539         if (!primary) {
 540                 DRM_ERROR("no primary plane found\n");
 541                 return -EINVAL;
 542         }
 543
 544         ret = drm_crtc_init_with_planes(drm, &malidp->crtc, primary, NULL,
 545                                         &malidp_crtc_funcs, NULL);
 546         if (ret)
 547                 return ret;
 548
 549         drm_crtc_helper_add(&malidp->crtc, &malidp_crtc_helper_funcs);
 550         drm_mode_crtc_set_gamma_size(&malidp->crtc, MALIDP_GAMMA_LUT_SIZE);
 551         /* No inverse-gamma: it is per-plane. */
 552         drm_crtc_enable_color_mgmt(&malidp->crtc, 0, true, MALIDP_GAMMA_LUT_SIZE);
 553
 554         malidp_se_set_enh_coeffs(malidp->dev);
 555
 556         return 0;
 557 }