drivers/gpu/drm/arc/arcpgu_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ARC PGU DRM driver.
   4  *
   5  * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
   6  */
   7
   8 #include <drm/drm_atomic.h>
   9 #include <drm/drm_atomic_helper.h>
  10 #include <drm/drm_device.h>
  11 #include <drm/drm_fb_cma_helper.h>
  12 #include <drm/drm_gem_cma_helper.h>
  13 #include <drm/drm_plane_helper.h>
  14 #include <drm/drm_probe_helper.h>
  15 #include <linux/clk.h>
  16 #include <linux/platform_data/simplefb.h>
  17
  18 #include "arcpgu.h"
  19 #include "arcpgu_regs.h"
  20
  21 #define ENCODE_PGU_XY(x, y)     ((((x) - 1) << 16) | ((y) - 1))
  22
  23 static const u32 arc_pgu_supported_formats[] = {
  24         DRM_FORMAT_RGB565,
  25         DRM_FORMAT_XRGB8888,
  26         DRM_FORMAT_ARGB8888,
  27 };
  28
  29 static void arc_pgu_set_pxl_fmt(struct arcpgu_drm_private *arcpgu)
  30 {
  31         const struct drm_framebuffer *fb = arcpgu->pipe.plane.state->fb;
  32         uint32_t pixel_format = fb->format->format;
  33         u32 format = DRM_FORMAT_INVALID;
  34         int i;
  35         u32 reg_ctrl;
  36
  37         for (i = 0; i < ARRAY_SIZE(arc_pgu_supported_formats); i++) {
  38                 if (arc_pgu_supported_formats[i] == pixel_format)
  39                         format = arc_pgu_supported_formats[i];
  40         }
  41
  42         if (WARN_ON(format == DRM_FORMAT_INVALID))
  43                 return;
  44
  45         reg_ctrl = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
  46         if (format == DRM_FORMAT_RGB565)
  47                 reg_ctrl &= ~ARCPGU_MODE_XRGB8888;
  48         else
  49                 reg_ctrl |= ARCPGU_MODE_XRGB8888;
  50         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, reg_ctrl);
  51 }
  52
  53 static enum drm_mode_status arc_pgu_mode_valid(struct drm_simple_display_pipe *pipe,
  54                                                const struct drm_display_mode *mode)
  55 {
  56         struct arcpgu_drm_private *arcpgu = pipe_to_arcpgu_priv(pipe);
  57         long rate, clk_rate = mode->clock * 1000;
  58         long diff = clk_rate / 200; /* +-0.5% allowed by HDMI spec */
  59
  60         rate = clk_round_rate(arcpgu->clk, clk_rate);
  61         if ((max(rate, clk_rate) - min(rate, clk_rate) < diff) && (rate > 0))
  62                 return MODE_OK;
  63
  64         return MODE_NOCLOCK;
  65 }
  66
  67 static void arc_pgu_mode_set(struct arcpgu_drm_private *arcpgu)
  68 {
  69         struct drm_display_mode *m = &arcpgu->pipe.crtc.state->adjusted_mode;
  70         u32 val;
  71
  72         arc_pgu_write(arcpgu, ARCPGU_REG_FMT,
  73                       ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal));
  74
  75         arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC,
  76                       ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay,
  77                                     m->crtc_hsync_end - m->crtc_hdisplay));
  78
  79         arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC,
  80                       ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay,
  81                                     m->crtc_vsync_end - m->crtc_vdisplay));
  82
  83         arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE,
  84                       ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start,
  85                                     m->crtc_vblank_end - m->crtc_vblank_start));
  86
  87         val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
  88
  89         if (m->flags & DRM_MODE_FLAG_PVSYNC)
  90                 val |= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST;
  91         else
  92                 val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST);
  93
  94         if (m->flags & DRM_MODE_FLAG_PHSYNC)
  95                 val |= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST;
  96         else
  97                 val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST);
  98
  99         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val);
 100         arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0);
 101         arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1);
 102
 103         arc_pgu_set_pxl_fmt(arcpgu);
 104
 105         clk_set_rate(arcpgu->clk, m->crtc_clock * 1000);
 106 }
 107
 108 static void arc_pgu_enable(struct drm_simple_display_pipe *pipe,
 109                            struct drm_crtc_state *crtc_state,
 110                            struct drm_plane_state *plane_state)
 111 {
 112         struct arcpgu_drm_private *arcpgu = pipe_to_arcpgu_priv(pipe);
 113
 114         arc_pgu_mode_set(arcpgu);
 115
 116         clk_prepare_enable(arcpgu->clk);
 117         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
 118                       arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
 119                       ARCPGU_CTRL_ENABLE_MASK);
 120 }
 121
 122 static void arc_pgu_disable(struct drm_simple_display_pipe *pipe)
 123 {
 124         struct arcpgu_drm_private *arcpgu = pipe_to_arcpgu_priv(pipe);
 125
 126         clk_disable_unprepare(arcpgu->clk);
 127         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
 128                               arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
 129                               ~ARCPGU_CTRL_ENABLE_MASK);
 130 }
 131
 132 static void arc_pgu_update(struct drm_simple_display_pipe *pipe,
 133                            struct drm_plane_state *state)
 134 {
 135         struct arcpgu_drm_private *arcpgu;
 136         struct drm_gem_cma_object *gem;
 137
 138         if (!pipe->plane.state->fb)
 139                 return;
 140
 141         arcpgu = pipe_to_arcpgu_priv(pipe);
 142         gem = drm_fb_cma_get_gem_obj(pipe->plane.state->fb, 0);
 143         arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr);
 144 }
 145
 146 static const struct drm_simple_display_pipe_funcs arc_pgu_pipe_funcs = {
 147         .update = arc_pgu_update,
 148         .mode_valid = arc_pgu_mode_valid,
 149         .enable = arc_pgu_enable,
 150         .disable = arc_pgu_disable,
 151 };
 152
 153 int arc_pgu_setup_pipe(struct drm_device *drm)
 154 {
 155         struct arcpgu_drm_private *arcpgu = dev_to_arcpgu(drm);
 156
 157         return drm_simple_display_pipe_init(drm, &arcpgu->pipe, &arc_pgu_pipe_funcs,
 158                                             arc_pgu_supported_formats,
 159                                             ARRAY_SIZE(arc_pgu_supported_formats),
 160                                             NULL, NULL);
 161 }