drivers/gpu/drm/arc/arcpgu_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ARC PGU DRM driver.
   4  *
   5  * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
   6  */
   7
   8 #include <drm/drm_atomic.h>
   9 #include <drm/drm_atomic_helper.h>
  10 #include <drm/drm_device.h>
  11 #include <drm/drm_fb_cma_helper.h>
  12 #include <drm/drm_gem_cma_helper.h>
  13 #include <drm/drm_plane_helper.h>
  14 #include <drm/drm_probe_helper.h>
  15 #include <linux/clk.h>
  16 #include <linux/platform_data/simplefb.h>
  17
  18 #include "arcpgu.h"
  19 #include "arcpgu_regs.h"
  20
  21 #define ENCODE_PGU_XY(x, y)     ((((x) - 1) << 16) | ((y) - 1))
  22
  23 static const u32 arc_pgu_supported_formats[] = {
  24         DRM_FORMAT_RGB565,
  25         DRM_FORMAT_XRGB8888,
  26         DRM_FORMAT_ARGB8888,
  27 };
  28
  29 static void arc_pgu_set_pxl_fmt(struct drm_crtc *crtc)
  30 {
  31         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
  32         const struct drm_framebuffer *fb = crtc->primary->state->fb;
  33         uint32_t pixel_format = fb->format->format;
  34         u32 format = DRM_FORMAT_INVALID;
  35         int i;
  36         u32 reg_ctrl;
  37
  38         for (i = 0; i < ARRAY_SIZE(arc_pgu_supported_formats); i++) {
  39                 if (arc_pgu_supported_formats[i] == pixel_format)
  40                         format = arc_pgu_supported_formats[i];
  41         }
  42
  43         if (WARN_ON(format == DRM_FORMAT_INVALID))
  44                 return;
  45
  46         reg_ctrl = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
  47         if (format == DRM_FORMAT_RGB565)
  48                 reg_ctrl &= ~ARCPGU_MODE_XRGB8888;
  49         else
  50                 reg_ctrl |= ARCPGU_MODE_XRGB8888;
  51         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, reg_ctrl);
  52 }
  53
  54 static const struct drm_crtc_funcs arc_pgu_crtc_funcs = {
  55         .destroy = drm_crtc_cleanup,
  56         .set_config = drm_atomic_helper_set_config,
  57         .page_flip = drm_atomic_helper_page_flip,
  58         .reset = drm_atomic_helper_crtc_reset,
  59         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
  60         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
  61 };
  62
  63 static enum drm_mode_status arc_pgu_crtc_mode_valid(struct drm_crtc *crtc,
  64                                                     const struct drm_display_mode *mode)
  65 {
  66         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
  67         long rate, clk_rate = mode->clock * 1000;
  68         long diff = clk_rate / 200; /* +-0.5% allowed by HDMI spec */
  69
  70         rate = clk_round_rate(arcpgu->clk, clk_rate);
  71         if ((max(rate, clk_rate) - min(rate, clk_rate) < diff) && (rate > 0))
  72                 return MODE_OK;
  73
  74         return MODE_NOCLOCK;
  75 }
  76
  77 static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc)
  78 {
  79         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
  80         struct drm_display_mode *m = &crtc->state->adjusted_mode;
  81         u32 val;
  82
  83         arc_pgu_write(arcpgu, ARCPGU_REG_FMT,
  84                       ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal));
  85
  86         arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC,
  87                       ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay,
  88                                     m->crtc_hsync_end - m->crtc_hdisplay));
  89
  90         arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC,
  91                       ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay,
  92                                     m->crtc_vsync_end - m->crtc_vdisplay));
  93
  94         arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE,
  95                       ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start,
  96                                     m->crtc_vblank_end - m->crtc_vblank_start));
  97
  98         val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
  99
 100         if (m->flags & DRM_MODE_FLAG_PVSYNC)
 101                 val |= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST;
 102         else
 103                 val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST);
 104
 105         if (m->flags & DRM_MODE_FLAG_PHSYNC)
 106                 val |= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST;
 107         else
 108                 val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST);
 109
 110         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val);
 111         arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0);
 112         arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1);
 113
 114         arc_pgu_set_pxl_fmt(crtc);
 115
 116         clk_set_rate(arcpgu->clk, m->crtc_clock * 1000);
 117 }
 118
 119 static void arc_pgu_crtc_atomic_enable(struct drm_crtc *crtc,
 120                                        struct drm_atomic_state *state)
 121 {
 122         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
 123
 124         clk_prepare_enable(arcpgu->clk);
 125         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
 126                       arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
 127                       ARCPGU_CTRL_ENABLE_MASK);
 128 }
 129
 130 static void arc_pgu_crtc_atomic_disable(struct drm_crtc *crtc,
 131                                         struct drm_atomic_state *state)
 132 {
 133         struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
 134
 135         clk_disable_unprepare(arcpgu->clk);
 136         arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
 137                               arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
 138                               ~ARCPGU_CTRL_ENABLE_MASK);
 139 }
 140
 141 static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = {
 142         .mode_valid     = arc_pgu_crtc_mode_valid,
 143         .mode_set_nofb  = arc_pgu_crtc_mode_set_nofb,
 144         .atomic_enable  = arc_pgu_crtc_atomic_enable,
 145         .atomic_disable = arc_pgu_crtc_atomic_disable,
 146 };
 147
 148 static void arc_pgu_plane_atomic_update(struct drm_plane *plane,
 149                                         struct drm_atomic_state *state)
 150 {
 151         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 152                                                                                  plane);
 153         struct arcpgu_drm_private *arcpgu;
 154         struct drm_gem_cma_object *gem;
 155
 156         if (!new_plane_state->crtc || !new_plane_state->fb)
 157                 return;
 158
 159         arcpgu = crtc_to_arcpgu_priv(new_plane_state->crtc);
 160         gem = drm_fb_cma_get_gem_obj(new_plane_state->fb, 0);
 161         arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr);
 162 }
 163
 164 static const struct drm_plane_helper_funcs arc_pgu_plane_helper_funcs = {
 165         .atomic_update = arc_pgu_plane_atomic_update,
 166 };
 167
 168 static const struct drm_plane_funcs arc_pgu_plane_funcs = {
 169         .update_plane           = drm_atomic_helper_update_plane,
 170         .disable_plane          = drm_atomic_helper_disable_plane,
 171         .destroy                = drm_plane_cleanup,
 172         .reset                  = drm_atomic_helper_plane_reset,
 173         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 174         .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
 175 };
 176
 177 static struct drm_plane *arc_pgu_plane_init(struct drm_device *drm)
 178 {
 179         struct arcpgu_drm_private *arcpgu = dev_to_arcpgu(drm);
 180         struct drm_plane *plane = NULL;
 181         int ret;
 182
 183         plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
 184         if (!plane)
 185                 return ERR_PTR(-ENOMEM);
 186
 187         ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs,
 188                                        arc_pgu_supported_formats,
 189                                        ARRAY_SIZE(arc_pgu_supported_formats),
 190                                        NULL,
 191                                        DRM_PLANE_TYPE_PRIMARY, NULL);
 192         if (ret)
 193                 return ERR_PTR(ret);
 194
 195         drm_plane_helper_add(plane, &arc_pgu_plane_helper_funcs);
 196         arcpgu->plane = plane;
 197
 198         return plane;
 199 }
 200
 201 int arc_pgu_setup_crtc(struct drm_device *drm)
 202 {
 203         struct arcpgu_drm_private *arcpgu = dev_to_arcpgu(drm);
 204         struct drm_plane *primary;
 205         int ret;
 206
 207         primary = arc_pgu_plane_init(drm);
 208         if (IS_ERR(primary))
 209                 return PTR_ERR(primary);
 210
 211         ret = drm_crtc_init_with_planes(drm, &arcpgu->crtc, primary, NULL,
 212                                         &arc_pgu_crtc_funcs, NULL);
 213         if (ret) {
 214                 drm_plane_cleanup(primary);
 215                 return ret;
 216         }
 217
 218         drm_crtc_helper_add(&arcpgu->crtc, &arc_pgu_crtc_helper_funcs);
 219         return 0;
 220 }