2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/types.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/gfp.h>
29 #include "tonga_smumgr.h"
31 #include "smu_ucode_xfer_vi.h"
32 #include "tonga_ppsmc.h"
33 #include "smu/smu_7_1_2_d.h"
34 #include "smu/smu_7_1_2_sh_mask.h"
35 #include "cgs_common.h"
37 #define TONGA_SMC_SIZE 0x20000
38 #define BUFFER_SIZE 80000
39 #define MAX_STRING_SIZE 15
40 #define BUFFER_SIZETWO 131072 /*128 *1024*/
43 * Set the address for reading/writing the SMC SRAM space.
44 * @param smumgr the address of the powerplay hardware manager.
45 * @param smcAddress the address in the SMC RAM to access.
47 static int tonga_set_smc_sram_address(struct pp_smumgr *smumgr,
48 uint32_t smcAddress, uint32_t limit)
50 if (smumgr == NULL || smumgr->device == NULL)
52 PP_ASSERT_WITH_CODE((0 == (3 & smcAddress)),
53 "SMC address must be 4 byte aligned.",
56 PP_ASSERT_WITH_CODE((limit > (smcAddress + 3)),
57 "SMC address is beyond the SMC RAM area.",
60 cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, smcAddress);
61 SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
67 * Copy bytes from an array into the SMC RAM space.
69 * @param smumgr the address of the powerplay SMU manager.
70 * @param smcStartAddress the start address in the SMC RAM to copy bytes to.
71 * @param src the byte array to copy the bytes from.
72 * @param byteCount the number of bytes to copy.
74 int tonga_copy_bytes_to_smc(struct pp_smumgr *smumgr,
75 uint32_t smcStartAddress, const uint8_t *src,
76 uint32_t byteCount, uint32_t limit)
79 uint32_t data, orig_data;
83 if (smumgr == NULL || smumgr->device == NULL)
85 PP_ASSERT_WITH_CODE((0 == (3 & smcStartAddress)),
86 "SMC address must be 4 byte aligned.",
89 PP_ASSERT_WITH_CODE((limit > (smcStartAddress + byteCount)),
90 "SMC address is beyond the SMC RAM area.",
93 addr = smcStartAddress;
95 while (byteCount >= 4) {
97 * Bytes are written into the
98 * SMC address space with the MSB first
100 data = (src[0] << 24) + (src[1] << 16) + (src[2] << 8) + src[3];
102 result = tonga_set_smc_sram_address(smumgr, addr, limit);
107 cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data);
114 if (0 != byteCount) {
115 /* Now write odd bytes left, do a read modify write cycle */
118 result = tonga_set_smc_sram_address(smumgr, addr, limit);
122 orig_data = cgs_read_register(smumgr->device,
124 extra_shift = 8 * (4 - byteCount);
126 while (byteCount > 0) {
127 data = (data << 8) + *src++;
131 data <<= extra_shift;
132 data |= (orig_data & ~((~0UL) << extra_shift));
134 result = tonga_set_smc_sram_address(smumgr, addr, limit);
138 cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data);
146 int tonga_program_jump_on_start(struct pp_smumgr *smumgr)
148 static unsigned char pData[] = { 0xE0, 0x00, 0x80, 0x40 };
150 tonga_copy_bytes_to_smc(smumgr, 0x0, pData, 4, sizeof(pData)+1);
156 * Return if the SMC is currently running.
158 * @param smumgr the address of the powerplay hardware manager.
160 static int tonga_is_smc_ram_running(struct pp_smumgr *smumgr)
162 return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
163 SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
164 && (0x20100 <= cgs_read_ind_register(smumgr->device,
165 CGS_IND_REG__SMC, ixSMC_PC_C)));
168 static int tonga_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
170 if (smumgr == NULL || smumgr->device == NULL)
173 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
175 cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
176 cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
178 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
184 * Send a message to the SMC, and wait for its response.
186 * @param smumgr the address of the powerplay hardware manager.
187 * @param msg the message to send.
188 * @return The response that came from the SMC.
190 static int tonga_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
192 if (smumgr == NULL || smumgr->device == NULL)
195 if (!tonga_is_smc_ram_running(smumgr))
198 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
200 1 == SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP),
201 "Failed to send Previous Message.",
204 cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
206 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
208 1 == SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP),
209 "Failed to send Message.",
216 * Send a message to the SMC, and do not wait for its response.
218 * @param smumgr the address of the powerplay hardware manager.
219 * @param msg the message to send.
220 * @return The response that came from the SMC.
222 static int tonga_send_msg_to_smc_without_waiting
223 (struct pp_smumgr *smumgr, uint16_t msg)
225 if (smumgr == NULL || smumgr->device == NULL)
228 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
230 1 == SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP),
231 "Failed to send Previous Message.",
233 cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
239 * Send a message to the SMC with parameter
241 * @param smumgr: the address of the powerplay hardware manager.
242 * @param msg: the message to send.
243 * @param parameter: the parameter to send
244 * @return The response that came from the SMC.
246 static int tonga_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
247 uint16_t msg, uint32_t parameter)
249 if (smumgr == NULL || smumgr->device == NULL)
252 if (!tonga_is_smc_ram_running(smumgr))
253 return PPSMC_Result_Failed;
255 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
256 cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
258 return tonga_send_msg_to_smc(smumgr, msg);
262 * Send a message to the SMC with parameter, do not wait for response
264 * @param smumgr: the address of the powerplay hardware manager.
265 * @param msg: the message to send.
266 * @param parameter: the parameter to send
267 * @return The response that came from the SMC.
269 static int tonga_send_msg_to_smc_with_parameter_without_waiting(
270 struct pp_smumgr *smumgr,
271 uint16_t msg, uint32_t parameter)
273 if (smumgr == NULL || smumgr->device == NULL)
276 SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
278 cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
280 return tonga_send_msg_to_smc_without_waiting(smumgr, msg);
284 * Read a 32bit value from the SMC SRAM space.
285 * ALL PARAMETERS ARE IN HOST BYTE ORDER.
286 * @param smumgr the address of the powerplay hardware manager.
287 * @param smcAddress the address in the SMC RAM to access.
288 * @param value and output parameter for the data read from the SMC SRAM.
290 int tonga_read_smc_sram_dword(struct pp_smumgr *smumgr,
291 uint32_t smcAddress, uint32_t *value,
296 result = tonga_set_smc_sram_address(smumgr, smcAddress, limit);
301 *value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_0);
307 * Write a 32bit value to the SMC SRAM space.
308 * ALL PARAMETERS ARE IN HOST BYTE ORDER.
309 * @param smumgr the address of the powerplay hardware manager.
310 * @param smcAddress the address in the SMC RAM to access.
311 * @param value to write to the SMC SRAM.
313 int tonga_write_smc_sram_dword(struct pp_smumgr *smumgr,
314 uint32_t smcAddress, uint32_t value,
319 result = tonga_set_smc_sram_address(smumgr, smcAddress, limit);
324 cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, value);
329 static int tonga_smu_fini(struct pp_smumgr *smumgr)
331 if (smumgr->backend != NULL) {
332 kfree(smumgr->backend);
333 smumgr->backend = NULL;
338 static enum cgs_ucode_id tonga_convert_fw_type_to_cgs(uint32_t fw_type)
340 enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM;
344 result = CGS_UCODE_ID_SMU;
347 result = CGS_UCODE_ID_SDMA0;
350 result = CGS_UCODE_ID_SDMA1;
353 result = CGS_UCODE_ID_CP_CE;
355 case UCODE_ID_CP_PFP:
356 result = CGS_UCODE_ID_CP_PFP;
359 result = CGS_UCODE_ID_CP_ME;
361 case UCODE_ID_CP_MEC:
362 result = CGS_UCODE_ID_CP_MEC;
364 case UCODE_ID_CP_MEC_JT1:
365 result = CGS_UCODE_ID_CP_MEC_JT1;
367 case UCODE_ID_CP_MEC_JT2:
368 result = CGS_UCODE_ID_CP_MEC_JT2;
371 result = CGS_UCODE_ID_RLC_G;
381 * Convert the PPIRI firmware type to SMU type mask.
382 * For MEC, we need to check all MEC related type
384 static uint16_t tonga_get_mask_for_firmware_type(uint16_t firmwareType)
388 switch (firmwareType) {
390 result = UCODE_ID_SDMA0_MASK;
393 result = UCODE_ID_SDMA1_MASK;
396 result = UCODE_ID_CP_CE_MASK;
398 case UCODE_ID_CP_PFP:
399 result = UCODE_ID_CP_PFP_MASK;
402 result = UCODE_ID_CP_ME_MASK;
404 case UCODE_ID_CP_MEC:
405 case UCODE_ID_CP_MEC_JT1:
406 case UCODE_ID_CP_MEC_JT2:
407 result = UCODE_ID_CP_MEC_MASK;
410 result = UCODE_ID_RLC_G_MASK;
420 * Check if the FW has been loaded,
421 * SMU will not return if loading has not finished.
423 static int tonga_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fwType)
425 uint16_t fwMask = tonga_get_mask_for_firmware_type(fwType);
427 if (0 != SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, SMC_IND,
428 SOFT_REGISTERS_TABLE_28, fwMask, fwMask)) {
429 printk(KERN_ERR "[ powerplay ] check firmware loading failed\n");
436 /* Populate one firmware image to the data structure */
437 static int tonga_populate_single_firmware_entry(struct pp_smumgr *smumgr,
438 uint16_t firmware_type,
439 struct SMU_Entry *pentry)
442 struct cgs_firmware_info info = {0};
444 result = cgs_get_firmware_info(
446 tonga_convert_fw_type_to_cgs(firmware_type),
451 pentry->id = (uint16_t)firmware_type;
452 pentry->image_addr_high = smu_upper_32_bits(info.mc_addr);
453 pentry->image_addr_low = smu_lower_32_bits(info.mc_addr);
454 pentry->meta_data_addr_high = 0;
455 pentry->meta_data_addr_low = 0;
456 pentry->data_size_byte = info.image_size;
457 pentry->num_register_entries = 0;
459 if (firmware_type == UCODE_ID_RLC_G)
470 static int tonga_request_smu_reload_fw(struct pp_smumgr *smumgr)
472 struct tonga_smumgr *tonga_smu =
473 (struct tonga_smumgr *)(smumgr->backend);
476 struct SMU_DRAMData_TOC *toc;
478 * First time this gets called during SmuMgr init,
479 * we haven't processed SMU header file yet,
480 * so Soft Register Start offset is unknown.
481 * However, for this case, UcodeLoadStatus is already 0,
482 * so we can skip this if the Soft Registers Start offset is 0.
484 cgs_write_ind_register(smumgr->device,
485 CGS_IND_REG__SMC, ixSOFT_REGISTERS_TABLE_28, 0);
487 tonga_send_msg_to_smc_with_parameter(smumgr,
488 PPSMC_MSG_SMU_DRAM_ADDR_HI,
489 tonga_smu->smu_buffer.mc_addr_high);
490 tonga_send_msg_to_smc_with_parameter(smumgr,
491 PPSMC_MSG_SMU_DRAM_ADDR_LO,
492 tonga_smu->smu_buffer.mc_addr_low);
494 toc = (struct SMU_DRAMData_TOC *)tonga_smu->pHeader;
495 toc->num_entries = 0;
496 toc->structure_version = 1;
499 0 == tonga_populate_single_firmware_entry(smumgr,
501 &toc->entry[toc->num_entries++]),
502 "Failed to Get Firmware Entry.\n",
505 0 == tonga_populate_single_firmware_entry(smumgr,
507 &toc->entry[toc->num_entries++]),
508 "Failed to Get Firmware Entry.\n",
511 0 == tonga_populate_single_firmware_entry
512 (smumgr, UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]),
513 "Failed to Get Firmware Entry.\n", return -1);
515 0 == tonga_populate_single_firmware_entry
516 (smumgr, UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]),
517 "Failed to Get Firmware Entry.\n", return -1);
519 0 == tonga_populate_single_firmware_entry
520 (smumgr, UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]),
521 "Failed to Get Firmware Entry.\n", return -1);
523 0 == tonga_populate_single_firmware_entry
524 (smumgr, UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]),
525 "Failed to Get Firmware Entry.\n", return -1);
527 0 == tonga_populate_single_firmware_entry
528 (smumgr, UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]),
529 "Failed to Get Firmware Entry.\n", return -1);
531 0 == tonga_populate_single_firmware_entry
532 (smumgr, UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]),
533 "Failed to Get Firmware Entry.\n", return -1);
535 0 == tonga_populate_single_firmware_entry
536 (smumgr, UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]),
537 "Failed to Get Firmware Entry.\n", return -1);
539 tonga_send_msg_to_smc_with_parameter(smumgr,
540 PPSMC_MSG_DRV_DRAM_ADDR_HI,
541 tonga_smu->header_buffer.mc_addr_high);
542 tonga_send_msg_to_smc_with_parameter(smumgr,
543 PPSMC_MSG_DRV_DRAM_ADDR_LO,
544 tonga_smu->header_buffer.mc_addr_low);
546 fw_to_load = UCODE_ID_RLC_G_MASK
547 + UCODE_ID_SDMA0_MASK
548 + UCODE_ID_SDMA1_MASK
549 + UCODE_ID_CP_CE_MASK
550 + UCODE_ID_CP_ME_MASK
551 + UCODE_ID_CP_PFP_MASK
552 + UCODE_ID_CP_MEC_MASK;
555 0 == tonga_send_msg_to_smc_with_parameter_without_waiting(
556 smumgr, PPSMC_MSG_LoadUcodes, fw_to_load),
557 "Fail to Request SMU Load uCode", return 0);
562 static int tonga_request_smu_load_specific_fw(struct pp_smumgr *smumgr,
563 uint32_t firmwareType)
569 * Upload the SMC firmware to the SMC microcontroller.
571 * @param smumgr the address of the powerplay hardware manager.
572 * @param pFirmware the data structure containing the various sections of the firmware.
574 static int tonga_smu_upload_firmware_image(struct pp_smumgr *smumgr)
579 struct cgs_firmware_info info = {0};
581 if (smumgr == NULL || smumgr->device == NULL)
584 cgs_get_firmware_info(smumgr->device,
585 tonga_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
587 if (info.image_size & 3) {
588 printk(KERN_ERR "[ powerplay ] SMC ucode is not 4 bytes aligned\n");
592 if (info.image_size > TONGA_SMC_SIZE) {
593 printk(KERN_ERR "[ powerplay ] SMC address is beyond the SMC RAM area\n");
597 cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, 0x20000);
598 SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
600 byte_count = info.image_size;
601 src = (const uint8_t *)info.kptr;
603 data = (uint32_t *)src;
604 for (; byte_count >= 4; data++, byte_count -= 4)
605 cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data[0]);
607 SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
612 static int tonga_start_in_protection_mode(struct pp_smumgr *smumgr)
617 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
618 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
620 result = tonga_smu_upload_firmware_image(smumgr);
625 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
629 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
630 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
632 /* De-assert reset */
633 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
634 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
636 /* Set SMU Auto Start */
637 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
638 SMU_INPUT_DATA, AUTO_START, 1);
640 /* Clear firmware interrupt enable flag */
641 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
642 ixFIRMWARE_FLAGS, 0);
644 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
645 RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
648 * Call Test SMU message with 0x20000 offset to trigger SMU start
650 tonga_send_msg_to_smc_offset(smumgr);
652 /* Wait for done bit to be set */
653 SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
654 SMU_STATUS, SMU_DONE, 0);
656 /* Check pass/failed indicator */
657 if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device,
658 CGS_IND_REG__SMC, SMU_STATUS, SMU_PASS)) {
659 printk(KERN_ERR "[ powerplay ] SMU Firmware start failed\n");
663 /* Wait for firmware to initialize */
664 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
665 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
671 static int tonga_start_in_non_protection_mode(struct pp_smumgr *smumgr)
675 /* wait for smc boot up */
676 SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
677 RCU_UC_EVENTS, boot_seq_done, 0);
679 /*Clear firmware interrupt enable flag*/
680 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
681 ixFIRMWARE_FLAGS, 0);
684 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
685 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
687 result = tonga_smu_upload_firmware_image(smumgr);
692 /* Set smc instruct start point at 0x0 */
693 tonga_program_jump_on_start(smumgr);
696 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
697 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
700 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
701 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
703 /* Wait for firmware to initialize */
704 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
705 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
710 static int tonga_start_smu(struct pp_smumgr *smumgr)
714 /* Only start SMC if SMC RAM is not running */
715 if (!tonga_is_smc_ram_running(smumgr)) {
716 /*Check if SMU is running in protected mode*/
717 if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
718 SMU_FIRMWARE, SMU_MODE)) {
719 result = tonga_start_in_non_protection_mode(smumgr);
723 result = tonga_start_in_protection_mode(smumgr);
729 result = tonga_request_smu_reload_fw(smumgr);
735 * Write a 32bit value to the SMC SRAM space.
736 * ALL PARAMETERS ARE IN HOST BYTE ORDER.
737 * @param smumgr the address of the powerplay hardware manager.
738 * @param smcAddress the address in the SMC RAM to access.
739 * @param value to write to the SMC SRAM.
741 static int tonga_smu_init(struct pp_smumgr *smumgr)
743 struct tonga_smumgr *tonga_smu;
744 uint8_t *internal_buf;
745 uint64_t mc_addr = 0;
746 /* Allocate memory for backend private data */
747 tonga_smu = (struct tonga_smumgr *)(smumgr->backend);
748 tonga_smu->header_buffer.data_size =
749 ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
750 tonga_smu->smu_buffer.data_size = 200*4096;
752 smu_allocate_memory(smumgr->device,
753 tonga_smu->header_buffer.data_size,
754 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
757 &tonga_smu->header_buffer.kaddr,
758 &tonga_smu->header_buffer.handle);
760 tonga_smu->pHeader = tonga_smu->header_buffer.kaddr;
761 tonga_smu->header_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
762 tonga_smu->header_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
764 PP_ASSERT_WITH_CODE((NULL != tonga_smu->pHeader),
766 kfree(smumgr->backend);
767 cgs_free_gpu_mem(smumgr->device,
768 (cgs_handle_t)tonga_smu->header_buffer.handle);
771 smu_allocate_memory(smumgr->device,
772 tonga_smu->smu_buffer.data_size,
773 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
776 &tonga_smu->smu_buffer.kaddr,
777 &tonga_smu->smu_buffer.handle);
779 internal_buf = tonga_smu->smu_buffer.kaddr;
780 tonga_smu->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
781 tonga_smu->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
783 PP_ASSERT_WITH_CODE((NULL != internal_buf),
785 kfree(smumgr->backend);
786 cgs_free_gpu_mem(smumgr->device,
787 (cgs_handle_t)tonga_smu->smu_buffer.handle);
793 static const struct pp_smumgr_func tonga_smu_funcs = {
794 .smu_init = &tonga_smu_init,
795 .smu_fini = &tonga_smu_fini,
796 .start_smu = &tonga_start_smu,
797 .check_fw_load_finish = &tonga_check_fw_load_finish,
798 .request_smu_load_fw = &tonga_request_smu_reload_fw,
799 .request_smu_load_specific_fw = &tonga_request_smu_load_specific_fw,
800 .send_msg_to_smc = &tonga_send_msg_to_smc,
801 .send_msg_to_smc_with_parameter = &tonga_send_msg_to_smc_with_parameter,
802 .download_pptable_settings = NULL,
803 .upload_pptable_settings = NULL,
806 int tonga_smum_init(struct pp_smumgr *smumgr)
808 struct tonga_smumgr *tonga_smu = NULL;
810 tonga_smu = kzalloc(sizeof(struct tonga_smumgr), GFP_KERNEL);
812 if (tonga_smu == NULL)
815 smumgr->backend = tonga_smu;
816 smumgr->smumgr_funcs = &tonga_smu_funcs;