drivers/gpu/drm/amd/powerplay/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26 #include <linux/reboot.h>
  27
  28 #define SMU_11_0_PARTIAL_PPTABLE
  29 #define SWSMU_CODE_LAYER_L3
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_smu.h"
  33 #include "atomfirmware.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_atombios.h"
  36 #include "smu_v11_0.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "amdgpu_ras.h"
  40 #include "smu_cmn.h"
  41
  42 #include "asic_reg/thm/thm_11_0_2_offset.h"
  43 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  44 #include "asic_reg/mp/mp_11_0_offset.h"
  45 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  46 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  47 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  48
  49 /*
  50  * DO NOT use these for err/warn/info/debug messages.
  51  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  52  * They are more MGPU friendly.
  53  */
  54 #undef pr_err
  55 #undef pr_warn
  56 #undef pr_info
  57 #undef pr_debug
  58
  59 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
  60 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  61 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
  62 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
  63 MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
  64 MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
  65
  66 #define SMU11_VOLTAGE_SCALE 4
  67
  68 #define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500  //500ms
  69
  70 #define LINK_WIDTH_MAX                          6
  71 #define LINK_SPEED_MAX                          3
  72
  73 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  74 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
  75 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
  76 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  77 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
  78 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
  79
  80 static int link_width[] = {0, 1, 2, 4, 8, 12, 16};
  81 static int link_speed[] = {25, 50, 80, 160};
  82
  83 int smu_v11_0_init_microcode(struct smu_context *smu)
  84 {
  85         struct amdgpu_device *adev = smu->adev;
  86         const char *chip_name;
  87         char fw_name[30];
  88         int err = 0;
  89         const struct smc_firmware_header_v1_0 *hdr;
  90         const struct common_firmware_header *header;
  91         struct amdgpu_firmware_info *ucode = NULL;
  92
  93         switch (adev->asic_type) {
  94         case CHIP_ARCTURUS:
  95                 chip_name = "arcturus";
  96                 break;
  97         case CHIP_NAVI10:
  98                 chip_name = "navi10";
  99                 break;
 100         case CHIP_NAVI14:
 101                 chip_name = "navi14";
 102                 break;
 103         case CHIP_NAVI12:
 104                 chip_name = "navi12";
 105                 break;
 106         case CHIP_SIENNA_CICHLID:
 107                 chip_name = "sienna_cichlid";
 108                 break;
 109         case CHIP_NAVY_FLOUNDER:
 110                 chip_name = "navy_flounder";
 111                 break;
 112         default:
 113                 dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
 114                 return -EINVAL;
 115         }
 116
 117         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 118
 119         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 120         if (err)
 121                 goto out;
 122         err = amdgpu_ucode_validate(adev->pm.fw);
 123         if (err)
 124                 goto out;
 125
 126         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 127         amdgpu_ucode_print_smc_hdr(&hdr->header);
 128         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 129
 130         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 131                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 132                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 133                 ucode->fw = adev->pm.fw;
 134                 header = (const struct common_firmware_header *)ucode->fw->data;
 135                 adev->firmware.fw_size +=
 136                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 137         }
 138
 139 out:
 140         if (err) {
 141                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 142                           fw_name);
 143                 release_firmware(adev->pm.fw);
 144                 adev->pm.fw = NULL;
 145         }
 146         return err;
 147 }
 148
 149 void smu_v11_0_fini_microcode(struct smu_context *smu)
 150 {
 151         struct amdgpu_device *adev = smu->adev;
 152
 153         release_firmware(adev->pm.fw);
 154         adev->pm.fw = NULL;
 155         adev->pm.fw_version = 0;
 156 }
 157
 158 int smu_v11_0_load_microcode(struct smu_context *smu)
 159 {
 160         struct amdgpu_device *adev = smu->adev;
 161         const uint32_t *src;
 162         const struct smc_firmware_header_v1_0 *hdr;
 163         uint32_t addr_start = MP1_SRAM;
 164         uint32_t i;
 165         uint32_t smc_fw_size;
 166         uint32_t mp1_fw_flags;
 167
 168         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 169         src = (const uint32_t *)(adev->pm.fw->data +
 170                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 171         smc_fw_size = hdr->header.ucode_size_bytes;
 172
 173         for (i = 1; i < smc_fw_size/4 - 1; i++) {
 174                 WREG32_PCIE(addr_start, src[i]);
 175                 addr_start += 4;
 176         }
 177
 178         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 179                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 180         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 181                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 182
 183         for (i = 0; i < adev->usec_timeout; i++) {
 184                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 185                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 186                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 187                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 188                         break;
 189                 udelay(1);
 190         }
 191
 192         if (i == adev->usec_timeout)
 193                 return -ETIME;
 194
 195         return 0;
 196 }
 197
 198 int smu_v11_0_check_fw_status(struct smu_context *smu)
 199 {
 200         struct amdgpu_device *adev = smu->adev;
 201         uint32_t mp1_fw_flags;
 202
 203         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 204                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 205
 206         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 207             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 208                 return 0;
 209
 210         return -EIO;
 211 }
 212
 213 int smu_v11_0_check_fw_version(struct smu_context *smu)
 214 {
 215         uint32_t if_version = 0xff, smu_version = 0xff;
 216         uint16_t smu_major;
 217         uint8_t smu_minor, smu_debug;
 218         int ret = 0;
 219
 220         ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
 221         if (ret)
 222                 return ret;
 223
 224         smu_major = (smu_version >> 16) & 0xffff;
 225         smu_minor = (smu_version >> 8) & 0xff;
 226         smu_debug = (smu_version >> 0) & 0xff;
 227
 228         switch (smu->adev->asic_type) {
 229         case CHIP_ARCTURUS:
 230                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
 231                 break;
 232         case CHIP_NAVI10:
 233                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
 234                 break;
 235         case CHIP_NAVI12:
 236                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
 237                 break;
 238         case CHIP_NAVI14:
 239                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
 240                 break;
 241         case CHIP_SIENNA_CICHLID:
 242                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
 243                 break;
 244         case CHIP_NAVY_FLOUNDER:
 245                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
 246                 break;
 247         default:
 248                 dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
 249                 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
 250                 break;
 251         }
 252
 253         /*
 254          * 1. if_version mismatch is not critical as our fw is designed
 255          * to be backward compatible.
 256          * 2. New fw usually brings some optimizations. But that's visible
 257          * only on the paired driver.
 258          * Considering above, we just leave user a warning message instead
 259          * of halt driver loading.
 260          */
 261         if (if_version != smu->smc_driver_if_version) {
 262                 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 263                         "smu fw version = 0x%08x (%d.%d.%d)\n",
 264                         smu->smc_driver_if_version, if_version,
 265                         smu_version, smu_major, smu_minor, smu_debug);
 266                 dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
 267         }
 268
 269         return ret;
 270 }
 271
 272 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 273 {
 274         struct amdgpu_device *adev = smu->adev;
 275         uint32_t ppt_offset_bytes;
 276         const struct smc_firmware_header_v2_0 *v2;
 277
 278         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 279
 280         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 281         *size = le32_to_cpu(v2->ppt_size_bytes);
 282         *table = (uint8_t *)v2 + ppt_offset_bytes;
 283
 284         return 0;
 285 }
 286
 287 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 288                                       uint32_t *size, uint32_t pptable_id)
 289 {
 290         struct amdgpu_device *adev = smu->adev;
 291         const struct smc_firmware_header_v2_1 *v2_1;
 292         struct smc_soft_pptable_entry *entries;
 293         uint32_t pptable_count = 0;
 294         int i = 0;
 295
 296         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 297         entries = (struct smc_soft_pptable_entry *)
 298                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 299         pptable_count = le32_to_cpu(v2_1->pptable_count);
 300         for (i = 0; i < pptable_count; i++) {
 301                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 302                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 303                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 304                         break;
 305                 }
 306         }
 307
 308         if (i == pptable_count)
 309                 return -EINVAL;
 310
 311         return 0;
 312 }
 313
 314 int smu_v11_0_setup_pptable(struct smu_context *smu)
 315 {
 316         struct amdgpu_device *adev = smu->adev;
 317         const struct smc_firmware_header_v1_0 *hdr;
 318         int ret, index;
 319         uint32_t size = 0;
 320         uint16_t atom_table_size;
 321         uint8_t frev, crev;
 322         void *table;
 323         uint16_t version_major, version_minor;
 324
 325         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 326         version_major = le16_to_cpu(hdr->header.header_version_major);
 327         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 328         if ((version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) ||
 329             adev->asic_type == CHIP_NAVY_FLOUNDER) {
 330                 dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
 331                 switch (version_minor) {
 332                 case 0:
 333                         ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 334                         break;
 335                 case 1:
 336                         ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 337                                                          smu->smu_table.boot_values.pp_table_id);
 338                         break;
 339                 default:
 340                         ret = -EINVAL;
 341                         break;
 342                 }
 343                 if (ret)
 344                         return ret;
 345
 346         } else {
 347                 dev_info(adev->dev, "use vbios provided pptable\n");
 348                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 349                                                     powerplayinfo);
 350
 351                 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
 352                                               (uint8_t **)&table);
 353                 if (ret)
 354                         return ret;
 355                 size = atom_table_size;
 356         }
 357
 358         if (!smu->smu_table.power_play_table)
 359                 smu->smu_table.power_play_table = table;
 360         if (!smu->smu_table.power_play_table_size)
 361                 smu->smu_table.power_play_table_size = size;
 362
 363         return 0;
 364 }
 365
 366 int smu_v11_0_init_smc_tables(struct smu_context *smu)
 367 {
 368         struct smu_table_context *smu_table = &smu->smu_table;
 369         struct smu_table *tables = smu_table->tables;
 370         int ret = 0;
 371
 372         smu_table->driver_pptable =
 373                 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
 374         if (!smu_table->driver_pptable) {
 375                 ret = -ENOMEM;
 376                 goto err0_out;
 377         }
 378
 379         smu_table->max_sustainable_clocks =
 380                 kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL);
 381         if (!smu_table->max_sustainable_clocks) {
 382                 ret = -ENOMEM;
 383                 goto err1_out;
 384         }
 385
 386         /* Arcturus does not support OVERDRIVE */
 387         if (tables[SMU_TABLE_OVERDRIVE].size) {
 388                 smu_table->overdrive_table =
 389                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 390                 if (!smu_table->overdrive_table) {
 391                         ret = -ENOMEM;
 392                         goto err2_out;
 393                 }
 394
 395                 smu_table->boot_overdrive_table =
 396                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 397                 if (!smu_table->boot_overdrive_table) {
 398                         ret = -ENOMEM;
 399                         goto err3_out;
 400                 }
 401         }
 402
 403         return 0;
 404
 405 err3_out:
 406         kfree(smu_table->overdrive_table);
 407 err2_out:
 408         kfree(smu_table->max_sustainable_clocks);
 409 err1_out:
 410         kfree(smu_table->driver_pptable);
 411 err0_out:
 412         return ret;
 413 }
 414
 415 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 416 {
 417         struct smu_table_context *smu_table = &smu->smu_table;
 418         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 419
 420         kfree(smu_table->gpu_metrics_table);
 421         kfree(smu_table->boot_overdrive_table);
 422         kfree(smu_table->overdrive_table);
 423         kfree(smu_table->max_sustainable_clocks);
 424         kfree(smu_table->driver_pptable);
 425         smu_table->gpu_metrics_table = NULL;
 426         smu_table->boot_overdrive_table = NULL;
 427         smu_table->overdrive_table = NULL;
 428         smu_table->max_sustainable_clocks = NULL;
 429         smu_table->driver_pptable = NULL;
 430         kfree(smu_table->hardcode_pptable);
 431         smu_table->hardcode_pptable = NULL;
 432
 433         kfree(smu_table->metrics_table);
 434         kfree(smu_table->watermarks_table);
 435         smu_table->metrics_table = NULL;
 436         smu_table->watermarks_table = NULL;
 437         smu_table->metrics_time = 0;
 438
 439         kfree(smu_dpm->dpm_context);
 440         kfree(smu_dpm->golden_dpm_context);
 441         kfree(smu_dpm->dpm_current_power_state);
 442         kfree(smu_dpm->dpm_request_power_state);
 443         smu_dpm->dpm_context = NULL;
 444         smu_dpm->golden_dpm_context = NULL;
 445         smu_dpm->dpm_context_size = 0;
 446         smu_dpm->dpm_current_power_state = NULL;
 447         smu_dpm->dpm_request_power_state = NULL;
 448
 449         return 0;
 450 }
 451
 452 int smu_v11_0_init_power(struct smu_context *smu)
 453 {
 454         struct smu_power_context *smu_power = &smu->smu_power;
 455
 456         if (smu_power->power_context || smu_power->power_context_size != 0)
 457                 return -EINVAL;
 458
 459         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 460                                            GFP_KERNEL);
 461         if (!smu_power->power_context)
 462                 return -ENOMEM;
 463         smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
 464
 465         return 0;
 466 }
 467
 468 int smu_v11_0_fini_power(struct smu_context *smu)
 469 {
 470         struct smu_power_context *smu_power = &smu->smu_power;
 471
 472         if (!smu_power->power_context || smu_power->power_context_size == 0)
 473                 return -EINVAL;
 474
 475         kfree(smu_power->power_context);
 476         smu_power->power_context = NULL;
 477         smu_power->power_context_size = 0;
 478
 479         return 0;
 480 }
 481
 482 static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
 483                                             uint8_t clk_id,
 484                                             uint8_t syspll_id,
 485                                             uint32_t *clk_freq)
 486 {
 487         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 488         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 489         int ret, index;
 490
 491         input.clk_id = clk_id;
 492         input.syspll_id = syspll_id;
 493         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 494         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 495                                             getsmuclockinfo);
 496
 497         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 498                                         (uint32_t *)&input);
 499         if (ret)
 500                 return -EINVAL;
 501
 502         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 503         *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 504
 505         return 0;
 506 }
 507
 508 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 509 {
 510         int ret, index;
 511         uint16_t size;
 512         uint8_t frev, crev;
 513         struct atom_common_table_header *header;
 514         struct atom_firmware_info_v3_3 *v_3_3;
 515         struct atom_firmware_info_v3_1 *v_3_1;
 516
 517         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 518                                             firmwareinfo);
 519
 520         ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
 521                                       (uint8_t **)&header);
 522         if (ret)
 523                 return ret;
 524
 525         if (header->format_revision != 3) {
 526                 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n");
 527                 return -EINVAL;
 528         }
 529
 530         switch (header->content_revision) {
 531         case 0:
 532         case 1:
 533         case 2:
 534                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 535                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 536                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 537                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 538                 smu->smu_table.boot_values.socclk = 0;
 539                 smu->smu_table.boot_values.dcefclk = 0;
 540                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 541                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 542                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 543                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 544                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 545                 smu->smu_table.boot_values.pp_table_id = 0;
 546                 break;
 547         case 3:
 548         default:
 549                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 550                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 551                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 552                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 553                 smu->smu_table.boot_values.socclk = 0;
 554                 smu->smu_table.boot_values.dcefclk = 0;
 555                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 556                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 557                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 558                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 559                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 560                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 561         }
 562
 563         smu->smu_table.boot_values.format_revision = header->format_revision;
 564         smu->smu_table.boot_values.content_revision = header->content_revision;
 565
 566         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 567                                          (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
 568                                          (uint8_t)0,
 569                                          &smu->smu_table.boot_values.socclk);
 570
 571         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 572                                          (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
 573                                          (uint8_t)0,
 574                                          &smu->smu_table.boot_values.dcefclk);
 575
 576         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 577                                          (uint8_t)SMU11_SYSPLL0_ECLK_ID,
 578                                          (uint8_t)0,
 579                                          &smu->smu_table.boot_values.eclk);
 580
 581         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 582                                          (uint8_t)SMU11_SYSPLL0_VCLK_ID,
 583                                          (uint8_t)0,
 584                                          &smu->smu_table.boot_values.vclk);
 585
 586         smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 587                                          (uint8_t)SMU11_SYSPLL0_DCLK_ID,
 588                                          (uint8_t)0,
 589                                          &smu->smu_table.boot_values.dclk);
 590
 591         if ((smu->smu_table.boot_values.format_revision == 3) &&
 592             (smu->smu_table.boot_values.content_revision >= 2))
 593                 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
 594                                                  (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
 595                                                  (uint8_t)SMU11_SYSPLL1_2_ID,
 596                                                  &smu->smu_table.boot_values.fclk);
 597
 598         return 0;
 599 }
 600
 601 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 602 {
 603         struct smu_table_context *smu_table = &smu->smu_table;
 604         struct smu_table *memory_pool = &smu_table->memory_pool;
 605         int ret = 0;
 606         uint64_t address;
 607         uint32_t address_low, address_high;
 608
 609         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 610                 return ret;
 611
 612         address = (uintptr_t)memory_pool->cpu_addr;
 613         address_high = (uint32_t)upper_32_bits(address);
 614         address_low  = (uint32_t)lower_32_bits(address);
 615
 616         ret = smu_cmn_send_smc_msg_with_param(smu,
 617                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 618                                           address_high,
 619                                           NULL);
 620         if (ret)
 621                 return ret;
 622         ret = smu_cmn_send_smc_msg_with_param(smu,
 623                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 624                                           address_low,
 625                                           NULL);
 626         if (ret)
 627                 return ret;
 628
 629         address = memory_pool->mc_address;
 630         address_high = (uint32_t)upper_32_bits(address);
 631         address_low  = (uint32_t)lower_32_bits(address);
 632
 633         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 634                                           address_high, NULL);
 635         if (ret)
 636                 return ret;
 637         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 638                                           address_low, NULL);
 639         if (ret)
 640                 return ret;
 641         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 642                                           (uint32_t)memory_pool->size, NULL);
 643         if (ret)
 644                 return ret;
 645
 646         return ret;
 647 }
 648
 649 int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 650 {
 651         int ret;
 652
 653         ret = smu_cmn_send_smc_msg_with_param(smu,
 654                                           SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
 655         if (ret)
 656                 dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!");
 657
 658         return ret;
 659 }
 660
 661 int smu_v11_0_set_driver_table_location(struct smu_context *smu)
 662 {
 663         struct smu_table *driver_table = &smu->smu_table.driver_table;
 664         int ret = 0;
 665
 666         if (driver_table->mc_address) {
 667                 ret = smu_cmn_send_smc_msg_with_param(smu,
 668                                 SMU_MSG_SetDriverDramAddrHigh,
 669                                 upper_32_bits(driver_table->mc_address),
 670                                 NULL);
 671                 if (!ret)
 672                         ret = smu_cmn_send_smc_msg_with_param(smu,
 673                                 SMU_MSG_SetDriverDramAddrLow,
 674                                 lower_32_bits(driver_table->mc_address),
 675                                 NULL);
 676         }
 677
 678         return ret;
 679 }
 680
 681 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 682 {
 683         int ret = 0;
 684         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 685
 686         if (tool_table->mc_address) {
 687                 ret = smu_cmn_send_smc_msg_with_param(smu,
 688                                 SMU_MSG_SetToolsDramAddrHigh,
 689                                 upper_32_bits(tool_table->mc_address),
 690                                 NULL);
 691                 if (!ret)
 692                         ret = smu_cmn_send_smc_msg_with_param(smu,
 693                                 SMU_MSG_SetToolsDramAddrLow,
 694                                 lower_32_bits(tool_table->mc_address),
 695                                 NULL);
 696         }
 697
 698         return ret;
 699 }
 700
 701 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 702 {
 703         int ret = 0;
 704         struct amdgpu_device *adev = smu->adev;
 705
 706         /* Navy_Flounder do not support to change display num currently */
 707         if (adev->asic_type == CHIP_NAVY_FLOUNDER)
 708                 return 0;
 709
 710         if (!smu->pm_enabled)
 711                 return ret;
 712
 713         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
 714         return ret;
 715 }
 716
 717
 718 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 719 {
 720         struct smu_feature *feature = &smu->smu_feature;
 721         int ret = 0;
 722         uint32_t feature_mask[2];
 723
 724         mutex_lock(&feature->mutex);
 725         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 726                 goto failed;
 727
 728         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 729
 730         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 731                                           feature_mask[1], NULL);
 732         if (ret)
 733                 goto failed;
 734
 735         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 736                                           feature_mask[0], NULL);
 737         if (ret)
 738                 goto failed;
 739
 740 failed:
 741         mutex_unlock(&feature->mutex);
 742         return ret;
 743 }
 744
 745 int smu_v11_0_system_features_control(struct smu_context *smu,
 746                                              bool en)
 747 {
 748         struct smu_feature *feature = &smu->smu_feature;
 749         uint32_t feature_mask[2];
 750         int ret = 0;
 751
 752         ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 753                                      SMU_MSG_DisableAllSmuFeatures), NULL);
 754         if (ret)
 755                 return ret;
 756
 757         bitmap_zero(feature->enabled, feature->feature_num);
 758         bitmap_zero(feature->supported, feature->feature_num);
 759
 760         if (en) {
 761                 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
 762                 if (ret)
 763                         return ret;
 764
 765                 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 766                             feature->feature_num);
 767                 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 768                             feature->feature_num);
 769         }
 770
 771         return ret;
 772 }
 773
 774 int smu_v11_0_notify_display_change(struct smu_context *smu)
 775 {
 776         int ret = 0;
 777
 778         if (!smu->pm_enabled)
 779                 return ret;
 780
 781         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 782             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 783                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
 784
 785         return ret;
 786 }
 787
 788 static int
 789 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 790                                     enum smu_clk_type clock_select)
 791 {
 792         int ret = 0;
 793         int clk_id;
 794
 795         if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 796             (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
 797                 return 0;
 798
 799         clk_id = smu_cmn_to_asic_specific_index(smu,
 800                                                 CMN2ASIC_MAPPING_CLK,
 801                                                 clock_select);
 802         if (clk_id < 0)
 803                 return -EINVAL;
 804
 805         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 806                                           clk_id << 16, clock);
 807         if (ret) {
 808                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 809                 return ret;
 810         }
 811
 812         if (*clock != 0)
 813                 return 0;
 814
 815         /* if DC limit is zero, return AC limit */
 816         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 817                                           clk_id << 16, clock);
 818         if (ret) {
 819                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 820                 return ret;
 821         }
 822
 823         return 0;
 824 }
 825
 826 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 827 {
 828         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
 829                         smu->smu_table.max_sustainable_clocks;
 830         int ret = 0;
 831
 832         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 833         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 834         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 835         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 836         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 837         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 838
 839         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 840                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 841                                                           &(max_sustainable_clocks->uclock),
 842                                                           SMU_UCLK);
 843                 if (ret) {
 844                         dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
 845                                __func__);
 846                         return ret;
 847                 }
 848         }
 849
 850         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 851                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 852                                                           &(max_sustainable_clocks->soc_clock),
 853                                                           SMU_SOCCLK);
 854                 if (ret) {
 855                         dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
 856                                __func__);
 857                         return ret;
 858                 }
 859         }
 860
 861         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 862                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 863                                                           &(max_sustainable_clocks->dcef_clock),
 864                                                           SMU_DCEFCLK);
 865                 if (ret) {
 866                         dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
 867                                __func__);
 868                         return ret;
 869                 }
 870
 871                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 872                                                           &(max_sustainable_clocks->display_clock),
 873                                                           SMU_DISPCLK);
 874                 if (ret) {
 875                         dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
 876                                __func__);
 877                         return ret;
 878                 }
 879                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 880                                                           &(max_sustainable_clocks->phy_clock),
 881                                                           SMU_PHYCLK);
 882                 if (ret) {
 883                         dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
 884                                __func__);
 885                         return ret;
 886                 }
 887                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 888                                                           &(max_sustainable_clocks->pixel_clock),
 889                                                           SMU_PIXCLK);
 890                 if (ret) {
 891                         dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
 892                                __func__);
 893                         return ret;
 894                 }
 895         }
 896
 897         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
 898                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
 899
 900         return 0;
 901 }
 902
 903 int smu_v11_0_get_current_power_limit(struct smu_context *smu,
 904                                       uint32_t *power_limit)
 905 {
 906         int power_src;
 907         int ret = 0;
 908
 909         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
 910                 return -EINVAL;
 911
 912         power_src = smu_cmn_to_asic_specific_index(smu,
 913                                         CMN2ASIC_MAPPING_PWR,
 914                                         smu->adev->pm.ac_power ?
 915                                         SMU_POWER_SOURCE_AC :
 916                                         SMU_POWER_SOURCE_DC);
 917         if (power_src < 0)
 918                 return -EINVAL;
 919
 920         ret = smu_cmn_send_smc_msg_with_param(smu,
 921                                           SMU_MSG_GetPptLimit,
 922                                           power_src << 16,
 923                                           power_limit);
 924         if (ret)
 925                 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
 926
 927         return ret;
 928 }
 929
 930 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
 931 {
 932         int ret = 0;
 933
 934         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
 935                 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
 936                 return -EOPNOTSUPP;
 937         }
 938
 939         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
 940         if (ret) {
 941                 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
 942                 return ret;
 943         }
 944
 945         smu->current_power_limit = n;
 946
 947         return 0;
 948 }
 949
 950 int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
 951 {
 952         if (smu->smu_table.thermal_controller_type)
 953                 return amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
 954
 955         return 0;
 956 }
 957
 958 int smu_v11_0_disable_thermal_alert(struct smu_context *smu)
 959 {
 960         return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
 961 }
 962
 963 static uint16_t convert_to_vddc(uint8_t vid)
 964 {
 965         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
 966 }
 967
 968 int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
 969 {
 970         struct amdgpu_device *adev = smu->adev;
 971         uint32_t vdd = 0, val_vid = 0;
 972
 973         if (!value)
 974                 return -EINVAL;
 975         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
 976                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
 977                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
 978
 979         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
 980
 981         *value = vdd;
 982
 983         return 0;
 984
 985 }
 986
 987 int
 988 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
 989                                         struct pp_display_clock_request
 990                                         *clock_req)
 991 {
 992         enum amd_pp_clock_type clk_type = clock_req->clock_type;
 993         int ret = 0;
 994         enum smu_clk_type clk_select = 0;
 995         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
 996
 997         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
 998                 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 999                 switch (clk_type) {
1000                 case amd_pp_dcef_clock:
1001                         clk_select = SMU_DCEFCLK;
1002                         break;
1003                 case amd_pp_disp_clock:
1004                         clk_select = SMU_DISPCLK;
1005                         break;
1006                 case amd_pp_pixel_clock:
1007                         clk_select = SMU_PIXCLK;
1008                         break;
1009                 case amd_pp_phy_clock:
1010                         clk_select = SMU_PHYCLK;
1011                         break;
1012                 case amd_pp_mem_clock:
1013                         clk_select = SMU_UCLK;
1014                         break;
1015                 default:
1016                         dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1017                         ret = -EINVAL;
1018                         break;
1019                 }
1020
1021                 if (ret)
1022                         goto failed;
1023
1024                 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1025                         return 0;
1026
1027                 ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1028
1029                 if(clk_select == SMU_UCLK)
1030                         smu->hard_min_uclk_req_from_dal = clk_freq;
1031         }
1032
1033 failed:
1034         return ret;
1035 }
1036
1037 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1038 {
1039         int ret = 0;
1040         struct amdgpu_device *adev = smu->adev;
1041
1042         switch (adev->asic_type) {
1043         case CHIP_NAVI10:
1044         case CHIP_NAVI14:
1045         case CHIP_NAVI12:
1046         case CHIP_SIENNA_CICHLID:
1047         case CHIP_NAVY_FLOUNDER:
1048                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1049                         return 0;
1050                 if (enable)
1051                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
1052                 else
1053                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
1054                 break;
1055         default:
1056                 break;
1057         }
1058
1059         return ret;
1060 }
1061
1062 uint32_t
1063 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1064 {
1065         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1066                 return AMD_FAN_CTRL_MANUAL;
1067         else
1068                 return AMD_FAN_CTRL_AUTO;
1069 }
1070
1071 static int
1072 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1073 {
1074         int ret = 0;
1075
1076         if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1077                 return 0;
1078
1079         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1080         if (ret)
1081                 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1082                        __func__, (auto_fan_control ? "Start" : "Stop"));
1083
1084         return ret;
1085 }
1086
1087 static int
1088 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1089 {
1090         struct amdgpu_device *adev = smu->adev;
1091
1092         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1093                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1094                                    CG_FDO_CTRL2, TMIN, 0));
1095         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1096                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1097                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1098
1099         return 0;
1100 }
1101
1102 int
1103 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1104 {
1105         struct amdgpu_device *adev = smu->adev;
1106         uint32_t duty100, duty;
1107         uint64_t tmp64;
1108
1109         if (speed > 100)
1110                 speed = 100;
1111
1112         if (smu_v11_0_auto_fan_control(smu, 0))
1113                 return -EINVAL;
1114
1115         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1116                                 CG_FDO_CTRL1, FMAX_DUTY100);
1117         if (!duty100)
1118                 return -EINVAL;
1119
1120         tmp64 = (uint64_t)speed * duty100;
1121         do_div(tmp64, 100);
1122         duty = (uint32_t)tmp64;
1123
1124         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1125                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1126                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1127
1128         return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1129 }
1130
1131 int
1132 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1133                                uint32_t mode)
1134 {
1135         int ret = 0;
1136
1137         switch (mode) {
1138         case AMD_FAN_CTRL_NONE:
1139                 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1140                 break;
1141         case AMD_FAN_CTRL_MANUAL:
1142                 ret = smu_v11_0_auto_fan_control(smu, 0);
1143                 break;
1144         case AMD_FAN_CTRL_AUTO:
1145                 ret = smu_v11_0_auto_fan_control(smu, 1);
1146                 break;
1147         default:
1148                 break;
1149         }
1150
1151         if (ret) {
1152                 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1153                 return -EINVAL;
1154         }
1155
1156         return ret;
1157 }
1158
1159 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1160                                        uint32_t speed)
1161 {
1162         struct amdgpu_device *adev = smu->adev;
1163         int ret;
1164         uint32_t tach_period, crystal_clock_freq;
1165
1166         if (!speed)
1167                 return -EINVAL;
1168
1169         ret = smu_v11_0_auto_fan_control(smu, 0);
1170         if (ret)
1171                 return ret;
1172
1173         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1174         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1175         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1176                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1177                                    CG_TACH_CTRL, TARGET_PERIOD,
1178                                    tach_period));
1179
1180         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1181
1182         return ret;
1183 }
1184
1185 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1186                                      uint32_t pstate)
1187 {
1188         int ret = 0;
1189         ret = smu_cmn_send_smc_msg_with_param(smu,
1190                                           SMU_MSG_SetXgmiMode,
1191                                           pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1192                                           NULL);
1193         return ret;
1194 }
1195
1196 static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
1197                                    struct amdgpu_irq_src *source,
1198                                    unsigned tyep,
1199                                    enum amdgpu_interrupt_state state)
1200 {
1201         struct smu_context *smu = &adev->smu;
1202         uint32_t low, high;
1203         uint32_t val = 0;
1204
1205         switch (state) {
1206         case AMDGPU_IRQ_STATE_DISABLE:
1207                 /* For THM irqs */
1208                 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1209                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1210                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1211                 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1212
1213                 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1214
1215                 /* For MP1 SW irqs */
1216                 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1217                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1218                 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1219
1220                 break;
1221         case AMDGPU_IRQ_STATE_ENABLE:
1222                 /* For THM irqs */
1223                 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1224                                 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1225                 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1226                                 smu->thermal_range.software_shutdown_temp);
1227
1228                 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1229                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1230                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1231                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1232                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1233                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1234                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1235                 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1236                 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1237
1238                 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1239                 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1240                 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1241                 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1242
1243                 /* For MP1 SW irqs */
1244                 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT);
1245                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1246                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1247                 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val);
1248
1249                 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1250                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1251                 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1252
1253                 break;
1254         default:
1255                 break;
1256         }
1257
1258         return 0;
1259 }
1260
1261 static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu)
1262 {
1263         return smu_cmn_send_smc_msg(smu,
1264                                 SMU_MSG_ReenableAcDcInterrupt,
1265                                 NULL);
1266 }
1267
1268 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1269 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1270
1271 #define SMUIO_11_0__SRCID__SMUIO_GPIO19                 83
1272
1273 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1274                                  struct amdgpu_irq_src *source,
1275                                  struct amdgpu_iv_entry *entry)
1276 {
1277         struct smu_context *smu = &adev->smu;
1278         uint32_t client_id = entry->client_id;
1279         uint32_t src_id = entry->src_id;
1280         /*
1281          * ctxid is used to distinguish different
1282          * events for SMCToHost interrupt.
1283          */
1284         uint32_t ctxid = entry->src_data[0];
1285         uint32_t data;
1286
1287         if (client_id == SOC15_IH_CLIENTID_THM) {
1288                 switch (src_id) {
1289                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1290                         dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1291                         /*
1292                          * SW CTF just occurred.
1293                          * Try to do a graceful shutdown to prevent further damage.
1294                          */
1295                         dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1296                         orderly_poweroff(true);
1297                 break;
1298                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1299                         dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1300                 break;
1301                 default:
1302                         dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1303                                 src_id);
1304                 break;
1305                 }
1306         } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1307                 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1308                 /*
1309                  * HW CTF just occurred. Shutdown to prevent further damage.
1310                  */
1311                 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1312                 orderly_poweroff(true);
1313         } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1314                 if (src_id == 0xfe) {
1315                         /* ACK SMUToHost interrupt */
1316                         data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1317                         data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1318                         WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data);
1319
1320                         switch (ctxid) {
1321                         case 0x3:
1322                                 dev_dbg(adev->dev, "Switched to AC mode!\n");
1323                                 smu_v11_0_ack_ac_dc_interrupt(&adev->smu);
1324                                 break;
1325                         case 0x4:
1326                                 dev_dbg(adev->dev, "Switched to DC mode!\n");
1327                                 smu_v11_0_ack_ac_dc_interrupt(&adev->smu);
1328                                 break;
1329                         case 0x7:
1330                                 /*
1331                                  * Increment the throttle interrupt counter
1332                                  */
1333                                 atomic64_inc(&smu->throttle_int_counter);
1334
1335                                 if (!atomic_read(&adev->throttling_logging_enabled))
1336                                         return 0;
1337
1338                                 if (__ratelimit(&adev->throttling_logging_rs))
1339                                         schedule_work(&smu->throttling_logging_work);
1340
1341                                 break;
1342                         }
1343                 }
1344         }
1345
1346         return 0;
1347 }
1348
1349 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1350 {
1351         .set = smu_v11_0_set_irq_state,
1352         .process = smu_v11_0_irq_process,
1353 };
1354
1355 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1356 {
1357         struct amdgpu_device *adev = smu->adev;
1358         struct amdgpu_irq_src *irq_src = &smu->irq_source;
1359         int ret = 0;
1360
1361         irq_src->num_types = 1;
1362         irq_src->funcs = &smu_v11_0_irq_funcs;
1363
1364         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1365                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1366                                 irq_src);
1367         if (ret)
1368                 return ret;
1369
1370         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1371                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1372                                 irq_src);
1373         if (ret)
1374                 return ret;
1375
1376         /* Register CTF(GPIO_19) interrupt */
1377         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1378                                 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1379                                 irq_src);
1380         if (ret)
1381                 return ret;
1382
1383         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1384                                 0xfe,
1385                                 irq_src);
1386         if (ret)
1387                 return ret;
1388
1389         return ret;
1390 }
1391
1392 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1393                 struct pp_smu_nv_clock_table *max_clocks)
1394 {
1395         struct smu_table_context *table_context = &smu->smu_table;
1396         struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1397
1398         if (!max_clocks || !table_context->max_sustainable_clocks)
1399                 return -EINVAL;
1400
1401         sustainable_clocks = table_context->max_sustainable_clocks;
1402
1403         max_clocks->dcfClockInKhz =
1404                         (unsigned int) sustainable_clocks->dcef_clock * 1000;
1405         max_clocks->displayClockInKhz =
1406                         (unsigned int) sustainable_clocks->display_clock * 1000;
1407         max_clocks->phyClockInKhz =
1408                         (unsigned int) sustainable_clocks->phy_clock * 1000;
1409         max_clocks->pixelClockInKhz =
1410                         (unsigned int) sustainable_clocks->pixel_clock * 1000;
1411         max_clocks->uClockInKhz =
1412                         (unsigned int) sustainable_clocks->uclock * 1000;
1413         max_clocks->socClockInKhz =
1414                         (unsigned int) sustainable_clocks->soc_clock * 1000;
1415         max_clocks->dscClockInKhz = 0;
1416         max_clocks->dppClockInKhz = 0;
1417         max_clocks->fabricClockInKhz = 0;
1418
1419         return 0;
1420 }
1421
1422 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1423 {
1424         int ret = 0;
1425
1426         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1427
1428         return ret;
1429 }
1430
1431 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1432 {
1433         return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
1434 }
1435
1436 bool smu_v11_0_baco_is_support(struct smu_context *smu)
1437 {
1438         struct smu_baco_context *smu_baco = &smu->smu_baco;
1439         bool baco_support;
1440
1441         mutex_lock(&smu_baco->mutex);
1442         baco_support = smu_baco->platform_support;
1443         mutex_unlock(&smu_baco->mutex);
1444
1445         if (!baco_support)
1446                 return false;
1447
1448         /* Arcturus does not support this bit mask */
1449         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1450            !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1451                 return false;
1452
1453         return true;
1454 }
1455
1456 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1457 {
1458         struct smu_baco_context *smu_baco = &smu->smu_baco;
1459         enum smu_baco_state baco_state;
1460
1461         mutex_lock(&smu_baco->mutex);
1462         baco_state = smu_baco->state;
1463         mutex_unlock(&smu_baco->mutex);
1464
1465         return baco_state;
1466 }
1467
1468 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1469 {
1470         struct smu_baco_context *smu_baco = &smu->smu_baco;
1471         struct amdgpu_device *adev = smu->adev;
1472         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1473         uint32_t data;
1474         int ret = 0;
1475
1476         if (smu_v11_0_baco_get_state(smu) == state)
1477                 return 0;
1478
1479         mutex_lock(&smu_baco->mutex);
1480
1481         if (state == SMU_BACO_STATE_ENTER) {
1482                 if (!ras || !ras->supported) {
1483                         data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1484                         data |= 0x80000000;
1485                         WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1486
1487                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
1488                 } else {
1489                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL);
1490                 }
1491         } else {
1492                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL);
1493                 if (ret)
1494                         goto out;
1495
1496                 /* clear vbios scratch 6 and 7 for coming asic reinit */
1497                 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1498                 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1499         }
1500         if (ret)
1501                 goto out;
1502
1503         smu_baco->state = state;
1504 out:
1505         mutex_unlock(&smu_baco->mutex);
1506         return ret;
1507 }
1508
1509 int smu_v11_0_baco_enter(struct smu_context *smu)
1510 {
1511         struct amdgpu_device *adev = smu->adev;
1512         int ret = 0;
1513
1514         /* Arcturus does not need this audio workaround */
1515         if (adev->asic_type != CHIP_ARCTURUS) {
1516                 ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1517                 if (ret)
1518                         return ret;
1519         }
1520
1521         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1522         if (ret)
1523                 return ret;
1524
1525         msleep(10);
1526
1527         return ret;
1528 }
1529
1530 int smu_v11_0_baco_exit(struct smu_context *smu)
1531 {
1532         int ret = 0;
1533
1534         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1535         if (ret)
1536                 return ret;
1537
1538         return ret;
1539 }
1540
1541 int smu_v11_0_mode1_reset(struct smu_context *smu)
1542 {
1543         int ret = 0;
1544
1545         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1546         if (!ret)
1547                 msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS);
1548
1549         return ret;
1550 }
1551
1552 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1553                                                  uint32_t *min, uint32_t *max)
1554 {
1555         int ret = 0, clk_id = 0;
1556         uint32_t param = 0;
1557         uint32_t clock_limit;
1558
1559         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1560                 switch (clk_type) {
1561                 case SMU_MCLK:
1562                 case SMU_UCLK:
1563                         clock_limit = smu->smu_table.boot_values.uclk;
1564                         break;
1565                 case SMU_GFXCLK:
1566                 case SMU_SCLK:
1567                         clock_limit = smu->smu_table.boot_values.gfxclk;
1568                         break;
1569                 case SMU_SOCCLK:
1570                         clock_limit = smu->smu_table.boot_values.socclk;
1571                         break;
1572                 default:
1573                         clock_limit = 0;
1574                         break;
1575                 }
1576
1577                 /* clock in Mhz unit */
1578                 if (min)
1579                         *min = clock_limit / 100;
1580                 if (max)
1581                         *max = clock_limit / 100;
1582
1583                 return 0;
1584         }
1585
1586         clk_id = smu_cmn_to_asic_specific_index(smu,
1587                                                 CMN2ASIC_MAPPING_CLK,
1588                                                 clk_type);
1589         if (clk_id < 0) {
1590                 ret = -EINVAL;
1591                 goto failed;
1592         }
1593         param = (clk_id & 0xffff) << 16;
1594
1595         if (max) {
1596                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1597                 if (ret)
1598                         goto failed;
1599         }
1600
1601         if (min) {
1602                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1603                 if (ret)
1604                         goto failed;
1605         }
1606
1607 failed:
1608         return ret;
1609 }
1610
1611 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
1612                                           enum smu_clk_type clk_type,
1613                                           uint32_t min,
1614                                           uint32_t max)
1615 {
1616         struct amdgpu_device *adev = smu->adev;
1617         int ret = 0, clk_id = 0;
1618         uint32_t param;
1619
1620         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1621                 return 0;
1622
1623         clk_id = smu_cmn_to_asic_specific_index(smu,
1624                                                 CMN2ASIC_MAPPING_CLK,
1625                                                 clk_type);
1626         if (clk_id < 0)
1627                 return clk_id;
1628
1629         if (clk_type == SMU_GFXCLK)
1630                 amdgpu_gfx_off_ctrl(adev, false);
1631
1632         if (max > 0) {
1633                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1634                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1635                                                   param, NULL);
1636                 if (ret)
1637                         goto out;
1638         }
1639
1640         if (min > 0) {
1641                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1642                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1643                                                   param, NULL);
1644                 if (ret)
1645                         goto out;
1646         }
1647
1648 out:
1649         if (clk_type == SMU_GFXCLK)
1650                 amdgpu_gfx_off_ctrl(adev, true);
1651
1652         return ret;
1653 }
1654
1655 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
1656                                           enum smu_clk_type clk_type,
1657                                           uint32_t min,
1658                                           uint32_t max)
1659 {
1660         int ret = 0, clk_id = 0;
1661         uint32_t param;
1662
1663         if (min <= 0 && max <= 0)
1664                 return -EINVAL;
1665
1666         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1667                 return 0;
1668
1669         clk_id = smu_cmn_to_asic_specific_index(smu,
1670                                                 CMN2ASIC_MAPPING_CLK,
1671                                                 clk_type);
1672         if (clk_id < 0)
1673                 return clk_id;
1674
1675         if (max > 0) {
1676                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1677                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1678                                                   param, NULL);
1679                 if (ret)
1680                         return ret;
1681         }
1682
1683         if (min > 0) {
1684                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1685                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1686                                                   param, NULL);
1687                 if (ret)
1688                         return ret;
1689         }
1690
1691         return ret;
1692 }
1693
1694 int smu_v11_0_set_performance_level(struct smu_context *smu,
1695                                     enum amd_dpm_forced_level level)
1696 {
1697         struct smu_11_0_dpm_context *dpm_context =
1698                                 smu->smu_dpm.dpm_context;
1699         struct smu_11_0_dpm_table *gfx_table =
1700                                 &dpm_context->dpm_tables.gfx_table;
1701         struct smu_11_0_dpm_table *mem_table =
1702                                 &dpm_context->dpm_tables.uclk_table;
1703         struct smu_11_0_dpm_table *soc_table =
1704                                 &dpm_context->dpm_tables.soc_table;
1705         struct smu_umd_pstate_table *pstate_table =
1706                                 &smu->pstate_table;
1707         struct amdgpu_device *adev = smu->adev;
1708         uint32_t sclk_min = 0, sclk_max = 0;
1709         uint32_t mclk_min = 0, mclk_max = 0;
1710         uint32_t socclk_min = 0, socclk_max = 0;
1711         int ret = 0;
1712
1713         switch (level) {
1714         case AMD_DPM_FORCED_LEVEL_HIGH:
1715                 sclk_min = sclk_max = gfx_table->max;
1716                 mclk_min = mclk_max = mem_table->max;
1717                 socclk_min = socclk_max = soc_table->max;
1718                 break;
1719         case AMD_DPM_FORCED_LEVEL_LOW:
1720                 sclk_min = sclk_max = gfx_table->min;
1721                 mclk_min = mclk_max = mem_table->min;
1722                 socclk_min = socclk_max = soc_table->min;
1723                 break;
1724         case AMD_DPM_FORCED_LEVEL_AUTO:
1725                 sclk_min = gfx_table->min;
1726                 sclk_max = gfx_table->max;
1727                 mclk_min = mem_table->min;
1728                 mclk_max = mem_table->max;
1729                 socclk_min = soc_table->min;
1730                 socclk_max = soc_table->max;
1731                 break;
1732         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1733                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1734                 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1735                 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1736                 break;
1737         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1738                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1739                 break;
1740         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1741                 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1742                 break;
1743         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1744                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1745                 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1746                 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1747                 break;
1748         case AMD_DPM_FORCED_LEVEL_MANUAL:
1749         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1750                 return 0;
1751         default:
1752                 dev_err(adev->dev, "Invalid performance level %d\n", level);
1753                 return -EINVAL;
1754         }
1755
1756         /*
1757          * Separate MCLK and SOCCLK soft min/max settings are not allowed
1758          * on Arcturus.
1759          */
1760         if (adev->asic_type == CHIP_ARCTURUS) {
1761                 mclk_min = mclk_max = 0;
1762                 socclk_min = socclk_max = 0;
1763         }
1764
1765         if (sclk_min && sclk_max) {
1766                 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1767                                                             SMU_GFXCLK,
1768                                                             sclk_min,
1769                                                             sclk_max);
1770                 if (ret)
1771                         return ret;
1772         }
1773
1774         if (mclk_min && mclk_max) {
1775                 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1776                                                             SMU_MCLK,
1777                                                             mclk_min,
1778                                                             mclk_max);
1779                 if (ret)
1780                         return ret;
1781         }
1782
1783         if (socclk_min && socclk_max) {
1784                 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1785                                                             SMU_SOCCLK,
1786                                                             socclk_min,
1787                                                             socclk_max);
1788                 if (ret)
1789                         return ret;
1790         }
1791
1792         return ret;
1793 }
1794
1795 int smu_v11_0_set_power_source(struct smu_context *smu,
1796                                enum smu_power_src_type power_src)
1797 {
1798         int pwr_source;
1799
1800         pwr_source = smu_cmn_to_asic_specific_index(smu,
1801                                                     CMN2ASIC_MAPPING_PWR,
1802                                                     (uint32_t)power_src);
1803         if (pwr_source < 0)
1804                 return -EINVAL;
1805
1806         return smu_cmn_send_smc_msg_with_param(smu,
1807                                         SMU_MSG_NotifyPowerSource,
1808                                         pwr_source,
1809                                         NULL);
1810 }
1811
1812 int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
1813                                     enum smu_clk_type clk_type,
1814                                     uint16_t level,
1815                                     uint32_t *value)
1816 {
1817         int ret = 0, clk_id = 0;
1818         uint32_t param;
1819
1820         if (!value)
1821                 return -EINVAL;
1822
1823         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1824                 return 0;
1825
1826         clk_id = smu_cmn_to_asic_specific_index(smu,
1827                                                 CMN2ASIC_MAPPING_CLK,
1828                                                 clk_type);
1829         if (clk_id < 0)
1830                 return clk_id;
1831
1832         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1833
1834         ret = smu_cmn_send_smc_msg_with_param(smu,
1835                                           SMU_MSG_GetDpmFreqByIndex,
1836                                           param,
1837                                           value);
1838         if (ret)
1839                 return ret;
1840
1841         /*
1842          * BIT31:  0 - Fine grained DPM, 1 - Dicrete DPM
1843          * now, we un-support it
1844          */
1845         *value = *value & 0x7fffffff;
1846
1847         return ret;
1848 }
1849
1850 int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
1851                                   enum smu_clk_type clk_type,
1852                                   uint32_t *value)
1853 {
1854         return smu_v11_0_get_dpm_freq_by_index(smu,
1855                                                clk_type,
1856                                                0xff,
1857                                                value);
1858 }
1859
1860 int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
1861                                    enum smu_clk_type clk_type,
1862                                    struct smu_11_0_dpm_table *single_dpm_table)
1863 {
1864         int ret = 0;
1865         uint32_t clk;
1866         int i;
1867
1868         ret = smu_v11_0_get_dpm_level_count(smu,
1869                                             clk_type,
1870                                             &single_dpm_table->count);
1871         if (ret) {
1872                 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1873                 return ret;
1874         }
1875
1876         for (i = 0; i < single_dpm_table->count; i++) {
1877                 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1878                                                       clk_type,
1879                                                       i,
1880                                                       &clk);
1881                 if (ret) {
1882                         dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1883                         return ret;
1884                 }
1885
1886                 single_dpm_table->dpm_levels[i].value = clk;
1887                 single_dpm_table->dpm_levels[i].enabled = true;
1888
1889                 if (i == 0)
1890                         single_dpm_table->min = clk;
1891                 else if (i == single_dpm_table->count - 1)
1892                         single_dpm_table->max = clk;
1893         }
1894
1895         return 0;
1896 }
1897
1898 int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
1899                                   enum smu_clk_type clk_type,
1900                                   uint32_t *min_value,
1901                                   uint32_t *max_value)
1902 {
1903         uint32_t level_count = 0;
1904         int ret = 0;
1905
1906         if (!min_value && !max_value)
1907                 return -EINVAL;
1908
1909         if (min_value) {
1910                 /* by default, level 0 clock value as min value */
1911                 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1912                                                       clk_type,
1913                                                       0,
1914                                                       min_value);
1915                 if (ret)
1916                         return ret;
1917         }
1918
1919         if (max_value) {
1920                 ret = smu_v11_0_get_dpm_level_count(smu,
1921                                                     clk_type,
1922                                                     &level_count);
1923                 if (ret)
1924                         return ret;
1925
1926                 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1927                                                       clk_type,
1928                                                       level_count - 1,
1929                                                       max_value);
1930                 if (ret)
1931                         return ret;
1932         }
1933
1934         return ret;
1935 }
1936
1937 int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu)
1938 {
1939         struct amdgpu_device *adev = smu->adev;
1940
1941         return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
1942                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
1943                 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
1944 }
1945
1946 int smu_v11_0_get_current_pcie_link_width(struct smu_context *smu)
1947 {
1948         uint32_t width_level;
1949
1950         width_level = smu_v11_0_get_current_pcie_link_width_level(smu);
1951         if (width_level > LINK_WIDTH_MAX)
1952                 width_level = 0;
1953
1954         return link_width[width_level];
1955 }
1956
1957 int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu)
1958 {
1959         struct amdgpu_device *adev = smu->adev;
1960
1961         return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
1962                 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
1963                 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1964 }
1965
1966 int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu)
1967 {
1968         uint32_t speed_level;
1969
1970         speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu);
1971         if (speed_level > LINK_SPEED_MAX)
1972                 speed_level = 0;
1973
1974         return link_speed[speed_level];
1975 }
1976
1977 void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics)
1978 {
1979         memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0));
1980
1981         gpu_metrics->common_header.structure_size =
1982                                 sizeof(struct gpu_metrics_v1_0);
1983         gpu_metrics->common_header.format_revision = 1;
1984         gpu_metrics->common_header.content_revision = 0;
1985
1986         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1987 }