drivers/gpu/drm/amd/powerplay/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26
  27 #include "pp_debug.h"
  28 #include "amdgpu.h"
  29 #include "amdgpu_smu.h"
  30 #include "atomfirmware.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "smu_v11_0.h"
  33 #include "soc15_common.h"
  34 #include "atom.h"
  35 #include "vega20_ppt.h"
  36 #include "navi10_ppt.h"
  37
  38 #include "asic_reg/thm/thm_11_0_2_offset.h"
  39 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  40 #include "asic_reg/mp/mp_11_0_offset.h"
  41 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  42 #include "asic_reg/nbio/nbio_7_4_offset.h"
  43 #include "asic_reg/nbio/nbio_7_4_sh_mask.h"
  44 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  45 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  46
  47 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
  48 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  49
  50 #define SMU11_VOLTAGE_SCALE 4
  51
  52 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
  53                                               uint16_t msg)
  54 {
  55         struct amdgpu_device *adev = smu->adev;
  56         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  57         return 0;
  58 }
  59
  60 static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
  61 {
  62         struct amdgpu_device *adev = smu->adev;
  63
  64         *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
  65         return 0;
  66 }
  67
  68 static int smu_v11_0_wait_for_response(struct smu_context *smu)
  69 {
  70         struct amdgpu_device *adev = smu->adev;
  71         uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
  72
  73         for (i = 0; i < timeout; i++) {
  74                 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  75                 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
  76                         break;
  77                 udelay(1);
  78         }
  79
  80         /* timeout means wrong logic */
  81         if (i == timeout)
  82                 return -ETIME;
  83
  84         return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
  85 }
  86
  87 static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
  88 {
  89         struct amdgpu_device *adev = smu->adev;
  90         int ret = 0, index = 0;
  91
  92         index = smu_msg_get_index(smu, msg);
  93         if (index < 0)
  94                 return index;
  95
  96         smu_v11_0_wait_for_response(smu);
  97
  98         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
  99
 100         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 101
 102         ret = smu_v11_0_wait_for_response(smu);
 103
 104         if (ret)
 105                 pr_err("Failed to send message 0x%x, response 0x%x\n", index,
 106                        ret);
 107
 108         return ret;
 109
 110 }
 111
 112 static int
 113 smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
 114                               uint32_t param)
 115 {
 116
 117         struct amdgpu_device *adev = smu->adev;
 118         int ret = 0, index = 0;
 119
 120         index = smu_msg_get_index(smu, msg);
 121         if (index < 0)
 122                 return index;
 123
 124         ret = smu_v11_0_wait_for_response(smu);
 125         if (ret)
 126                 pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
 127                        index, ret, param);
 128
 129         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 130
 131         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
 132
 133         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 134
 135         ret = smu_v11_0_wait_for_response(smu);
 136         if (ret)
 137                 pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n",
 138                        index, ret, param);
 139
 140         return ret;
 141 }
 142
 143 static int smu_v11_0_init_microcode(struct smu_context *smu)
 144 {
 145         struct amdgpu_device *adev = smu->adev;
 146         const char *chip_name;
 147         char fw_name[30];
 148         int err = 0;
 149         const struct smc_firmware_header_v1_0 *hdr;
 150         const struct common_firmware_header *header;
 151         struct amdgpu_firmware_info *ucode = NULL;
 152
 153         switch (adev->asic_type) {
 154         case CHIP_VEGA20:
 155                 chip_name = "vega20";
 156                 break;
 157         case CHIP_NAVI10:
 158                 chip_name = "navi10";
 159                 break;
 160         default:
 161                 BUG();
 162         }
 163
 164         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 165
 166         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 167         if (err)
 168                 goto out;
 169         err = amdgpu_ucode_validate(adev->pm.fw);
 170         if (err)
 171                 goto out;
 172
 173         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 174         amdgpu_ucode_print_smc_hdr(&hdr->header);
 175         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 176
 177         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 178                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 179                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 180                 ucode->fw = adev->pm.fw;
 181                 header = (const struct common_firmware_header *)ucode->fw->data;
 182                 adev->firmware.fw_size +=
 183                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 184         }
 185
 186 out:
 187         if (err) {
 188                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 189                           fw_name);
 190                 release_firmware(adev->pm.fw);
 191                 adev->pm.fw = NULL;
 192         }
 193         return err;
 194 }
 195
 196 static int smu_v11_0_load_microcode(struct smu_context *smu)
 197 {
 198         struct amdgpu_device *adev = smu->adev;
 199         const uint32_t *src;
 200         const struct smc_firmware_header_v1_0 *hdr;
 201         uint32_t addr_start = MP1_SRAM;
 202         uint32_t i;
 203         uint32_t mp1_fw_flags;
 204
 205         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 206         src = (const uint32_t *)(adev->pm.fw->data +
 207                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 208
 209         for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
 210                 WREG32_PCIE(addr_start, src[i]);
 211                 addr_start += 4;
 212         }
 213
 214         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 215                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 216         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 217                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 218
 219         for (i = 0; i < adev->usec_timeout; i++) {
 220                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 221                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 222                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 223                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 224                         break;
 225                 udelay(1);
 226         }
 227
 228         if (i == adev->usec_timeout)
 229                 return -ETIME;
 230
 231         return 0;
 232 }
 233
 234 static int smu_v11_0_check_fw_status(struct smu_context *smu)
 235 {
 236         struct amdgpu_device *adev = smu->adev;
 237         uint32_t mp1_fw_flags;
 238
 239         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 240                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 241
 242         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 243             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 244                 return 0;
 245
 246         return -EIO;
 247 }
 248
 249 static int smu_v11_0_check_fw_version(struct smu_context *smu)
 250 {
 251         uint32_t if_version = 0xff, smu_version = 0xff;
 252         uint16_t smu_major;
 253         uint8_t smu_minor, smu_debug;
 254         int ret = 0;
 255
 256         ret = smu_get_smc_version(smu, &if_version, &smu_version);
 257         if (ret)
 258                 return ret;
 259
 260         smu_major = (smu_version >> 16) & 0xffff;
 261         smu_minor = (smu_version >> 8) & 0xff;
 262         smu_debug = (smu_version >> 0) & 0xff;
 263
 264         /*
 265          * 1. if_version mismatch is not critical as our fw is designed
 266          * to be backward compatible.
 267          * 2. New fw usually brings some optimizations. But that's visible
 268          * only on the paired driver.
 269          * Considering above, we just leave user a warning message instead
 270          * of halt driver loading.
 271          */
 272         if (if_version != smu->smc_if_version) {
 273                 pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 274                         "smu fw version = 0x%08x (%d.%d.%d)\n",
 275                         smu->smc_if_version, if_version,
 276                         smu_version, smu_major, smu_minor, smu_debug);
 277                 pr_warn("SMU driver if version not matched\n");
 278         }
 279
 280         return ret;
 281 }
 282
 283 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 284 {
 285         struct amdgpu_device *adev = smu->adev;
 286         uint32_t ppt_offset_bytes;
 287         const struct smc_firmware_header_v2_0 *v2;
 288
 289         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 290
 291         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 292         *size = le32_to_cpu(v2->ppt_size_bytes);
 293         *table = (uint8_t *)v2 + ppt_offset_bytes;
 294
 295         return 0;
 296 }
 297
 298 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table, uint32_t *size, uint32_t pptable_id)
 299 {
 300         struct amdgpu_device *adev = smu->adev;
 301         const struct smc_firmware_header_v2_1 *v2_1;
 302         struct smc_soft_pptable_entry *entries;
 303         uint32_t pptable_count = 0;
 304         int i = 0;
 305
 306         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 307         entries = (struct smc_soft_pptable_entry *)
 308                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 309         pptable_count = le32_to_cpu(v2_1->pptable_count);
 310         for (i = 0; i < pptable_count; i++) {
 311                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 312                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 313                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 314                         break;
 315                 }
 316         }
 317
 318         if (i == pptable_count)
 319                 return -EINVAL;
 320
 321         return 0;
 322 }
 323
 324 static int smu_v11_0_setup_pptable(struct smu_context *smu)
 325 {
 326         struct amdgpu_device *adev = smu->adev;
 327         const struct smc_firmware_header_v1_0 *hdr;
 328         int ret, index;
 329         uint32_t size = 0;
 330         uint16_t atom_table_size;
 331         uint8_t frev, crev;
 332         void *table;
 333         uint16_t version_major, version_minor;
 334
 335         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 336         version_major = le16_to_cpu(hdr->header.header_version_major);
 337         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 338         if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 339                 switch (version_minor) {
 340                 case 0:
 341                         ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 342                         break;
 343                 case 1:
 344                         ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 345                                                          smu->smu_table.boot_values.pp_table_id);
 346                         break;
 347                 default:
 348                         ret = -EINVAL;
 349                         break;
 350                 }
 351                 if (ret)
 352                         return ret;
 353
 354         } else {
 355                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 356                                                     powerplayinfo);
 357
 358                 ret = smu_get_atom_data_table(smu, index, &atom_table_size, &frev, &crev,
 359                                               (uint8_t **)&table);
 360                 if (ret)
 361                         return ret;
 362                 size = atom_table_size;
 363         }
 364
 365         if (!smu->smu_table.power_play_table)
 366                 smu->smu_table.power_play_table = table;
 367         if (!smu->smu_table.power_play_table_size)
 368                 smu->smu_table.power_play_table_size = size;
 369
 370         return 0;
 371 }
 372
 373 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
 374 {
 375         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 376
 377         if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
 378                 return -EINVAL;
 379
 380         return smu_alloc_dpm_context(smu);
 381 }
 382
 383 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
 384 {
 385         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 386
 387         if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
 388                 return -EINVAL;
 389
 390         kfree(smu_dpm->dpm_context);
 391         kfree(smu_dpm->golden_dpm_context);
 392         kfree(smu_dpm->dpm_current_power_state);
 393         kfree(smu_dpm->dpm_request_power_state);
 394         smu_dpm->dpm_context = NULL;
 395         smu_dpm->golden_dpm_context = NULL;
 396         smu_dpm->dpm_context_size = 0;
 397         smu_dpm->dpm_current_power_state = NULL;
 398         smu_dpm->dpm_request_power_state = NULL;
 399
 400         return 0;
 401 }
 402
 403 static int smu_v11_0_init_smc_tables(struct smu_context *smu)
 404 {
 405         struct smu_table_context *smu_table = &smu->smu_table;
 406         struct smu_table *tables = NULL;
 407         int ret = 0;
 408
 409         if (smu_table->tables || smu_table->table_count == 0)
 410                 return -EINVAL;
 411
 412         tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
 413                          GFP_KERNEL);
 414         if (!tables)
 415                 return -ENOMEM;
 416
 417         smu_table->tables = tables;
 418
 419         ret = smu_tables_init(smu, tables);
 420         if (ret)
 421                 return ret;
 422
 423         ret = smu_v11_0_init_dpm_context(smu);
 424         if (ret)
 425                 return ret;
 426
 427         return 0;
 428 }
 429
 430 static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 431 {
 432         struct smu_table_context *smu_table = &smu->smu_table;
 433         int ret = 0;
 434
 435         if (!smu_table->tables || smu_table->table_count == 0)
 436                 return -EINVAL;
 437
 438         kfree(smu_table->tables);
 439         kfree(smu_table->metrics_table);
 440         smu_table->tables = NULL;
 441         smu_table->table_count = 0;
 442         smu_table->metrics_table = NULL;
 443         smu_table->metrics_time = 0;
 444
 445         ret = smu_v11_0_fini_dpm_context(smu);
 446         if (ret)
 447                 return ret;
 448         return 0;
 449 }
 450
 451 static int smu_v11_0_init_power(struct smu_context *smu)
 452 {
 453         struct smu_power_context *smu_power = &smu->smu_power;
 454
 455         if (!smu->pm_enabled)
 456                 return 0;
 457         if (smu_power->power_context || smu_power->power_context_size != 0)
 458                 return -EINVAL;
 459
 460         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 461                                            GFP_KERNEL);
 462         if (!smu_power->power_context)
 463                 return -ENOMEM;
 464         smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
 465
 466         return 0;
 467 }
 468
 469 static int smu_v11_0_fini_power(struct smu_context *smu)
 470 {
 471         struct smu_power_context *smu_power = &smu->smu_power;
 472
 473         if (!smu->pm_enabled)
 474                 return 0;
 475         if (!smu_power->power_context || smu_power->power_context_size == 0)
 476                 return -EINVAL;
 477
 478         kfree(smu_power->power_context);
 479         smu_power->power_context = NULL;
 480         smu_power->power_context_size = 0;
 481
 482         return 0;
 483 }
 484
 485 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 486 {
 487         int ret, index;
 488         uint16_t size;
 489         uint8_t frev, crev;
 490         struct atom_common_table_header *header;
 491         struct atom_firmware_info_v3_3 *v_3_3;
 492         struct atom_firmware_info_v3_1 *v_3_1;
 493
 494         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 495                                             firmwareinfo);
 496
 497         ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
 498                                       (uint8_t **)&header);
 499         if (ret)
 500                 return ret;
 501
 502         if (header->format_revision != 3) {
 503                 pr_err("unknown atom_firmware_info version! for smu11\n");
 504                 return -EINVAL;
 505         }
 506
 507         switch (header->content_revision) {
 508         case 0:
 509         case 1:
 510         case 2:
 511                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 512                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 513                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 514                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 515                 smu->smu_table.boot_values.socclk = 0;
 516                 smu->smu_table.boot_values.dcefclk = 0;
 517                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 518                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 519                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 520                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 521                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 522                 smu->smu_table.boot_values.pp_table_id = 0;
 523                 break;
 524         case 3:
 525         default:
 526                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 527                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 528                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 529                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 530                 smu->smu_table.boot_values.socclk = 0;
 531                 smu->smu_table.boot_values.dcefclk = 0;
 532                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 533                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 534                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 535                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 536                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 537                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 538         }
 539
 540         return 0;
 541 }
 542
 543 static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
 544 {
 545         int ret, index;
 546         struct amdgpu_device *adev = smu->adev;
 547         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 548         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 549
 550         input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
 551         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 552         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 553                                             getsmuclockinfo);
 554
 555         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 556                                         (uint32_t *)&input);
 557         if (ret)
 558                 return -EINVAL;
 559
 560         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 561         smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 562
 563         memset(&input, 0, sizeof(input));
 564         input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
 565         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 566         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 567                                             getsmuclockinfo);
 568
 569         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 570                                         (uint32_t *)&input);
 571         if (ret)
 572                 return -EINVAL;
 573
 574         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 575         smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 576
 577         memset(&input, 0, sizeof(input));
 578         input.clk_id = SMU11_SYSPLL0_ECLK_ID;
 579         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 580         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 581                                             getsmuclockinfo);
 582
 583         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 584                                         (uint32_t *)&input);
 585         if (ret)
 586                 return -EINVAL;
 587
 588         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 589         smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 590
 591         memset(&input, 0, sizeof(input));
 592         input.clk_id = SMU11_SYSPLL0_VCLK_ID;
 593         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 594         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 595                                             getsmuclockinfo);
 596
 597         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 598                                         (uint32_t *)&input);
 599         if (ret)
 600                 return -EINVAL;
 601
 602         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 603         smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 604
 605         memset(&input, 0, sizeof(input));
 606         input.clk_id = SMU11_SYSPLL0_DCLK_ID;
 607         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 608         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 609                                             getsmuclockinfo);
 610
 611         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 612                                         (uint32_t *)&input);
 613         if (ret)
 614                 return -EINVAL;
 615
 616         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 617         smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 618
 619         return 0;
 620 }
 621
 622 static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 623 {
 624         struct smu_table_context *smu_table = &smu->smu_table;
 625         struct smu_table *memory_pool = &smu_table->memory_pool;
 626         int ret = 0;
 627         uint64_t address;
 628         uint32_t address_low, address_high;
 629
 630         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 631                 return ret;
 632
 633         address = (uintptr_t)memory_pool->cpu_addr;
 634         address_high = (uint32_t)upper_32_bits(address);
 635         address_low  = (uint32_t)lower_32_bits(address);
 636
 637         ret = smu_send_smc_msg_with_param(smu,
 638                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 639                                           address_high);
 640         if (ret)
 641                 return ret;
 642         ret = smu_send_smc_msg_with_param(smu,
 643                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 644                                           address_low);
 645         if (ret)
 646                 return ret;
 647
 648         address = memory_pool->mc_address;
 649         address_high = (uint32_t)upper_32_bits(address);
 650         address_low  = (uint32_t)lower_32_bits(address);
 651
 652         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 653                                           address_high);
 654         if (ret)
 655                 return ret;
 656         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 657                                           address_low);
 658         if (ret)
 659                 return ret;
 660         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 661                                           (uint32_t)memory_pool->size);
 662         if (ret)
 663                 return ret;
 664
 665         return ret;
 666 }
 667
 668 static int smu_v11_0_check_pptable(struct smu_context *smu)
 669 {
 670         int ret;
 671
 672         ret = smu_check_powerplay_table(smu);
 673         return ret;
 674 }
 675
 676 static int smu_v11_0_parse_pptable(struct smu_context *smu)
 677 {
 678         int ret;
 679
 680         struct smu_table_context *table_context = &smu->smu_table;
 681         struct smu_table *table = &table_context->tables[SMU_TABLE_PPTABLE];
 682
 683         if (table_context->driver_pptable)
 684                 return -EINVAL;
 685
 686         table_context->driver_pptable = kzalloc(table->size, GFP_KERNEL);
 687
 688         if (!table_context->driver_pptable)
 689                 return -ENOMEM;
 690
 691         ret = smu_store_powerplay_table(smu);
 692         if (ret)
 693                 return -EINVAL;
 694
 695         ret = smu_append_powerplay_table(smu);
 696
 697         return ret;
 698 }
 699
 700 static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
 701 {
 702         int ret;
 703
 704         ret = smu_set_default_dpm_table(smu);
 705
 706         return ret;
 707 }
 708
 709 static int smu_v11_0_write_pptable(struct smu_context *smu)
 710 {
 711         struct smu_table_context *table_context = &smu->smu_table;
 712         int ret = 0;
 713
 714         ret = smu_update_table(smu, SMU_TABLE_PPTABLE, 0,
 715                                table_context->driver_pptable, true);
 716
 717         return ret;
 718 }
 719
 720 static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
 721 {
 722         int ret = 0;
 723         struct smu_table_context *smu_table = &smu->smu_table;
 724         struct smu_table *table = NULL;
 725
 726         table = &smu_table->tables[SMU_TABLE_WATERMARKS];
 727         if (!table)
 728                 return -EINVAL;
 729
 730         if (!table->cpu_addr)
 731                 return -EINVAL;
 732
 733         ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
 734                                 true);
 735
 736         return ret;
 737 }
 738
 739 static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 740 {
 741         int ret;
 742
 743         ret = smu_send_smc_msg_with_param(smu,
 744                                           SMU_MSG_SetMinDeepSleepDcefclk, clk);
 745         if (ret)
 746                 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
 747
 748         return ret;
 749 }
 750
 751 static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
 752 {
 753         struct smu_table_context *table_context = &smu->smu_table;
 754
 755         if (!smu->pm_enabled)
 756                 return 0;
 757         if (!table_context)
 758                 return -EINVAL;
 759
 760         return smu_set_deep_sleep_dcefclk(smu,
 761                                           table_context->boot_values.dcefclk / 100);
 762 }
 763
 764 static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 765 {
 766         int ret = 0;
 767         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 768
 769         if (tool_table->mc_address) {
 770                 ret = smu_send_smc_msg_with_param(smu,
 771                                 SMU_MSG_SetToolsDramAddrHigh,
 772                                 upper_32_bits(tool_table->mc_address));
 773                 if (!ret)
 774                         ret = smu_send_smc_msg_with_param(smu,
 775                                 SMU_MSG_SetToolsDramAddrLow,
 776                                 lower_32_bits(tool_table->mc_address));
 777         }
 778
 779         return ret;
 780 }
 781
 782 static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 783 {
 784         int ret = 0;
 785
 786         if (!smu->pm_enabled)
 787                 return ret;
 788
 789         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count);
 790         return ret;
 791 }
 792
 793 static int smu_v11_0_update_feature_enable_state(struct smu_context *smu, uint32_t feature_id, bool enabled)
 794 {
 795         uint32_t feature_low = 0, feature_high = 0;
 796         int ret = 0;
 797
 798         if (!smu->pm_enabled)
 799                 return ret;
 800         if (feature_id >= 0 && feature_id < 31)
 801                 feature_low = (1 << feature_id);
 802         else if (feature_id > 31 && feature_id < 63)
 803                 feature_high = (1 << feature_id);
 804         else
 805                 return -EINVAL;
 806
 807         if (enabled) {
 808                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
 809                                                   feature_low);
 810                 if (ret)
 811                         return ret;
 812                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
 813                                                   feature_high);
 814                 if (ret)
 815                         return ret;
 816
 817         } else {
 818                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
 819                                                   feature_low);
 820                 if (ret)
 821                         return ret;
 822                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
 823                                                   feature_high);
 824                 if (ret)
 825                         return ret;
 826
 827         }
 828
 829         return ret;
 830 }
 831
 832 static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 833 {
 834         struct smu_feature *feature = &smu->smu_feature;
 835         int ret = 0;
 836         uint32_t feature_mask[2];
 837
 838         mutex_lock(&feature->mutex);
 839         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 840                 goto failed;
 841
 842         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 843
 844         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 845                                           feature_mask[1]);
 846         if (ret)
 847                 goto failed;
 848
 849         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 850                                           feature_mask[0]);
 851         if (ret)
 852                 goto failed;
 853
 854 failed:
 855         mutex_unlock(&feature->mutex);
 856         return ret;
 857 }
 858
 859 static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
 860                                       uint32_t *feature_mask, uint32_t num)
 861 {
 862         uint32_t feature_mask_high = 0, feature_mask_low = 0;
 863         int ret = 0;
 864
 865         if (!feature_mask || num < 2)
 866                 return -EINVAL;
 867
 868         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
 869         if (ret)
 870                 return ret;
 871         ret = smu_read_smc_arg(smu, &feature_mask_high);
 872         if (ret)
 873                 return ret;
 874
 875         ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
 876         if (ret)
 877                 return ret;
 878         ret = smu_read_smc_arg(smu, &feature_mask_low);
 879         if (ret)
 880                 return ret;
 881
 882         feature_mask[0] = feature_mask_low;
 883         feature_mask[1] = feature_mask_high;
 884
 885         return ret;
 886 }
 887
 888 static int smu_v11_0_system_features_control(struct smu_context *smu,
 889                                              bool en)
 890 {
 891         struct smu_feature *feature = &smu->smu_feature;
 892         uint32_t feature_mask[2];
 893         int ret = 0;
 894
 895         if (smu->pm_enabled) {
 896                 ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 897                                              SMU_MSG_DisableAllSmuFeatures));
 898                 if (ret)
 899                         return ret;
 900         }
 901
 902         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 903         if (ret)
 904                 return ret;
 905
 906         bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 907                     feature->feature_num);
 908         bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 909                     feature->feature_num);
 910
 911         return ret;
 912 }
 913
 914 static int smu_v11_0_notify_display_change(struct smu_context *smu)
 915 {
 916         int ret = 0;
 917
 918         if (!smu->pm_enabled)
 919                 return ret;
 920         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 921             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 922                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
 923
 924         return ret;
 925 }
 926
 927 static int
 928 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 929                                     enum smu_clk_type clock_select)
 930 {
 931         int ret = 0;
 932
 933         if (!smu->pm_enabled)
 934                 return ret;
 935         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 936                                           smu_clk_get_index(smu, clock_select) << 16);
 937         if (ret) {
 938                 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 939                 return ret;
 940         }
 941
 942         ret = smu_read_smc_arg(smu, clock);
 943         if (ret)
 944                 return ret;
 945
 946         if (*clock != 0)
 947                 return 0;
 948
 949         /* if DC limit is zero, return AC limit */
 950         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 951                                           smu_clk_get_index(smu, clock_select) << 16);
 952         if (ret) {
 953                 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 954                 return ret;
 955         }
 956
 957         ret = smu_read_smc_arg(smu, clock);
 958
 959         return ret;
 960 }
 961
 962 static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 963 {
 964         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
 965         int ret = 0;
 966
 967         max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
 968                                          GFP_KERNEL);
 969         smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
 970
 971         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 972         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 973         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 974         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 975         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 976         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 977
 978         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 979                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 980                                                           &(max_sustainable_clocks->uclock),
 981                                                           SMU_UCLK);
 982                 if (ret) {
 983                         pr_err("[%s] failed to get max UCLK from SMC!",
 984                                __func__);
 985                         return ret;
 986                 }
 987         }
 988
 989         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 990                 ret = smu_v11_0_get_max_sustainable_clock(smu,
 991                                                           &(max_sustainable_clocks->soc_clock),
 992                                                           SMU_SOCCLK);
 993                 if (ret) {
 994                         pr_err("[%s] failed to get max SOCCLK from SMC!",
 995                                __func__);
 996                         return ret;
 997                 }
 998         }
 999
1000         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1001                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1002                                                           &(max_sustainable_clocks->dcef_clock),
1003                                                           SMU_DCEFCLK);
1004                 if (ret) {
1005                         pr_err("[%s] failed to get max DCEFCLK from SMC!",
1006                                __func__);
1007                         return ret;
1008                 }
1009
1010                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1011                                                           &(max_sustainable_clocks->display_clock),
1012                                                           SMU_DISPCLK);
1013                 if (ret) {
1014                         pr_err("[%s] failed to get max DISPCLK from SMC!",
1015                                __func__);
1016                         return ret;
1017                 }
1018                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1019                                                           &(max_sustainable_clocks->phy_clock),
1020                                                           SMU_PHYCLK);
1021                 if (ret) {
1022                         pr_err("[%s] failed to get max PHYCLK from SMC!",
1023                                __func__);
1024                         return ret;
1025                 }
1026                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1027                                                           &(max_sustainable_clocks->pixel_clock),
1028                                                           SMU_PIXCLK);
1029                 if (ret) {
1030                         pr_err("[%s] failed to get max PIXCLK from SMC!",
1031                                __func__);
1032                         return ret;
1033                 }
1034         }
1035
1036         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1037                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1038
1039         return 0;
1040 }
1041
1042 static int smu_v11_0_get_power_limit(struct smu_context *smu,
1043                                      uint32_t *limit,
1044                                      bool get_default)
1045 {
1046         int ret = 0;
1047
1048         if (get_default) {
1049                 mutex_lock(&smu->mutex);
1050                 *limit = smu->default_power_limit;
1051                 if (smu->od_enabled) {
1052                         *limit *= (100 + smu->smu_table.TDPODLimit);
1053                         *limit /= 100;
1054                 }
1055                 mutex_unlock(&smu->mutex);
1056         } else {
1057                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1058                         smu_power_get_index(smu, SMU_POWER_SOURCE_AC) << 16);
1059                 if (ret) {
1060                         pr_err("[%s] get PPT limit failed!", __func__);
1061                         return ret;
1062                 }
1063                 smu_read_smc_arg(smu, limit);
1064                 smu->power_limit = *limit;
1065         }
1066
1067         return ret;
1068 }
1069
1070 static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1071 {
1072         uint32_t max_power_limit;
1073         int ret = 0;
1074
1075         if (n == 0)
1076                 n = smu->default_power_limit;
1077
1078         max_power_limit = smu->default_power_limit;
1079
1080         if (smu->od_enabled) {
1081                 max_power_limit *= (100 + smu->smu_table.TDPODLimit);
1082                 max_power_limit /= 100;
1083         }
1084
1085         if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1086                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
1087         if (ret) {
1088                 pr_err("[%s] Set power limit Failed!", __func__);
1089                 return ret;
1090         }
1091
1092         return ret;
1093 }
1094
1095 static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
1096                                           enum smu_clk_type clk_id,
1097                                           uint32_t *value)
1098 {
1099         int ret = 0;
1100         uint32_t freq = 0;
1101
1102         if (clk_id >= SMU_CLK_COUNT || !value)
1103                 return -EINVAL;
1104
1105         /* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */
1106         if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) == 0)
1107                 ret =  smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
1108         else {
1109                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
1110                                                   (smu_clk_get_index(smu, clk_id) << 16));
1111                 if (ret)
1112                         return ret;
1113
1114                 ret = smu_read_smc_arg(smu, &freq);
1115                 if (ret)
1116                         return ret;
1117         }
1118
1119         freq *= 100;
1120         *value = freq;
1121
1122         return ret;
1123 }
1124
1125 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1126                                        struct smu_temperature_range *range)
1127 {
1128         struct amdgpu_device *adev = smu->adev;
1129         int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
1130         int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
1131         uint32_t val;
1132
1133         if (!range)
1134                 return -EINVAL;
1135
1136         if (low < range->min)
1137                 low = range->min;
1138         if (high > range->max)
1139                 high = range->max;
1140
1141         low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, range->min);
1142         high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, range->max);
1143
1144         if (low > high)
1145                 return -EINVAL;
1146
1147         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1148         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1149         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1150         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1151         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1152         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1153         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1154         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1155
1156         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1157
1158         return 0;
1159 }
1160
1161 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1162 {
1163         struct amdgpu_device *adev = smu->adev;
1164         uint32_t val = 0;
1165
1166         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1167         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1168         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1169
1170         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1171
1172         return 0;
1173 }
1174
1175 static int smu_v11_0_start_thermal_control(struct smu_context *smu)
1176 {
1177         int ret = 0;
1178         struct smu_temperature_range range = {
1179                 TEMP_RANGE_MIN,
1180                 TEMP_RANGE_MAX,
1181                 TEMP_RANGE_MAX,
1182                 TEMP_RANGE_MIN,
1183                 TEMP_RANGE_MAX,
1184                 TEMP_RANGE_MAX,
1185                 TEMP_RANGE_MIN,
1186                 TEMP_RANGE_MAX,
1187                 TEMP_RANGE_MAX};
1188         struct amdgpu_device *adev = smu->adev;
1189
1190         if (!smu->pm_enabled)
1191                 return ret;
1192
1193         ret = smu_get_thermal_temperature_range(smu, &range);
1194         if (ret)
1195                 return ret;
1196
1197         if (smu->smu_table.thermal_controller_type) {
1198                 ret = smu_v11_0_set_thermal_range(smu, &range);
1199                 if (ret)
1200                         return ret;
1201
1202                 ret = smu_v11_0_enable_thermal_alert(smu);
1203                 if (ret)
1204                         return ret;
1205
1206                 ret = smu_set_thermal_fan_table(smu);
1207                 if (ret)
1208                         return ret;
1209         }
1210
1211         adev->pm.dpm.thermal.min_temp = range.min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1212         adev->pm.dpm.thermal.max_temp = range.max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1213         adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1214         adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1215         adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1216         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1217         adev->pm.dpm.thermal.min_mem_temp = range.mem_min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1218         adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1219         adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1220         adev->pm.dpm.thermal.min_temp = range.min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1221         adev->pm.dpm.thermal.max_temp = range.max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1222
1223         return ret;
1224 }
1225
1226 static uint16_t convert_to_vddc(uint8_t vid)
1227 {
1228         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1229 }
1230
1231 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1232 {
1233         struct amdgpu_device *adev = smu->adev;
1234         uint32_t vdd = 0, val_vid = 0;
1235
1236         if (!value)
1237                 return -EINVAL;
1238         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1239                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1240                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1241
1242         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1243
1244         *value = vdd;
1245
1246         return 0;
1247
1248 }
1249
1250 static int smu_v11_0_read_sensor(struct smu_context *smu,
1251                                  enum amd_pp_sensors sensor,
1252                                  void *data, uint32_t *size)
1253 {
1254         int ret = 0;
1255         switch (sensor) {
1256         case AMDGPU_PP_SENSOR_GFX_MCLK:
1257                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1258                 *size = 4;
1259                 break;
1260         case AMDGPU_PP_SENSOR_GFX_SCLK:
1261                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1262                 *size = 4;
1263                 break;
1264         case AMDGPU_PP_SENSOR_VDDGFX:
1265                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1266                 *size = 4;
1267                 break;
1268         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1269                 *(uint32_t *)data = 0;
1270                 *size = 4;
1271                 break;
1272         default:
1273                 ret = smu_common_read_sensor(smu, sensor, data, size);
1274                 break;
1275         }
1276
1277         /* try get sensor data by asic */
1278         if (ret)
1279                 ret = smu_asic_read_sensor(smu, sensor, data, size);
1280
1281         if (ret)
1282                 *size = 0;
1283
1284         return ret;
1285 }
1286
1287 static int
1288 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1289                                         struct pp_display_clock_request
1290                                         *clock_req)
1291 {
1292         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1293         int ret = 0;
1294         enum smu_clk_type clk_select = 0;
1295         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1296
1297         if (!smu->pm_enabled)
1298                 return -EINVAL;
1299
1300         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1301                 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1302                 switch (clk_type) {
1303                 case amd_pp_dcef_clock:
1304                         clk_select = SMU_DCEFCLK;
1305                         break;
1306                 case amd_pp_disp_clock:
1307                         clk_select = SMU_DISPCLK;
1308                         break;
1309                 case amd_pp_pixel_clock:
1310                         clk_select = SMU_PIXCLK;
1311                         break;
1312                 case amd_pp_phy_clock:
1313                         clk_select = SMU_PHYCLK;
1314                         break;
1315                 case amd_pp_mem_clock:
1316                         clk_select = SMU_UCLK;
1317                         break;
1318                 default:
1319                         pr_info("[%s] Invalid Clock Type!", __func__);
1320                         ret = -EINVAL;
1321                         break;
1322                 }
1323
1324                 if (ret)
1325                         goto failed;
1326
1327                 mutex_lock(&smu->mutex);
1328                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1329                         (smu_clk_get_index(smu, clk_select) << 16) | clk_freq);
1330                 mutex_unlock(&smu->mutex);
1331         }
1332
1333 failed:
1334         return ret;
1335 }
1336
1337 static int
1338 smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
1339                                           dm_pp_wm_sets_with_clock_ranges_soc15
1340                                           *clock_ranges)
1341 {
1342         int ret = 0;
1343         struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
1344         void *table = watermarks->cpu_addr;
1345
1346         if (!smu->disable_watermark &&
1347             smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1348             smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1349                 smu_set_watermarks_table(smu, table, clock_ranges);
1350                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1351                 smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1352         }
1353
1354         return ret;
1355 }
1356
1357 static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1358 {
1359         int ret = 0;
1360         struct amdgpu_device *adev = smu->adev;
1361
1362         switch (adev->asic_type) {
1363         case CHIP_VEGA20:
1364                 break;
1365         case CHIP_NAVI10:
1366                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1367                         return 0;
1368                 mutex_lock(&smu->mutex);
1369                 if (enable)
1370                         ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
1371                 else
1372                         ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
1373                 mutex_unlock(&smu->mutex);
1374                 break;
1375         default:
1376                 break;
1377         }
1378
1379         return ret;
1380 }
1381
1382 static uint32_t
1383 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1384 {
1385         if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1386                 return AMD_FAN_CTRL_MANUAL;
1387         else
1388                 return AMD_FAN_CTRL_AUTO;
1389 }
1390
1391 static int
1392 smu_v11_0_smc_fan_control(struct smu_context *smu, bool start)
1393 {
1394         int ret = 0;
1395
1396         if (!smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1397                 return 0;
1398
1399         ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, start);
1400         if (ret)
1401                 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1402                        __func__, (start ? "Start" : "Stop"));
1403
1404         return ret;
1405 }
1406
1407 static int
1408 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1409 {
1410         struct amdgpu_device *adev = smu->adev;
1411
1412         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1413                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1414                                    CG_FDO_CTRL2, TMIN, 0));
1415         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1416                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1417                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1418
1419         return 0;
1420 }
1421
1422 static int
1423 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1424 {
1425         struct amdgpu_device *adev = smu->adev;
1426         uint32_t duty100;
1427         uint32_t duty;
1428         uint64_t tmp64;
1429         bool stop = 0;
1430
1431         if (speed > 100)
1432                 speed = 100;
1433
1434         if (smu_v11_0_smc_fan_control(smu, stop))
1435                 return -EINVAL;
1436         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1437                                 CG_FDO_CTRL1, FMAX_DUTY100);
1438         if (!duty100)
1439                 return -EINVAL;
1440
1441         tmp64 = (uint64_t)speed * duty100;
1442         do_div(tmp64, 100);
1443         duty = (uint32_t)tmp64;
1444
1445         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1446                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1447                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1448
1449         return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1450 }
1451
1452 static int
1453 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1454                                uint32_t mode)
1455 {
1456         int ret = 0;
1457         bool start = 1;
1458         bool stop  = 0;
1459
1460         switch (mode) {
1461         case AMD_FAN_CTRL_NONE:
1462                 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1463                 break;
1464         case AMD_FAN_CTRL_MANUAL:
1465                 ret = smu_v11_0_smc_fan_control(smu, stop);
1466                 break;
1467         case AMD_FAN_CTRL_AUTO:
1468                 ret = smu_v11_0_smc_fan_control(smu, start);
1469                 break;
1470         default:
1471                 break;
1472         }
1473
1474         if (ret) {
1475                 pr_err("[%s]Set fan control mode failed!", __func__);
1476                 return -EINVAL;
1477         }
1478
1479         return ret;
1480 }
1481
1482 static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1483                                        uint32_t speed)
1484 {
1485         struct amdgpu_device *adev = smu->adev;
1486         int ret;
1487         uint32_t tach_period, crystal_clock_freq;
1488         bool stop = 0;
1489
1490         if (!speed)
1491                 return -EINVAL;
1492
1493         mutex_lock(&(smu->mutex));
1494         ret = smu_v11_0_smc_fan_control(smu, stop);
1495         if (ret)
1496                 goto set_fan_speed_rpm_failed;
1497
1498         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1499         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1500         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1501                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1502                                    CG_TACH_CTRL, TARGET_PERIOD,
1503                                    tach_period));
1504
1505         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1506
1507 set_fan_speed_rpm_failed:
1508         mutex_unlock(&(smu->mutex));
1509         return ret;
1510 }
1511
1512 #define XGMI_STATE_D0 1
1513 #define XGMI_STATE_D3 0
1514
1515 static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1516                                      uint32_t pstate)
1517 {
1518         int ret = 0;
1519         mutex_lock(&(smu->mutex));
1520         ret = smu_send_smc_msg_with_param(smu,
1521                                           SMU_MSG_SetXgmiMode,
1522                                           pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
1523         mutex_unlock(&(smu->mutex));
1524         return ret;
1525 }
1526
1527 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1528 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1529
1530 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1531                                  struct amdgpu_irq_src *source,
1532                                  struct amdgpu_iv_entry *entry)
1533 {
1534         uint32_t client_id = entry->client_id;
1535         uint32_t src_id = entry->src_id;
1536
1537         if (client_id == SOC15_IH_CLIENTID_THM) {
1538                 switch (src_id) {
1539                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1540                         pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
1541                                 PCI_BUS_NUM(adev->pdev->devfn),
1542                                 PCI_SLOT(adev->pdev->devfn),
1543                                 PCI_FUNC(adev->pdev->devfn));
1544                 break;
1545                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1546                         pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
1547                                 PCI_BUS_NUM(adev->pdev->devfn),
1548                                 PCI_SLOT(adev->pdev->devfn),
1549                                 PCI_FUNC(adev->pdev->devfn));
1550                 break;
1551                 default:
1552                         pr_warn("GPU under temperature range unknown src id (%d), detected on PCIe %d:%d.%d!\n",
1553                                 src_id,
1554                                 PCI_BUS_NUM(adev->pdev->devfn),
1555                                 PCI_SLOT(adev->pdev->devfn),
1556                                 PCI_FUNC(adev->pdev->devfn));
1557                 break;
1558
1559                 }
1560         }
1561
1562         return 0;
1563 }
1564
1565 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1566 {
1567         .process = smu_v11_0_irq_process,
1568 };
1569
1570 static int smu_v11_0_register_irq_handler(struct smu_context *smu)
1571 {
1572         struct amdgpu_device *adev = smu->adev;
1573         struct amdgpu_irq_src *irq_src = smu->irq_source;
1574         int ret = 0;
1575
1576         /* already register */
1577         if (irq_src)
1578                 return 0;
1579
1580         irq_src = kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
1581         if (!irq_src)
1582                 return -ENOMEM;
1583         smu->irq_source = irq_src;
1584
1585         irq_src->funcs = &smu_v11_0_irq_funcs;
1586
1587         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1588                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1589                                 irq_src);
1590         if (ret)
1591                 return ret;
1592
1593         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1594                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1595                                 irq_src);
1596         if (ret)
1597                 return ret;
1598
1599         return ret;
1600 }
1601
1602 static int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1603                 struct pp_smu_nv_clock_table *max_clocks)
1604 {
1605         struct smu_table_context *table_context = &smu->smu_table;
1606         struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1607
1608         if (!max_clocks || !table_context->max_sustainable_clocks)
1609                 return -EINVAL;
1610
1611         sustainable_clocks = table_context->max_sustainable_clocks;
1612
1613         max_clocks->dcfClockInKhz =
1614                         (unsigned int) sustainable_clocks->dcef_clock * 1000;
1615         max_clocks->displayClockInKhz =
1616                         (unsigned int) sustainable_clocks->display_clock * 1000;
1617         max_clocks->phyClockInKhz =
1618                         (unsigned int) sustainable_clocks->phy_clock * 1000;
1619         max_clocks->pixelClockInKhz =
1620                         (unsigned int) sustainable_clocks->pixel_clock * 1000;
1621         max_clocks->uClockInKhz =
1622                         (unsigned int) sustainable_clocks->uclock * 1000;
1623         max_clocks->socClockInKhz =
1624                         (unsigned int) sustainable_clocks->soc_clock * 1000;
1625         max_clocks->dscClockInKhz = 0;
1626         max_clocks->dppClockInKhz = 0;
1627         max_clocks->fabricClockInKhz = 0;
1628
1629         return 0;
1630 }
1631
1632 static int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1633 {
1634         int ret = 0;
1635
1636         mutex_lock(&smu->mutex);
1637         ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME);
1638         mutex_unlock(&smu->mutex);
1639
1640         return ret;
1641 }
1642
1643 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1644 {
1645         return smu_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq);
1646 }
1647
1648 static bool smu_v11_0_baco_is_support(struct smu_context *smu)
1649 {
1650         struct amdgpu_device *adev = smu->adev;
1651         struct smu_baco_context *smu_baco = &smu->smu_baco;
1652         uint32_t val;
1653         bool baco_support;
1654
1655         mutex_lock(&smu_baco->mutex);
1656         baco_support = smu_baco->platform_support;
1657         mutex_unlock(&smu_baco->mutex);
1658
1659         if (!baco_support)
1660                 return false;
1661
1662         if (!smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1663                 return false;
1664
1665         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1666         if (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
1667                 return true;
1668
1669         return false;
1670 }
1671
1672 static enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1673 {
1674         struct smu_baco_context *smu_baco = &smu->smu_baco;
1675         enum smu_baco_state baco_state = SMU_BACO_STATE_EXIT;
1676
1677         mutex_lock(&smu_baco->mutex);
1678         baco_state = smu_baco->state;
1679         mutex_unlock(&smu_baco->mutex);
1680
1681         return baco_state;
1682 }
1683
1684 static int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1685 {
1686
1687         struct smu_baco_context *smu_baco = &smu->smu_baco;
1688         int ret = 0;
1689
1690         if (smu_v11_0_baco_get_state(smu) == state)
1691                 return 0;
1692
1693         mutex_lock(&smu_baco->mutex);
1694
1695         if (state == SMU_BACO_STATE_ENTER)
1696                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, BACO_SEQ_BACO);
1697         else
1698                 ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco);
1699         if (ret)
1700                 goto out;
1701
1702         smu_baco->state = state;
1703 out:
1704         mutex_unlock(&smu_baco->mutex);
1705         return ret;
1706 }
1707
1708 static int smu_v11_0_baco_reset(struct smu_context *smu)
1709 {
1710         int ret = 0;
1711
1712         ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1713         if (ret)
1714                 return ret;
1715
1716         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1717         if (ret)
1718                 return ret;
1719
1720         msleep(10);
1721
1722         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1723         if (ret)
1724                 return ret;
1725
1726         return ret;
1727 }
1728
1729 static const struct smu_funcs smu_v11_0_funcs = {
1730         .init_microcode = smu_v11_0_init_microcode,
1731         .load_microcode = smu_v11_0_load_microcode,
1732         .check_fw_status = smu_v11_0_check_fw_status,
1733         .check_fw_version = smu_v11_0_check_fw_version,
1734         .send_smc_msg = smu_v11_0_send_msg,
1735         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
1736         .read_smc_arg = smu_v11_0_read_arg,
1737         .setup_pptable = smu_v11_0_setup_pptable,
1738         .init_smc_tables = smu_v11_0_init_smc_tables,
1739         .fini_smc_tables = smu_v11_0_fini_smc_tables,
1740         .init_power = smu_v11_0_init_power,
1741         .fini_power = smu_v11_0_fini_power,
1742         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
1743         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
1744         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
1745         .check_pptable = smu_v11_0_check_pptable,
1746         .parse_pptable = smu_v11_0_parse_pptable,
1747         .populate_smc_pptable = smu_v11_0_populate_smc_pptable,
1748         .write_pptable = smu_v11_0_write_pptable,
1749         .write_watermarks_table = smu_v11_0_write_watermarks_table,
1750         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
1751         .set_tool_table_location = smu_v11_0_set_tool_table_location,
1752         .init_display_count = smu_v11_0_init_display_count,
1753         .set_allowed_mask = smu_v11_0_set_allowed_mask,
1754         .get_enabled_mask = smu_v11_0_get_enabled_mask,
1755         .system_features_control = smu_v11_0_system_features_control,
1756         .update_feature_enable_state = smu_v11_0_update_feature_enable_state,
1757         .notify_display_change = smu_v11_0_notify_display_change,
1758         .get_power_limit = smu_v11_0_get_power_limit,
1759         .set_power_limit = smu_v11_0_set_power_limit,
1760         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
1761         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
1762         .start_thermal_control = smu_v11_0_start_thermal_control,
1763         .read_sensor = smu_v11_0_read_sensor,
1764         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
1765         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
1766         .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
1767         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
1768         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
1769         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
1770         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
1771         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
1772         .gfx_off_control = smu_v11_0_gfx_off_control,
1773         .register_irq_handler = smu_v11_0_register_irq_handler,
1774         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
1775         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
1776         .baco_is_support = smu_v11_0_baco_is_support,
1777         .baco_get_state = smu_v11_0_baco_get_state,
1778         .baco_set_state = smu_v11_0_baco_set_state,
1779         .baco_reset = smu_v11_0_baco_reset,
1780 };
1781
1782 void smu_v11_0_set_smu_funcs(struct smu_context *smu)
1783 {
1784         struct amdgpu_device *adev = smu->adev;
1785
1786         smu->funcs = &smu_v11_0_funcs;
1787         switch (adev->asic_type) {
1788         case CHIP_VEGA20:
1789                 vega20_set_ppt_funcs(smu);
1790                 break;
1791         case CHIP_NAVI10:
1792                 navi10_set_ppt_funcs(smu);
1793                 break;
1794         default:
1795                 pr_warn("Unknown asic for smu11\n");
1796         }
1797 }