drivers/gpu/drm/amd/powerplay/smu_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26
  27 #define SMU_11_0_PARTIAL_PPTABLE
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_smu.h"
  31 #include "smu_internal.h"
  32 #include "atomfirmware.h"
  33 #include "amdgpu_atomfirmware.h"
  34 #include "smu_v11_0.h"
  35 #include "smu_v11_0_pptable.h"
  36 #include "soc15_common.h"
  37 #include "atom.h"
  38 #include "amd_pcie.h"
  39 #include "amdgpu_ras.h"
  40
  41 #include "asic_reg/thm/thm_11_0_2_offset.h"
  42 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
  43 #include "asic_reg/mp/mp_11_0_offset.h"
  44 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  45 #include "asic_reg/nbio/nbio_7_4_offset.h"
  46 #include "asic_reg/nbio/nbio_7_4_sh_mask.h"
  47 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
  48 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
  49
  50 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
  51 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
  52 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
  53 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
  54 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
  55
  56 #define SMU11_VOLTAGE_SCALE 4
  57
  58 static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
  59                                               uint16_t msg)
  60 {
  61         struct amdgpu_device *adev = smu->adev;
  62         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
  63         return 0;
  64 }
  65
  66 static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
  67 {
  68         struct amdgpu_device *adev = smu->adev;
  69
  70         *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
  71         return 0;
  72 }
  73
  74 static int smu_v11_0_wait_for_response(struct smu_context *smu)
  75 {
  76         struct amdgpu_device *adev = smu->adev;
  77         uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
  78
  79         for (i = 0; i < timeout; i++) {
  80                 cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  81                 if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
  82                         return cur_value == 0x1 ? 0 : -EIO;
  83
  84                 udelay(1);
  85         }
  86
  87         /* timeout means wrong logic */
  88         return -ETIME;
  89 }
  90
  91 int
  92 smu_v11_0_send_msg_with_param(struct smu_context *smu,
  93                               enum smu_message_type msg,
  94                               uint32_t param,
  95                               uint32_t *read_arg)
  96 {
  97         struct amdgpu_device *adev = smu->adev;
  98         int ret = 0, index = 0;
  99
 100         index = smu_msg_get_index(smu, msg);
 101         if (index < 0)
 102                 return index;
 103
 104         mutex_lock(&smu->message_lock);
 105         ret = smu_v11_0_wait_for_response(smu);
 106         if (ret) {
 107                 pr_err("Msg issuing pre-check failed and "
 108                        "SMU may be not in the right state!\n");
 109                 goto out;
 110         }
 111
 112         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 113
 114         WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
 115
 116         smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
 117
 118         ret = smu_v11_0_wait_for_response(smu);
 119         if (ret) {
 120                 pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
 121                        smu_get_message_name(smu, msg), index, param, ret);
 122                 goto out;
 123         }
 124         if (read_arg) {
 125                 ret = smu_v11_0_read_arg(smu, read_arg);
 126                 if (ret) {
 127                         pr_err("failed to read message arg: %10s (%d) \tparam: 0x%08x response %#x\n",
 128                                smu_get_message_name(smu, msg), index, param, ret);
 129                         goto out;
 130                 }
 131         }
 132 out:
 133         mutex_unlock(&smu->message_lock);
 134         return ret;
 135 }
 136
 137 int smu_v11_0_init_microcode(struct smu_context *smu)
 138 {
 139         struct amdgpu_device *adev = smu->adev;
 140         const char *chip_name;
 141         char fw_name[30];
 142         int err = 0;
 143         const struct smc_firmware_header_v1_0 *hdr;
 144         const struct common_firmware_header *header;
 145         struct amdgpu_firmware_info *ucode = NULL;
 146
 147         switch (adev->asic_type) {
 148         case CHIP_VEGA20:
 149                 chip_name = "vega20";
 150                 break;
 151         case CHIP_ARCTURUS:
 152                 chip_name = "arcturus";
 153                 break;
 154         case CHIP_NAVI10:
 155                 chip_name = "navi10";
 156                 break;
 157         case CHIP_NAVI14:
 158                 chip_name = "navi14";
 159                 break;
 160         case CHIP_NAVI12:
 161                 chip_name = "navi12";
 162                 break;
 163         default:
 164                 BUG();
 165         }
 166
 167         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
 168
 169         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 170         if (err)
 171                 goto out;
 172         err = amdgpu_ucode_validate(adev->pm.fw);
 173         if (err)
 174                 goto out;
 175
 176         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 177         amdgpu_ucode_print_smc_hdr(&hdr->header);
 178         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 179
 180         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 181                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 182                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 183                 ucode->fw = adev->pm.fw;
 184                 header = (const struct common_firmware_header *)ucode->fw->data;
 185                 adev->firmware.fw_size +=
 186                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 187         }
 188
 189 out:
 190         if (err) {
 191                 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
 192                           fw_name);
 193                 release_firmware(adev->pm.fw);
 194                 adev->pm.fw = NULL;
 195         }
 196         return err;
 197 }
 198
 199 int smu_v11_0_load_microcode(struct smu_context *smu)
 200 {
 201         struct amdgpu_device *adev = smu->adev;
 202         const uint32_t *src;
 203         const struct smc_firmware_header_v1_0 *hdr;
 204         uint32_t addr_start = MP1_SRAM;
 205         uint32_t i;
 206         uint32_t mp1_fw_flags;
 207
 208         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 209         src = (const uint32_t *)(adev->pm.fw->data +
 210                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 211
 212         for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
 213                 WREG32_PCIE(addr_start, src[i]);
 214                 addr_start += 4;
 215         }
 216
 217         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 218                 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 219         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 220                 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 221
 222         for (i = 0; i < adev->usec_timeout; i++) {
 223                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 224                         (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 225                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 226                         MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 227                         break;
 228                 udelay(1);
 229         }
 230
 231         if (i == adev->usec_timeout)
 232                 return -ETIME;
 233
 234         return 0;
 235 }
 236
 237 int smu_v11_0_check_fw_status(struct smu_context *smu)
 238 {
 239         struct amdgpu_device *adev = smu->adev;
 240         uint32_t mp1_fw_flags;
 241
 242         mp1_fw_flags = RREG32_PCIE(MP1_Public |
 243                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 244
 245         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 246             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 247                 return 0;
 248
 249         return -EIO;
 250 }
 251
 252 int smu_v11_0_check_fw_version(struct smu_context *smu)
 253 {
 254         uint32_t if_version = 0xff, smu_version = 0xff;
 255         uint16_t smu_major;
 256         uint8_t smu_minor, smu_debug;
 257         int ret = 0;
 258
 259         ret = smu_get_smc_version(smu, &if_version, &smu_version);
 260         if (ret)
 261                 return ret;
 262
 263         smu_major = (smu_version >> 16) & 0xffff;
 264         smu_minor = (smu_version >> 8) & 0xff;
 265         smu_debug = (smu_version >> 0) & 0xff;
 266
 267         switch (smu->adev->asic_type) {
 268         case CHIP_VEGA20:
 269                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_VG20;
 270                 break;
 271         case CHIP_ARCTURUS:
 272                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
 273                 break;
 274         case CHIP_NAVI10:
 275                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV10;
 276                 break;
 277         case CHIP_NAVI12:
 278                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV12;
 279                 break;
 280         case CHIP_NAVI14:
 281                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV14;
 282                 break;
 283         default:
 284                 pr_err("smu unsupported asic type:%d.\n", smu->adev->asic_type);
 285                 smu->smc_if_version = SMU11_DRIVER_IF_VERSION_INV;
 286                 break;
 287         }
 288
 289         /*
 290          * 1. if_version mismatch is not critical as our fw is designed
 291          * to be backward compatible.
 292          * 2. New fw usually brings some optimizations. But that's visible
 293          * only on the paired driver.
 294          * Considering above, we just leave user a warning message instead
 295          * of halt driver loading.
 296          */
 297         if (if_version != smu->smc_if_version) {
 298                 pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 299                         "smu fw version = 0x%08x (%d.%d.%d)\n",
 300                         smu->smc_if_version, if_version,
 301                         smu_version, smu_major, smu_minor, smu_debug);
 302                 pr_warn("SMU driver if version not matched\n");
 303         }
 304
 305         return ret;
 306 }
 307
 308 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 309 {
 310         struct amdgpu_device *adev = smu->adev;
 311         uint32_t ppt_offset_bytes;
 312         const struct smc_firmware_header_v2_0 *v2;
 313
 314         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 315
 316         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 317         *size = le32_to_cpu(v2->ppt_size_bytes);
 318         *table = (uint8_t *)v2 + ppt_offset_bytes;
 319
 320         return 0;
 321 }
 322
 323 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 324                                       uint32_t *size, uint32_t pptable_id)
 325 {
 326         struct amdgpu_device *adev = smu->adev;
 327         const struct smc_firmware_header_v2_1 *v2_1;
 328         struct smc_soft_pptable_entry *entries;
 329         uint32_t pptable_count = 0;
 330         int i = 0;
 331
 332         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 333         entries = (struct smc_soft_pptable_entry *)
 334                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 335         pptable_count = le32_to_cpu(v2_1->pptable_count);
 336         for (i = 0; i < pptable_count; i++) {
 337                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 338                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 339                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 340                         break;
 341                 }
 342         }
 343
 344         if (i == pptable_count)
 345                 return -EINVAL;
 346
 347         return 0;
 348 }
 349
 350 int smu_v11_0_setup_pptable(struct smu_context *smu)
 351 {
 352         struct amdgpu_device *adev = smu->adev;
 353         const struct smc_firmware_header_v1_0 *hdr;
 354         int ret, index;
 355         uint32_t size = 0;
 356         uint16_t atom_table_size;
 357         uint8_t frev, crev;
 358         void *table;
 359         uint16_t version_major, version_minor;
 360
 361         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 362         version_major = le16_to_cpu(hdr->header.header_version_major);
 363         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 364         if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
 365                 pr_info("use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
 366                 switch (version_minor) {
 367                 case 0:
 368                         ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
 369                         break;
 370                 case 1:
 371                         ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
 372                                                          smu->smu_table.boot_values.pp_table_id);
 373                         break;
 374                 default:
 375                         ret = -EINVAL;
 376                         break;
 377                 }
 378                 if (ret)
 379                         return ret;
 380
 381         } else {
 382                 pr_info("use vbios provided pptable\n");
 383                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 384                                                     powerplayinfo);
 385
 386                 ret = smu_get_atom_data_table(smu, index, &atom_table_size, &frev, &crev,
 387                                               (uint8_t **)&table);
 388                 if (ret)
 389                         return ret;
 390                 size = atom_table_size;
 391         }
 392
 393         if (!smu->smu_table.power_play_table)
 394                 smu->smu_table.power_play_table = table;
 395         if (!smu->smu_table.power_play_table_size)
 396                 smu->smu_table.power_play_table_size = size;
 397
 398         return 0;
 399 }
 400
 401 static int smu_v11_0_init_dpm_context(struct smu_context *smu)
 402 {
 403         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 404
 405         if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
 406                 return -EINVAL;
 407
 408         return smu_alloc_dpm_context(smu);
 409 }
 410
 411 static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
 412 {
 413         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 414
 415         if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
 416                 return -EINVAL;
 417
 418         kfree(smu_dpm->dpm_context);
 419         kfree(smu_dpm->golden_dpm_context);
 420         kfree(smu_dpm->dpm_current_power_state);
 421         kfree(smu_dpm->dpm_request_power_state);
 422         smu_dpm->dpm_context = NULL;
 423         smu_dpm->golden_dpm_context = NULL;
 424         smu_dpm->dpm_context_size = 0;
 425         smu_dpm->dpm_current_power_state = NULL;
 426         smu_dpm->dpm_request_power_state = NULL;
 427
 428         return 0;
 429 }
 430
 431 int smu_v11_0_init_smc_tables(struct smu_context *smu)
 432 {
 433         struct smu_table_context *smu_table = &smu->smu_table;
 434         struct smu_table *tables = NULL;
 435         int ret = 0;
 436
 437         if (smu_table->tables)
 438                 return -EINVAL;
 439
 440         tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
 441                          GFP_KERNEL);
 442         if (!tables)
 443                 return -ENOMEM;
 444
 445         smu_table->tables = tables;
 446
 447         ret = smu_tables_init(smu, tables);
 448         if (ret)
 449                 return ret;
 450
 451         ret = smu_v11_0_init_dpm_context(smu);
 452         if (ret)
 453                 return ret;
 454
 455         return 0;
 456 }
 457
 458 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
 459 {
 460         struct smu_table_context *smu_table = &smu->smu_table;
 461         int ret = 0;
 462
 463         if (!smu_table->tables)
 464                 return -EINVAL;
 465
 466         kfree(smu_table->tables);
 467         kfree(smu_table->metrics_table);
 468         kfree(smu_table->watermarks_table);
 469         smu_table->tables = NULL;
 470         smu_table->metrics_table = NULL;
 471         smu_table->watermarks_table = NULL;
 472         smu_table->metrics_time = 0;
 473
 474         ret = smu_v11_0_fini_dpm_context(smu);
 475         if (ret)
 476                 return ret;
 477         return 0;
 478 }
 479
 480 int smu_v11_0_init_power(struct smu_context *smu)
 481 {
 482         struct smu_power_context *smu_power = &smu->smu_power;
 483
 484         if (!smu->pm_enabled)
 485                 return 0;
 486         if (smu_power->power_context || smu_power->power_context_size != 0)
 487                 return -EINVAL;
 488
 489         smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 490                                            GFP_KERNEL);
 491         if (!smu_power->power_context)
 492                 return -ENOMEM;
 493         smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
 494
 495         return 0;
 496 }
 497
 498 int smu_v11_0_fini_power(struct smu_context *smu)
 499 {
 500         struct smu_power_context *smu_power = &smu->smu_power;
 501
 502         if (!smu->pm_enabled)
 503                 return 0;
 504         if (!smu_power->power_context || smu_power->power_context_size == 0)
 505                 return -EINVAL;
 506
 507         kfree(smu_power->power_context);
 508         smu_power->power_context = NULL;
 509         smu_power->power_context_size = 0;
 510
 511         return 0;
 512 }
 513
 514 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 515 {
 516         int ret, index;
 517         uint16_t size;
 518         uint8_t frev, crev;
 519         struct atom_common_table_header *header;
 520         struct atom_firmware_info_v3_3 *v_3_3;
 521         struct atom_firmware_info_v3_1 *v_3_1;
 522
 523         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 524                                             firmwareinfo);
 525
 526         ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
 527                                       (uint8_t **)&header);
 528         if (ret)
 529                 return ret;
 530
 531         if (header->format_revision != 3) {
 532                 pr_err("unknown atom_firmware_info version! for smu11\n");
 533                 return -EINVAL;
 534         }
 535
 536         switch (header->content_revision) {
 537         case 0:
 538         case 1:
 539         case 2:
 540                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 541                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 542                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 543                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 544                 smu->smu_table.boot_values.socclk = 0;
 545                 smu->smu_table.boot_values.dcefclk = 0;
 546                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 547                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 548                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 549                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 550                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 551                 smu->smu_table.boot_values.pp_table_id = 0;
 552                 break;
 553         case 3:
 554         default:
 555                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 556                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 557                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 558                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 559                 smu->smu_table.boot_values.socclk = 0;
 560                 smu->smu_table.boot_values.dcefclk = 0;
 561                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 562                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 563                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 564                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 565                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 566                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 567         }
 568
 569         smu->smu_table.boot_values.format_revision = header->format_revision;
 570         smu->smu_table.boot_values.content_revision = header->content_revision;
 571
 572         return 0;
 573 }
 574
 575 int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
 576 {
 577         int ret, index;
 578         struct amdgpu_device *adev = smu->adev;
 579         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 580         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 581
 582         input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
 583         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 584         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 585                                             getsmuclockinfo);
 586
 587         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 588                                         (uint32_t *)&input);
 589         if (ret)
 590                 return -EINVAL;
 591
 592         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 593         smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 594
 595         memset(&input, 0, sizeof(input));
 596         input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
 597         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 598         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 599                                             getsmuclockinfo);
 600
 601         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 602                                         (uint32_t *)&input);
 603         if (ret)
 604                 return -EINVAL;
 605
 606         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 607         smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 608
 609         memset(&input, 0, sizeof(input));
 610         input.clk_id = SMU11_SYSPLL0_ECLK_ID;
 611         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 612         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 613                                             getsmuclockinfo);
 614
 615         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 616                                         (uint32_t *)&input);
 617         if (ret)
 618                 return -EINVAL;
 619
 620         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 621         smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 622
 623         memset(&input, 0, sizeof(input));
 624         input.clk_id = SMU11_SYSPLL0_VCLK_ID;
 625         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 626         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 627                                             getsmuclockinfo);
 628
 629         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 630                                         (uint32_t *)&input);
 631         if (ret)
 632                 return -EINVAL;
 633
 634         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 635         smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 636
 637         memset(&input, 0, sizeof(input));
 638         input.clk_id = SMU11_SYSPLL0_DCLK_ID;
 639         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 640         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 641                                             getsmuclockinfo);
 642
 643         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 644                                         (uint32_t *)&input);
 645         if (ret)
 646                 return -EINVAL;
 647
 648         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 649         smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 650
 651         if ((smu->smu_table.boot_values.format_revision == 3) &&
 652             (smu->smu_table.boot_values.content_revision >= 2)) {
 653                 memset(&input, 0, sizeof(input));
 654                 input.clk_id = SMU11_SYSPLL1_0_FCLK_ID;
 655                 input.syspll_id = SMU11_SYSPLL1_2_ID;
 656                 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 657                 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 658                                                     getsmuclockinfo);
 659
 660                 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 661                                                 (uint32_t *)&input);
 662                 if (ret)
 663                         return -EINVAL;
 664
 665                 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 666                 smu->smu_table.boot_values.fclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 667         }
 668
 669         return 0;
 670 }
 671
 672 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
 673 {
 674         struct smu_table_context *smu_table = &smu->smu_table;
 675         struct smu_table *memory_pool = &smu_table->memory_pool;
 676         int ret = 0;
 677         uint64_t address;
 678         uint32_t address_low, address_high;
 679
 680         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 681                 return ret;
 682
 683         address = (uintptr_t)memory_pool->cpu_addr;
 684         address_high = (uint32_t)upper_32_bits(address);
 685         address_low  = (uint32_t)lower_32_bits(address);
 686
 687         ret = smu_send_smc_msg_with_param(smu,
 688                                           SMU_MSG_SetSystemVirtualDramAddrHigh,
 689                                           address_high,
 690                                           NULL);
 691         if (ret)
 692                 return ret;
 693         ret = smu_send_smc_msg_with_param(smu,
 694                                           SMU_MSG_SetSystemVirtualDramAddrLow,
 695                                           address_low,
 696                                           NULL);
 697         if (ret)
 698                 return ret;
 699
 700         address = memory_pool->mc_address;
 701         address_high = (uint32_t)upper_32_bits(address);
 702         address_low  = (uint32_t)lower_32_bits(address);
 703
 704         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 705                                           address_high, NULL);
 706         if (ret)
 707                 return ret;
 708         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 709                                           address_low, NULL);
 710         if (ret)
 711                 return ret;
 712         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 713                                           (uint32_t)memory_pool->size, NULL);
 714         if (ret)
 715                 return ret;
 716
 717         return ret;
 718 }
 719
 720 int smu_v11_0_check_pptable(struct smu_context *smu)
 721 {
 722         int ret;
 723
 724         ret = smu_check_powerplay_table(smu);
 725         return ret;
 726 }
 727
 728 int smu_v11_0_parse_pptable(struct smu_context *smu)
 729 {
 730         int ret;
 731
 732         struct smu_table_context *table_context = &smu->smu_table;
 733         struct smu_table *table = &table_context->tables[SMU_TABLE_PPTABLE];
 734
 735         if (table_context->driver_pptable)
 736                 return -EINVAL;
 737
 738         table_context->driver_pptable = kzalloc(table->size, GFP_KERNEL);
 739
 740         if (!table_context->driver_pptable)
 741                 return -ENOMEM;
 742
 743         ret = smu_store_powerplay_table(smu);
 744         if (ret)
 745                 return -EINVAL;
 746
 747         ret = smu_append_powerplay_table(smu);
 748
 749         return ret;
 750 }
 751
 752 int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
 753 {
 754         int ret;
 755
 756         ret = smu_set_default_dpm_table(smu);
 757
 758         return ret;
 759 }
 760
 761 int smu_v11_0_write_pptable(struct smu_context *smu)
 762 {
 763         struct smu_table_context *table_context = &smu->smu_table;
 764         int ret = 0;
 765
 766         ret = smu_update_table(smu, SMU_TABLE_PPTABLE, 0,
 767                                table_context->driver_pptable, true);
 768
 769         return ret;
 770 }
 771
 772 int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 773 {
 774         int ret;
 775
 776         ret = smu_send_smc_msg_with_param(smu,
 777                                           SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
 778         if (ret)
 779                 pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");
 780
 781         return ret;
 782 }
 783
 784 int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
 785 {
 786         struct smu_table_context *table_context = &smu->smu_table;
 787
 788         if (!smu->pm_enabled)
 789                 return 0;
 790         if (!table_context)
 791                 return -EINVAL;
 792
 793         return smu_v11_0_set_deep_sleep_dcefclk(smu, table_context->boot_values.dcefclk / 100);
 794 }
 795
 796 int smu_v11_0_set_driver_table_location(struct smu_context *smu)
 797 {
 798         struct smu_table *driver_table = &smu->smu_table.driver_table;
 799         int ret = 0;
 800
 801         if (driver_table->mc_address) {
 802                 ret = smu_send_smc_msg_with_param(smu,
 803                                 SMU_MSG_SetDriverDramAddrHigh,
 804                                 upper_32_bits(driver_table->mc_address),
 805                                 NULL);
 806                 if (!ret)
 807                         ret = smu_send_smc_msg_with_param(smu,
 808                                 SMU_MSG_SetDriverDramAddrLow,
 809                                 lower_32_bits(driver_table->mc_address),
 810                                 NULL);
 811         }
 812
 813         return ret;
 814 }
 815
 816 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
 817 {
 818         int ret = 0;
 819         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 820
 821         if (tool_table->mc_address) {
 822                 ret = smu_send_smc_msg_with_param(smu,
 823                                 SMU_MSG_SetToolsDramAddrHigh,
 824                                 upper_32_bits(tool_table->mc_address),
 825                                 NULL);
 826                 if (!ret)
 827                         ret = smu_send_smc_msg_with_param(smu,
 828                                 SMU_MSG_SetToolsDramAddrLow,
 829                                 lower_32_bits(tool_table->mc_address),
 830                                 NULL);
 831         }
 832
 833         return ret;
 834 }
 835
 836 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 837 {
 838         int ret = 0;
 839
 840         if (!smu->pm_enabled)
 841                 return ret;
 842
 843         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
 844         return ret;
 845 }
 846
 847
 848 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 849 {
 850         struct smu_feature *feature = &smu->smu_feature;
 851         int ret = 0;
 852         uint32_t feature_mask[2];
 853
 854         mutex_lock(&feature->mutex);
 855         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
 856                 goto failed;
 857
 858         bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
 859
 860         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 861                                           feature_mask[1], NULL);
 862         if (ret)
 863                 goto failed;
 864
 865         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
 866                                           feature_mask[0], NULL);
 867         if (ret)
 868                 goto failed;
 869
 870 failed:
 871         mutex_unlock(&feature->mutex);
 872         return ret;
 873 }
 874
 875 int smu_v11_0_get_enabled_mask(struct smu_context *smu,
 876                                       uint32_t *feature_mask, uint32_t num)
 877 {
 878         uint32_t feature_mask_high = 0, feature_mask_low = 0;
 879         struct smu_feature *feature = &smu->smu_feature;
 880         int ret = 0;
 881
 882         if (!feature_mask || num < 2)
 883                 return -EINVAL;
 884
 885         if (bitmap_empty(feature->enabled, feature->feature_num)) {
 886                 ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh, &feature_mask_high);
 887                 if (ret)
 888                         return ret;
 889
 890                 ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow, &feature_mask_low);
 891                 if (ret)
 892                         return ret;
 893
 894                 feature_mask[0] = feature_mask_low;
 895                 feature_mask[1] = feature_mask_high;
 896         } else {
 897                 bitmap_copy((unsigned long *)feature_mask, feature->enabled,
 898                              feature->feature_num);
 899         }
 900
 901         return ret;
 902 }
 903
 904 int smu_v11_0_system_features_control(struct smu_context *smu,
 905                                              bool en)
 906 {
 907         struct smu_feature *feature = &smu->smu_feature;
 908         uint32_t feature_mask[2];
 909         int ret = 0;
 910
 911         ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 912                                      SMU_MSG_DisableAllSmuFeatures), NULL);
 913         if (ret)
 914                 return ret;
 915
 916         bitmap_zero(feature->enabled, feature->feature_num);
 917         bitmap_zero(feature->supported, feature->feature_num);
 918
 919         if (en) {
 920                 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 921                 if (ret)
 922                         return ret;
 923
 924                 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 925                             feature->feature_num);
 926                 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 927                             feature->feature_num);
 928         }
 929
 930         return ret;
 931 }
 932
 933 int smu_v11_0_notify_display_change(struct smu_context *smu)
 934 {
 935         int ret = 0;
 936
 937         if (!smu->pm_enabled)
 938                 return ret;
 939         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 940             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 941                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
 942
 943         return ret;
 944 }
 945
 946 static int
 947 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 948                                     enum smu_clk_type clock_select)
 949 {
 950         int ret = 0;
 951         int clk_id;
 952
 953         if (!smu->pm_enabled)
 954                 return ret;
 955
 956         if ((smu_msg_get_index(smu, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 957             (smu_msg_get_index(smu, SMU_MSG_GetMaxDpmFreq) < 0))
 958                 return 0;
 959
 960         clk_id = smu_clk_get_index(smu, clock_select);
 961         if (clk_id < 0)
 962                 return -EINVAL;
 963
 964         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 965                                           clk_id << 16, clock);
 966         if (ret) {
 967                 pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 968                 return ret;
 969         }
 970
 971         if (*clock != 0)
 972                 return 0;
 973
 974         /* if DC limit is zero, return AC limit */
 975         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 976                                           clk_id << 16, clock);
 977         if (ret) {
 978                 pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 979                 return ret;
 980         }
 981
 982         return 0;
 983 }
 984
 985 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 986 {
 987         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
 988         int ret = 0;
 989
 990         if (!smu->smu_table.max_sustainable_clocks)
 991                 max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
 992                                          GFP_KERNEL);
 993         else
 994                 max_sustainable_clocks = smu->smu_table.max_sustainable_clocks;
 995
 996         smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
 997
 998         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 999         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
1000         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
1001         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
1002         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
1003         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
1004
1005         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1006                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1007                                                           &(max_sustainable_clocks->uclock),
1008                                                           SMU_UCLK);
1009                 if (ret) {
1010                         pr_err("[%s] failed to get max UCLK from SMC!",
1011                                __func__);
1012                         return ret;
1013                 }
1014         }
1015
1016         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1017                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1018                                                           &(max_sustainable_clocks->soc_clock),
1019                                                           SMU_SOCCLK);
1020                 if (ret) {
1021                         pr_err("[%s] failed to get max SOCCLK from SMC!",
1022                                __func__);
1023                         return ret;
1024                 }
1025         }
1026
1027         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1028                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1029                                                           &(max_sustainable_clocks->dcef_clock),
1030                                                           SMU_DCEFCLK);
1031                 if (ret) {
1032                         pr_err("[%s] failed to get max DCEFCLK from SMC!",
1033                                __func__);
1034                         return ret;
1035                 }
1036
1037                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1038                                                           &(max_sustainable_clocks->display_clock),
1039                                                           SMU_DISPCLK);
1040                 if (ret) {
1041                         pr_err("[%s] failed to get max DISPCLK from SMC!",
1042                                __func__);
1043                         return ret;
1044                 }
1045                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1046                                                           &(max_sustainable_clocks->phy_clock),
1047                                                           SMU_PHYCLK);
1048                 if (ret) {
1049                         pr_err("[%s] failed to get max PHYCLK from SMC!",
1050                                __func__);
1051                         return ret;
1052                 }
1053                 ret = smu_v11_0_get_max_sustainable_clock(smu,
1054                                                           &(max_sustainable_clocks->pixel_clock),
1055                                                           SMU_PIXCLK);
1056                 if (ret) {
1057                         pr_err("[%s] failed to get max PIXCLK from SMC!",
1058                                __func__);
1059                         return ret;
1060                 }
1061         }
1062
1063         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1064                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1065
1066         return 0;
1067 }
1068
1069 uint32_t smu_v11_0_get_max_power_limit(struct smu_context *smu) {
1070         uint32_t od_limit, max_power_limit;
1071         struct smu_11_0_powerplay_table *powerplay_table = NULL;
1072         struct smu_table_context *table_context = &smu->smu_table;
1073         powerplay_table = table_context->power_play_table;
1074
1075         max_power_limit = smu_get_pptable_power_limit(smu);
1076
1077         if (!max_power_limit) {
1078                 // If we couldn't get the table limit, fall back on first-read value
1079                 if (!smu->default_power_limit)
1080                         smu->default_power_limit = smu->power_limit;
1081                 max_power_limit = smu->default_power_limit;
1082         }
1083
1084         if (smu->od_enabled) {
1085                 od_limit = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1086
1087                 pr_debug("ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_limit, smu->default_power_limit);
1088
1089                 max_power_limit *= (100 + od_limit);
1090                 max_power_limit /= 100;
1091         }
1092
1093         return max_power_limit;
1094 }
1095
1096 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
1097 {
1098         int ret = 0;
1099         uint32_t max_power_limit;
1100
1101         max_power_limit = smu_v11_0_get_max_power_limit(smu);
1102
1103         if (n > max_power_limit) {
1104                 pr_err("New power limit (%d) is over the max allowed %d\n",
1105                                 n,
1106                                 max_power_limit);
1107                 return -EINVAL;
1108         }
1109
1110         if (n == 0)
1111                 n = smu->default_power_limit;
1112
1113         if (!smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1114                 pr_err("Setting new power limit is not supported!\n");
1115                 return -EOPNOTSUPP;
1116         }
1117
1118         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
1119         if (ret) {
1120                 pr_err("[%s] Set power limit Failed!\n", __func__);
1121                 return ret;
1122         }
1123         smu->power_limit = n;
1124
1125         return 0;
1126 }
1127
1128 int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
1129                                           enum smu_clk_type clk_id,
1130                                           uint32_t *value)
1131 {
1132         int ret = 0;
1133         uint32_t freq = 0;
1134         int asic_clk_id;
1135
1136         if (clk_id >= SMU_CLK_COUNT || !value)
1137                 return -EINVAL;
1138
1139         asic_clk_id = smu_clk_get_index(smu, clk_id);
1140         if (asic_clk_id < 0)
1141                 return -EINVAL;
1142
1143         /* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */
1144         if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) < 0)
1145                 ret =  smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
1146         else {
1147                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
1148                                                   (asic_clk_id << 16), &freq);
1149                 if (ret)
1150                         return ret;
1151         }
1152
1153         freq *= 100;
1154         *value = freq;
1155
1156         return ret;
1157 }
1158
1159 static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1160                                        struct smu_temperature_range range)
1161 {
1162         struct amdgpu_device *adev = smu->adev;
1163         int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
1164         int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
1165         uint32_t val;
1166         struct smu_table_context *table_context = &smu->smu_table;
1167         struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1168
1169         low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1170                         range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1171         high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP, powerplay_table->software_shutdown_temp);
1172
1173         if (low > high)
1174                 return -EINVAL;
1175
1176         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1177         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1178         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1179         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1180         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1181         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1182         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1183         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1184
1185         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1186
1187         return 0;
1188 }
1189
1190 static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1191 {
1192         struct amdgpu_device *adev = smu->adev;
1193         uint32_t val = 0;
1194
1195         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1196         val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1197         val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1198
1199         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1200
1201         return 0;
1202 }
1203
1204 int smu_v11_0_start_thermal_control(struct smu_context *smu)
1205 {
1206         int ret = 0;
1207         struct smu_temperature_range range;
1208         struct amdgpu_device *adev = smu->adev;
1209
1210         if (!smu->pm_enabled)
1211                 return ret;
1212
1213         memcpy(&range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1214
1215         ret = smu_get_thermal_temperature_range(smu, &range);
1216         if (ret)
1217                 return ret;
1218
1219         if (smu->smu_table.thermal_controller_type) {
1220                 ret = smu_v11_0_set_thermal_range(smu, range);
1221                 if (ret)
1222                         return ret;
1223
1224                 ret = smu_v11_0_enable_thermal_alert(smu);
1225                 if (ret)
1226                         return ret;
1227
1228                 ret = smu_set_thermal_fan_table(smu);
1229                 if (ret)
1230                         return ret;
1231         }
1232
1233         adev->pm.dpm.thermal.min_temp = range.min;
1234         adev->pm.dpm.thermal.max_temp = range.max;
1235         adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
1236         adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
1237         adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
1238         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
1239         adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
1240         adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
1241         adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
1242
1243         return ret;
1244 }
1245
1246 int smu_v11_0_stop_thermal_control(struct smu_context *smu)
1247 {
1248         struct amdgpu_device *adev = smu->adev;
1249
1250         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1251
1252         return 0;
1253 }
1254
1255 static uint16_t convert_to_vddc(uint8_t vid)
1256 {
1257         return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1258 }
1259
1260 static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1261 {
1262         struct amdgpu_device *adev = smu->adev;
1263         uint32_t vdd = 0, val_vid = 0;
1264
1265         if (!value)
1266                 return -EINVAL;
1267         val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1268                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1269                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1270
1271         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1272
1273         *value = vdd;
1274
1275         return 0;
1276
1277 }
1278
1279 int smu_v11_0_read_sensor(struct smu_context *smu,
1280                                  enum amd_pp_sensors sensor,
1281                                  void *data, uint32_t *size)
1282 {
1283         int ret = 0;
1284
1285         if(!data || !size)
1286                 return -EINVAL;
1287
1288         switch (sensor) {
1289         case AMDGPU_PP_SENSOR_GFX_MCLK:
1290                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1291                 *size = 4;
1292                 break;
1293         case AMDGPU_PP_SENSOR_GFX_SCLK:
1294                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1295                 *size = 4;
1296                 break;
1297         case AMDGPU_PP_SENSOR_VDDGFX:
1298                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1299                 *size = 4;
1300                 break;
1301         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
1302                 *(uint32_t *)data = 0;
1303                 *size = 4;
1304                 break;
1305         default:
1306                 ret = smu_common_read_sensor(smu, sensor, data, size);
1307                 break;
1308         }
1309
1310         if (ret)
1311                 *size = 0;
1312
1313         return ret;
1314 }
1315
1316 int
1317 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1318                                         struct pp_display_clock_request
1319                                         *clock_req)
1320 {
1321         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1322         int ret = 0;
1323         enum smu_clk_type clk_select = 0;
1324         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1325
1326         if (!smu->pm_enabled)
1327                 return -EINVAL;
1328
1329         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1330                 smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1331                 switch (clk_type) {
1332                 case amd_pp_dcef_clock:
1333                         clk_select = SMU_DCEFCLK;
1334                         break;
1335                 case amd_pp_disp_clock:
1336                         clk_select = SMU_DISPCLK;
1337                         break;
1338                 case amd_pp_pixel_clock:
1339                         clk_select = SMU_PIXCLK;
1340                         break;
1341                 case amd_pp_phy_clock:
1342                         clk_select = SMU_PHYCLK;
1343                         break;
1344                 case amd_pp_mem_clock:
1345                         clk_select = SMU_UCLK;
1346                         break;
1347                 default:
1348                         pr_info("[%s] Invalid Clock Type!", __func__);
1349                         ret = -EINVAL;
1350                         break;
1351                 }
1352
1353                 if (ret)
1354                         goto failed;
1355
1356                 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1357                         return 0;
1358
1359                 ret = smu_set_hard_freq_range(smu, clk_select, clk_freq, 0);
1360
1361                 if(clk_select == SMU_UCLK)
1362                         smu->hard_min_uclk_req_from_dal = clk_freq;
1363         }
1364
1365 failed:
1366         return ret;
1367 }
1368
1369 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1370 {
1371         int ret = 0;
1372         struct amdgpu_device *adev = smu->adev;
1373
1374         switch (adev->asic_type) {
1375         case CHIP_VEGA20:
1376                 break;
1377         case CHIP_NAVI10:
1378         case CHIP_NAVI14:
1379         case CHIP_NAVI12:
1380                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1381                         return 0;
1382                 if (enable)
1383                         ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
1384                 else
1385                         ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
1386                 break;
1387         default:
1388                 break;
1389         }
1390
1391         return ret;
1392 }
1393
1394 uint32_t
1395 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1396 {
1397         if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1398                 return AMD_FAN_CTRL_MANUAL;
1399         else
1400                 return AMD_FAN_CTRL_AUTO;
1401 }
1402
1403 static int
1404 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1405 {
1406         int ret = 0;
1407
1408         if (!smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1409                 return 0;
1410
1411         ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1412         if (ret)
1413                 pr_err("[%s]%s smc FAN CONTROL feature failed!",
1414                        __func__, (auto_fan_control ? "Start" : "Stop"));
1415
1416         return ret;
1417 }
1418
1419 static int
1420 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1421 {
1422         struct amdgpu_device *adev = smu->adev;
1423
1424         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1425                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1426                                    CG_FDO_CTRL2, TMIN, 0));
1427         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1428                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1429                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1430
1431         return 0;
1432 }
1433
1434 int
1435 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1436 {
1437         struct amdgpu_device *adev = smu->adev;
1438         uint32_t duty100, duty;
1439         uint64_t tmp64;
1440
1441         if (speed > 100)
1442                 speed = 100;
1443
1444         if (smu_v11_0_auto_fan_control(smu, 0))
1445                 return -EINVAL;
1446
1447         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1448                                 CG_FDO_CTRL1, FMAX_DUTY100);
1449         if (!duty100)
1450                 return -EINVAL;
1451
1452         tmp64 = (uint64_t)speed * duty100;
1453         do_div(tmp64, 100);
1454         duty = (uint32_t)tmp64;
1455
1456         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1457                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1458                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1459
1460         return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1461 }
1462
1463 int
1464 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1465                                uint32_t mode)
1466 {
1467         int ret = 0;
1468
1469         switch (mode) {
1470         case AMD_FAN_CTRL_NONE:
1471                 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1472                 break;
1473         case AMD_FAN_CTRL_MANUAL:
1474                 ret = smu_v11_0_auto_fan_control(smu, 0);
1475                 break;
1476         case AMD_FAN_CTRL_AUTO:
1477                 ret = smu_v11_0_auto_fan_control(smu, 1);
1478                 break;
1479         default:
1480                 break;
1481         }
1482
1483         if (ret) {
1484                 pr_err("[%s]Set fan control mode failed!", __func__);
1485                 return -EINVAL;
1486         }
1487
1488         return ret;
1489 }
1490
1491 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1492                                        uint32_t speed)
1493 {
1494         struct amdgpu_device *adev = smu->adev;
1495         int ret;
1496         uint32_t tach_period, crystal_clock_freq;
1497
1498         if (!speed)
1499                 return -EINVAL;
1500
1501         ret = smu_v11_0_auto_fan_control(smu, 0);
1502         if (ret)
1503                 return ret;
1504
1505         crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1506         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1507         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1508                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1509                                    CG_TACH_CTRL, TARGET_PERIOD,
1510                                    tach_period));
1511
1512         ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1513
1514         return ret;
1515 }
1516
1517 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1518                                      uint32_t pstate)
1519 {
1520         int ret = 0;
1521         ret = smu_send_smc_msg_with_param(smu,
1522                                           SMU_MSG_SetXgmiMode,
1523                                           pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1524                                           NULL);
1525         return ret;
1526 }
1527
1528 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1529 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1530
1531 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1532                                  struct amdgpu_irq_src *source,
1533                                  struct amdgpu_iv_entry *entry)
1534 {
1535         uint32_t client_id = entry->client_id;
1536         uint32_t src_id = entry->src_id;
1537
1538         if (client_id == SOC15_IH_CLIENTID_THM) {
1539                 switch (src_id) {
1540                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1541                         pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
1542                                 PCI_BUS_NUM(adev->pdev->devfn),
1543                                 PCI_SLOT(adev->pdev->devfn),
1544                                 PCI_FUNC(adev->pdev->devfn));
1545                 break;
1546                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1547                         pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
1548                                 PCI_BUS_NUM(adev->pdev->devfn),
1549                                 PCI_SLOT(adev->pdev->devfn),
1550                                 PCI_FUNC(adev->pdev->devfn));
1551                 break;
1552                 default:
1553                         pr_warn("GPU under temperature range unknown src id (%d), detected on PCIe %d:%d.%d!\n",
1554                                 src_id,
1555                                 PCI_BUS_NUM(adev->pdev->devfn),
1556                                 PCI_SLOT(adev->pdev->devfn),
1557                                 PCI_FUNC(adev->pdev->devfn));
1558                 break;
1559
1560                 }
1561         }
1562
1563         return 0;
1564 }
1565
1566 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1567 {
1568         .process = smu_v11_0_irq_process,
1569 };
1570
1571 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1572 {
1573         struct amdgpu_device *adev = smu->adev;
1574         struct amdgpu_irq_src *irq_src = smu->irq_source;
1575         int ret = 0;
1576
1577         /* already register */
1578         if (irq_src)
1579                 return 0;
1580
1581         irq_src = kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
1582         if (!irq_src)
1583                 return -ENOMEM;
1584         smu->irq_source = irq_src;
1585
1586         irq_src->funcs = &smu_v11_0_irq_funcs;
1587
1588         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1589                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1590                                 irq_src);
1591         if (ret)
1592                 return ret;
1593
1594         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1595                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1596                                 irq_src);
1597         if (ret)
1598                 return ret;
1599
1600         return ret;
1601 }
1602
1603 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1604                 struct pp_smu_nv_clock_table *max_clocks)
1605 {
1606         struct smu_table_context *table_context = &smu->smu_table;
1607         struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1608
1609         if (!max_clocks || !table_context->max_sustainable_clocks)
1610                 return -EINVAL;
1611
1612         sustainable_clocks = table_context->max_sustainable_clocks;
1613
1614         max_clocks->dcfClockInKhz =
1615                         (unsigned int) sustainable_clocks->dcef_clock * 1000;
1616         max_clocks->displayClockInKhz =
1617                         (unsigned int) sustainable_clocks->display_clock * 1000;
1618         max_clocks->phyClockInKhz =
1619                         (unsigned int) sustainable_clocks->phy_clock * 1000;
1620         max_clocks->pixelClockInKhz =
1621                         (unsigned int) sustainable_clocks->pixel_clock * 1000;
1622         max_clocks->uClockInKhz =
1623                         (unsigned int) sustainable_clocks->uclock * 1000;
1624         max_clocks->socClockInKhz =
1625                         (unsigned int) sustainable_clocks->soc_clock * 1000;
1626         max_clocks->dscClockInKhz = 0;
1627         max_clocks->dppClockInKhz = 0;
1628         max_clocks->fabricClockInKhz = 0;
1629
1630         return 0;
1631 }
1632
1633 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1634 {
1635         int ret = 0;
1636
1637         ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1638
1639         return ret;
1640 }
1641
1642 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1643 {
1644         return smu_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
1645 }
1646
1647 bool smu_v11_0_baco_is_support(struct smu_context *smu)
1648 {
1649         struct amdgpu_device *adev = smu->adev;
1650         struct smu_baco_context *smu_baco = &smu->smu_baco;
1651         uint32_t val;
1652         bool baco_support;
1653
1654         mutex_lock(&smu_baco->mutex);
1655         baco_support = smu_baco->platform_support;
1656         mutex_unlock(&smu_baco->mutex);
1657
1658         if (!baco_support)
1659                 return false;
1660
1661         /* Arcturus does not support this bit mask */
1662         if (smu_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1663            !smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1664                 return false;
1665
1666         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1667         if (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
1668                 return true;
1669
1670         return false;
1671 }
1672
1673 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1674 {
1675         struct smu_baco_context *smu_baco = &smu->smu_baco;
1676         enum smu_baco_state baco_state;
1677
1678         mutex_lock(&smu_baco->mutex);
1679         baco_state = smu_baco->state;
1680         mutex_unlock(&smu_baco->mutex);
1681
1682         return baco_state;
1683 }
1684
1685 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1686 {
1687
1688         struct smu_baco_context *smu_baco = &smu->smu_baco;
1689         struct amdgpu_device *adev = smu->adev;
1690         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1691         uint32_t bif_doorbell_intr_cntl;
1692         uint32_t data;
1693         int ret = 0;
1694
1695         if (smu_v11_0_baco_get_state(smu) == state)
1696                 return 0;
1697
1698         mutex_lock(&smu_baco->mutex);
1699
1700         bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
1701
1702         if (state == SMU_BACO_STATE_ENTER) {
1703                 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
1704                                                 BIF_DOORBELL_INT_CNTL,
1705                                                 DOORBELL_INTERRUPT_DISABLE, 1);
1706                 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
1707
1708                 if (!ras || !ras->supported) {
1709                         data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1710                         data |= 0x80000000;
1711                         WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1712
1713                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
1714                 } else {
1715                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL);
1716                 }
1717         } else {
1718                 ret = smu_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL);
1719                 if (ret)
1720                         goto out;
1721
1722                 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
1723                                                 BIF_DOORBELL_INT_CNTL,
1724                                                 DOORBELL_INTERRUPT_DISABLE, 0);
1725                 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
1726
1727                 /* clear vbios scratch 6 and 7 for coming asic reinit */
1728                 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1729                 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1730         }
1731         if (ret)
1732                 goto out;
1733
1734         smu_baco->state = state;
1735 out:
1736         mutex_unlock(&smu_baco->mutex);
1737         return ret;
1738 }
1739
1740 int smu_v11_0_baco_enter(struct smu_context *smu)
1741 {
1742         struct amdgpu_device *adev = smu->adev;
1743         int ret = 0;
1744
1745         /* Arcturus does not need this audio workaround */
1746         if (adev->asic_type != CHIP_ARCTURUS) {
1747                 ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1748                 if (ret)
1749                         return ret;
1750         }
1751
1752         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1753         if (ret)
1754                 return ret;
1755
1756         msleep(10);
1757
1758         return ret;
1759 }
1760
1761 int smu_v11_0_baco_exit(struct smu_context *smu)
1762 {
1763         int ret = 0;
1764
1765         ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1766         if (ret)
1767                 return ret;
1768
1769         return ret;
1770 }
1771
1772 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1773                                                  uint32_t *min, uint32_t *max)
1774 {
1775         int ret = 0, clk_id = 0;
1776         uint32_t param = 0;
1777
1778         clk_id = smu_clk_get_index(smu, clk_type);
1779         if (clk_id < 0) {
1780                 ret = -EINVAL;
1781                 goto failed;
1782         }
1783         param = (clk_id & 0xffff) << 16;
1784
1785         if (max) {
1786                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1787                 if (ret)
1788                         goto failed;
1789         }
1790
1791         if (min) {
1792                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1793                 if (ret)
1794                         goto failed;
1795         }
1796
1797 failed:
1798         return ret;
1799 }
1800
1801 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
1802                             uint32_t min, uint32_t max)
1803 {
1804         int ret = 0, clk_id = 0;
1805         uint32_t param;
1806
1807         clk_id = smu_clk_get_index(smu, clk_type);
1808         if (clk_id < 0)
1809                 return clk_id;
1810
1811         if (max > 0) {
1812                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1813                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1814                                                   param, NULL);
1815                 if (ret)
1816                         return ret;
1817         }
1818
1819         if (min > 0) {
1820                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1821                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1822                                                   param, NULL);
1823                 if (ret)
1824                         return ret;
1825         }
1826
1827         return ret;
1828 }
1829
1830 int smu_v11_0_override_pcie_parameters(struct smu_context *smu)
1831 {
1832         struct amdgpu_device *adev = smu->adev;
1833         uint32_t pcie_gen = 0, pcie_width = 0;
1834         int ret;
1835
1836         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1837                 pcie_gen = 3;
1838         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1839                 pcie_gen = 2;
1840         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1841                 pcie_gen = 1;
1842         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1843                 pcie_gen = 0;
1844
1845         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1846          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1847          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
1848          */
1849         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1850                 pcie_width = 6;
1851         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1852                 pcie_width = 5;
1853         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1854                 pcie_width = 4;
1855         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1856                 pcie_width = 3;
1857         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1858                 pcie_width = 2;
1859         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1860                 pcie_width = 1;
1861
1862         ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1863
1864         if (ret)
1865                 pr_err("[%s] Attempt to override pcie params failed!\n", __func__);
1866
1867         return ret;
1868
1869 }
1870
1871 int smu_v11_0_set_default_od_settings(struct smu_context *smu, bool initialize, size_t overdrive_table_size)
1872 {
1873         struct smu_table_context *table_context = &smu->smu_table;
1874         int ret = 0;
1875
1876         if (initialize) {
1877                 if (table_context->overdrive_table) {
1878                         return -EINVAL;
1879                 }
1880                 table_context->overdrive_table = kzalloc(overdrive_table_size, GFP_KERNEL);
1881                 if (!table_context->overdrive_table) {
1882                         return -ENOMEM;
1883                 }
1884                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, false);
1885                 if (ret) {
1886                         pr_err("Failed to export overdrive table!\n");
1887                         return ret;
1888                 }
1889                 if (!table_context->boot_overdrive_table) {
1890                         table_context->boot_overdrive_table = kmemdup(table_context->overdrive_table, overdrive_table_size, GFP_KERNEL);
1891                         if (!table_context->boot_overdrive_table) {
1892                                 return -ENOMEM;
1893                         }
1894                 }
1895         }
1896         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, table_context->overdrive_table, true);
1897         if (ret) {
1898                 pr_err("Failed to import overdrive table!\n");
1899                 return ret;
1900         }
1901         return ret;
1902 }
1903
1904 int smu_v11_0_set_performance_level(struct smu_context *smu,
1905                                     enum amd_dpm_forced_level level)
1906 {
1907         int ret = 0;
1908         uint32_t sclk_mask, mclk_mask, soc_mask;
1909
1910         switch (level) {
1911         case AMD_DPM_FORCED_LEVEL_HIGH:
1912                 ret = smu_force_dpm_limit_value(smu, true);
1913                 break;
1914         case AMD_DPM_FORCED_LEVEL_LOW:
1915                 ret = smu_force_dpm_limit_value(smu, false);
1916                 break;
1917         case AMD_DPM_FORCED_LEVEL_AUTO:
1918         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1919                 ret = smu_unforce_dpm_levels(smu);
1920                 break;
1921         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1922         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1923         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1924                 ret = smu_get_profiling_clk_mask(smu, level,
1925                                                  &sclk_mask,
1926                                                  &mclk_mask,
1927                                                  &soc_mask);
1928                 if (ret)
1929                         return ret;
1930                 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1931                 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1932                 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1933                 break;
1934         case AMD_DPM_FORCED_LEVEL_MANUAL:
1935         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1936         default:
1937                 break;
1938         }
1939         return ret;
1940 }
1941