drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include <linux/pci.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "smu_internal.h"
  30 #include "atomfirmware.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "smu_v11_0.h"
  33 #include "smu11_driver_if_sienna_cichlid.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "sienna_cichlid_ppt.h"
  37 #include "smu_v11_0_pptable.h"
  38 #include "smu_v11_0_7_ppsmc.h"
  39
  40 #include "nbio/nbio_2_3_sh_mask.h"
  41 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  42
  43 #define FEATURE_MASK(feature) (1ULL << feature)
  44 #define SMC_DPM_FEATURE ( \
  45         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  46         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  47         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  48         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  49         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  50         FEATURE_MASK(FEATURE_DPM_FCLK_BIT)       | \
  51         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
  52
  53 #define MSG_MAP(msg, index) \
  54         [SMU_MSG_##msg] = {1, (index)}
  55
  56 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
  57         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
  58         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
  59         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion),
  60         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow),
  61         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  62         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures),
  63         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures),
  64         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow),
  65         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh),
  66         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow),
  67         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh),
  68         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow),
  69         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh),
  70         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask),
  71         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit),
  72         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh),
  73         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow),
  74         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh),
  75         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow),
  76         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram),
  77         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu),
  78         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable),
  79         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco),
  80         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq),
  81         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq),
  82         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq),
  83         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq),
  84         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq),
  85         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq),
  86         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex),
  87         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode),
  88         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh),
  89         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow),
  90         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters),
  91         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt),
  92         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource),
  93         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch),
  94         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps),
  95         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload),
  96         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff),
  97         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff),
  98         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit),
  99         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq),
 100         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco),
 101         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn),
 102         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn),
 103         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg),
 104         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg),
 105         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME),
 106         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3),
 107 };
 108
 109 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
 110         CLK_MAP(GFXCLK,         PPCLK_GFXCLK),
 111         CLK_MAP(SCLK,           PPCLK_GFXCLK),
 112         CLK_MAP(SOCCLK,         PPCLK_SOCCLK),
 113         CLK_MAP(FCLK,           PPCLK_FCLK),
 114         CLK_MAP(UCLK,           PPCLK_UCLK),
 115         CLK_MAP(MCLK,           PPCLK_UCLK),
 116         CLK_MAP(DCLK,           PPCLK_DCLK_0),
 117         CLK_MAP(DCLK1,          PPCLK_DCLK_0),
 118         CLK_MAP(VCLK,           PPCLK_VCLK_1),
 119         CLK_MAP(VCLK1,          PPCLK_VCLK_1),
 120         CLK_MAP(DCEFCLK,        PPCLK_DCEFCLK),
 121         CLK_MAP(DISPCLK,        PPCLK_DISPCLK),
 122         CLK_MAP(PIXCLK,         PPCLK_PIXCLK),
 123         CLK_MAP(PHYCLK,         PPCLK_PHYCLK),
 124 };
 125
 126 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
 127         FEA_MAP(DPM_PREFETCHER),
 128         FEA_MAP(DPM_GFXCLK),
 129         FEA_MAP(DPM_GFX_GPO),
 130         FEA_MAP(DPM_UCLK),
 131         FEA_MAP(DPM_SOCCLK),
 132         FEA_MAP(DPM_MP0CLK),
 133         FEA_MAP(DPM_LINK),
 134         FEA_MAP(DPM_DCEFCLK),
 135         FEA_MAP(MEM_VDDCI_SCALING),
 136         FEA_MAP(MEM_MVDD_SCALING),
 137         FEA_MAP(DS_GFXCLK),
 138         FEA_MAP(DS_SOCCLK),
 139         FEA_MAP(DS_LCLK),
 140         FEA_MAP(DS_DCEFCLK),
 141         FEA_MAP(DS_UCLK),
 142         FEA_MAP(GFX_ULV),
 143         FEA_MAP(FW_DSTATE),
 144         FEA_MAP(GFXOFF),
 145         FEA_MAP(BACO),
 146         FEA_MAP(MM_DPM_PG),
 147         FEA_MAP(RSMU_SMN_CG),
 148         FEA_MAP(PPT),
 149         FEA_MAP(TDC),
 150         FEA_MAP(APCC_PLUS),
 151         FEA_MAP(GTHR),
 152         FEA_MAP(ACDC),
 153         FEA_MAP(VR0HOT),
 154         FEA_MAP(VR1HOT),
 155         FEA_MAP(FW_CTF),
 156         FEA_MAP(FAN_CONTROL),
 157         FEA_MAP(THERMAL),
 158         FEA_MAP(GFX_DCS),
 159         FEA_MAP(RM),
 160         FEA_MAP(LED_DISPLAY),
 161         FEA_MAP(GFX_SS),
 162         FEA_MAP(OUT_OF_BAND_MONITOR),
 163         FEA_MAP(TEMP_DEPENDENT_VMIN),
 164         FEA_MAP(MMHUB_PG),
 165         FEA_MAP(ATHUB_PG),
 166         FEA_MAP(APCC_DFLL),
 167 };
 168
 169 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
 170         TAB_MAP(PPTABLE),
 171         TAB_MAP(WATERMARKS),
 172         TAB_MAP(AVFS_PSM_DEBUG),
 173         TAB_MAP(AVFS_FUSE_OVERRIDE),
 174         TAB_MAP(PMSTATUSLOG),
 175         TAB_MAP(SMU_METRICS),
 176         TAB_MAP(DRIVER_SMU_CONFIG),
 177         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 178         TAB_MAP(OVERDRIVE),
 179         TAB_MAP(I2C_COMMANDS),
 180         TAB_MAP(PACE),
 181 };
 182
 183 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 184         PWR_MAP(AC),
 185         PWR_MAP(DC),
 186 };
 187
 188 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 189         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 190         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 191         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 192         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 193         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 194         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_CUSTOM_BIT),
 195         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 196 };
 197
 198 static int sienna_cichlid_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 199 {
 200         struct smu_11_0_cmn2aisc_mapping mapping;
 201
 202         if (index >= SMU_MSG_MAX_COUNT)
 203                 return -EINVAL;
 204
 205         mapping = sienna_cichlid_message_map[index];
 206         if (!(mapping.valid_mapping)) {
 207                 return -EINVAL;
 208         }
 209
 210         return mapping.map_to;
 211 }
 212
 213 static int sienna_cichlid_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 214 {
 215         struct smu_11_0_cmn2aisc_mapping mapping;
 216
 217         if (index >= SMU_CLK_COUNT)
 218                 return -EINVAL;
 219
 220         mapping = sienna_cichlid_clk_map[index];
 221         if (!(mapping.valid_mapping)) {
 222                 return -EINVAL;
 223         }
 224
 225         return mapping.map_to;
 226 }
 227
 228 static int sienna_cichlid_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 229 {
 230         struct smu_11_0_cmn2aisc_mapping mapping;
 231
 232         if (index >= SMU_FEATURE_COUNT)
 233                 return -EINVAL;
 234
 235         mapping = sienna_cichlid_feature_mask_map[index];
 236         if (!(mapping.valid_mapping)) {
 237                 return -EINVAL;
 238         }
 239
 240         return mapping.map_to;
 241 }
 242
 243 static int sienna_cichlid_get_smu_table_index(struct smu_context *smc, uint32_t index)
 244 {
 245         struct smu_11_0_cmn2aisc_mapping mapping;
 246
 247         if (index >= SMU_TABLE_COUNT)
 248                 return -EINVAL;
 249
 250         mapping = sienna_cichlid_table_map[index];
 251         if (!(mapping.valid_mapping)) {
 252                 return -EINVAL;
 253         }
 254
 255         return mapping.map_to;
 256 }
 257
 258 static int sienna_cichlid_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 259 {
 260         struct smu_11_0_cmn2aisc_mapping mapping;
 261
 262         if (index >= SMU_POWER_SOURCE_COUNT)
 263                 return -EINVAL;
 264
 265         mapping = sienna_cichlid_pwr_src_map[index];
 266         if (!(mapping.valid_mapping)) {
 267                 return -EINVAL;
 268         }
 269
 270         return mapping.map_to;
 271 }
 272
 273 static int sienna_cichlid_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 274 {
 275         struct smu_11_0_cmn2aisc_mapping mapping;
 276
 277         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 278                 return -EINVAL;
 279
 280         mapping = sienna_cichlid_workload_map[profile];
 281         if (!(mapping.valid_mapping)) {
 282                 return -EINVAL;
 283         }
 284
 285         return mapping.map_to;
 286 }
 287
 288 static int
 289 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 290                                   uint32_t *feature_mask, uint32_t num)
 291 {
 292         struct amdgpu_device *adev = smu->adev;
 293
 294         if (num > 2)
 295                 return -EINVAL;
 296
 297         memset(feature_mask, 0, sizeof(uint32_t) * num);
 298
 299         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 300                                 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
 301                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 302                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 303                                 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
 304                                 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
 305                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 306                                 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
 307                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 308                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 309                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 310                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 311                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 312                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 313                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 314                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 315                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 316                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 317                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 318
 319         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
 320                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 321                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
 322         }
 323
 324         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 325                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 326                                         | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 327                                         | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 328
 329         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 330                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 331
 332         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 333                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 334
 335         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 336                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 337
 338         if (adev->pm.pp_feature & PP_ULV_MASK)
 339                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 340
 341         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 342                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 343
 344         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 345                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 346
 347         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 348                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 349
 350         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
 351             smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 352                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
 353
 354         return 0;
 355 }
 356
 357 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
 358 {
 359         return 0;
 360 }
 361
 362 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
 363 {
 364         struct smu_table_context *table_context = &smu->smu_table;
 365         PPTable_t *smc_pptable = table_context->driver_pptable;
 366         struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
 367         int index, ret;
 368         int i;
 369
 370         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 371                                             smc_dpm_info);
 372
 373         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 374                                       (uint8_t **)&smc_dpm_table);
 375         if (ret)
 376                 return ret;
 377
 378         memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 379                sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS);
 380
 381         /* SVI2 Board Parameters */
 382         smc_pptable->VddGfxVrMapping = smc_dpm_table->VddGfxVrMapping;
 383         smc_pptable->VddSocVrMapping = smc_dpm_table->VddSocVrMapping;
 384         smc_pptable->VddMem0VrMapping = smc_dpm_table->VddMem0VrMapping;
 385         smc_pptable->VddMem1VrMapping = smc_dpm_table->VddMem1VrMapping;
 386         smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->GfxUlvPhaseSheddingMask;
 387         smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->SocUlvPhaseSheddingMask;
 388         smc_pptable->VddciUlvPhaseSheddingMask = smc_dpm_table->VddciUlvPhaseSheddingMask;
 389         smc_pptable->MvddUlvPhaseSheddingMask = smc_dpm_table->MvddUlvPhaseSheddingMask;
 390
 391         /* Telemetry Settings */
 392         smc_pptable->GfxMaxCurrent = smc_dpm_table->GfxMaxCurrent;
 393         smc_pptable->GfxOffset = smc_dpm_table->GfxOffset;
 394         smc_pptable->Padding_TelemetryGfx = smc_dpm_table->Padding_TelemetryGfx;
 395         smc_pptable->SocMaxCurrent = smc_dpm_table->SocMaxCurrent;
 396         smc_pptable->SocOffset = smc_dpm_table->SocOffset;
 397         smc_pptable->Padding_TelemetrySoc = smc_dpm_table->Padding_TelemetrySoc;
 398         smc_pptable->Mem0MaxCurrent = smc_dpm_table->Mem0MaxCurrent;
 399         smc_pptable->Mem0Offset = smc_dpm_table->Mem0Offset;
 400         smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->Padding_TelemetryMem0;
 401         smc_pptable->Mem1MaxCurrent = smc_dpm_table->Mem1MaxCurrent;
 402         smc_pptable->Mem1Offset = smc_dpm_table->Mem1Offset;
 403         smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->Padding_TelemetryMem1;
 404         smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
 405
 406         /* GPIO Settings */
 407         smc_pptable->AcDcGpio = smc_dpm_table->AcDcGpio;
 408         smc_pptable->AcDcPolarity = smc_dpm_table->AcDcPolarity;
 409         smc_pptable->VR0HotGpio = smc_dpm_table->VR0HotGpio;
 410         smc_pptable->VR0HotPolarity = smc_dpm_table->VR0HotPolarity;
 411         smc_pptable->VR1HotGpio = smc_dpm_table->VR1HotGpio;
 412         smc_pptable->VR1HotPolarity = smc_dpm_table->VR1HotPolarity;
 413         smc_pptable->GthrGpio = smc_dpm_table->GthrGpio;
 414         smc_pptable->GthrPolarity = smc_dpm_table->GthrPolarity;
 415
 416         /* LED Display Settings */
 417         smc_pptable->LedPin0 = smc_dpm_table->LedPin0;
 418         smc_pptable->LedPin1 = smc_dpm_table->LedPin1;
 419         smc_pptable->LedPin2 = smc_dpm_table->LedPin2;
 420         smc_pptable->LedEnableMask = smc_dpm_table->LedEnableMask;
 421         smc_pptable->LedPcie = smc_dpm_table->LedPcie;
 422         smc_pptable->LedError = smc_dpm_table->LedError;
 423         smc_pptable->LedSpare1[0] = smc_dpm_table->LedSpare1[0];
 424         smc_pptable->LedSpare1[1] = smc_dpm_table->LedSpare1[1];
 425
 426         /* GFXCLK PLL Spread Spectrum */
 427         smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->PllGfxclkSpreadEnabled;
 428         smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->PllGfxclkSpreadPercent;
 429         smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->PllGfxclkSpreadFreq;
 430
 431         /* GFXCLK DFLL Spread Spectrum */
 432         smc_pptable->DfllGfxclkSpreadEnabled = smc_dpm_table->DfllGfxclkSpreadEnabled;
 433         smc_pptable->DfllGfxclkSpreadPercent = smc_dpm_table->DfllGfxclkSpreadPercent;
 434         smc_pptable->DfllGfxclkSpreadFreq = smc_dpm_table->DfllGfxclkSpreadFreq;
 435
 436         /* UCLK Spread Spectrum */
 437         smc_pptable->UclkSpreadEnabled = smc_dpm_table->UclkSpreadEnabled;
 438         smc_pptable->UclkSpreadPercent = smc_dpm_table->UclkSpreadPercent;
 439         smc_pptable->UclkSpreadFreq = smc_dpm_table->UclkSpreadFreq;
 440
 441         /* FCLK Spred Spectrum */
 442         smc_pptable->FclkSpreadEnabled = smc_dpm_table->FclkSpreadEnabled;
 443         smc_pptable->FclkSpreadPercent = smc_dpm_table->FclkSpreadPercent;
 444         smc_pptable->FclkSpreadFreq = smc_dpm_table->FclkSpreadFreq;
 445
 446         /* Memory Config */
 447         smc_pptable->MemoryChannelEnabled = smc_dpm_table->MemoryChannelEnabled;
 448         smc_pptable->DramBitWidth = smc_dpm_table->DramBitWidth;
 449         smc_pptable->PaddingMem1[0] = smc_dpm_table->PaddingMem1[0];
 450         smc_pptable->PaddingMem1[1] = smc_dpm_table->PaddingMem1[1];
 451         smc_pptable->PaddingMem1[2] = smc_dpm_table->PaddingMem1[2];
 452
 453         /* Total board power */
 454         smc_pptable->TotalBoardPower = smc_dpm_table->TotalBoardPower;
 455         smc_pptable->BoardPowerPadding = smc_dpm_table->BoardPowerPadding;
 456
 457         /* XGMI Training */
 458         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) {
 459                 smc_pptable->XgmiLinkSpeed[i] = smc_dpm_table->XgmiLinkSpeed[i];
 460                 smc_pptable->XgmiLinkWidth[i] = smc_dpm_table->XgmiLinkWidth[i];
 461                 smc_pptable->XgmiFclkFreq[i] = smc_dpm_table->XgmiFclkFreq[i];
 462                 smc_pptable->XgmiSocVoltage[i] = smc_dpm_table->XgmiSocVoltage[i];
 463         }
 464
 465         return 0;
 466 }
 467
 468 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
 469 {
 470         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 471         struct smu_table_context *table_context = &smu->smu_table;
 472         struct smu_baco_context *smu_baco = &smu->smu_baco;
 473
 474         if (!table_context->power_play_table)
 475                 return -EINVAL;
 476
 477         powerplay_table = table_context->power_play_table;
 478
 479         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 480                sizeof(PPTable_t));
 481
 482         table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
 483
 484         mutex_lock(&smu_baco->mutex);
 485         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 486             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 487                 smu_baco->platform_support = true;
 488         mutex_unlock(&smu_baco->mutex);
 489
 490         return 0;
 491 }
 492
 493 static int sienna_cichlid_tables_init(struct smu_context *smu, struct smu_table *tables)
 494 {
 495         struct smu_table_context *smu_table = &smu->smu_table;
 496
 497         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 498                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 499         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 500                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 501         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 502                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 503         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 504                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 505         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 506                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 507         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 508                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 509                        AMDGPU_GEM_DOMAIN_VRAM);
 510
 511         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 512         if (!smu_table->metrics_table)
 513                 return -ENOMEM;
 514         smu_table->metrics_time = 0;
 515
 516         return 0;
 517 }
 518
 519 static int sienna_cichlid_get_metrics_table(struct smu_context *smu,
 520                                     SmuMetrics_t *metrics_table)
 521 {
 522         struct smu_table_context *smu_table= &smu->smu_table;
 523         int ret = 0;
 524
 525         mutex_lock(&smu->metrics_lock);
 526         if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
 527                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 528                                 (void *)smu_table->metrics_table, false);
 529                 if (ret) {
 530                         pr_info("Failed to export SMU metrics table!\n");
 531                         mutex_unlock(&smu->metrics_lock);
 532                         return ret;
 533                 }
 534                 smu_table->metrics_time = jiffies;
 535         }
 536
 537         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
 538         mutex_unlock(&smu->metrics_lock);
 539
 540         return ret;
 541 }
 542
 543 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
 544 {
 545         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 546
 547         if (smu_dpm->dpm_context)
 548                 return -EINVAL;
 549
 550         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 551                                        GFP_KERNEL);
 552         if (!smu_dpm->dpm_context)
 553                 return -ENOMEM;
 554
 555         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 556
 557         return 0;
 558 }
 559
 560 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 561 {
 562         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 563         struct smu_table_context *table_context = &smu->smu_table;
 564         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 565         PPTable_t *driver_ppt = NULL;
 566         int i;
 567
 568         driver_ppt = table_context->driver_pptable;
 569
 570         dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
 571         dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
 572
 573         dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
 574         dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
 575
 576         dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
 577         dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
 578
 579         dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
 580         dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
 581
 582         dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
 583         dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
 584
 585         dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
 586         dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
 587
 588         dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
 589         dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
 590
 591         dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
 592         dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
 593
 594         dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
 595         dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
 596
 597         for (i = 0; i < MAX_PCIE_CONF; i++) {
 598                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
 599                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
 600         }
 601
 602         return 0;
 603 }
 604
 605 static int sienna_cichlid_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
 606 {
 607         struct smu_power_context *smu_power = &smu->smu_power;
 608         struct smu_power_gate *power_gate = &smu_power->power_gate;
 609         int ret = 0;
 610
 611         if (enable) {
 612                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 613                 if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 614                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
 615                         if (ret)
 616                                 return ret;
 617                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0x10000, NULL);
 618                         if (ret)
 619                                 return ret;
 620                 }
 621                 power_gate->vcn_gated = false;
 622         } else {
 623                 if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 624                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
 625                         if (ret)
 626                                 return ret;
 627                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0x10000, NULL);
 628                         if (ret)
 629                                 return ret;
 630                 }
 631                 power_gate->vcn_gated = true;
 632         }
 633
 634         return ret;
 635 }
 636
 637 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 638 {
 639         struct smu_power_context *smu_power = &smu->smu_power;
 640         struct smu_power_gate *power_gate = &smu_power->power_gate;
 641         int ret = 0;
 642
 643         if (enable) {
 644                 if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 645                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
 646                         if (ret)
 647                                 return ret;
 648                 }
 649                 power_gate->jpeg_gated = false;
 650         } else {
 651                 if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 652                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
 653                         if (ret)
 654                                 return ret;
 655                 }
 656                 power_gate->jpeg_gated = true;
 657         }
 658
 659         return ret;
 660 }
 661
 662 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
 663                                        enum smu_clk_type clk_type,
 664                                        uint32_t *value)
 665 {
 666         int ret = 0, clk_id = 0;
 667         SmuMetrics_t metrics;
 668
 669         ret = sienna_cichlid_get_metrics_table(smu, &metrics);
 670         if (ret)
 671                 return ret;
 672
 673         clk_id = smu_clk_get_index(smu, clk_type);
 674         if (clk_id < 0)
 675                 return clk_id;
 676
 677         *value = metrics.CurrClock[clk_id];
 678
 679         return ret;
 680 }
 681
 682 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 683 {
 684         PPTable_t *pptable = smu->smu_table.driver_pptable;
 685         DpmDescriptor_t *dpm_desc = NULL;
 686         uint32_t clk_index = 0;
 687
 688         clk_index = smu_clk_get_index(smu, clk_type);
 689         dpm_desc = &pptable->DpmDescriptor[clk_index];
 690
 691         /* 0 - Fine grained DPM, 1 - Discrete DPM */
 692         return dpm_desc->SnapToDiscrete == 0 ? true : false;
 693 }
 694
 695 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
 696                         enum smu_clk_type clk_type, char *buf)
 697 {
 698         struct amdgpu_device *adev = smu->adev;
 699         struct smu_table_context *table_context = &smu->smu_table;
 700         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 701         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 702         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 703         int i, size = 0, ret = 0;
 704         uint32_t cur_value = 0, value = 0, count = 0;
 705         uint32_t freq_values[3] = {0};
 706         uint32_t mark_index = 0;
 707         uint32_t gen_speed, lane_width;
 708
 709         switch (clk_type) {
 710         case SMU_GFXCLK:
 711         case SMU_SCLK:
 712         case SMU_SOCCLK:
 713         case SMU_MCLK:
 714         case SMU_UCLK:
 715         case SMU_FCLK:
 716         case SMU_DCEFCLK:
 717                 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
 718                 if (ret)
 719                         return size;
 720
 721                 /* 10KHz -> MHz */
 722                 cur_value = cur_value / 100;
 723
 724                 ret = smu_get_dpm_level_count(smu, clk_type, &count);
 725                 if (ret)
 726                         return size;
 727
 728                 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
 729                         for (i = 0; i < count; i++) {
 730                                 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
 731                                 if (ret)
 732                                         return size;
 733
 734                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 735                                                 cur_value == value ? "*" : "");
 736                         }
 737                 } else {
 738                         ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
 739                         if (ret)
 740                                 return size;
 741                         ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
 742                         if (ret)
 743                                 return size;
 744
 745                         freq_values[1] = cur_value;
 746                         mark_index = cur_value == freq_values[0] ? 0 :
 747                                      cur_value == freq_values[2] ? 2 : 1;
 748                         if (mark_index != 1)
 749                                 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
 750
 751                         for (i = 0; i < 3; i++) {
 752                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
 753                                                 i == mark_index ? "*" : "");
 754                         }
 755
 756                 }
 757                 break;
 758         case SMU_PCIE:
 759                 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
 760                              PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
 761                         >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
 762                 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
 763                               PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
 764                         >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
 765                 for (i = 0; i < NUM_LINK_LEVELS; i++)
 766                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
 767                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
 768                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
 769                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
 770                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
 771                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
 772                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
 773                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
 774                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
 775                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
 776                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
 777                                         pptable->LclkFreq[i],
 778                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
 779                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
 780                                         "*" : "");
 781                 break;
 782         default:
 783                 break;
 784         }
 785
 786         return size;
 787 }
 788
 789 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
 790                                    enum smu_clk_type clk_type, uint32_t mask)
 791 {
 792
 793         int ret = 0, size = 0;
 794         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
 795
 796         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 797         soft_max_level = mask ? (fls(mask) - 1) : 0;
 798
 799         switch (clk_type) {
 800         case SMU_GFXCLK:
 801         case SMU_SCLK:
 802         case SMU_SOCCLK:
 803         case SMU_MCLK:
 804         case SMU_UCLK:
 805         case SMU_DCEFCLK:
 806         case SMU_FCLK:
 807                 /* There is only 2 levels for fine grained DPM */
 808                 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
 809                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
 810                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
 811                 }
 812
 813                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
 814                 if (ret)
 815                         return size;
 816
 817                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
 818                 if (ret)
 819                         return size;
 820
 821                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
 822                 if (ret)
 823                         return size;
 824                 break;
 825         default:
 826                 break;
 827         }
 828
 829         return size;
 830 }
 831
 832 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
 833 {
 834         int ret = 0;
 835         uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
 836
 837         ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
 838         if (ret)
 839                 return ret;
 840
 841         smu->pstate_sclk = min_sclk_freq * 100;
 842
 843         ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
 844         if (ret)
 845                 return ret;
 846
 847         smu->pstate_mclk = min_mclk_freq * 100;
 848
 849         return ret;
 850 }
 851
 852 static int sienna_cichlid_get_clock_by_type_with_latency(struct smu_context *smu,
 853                                                  enum smu_clk_type clk_type,
 854                                                  struct pp_clock_levels_with_latency *clocks)
 855 {
 856         int ret = 0, i = 0;
 857         uint32_t level_count = 0, freq = 0;
 858
 859         switch (clk_type) {
 860         case SMU_GFXCLK:
 861         case SMU_DCEFCLK:
 862         case SMU_SOCCLK:
 863                 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
 864                 if (ret)
 865                         return ret;
 866
 867                 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
 868                 clocks->num_levels = level_count;
 869
 870                 for (i = 0; i < level_count; i++) {
 871                         ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
 872                         if (ret)
 873                                 return ret;
 874
 875                         clocks->data[i].clocks_in_khz = freq * 1000;
 876                         clocks->data[i].latency_in_us = 0;
 877                 }
 878                 break;
 879         default:
 880                 break;
 881         }
 882
 883         return ret;
 884 }
 885
 886 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
 887 {
 888         int ret = 0;
 889         uint32_t max_freq = 0;
 890
 891         /* Sienna_Cichlid do not support to change display num currently */
 892         return 0;
 893 #if 0
 894         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
 895         if (ret)
 896                 return ret;
 897 #endif
 898
 899         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 900                 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
 901                 if (ret)
 902                         return ret;
 903                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
 904                 if (ret)
 905                         return ret;
 906         }
 907
 908         return ret;
 909 }
 910
 911 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
 912 {
 913         int ret = 0;
 914
 915         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 916             !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 917                 ret = smu_write_watermarks_table(smu);
 918                 if (ret)
 919                         return ret;
 920
 921                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
 922         }
 923
 924         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 925             smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
 926             smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 927                 /* Sienna_Cichlid do not support to change display num currently */
 928                 ret = 0;
 929 #if 0
 930                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
 931                                                   smu->display_config->num_display, NULL);
 932 #endif
 933                 if (ret)
 934                         return ret;
 935         }
 936
 937         return ret;
 938 }
 939
 940 static int sienna_cichlid_force_dpm_limit_value(struct smu_context *smu, bool highest)
 941 {
 942         int ret = 0, i = 0;
 943         uint32_t min_freq, max_freq, force_freq;
 944         enum smu_clk_type clk_type;
 945
 946         enum smu_clk_type clks[] = {
 947                 SMU_GFXCLK,
 948                 SMU_MCLK,
 949                 SMU_SOCCLK,
 950         };
 951
 952         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 953                 clk_type = clks[i];
 954                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
 955                 if (ret)
 956                         return ret;
 957
 958                 force_freq = highest ? max_freq : min_freq;
 959                 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq, false);
 960                 if (ret)
 961                         return ret;
 962         }
 963
 964         return ret;
 965 }
 966
 967 static int sienna_cichlid_unforce_dpm_levels(struct smu_context *smu)
 968 {
 969         int ret = 0, i = 0;
 970         uint32_t min_freq, max_freq;
 971         enum smu_clk_type clk_type;
 972
 973         enum smu_clk_type clks[] = {
 974                 SMU_GFXCLK,
 975                 SMU_MCLK,
 976                 SMU_SOCCLK,
 977         };
 978
 979         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 980                 clk_type = clks[i];
 981                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
 982                 if (ret)
 983                         return ret;
 984
 985                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
 986                 if (ret)
 987                         return ret;
 988         }
 989
 990         return ret;
 991 }
 992
 993 static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)
 994 {
 995         int ret = 0;
 996         SmuMetrics_t metrics;
 997
 998         if (!value)
 999                 return -EINVAL;
1000
1001         ret = sienna_cichlid_get_metrics_table(smu, &metrics);
1002         if (ret)
1003                 return ret;
1004
1005         *value = metrics.AverageSocketPower << 8;
1006
1007         return 0;
1008 }
1009
1010 static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu,
1011                                                enum amd_pp_sensors sensor,
1012                                                uint32_t *value)
1013 {
1014         int ret = 0;
1015         SmuMetrics_t metrics;
1016
1017         if (!value)
1018                 return -EINVAL;
1019
1020         ret = sienna_cichlid_get_metrics_table(smu, &metrics);
1021         if (ret)
1022                 return ret;
1023
1024         switch (sensor) {
1025         case AMDGPU_PP_SENSOR_GPU_LOAD:
1026                 *value = metrics.AverageGfxActivity;
1027                 break;
1028         case AMDGPU_PP_SENSOR_MEM_LOAD:
1029                 *value = metrics.AverageUclkActivity;
1030                 break;
1031         default:
1032                 pr_err("Invalid sensor for retrieving clock activity\n");
1033                 return -EINVAL;
1034         }
1035
1036         return 0;
1037 }
1038
1039 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1040 {
1041         int ret = 0;
1042         uint32_t feature_mask[2];
1043         unsigned long feature_enabled;
1044         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1045         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1046                            ((uint64_t)feature_mask[1] << 32));
1047         return !!(feature_enabled & SMC_DPM_FEATURE);
1048 }
1049
1050 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1051                                     uint32_t *speed)
1052 {
1053         SmuMetrics_t metrics;
1054         int ret = 0;
1055
1056         if (!speed)
1057                 return -EINVAL;
1058
1059         ret = sienna_cichlid_get_metrics_table(smu, &metrics);
1060         if (ret)
1061                 return ret;
1062
1063         *speed = metrics.CurrFanSpeed;
1064
1065         return ret;
1066 }
1067
1068 static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu,
1069                                         uint32_t *speed)
1070 {
1071         int ret = 0;
1072         uint32_t percent = 0;
1073         uint32_t current_rpm;
1074         PPTable_t *pptable = smu->smu_table.driver_pptable;
1075
1076         ret = sienna_cichlid_get_fan_speed_rpm(smu, &current_rpm);
1077         if (ret)
1078                 return ret;
1079
1080         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1081         *speed = percent > 100 ? 100 : percent;
1082
1083         return ret;
1084 }
1085
1086 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1087 {
1088         DpmActivityMonitorCoeffInt_t activity_monitor;
1089         uint32_t i, size = 0;
1090         int16_t workload_type = 0;
1091         static const char *profile_name[] = {
1092                                         "BOOTUP_DEFAULT",
1093                                         "3D_FULL_SCREEN",
1094                                         "POWER_SAVING",
1095                                         "VIDEO",
1096                                         "VR",
1097                                         "COMPUTE",
1098                                         "CUSTOM"};
1099         static const char *title[] = {
1100                         "PROFILE_INDEX(NAME)",
1101                         "CLOCK_TYPE(NAME)",
1102                         "FPS",
1103                         "MinFreqType",
1104                         "MinActiveFreqType",
1105                         "MinActiveFreq",
1106                         "BoosterFreqType",
1107                         "BoosterFreq",
1108                         "PD_Data_limit_c",
1109                         "PD_Data_error_coeff",
1110                         "PD_Data_error_rate_coeff"};
1111         int result = 0;
1112
1113         if (!buf)
1114                 return -EINVAL;
1115
1116         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1117                         title[0], title[1], title[2], title[3], title[4], title[5],
1118                         title[6], title[7], title[8], title[9], title[10]);
1119
1120         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1121                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1122                 workload_type = smu_workload_get_type(smu, i);
1123                 if (workload_type < 0)
1124                         return -EINVAL;
1125
1126                 result = smu_update_table(smu,
1127                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1128                                           (void *)(&activity_monitor), false);
1129                 if (result) {
1130                         pr_err("[%s] Failed to get activity monitor!", __func__);
1131                         return result;
1132                 }
1133
1134                 size += sprintf(buf + size, "%2d %14s%s:\n",
1135                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1136
1137                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1138                         " ",
1139                         0,
1140                         "GFXCLK",
1141                         activity_monitor.Gfx_FPS,
1142                         activity_monitor.Gfx_MinFreqStep,
1143                         activity_monitor.Gfx_MinActiveFreqType,
1144                         activity_monitor.Gfx_MinActiveFreq,
1145                         activity_monitor.Gfx_BoosterFreqType,
1146                         activity_monitor.Gfx_BoosterFreq,
1147                         activity_monitor.Gfx_PD_Data_limit_c,
1148                         activity_monitor.Gfx_PD_Data_error_coeff,
1149                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1150
1151                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1152                         " ",
1153                         1,
1154                         "SOCCLK",
1155                         activity_monitor.Fclk_FPS,
1156                         activity_monitor.Fclk_MinFreqStep,
1157                         activity_monitor.Fclk_MinActiveFreqType,
1158                         activity_monitor.Fclk_MinActiveFreq,
1159                         activity_monitor.Fclk_BoosterFreqType,
1160                         activity_monitor.Fclk_BoosterFreq,
1161                         activity_monitor.Fclk_PD_Data_limit_c,
1162                         activity_monitor.Fclk_PD_Data_error_coeff,
1163                         activity_monitor.Fclk_PD_Data_error_rate_coeff);
1164
1165                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1166                         " ",
1167                         2,
1168                         "MEMLK",
1169                         activity_monitor.Mem_FPS,
1170                         activity_monitor.Mem_MinFreqStep,
1171                         activity_monitor.Mem_MinActiveFreqType,
1172                         activity_monitor.Mem_MinActiveFreq,
1173                         activity_monitor.Mem_BoosterFreqType,
1174                         activity_monitor.Mem_BoosterFreq,
1175                         activity_monitor.Mem_PD_Data_limit_c,
1176                         activity_monitor.Mem_PD_Data_error_coeff,
1177                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1178         }
1179
1180         return size;
1181 }
1182
1183 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1184 {
1185         DpmActivityMonitorCoeffInt_t activity_monitor;
1186         int workload_type, ret = 0;
1187
1188         smu->power_profile_mode = input[size];
1189
1190         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1191                 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1192                 return -EINVAL;
1193         }
1194
1195         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1196                 if (size < 0)
1197                         return -EINVAL;
1198
1199                 ret = smu_update_table(smu,
1200                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1201                                        (void *)(&activity_monitor), false);
1202                 if (ret) {
1203                         pr_err("[%s] Failed to get activity monitor!", __func__);
1204                         return ret;
1205                 }
1206
1207                 switch (input[0]) {
1208                 case 0: /* Gfxclk */
1209                         activity_monitor.Gfx_FPS = input[1];
1210                         activity_monitor.Gfx_MinFreqStep = input[2];
1211                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1212                         activity_monitor.Gfx_MinActiveFreq = input[4];
1213                         activity_monitor.Gfx_BoosterFreqType = input[5];
1214                         activity_monitor.Gfx_BoosterFreq = input[6];
1215                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1216                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1217                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1218                         break;
1219                 case 1: /* Socclk */
1220                         activity_monitor.Fclk_FPS = input[1];
1221                         activity_monitor.Fclk_MinFreqStep = input[2];
1222                         activity_monitor.Fclk_MinActiveFreqType = input[3];
1223                         activity_monitor.Fclk_MinActiveFreq = input[4];
1224                         activity_monitor.Fclk_BoosterFreqType = input[5];
1225                         activity_monitor.Fclk_BoosterFreq = input[6];
1226                         activity_monitor.Fclk_PD_Data_limit_c = input[7];
1227                         activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1228                         activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1229                         break;
1230                 case 2: /* Memlk */
1231                         activity_monitor.Mem_FPS = input[1];
1232                         activity_monitor.Mem_MinFreqStep = input[2];
1233                         activity_monitor.Mem_MinActiveFreqType = input[3];
1234                         activity_monitor.Mem_MinActiveFreq = input[4];
1235                         activity_monitor.Mem_BoosterFreqType = input[5];
1236                         activity_monitor.Mem_BoosterFreq = input[6];
1237                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1238                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1239                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1240                         break;
1241                 }
1242
1243                 ret = smu_update_table(smu,
1244                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1245                                        (void *)(&activity_monitor), true);
1246                 if (ret) {
1247                         pr_err("[%s] Failed to set activity monitor!", __func__);
1248                         return ret;
1249                 }
1250         }
1251
1252         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1253         workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1254         if (workload_type < 0)
1255                 return -EINVAL;
1256         smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1257                                     1 << workload_type, NULL);
1258
1259         return ret;
1260 }
1261
1262 static int sienna_cichlid_get_profiling_clk_mask(struct smu_context *smu,
1263                                          enum amd_dpm_forced_level level,
1264                                          uint32_t *sclk_mask,
1265                                          uint32_t *mclk_mask,
1266                                          uint32_t *soc_mask)
1267 {
1268         int ret = 0;
1269         uint32_t level_count = 0;
1270
1271         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1272                 if (sclk_mask)
1273                         *sclk_mask = 0;
1274         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1275                 if (mclk_mask)
1276                         *mclk_mask = 0;
1277         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1278                 if(sclk_mask) {
1279                         ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1280                         if (ret)
1281                                 return ret;
1282                         *sclk_mask = level_count - 1;
1283                 }
1284
1285                 if(mclk_mask) {
1286                         ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1287                         if (ret)
1288                                 return ret;
1289                         *mclk_mask = level_count - 1;
1290                 }
1291
1292                 if(soc_mask) {
1293                         ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1294                         if (ret)
1295                                 return ret;
1296                         *soc_mask = level_count - 1;
1297                 }
1298         }
1299
1300         return ret;
1301 }
1302
1303 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1304 {
1305         struct smu_clocks min_clocks = {0};
1306         struct pp_display_clock_request clock_req;
1307         int ret = 0;
1308
1309         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1310         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1311         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1312
1313         if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1314                 clock_req.clock_type = amd_pp_dcef_clock;
1315                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1316
1317                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1318                 if (!ret) {
1319                         if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1320                                 pr_err("Attempt to set divider for DCEFCLK Failed as it not support currently!");
1321                                 return ret;
1322                         }
1323                 } else {
1324                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1325                 }
1326         }
1327
1328         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1329                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1330                 if (ret) {
1331                         pr_err("[%s] Set hard min uclk failed!", __func__);
1332                         return ret;
1333                 }
1334         }
1335
1336         return 0;
1337 }
1338
1339 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1340                                        void *watermarks, struct
1341                                        dm_pp_wm_sets_with_clock_ranges_soc15
1342                                        *clock_ranges)
1343 {
1344         int i;
1345         Watermarks_t *table = watermarks;
1346
1347         if (!table || !clock_ranges)
1348                 return -EINVAL;
1349
1350         if (clock_ranges->num_wm_dmif_sets > 4 ||
1351             clock_ranges->num_wm_mcif_sets > 4)
1352                 return -EINVAL;
1353
1354         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1355                 table->WatermarkRow[1][i].MinClock =
1356                         cpu_to_le16((uint16_t)
1357                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1358                         1000));
1359                 table->WatermarkRow[1][i].MaxClock =
1360                         cpu_to_le16((uint16_t)
1361                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1362                         1000));
1363                 table->WatermarkRow[1][i].MinUclk =
1364                         cpu_to_le16((uint16_t)
1365                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1366                         1000));
1367                 table->WatermarkRow[1][i].MaxUclk =
1368                         cpu_to_le16((uint16_t)
1369                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1370                         1000));
1371                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1372                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1373         }
1374
1375         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1376                 table->WatermarkRow[0][i].MinClock =
1377                         cpu_to_le16((uint16_t)
1378                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1379                         1000));
1380                 table->WatermarkRow[0][i].MaxClock =
1381                         cpu_to_le16((uint16_t)
1382                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1383                         1000));
1384                 table->WatermarkRow[0][i].MinUclk =
1385                         cpu_to_le16((uint16_t)
1386                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1387                         1000));
1388                 table->WatermarkRow[0][i].MaxUclk =
1389                         cpu_to_le16((uint16_t)
1390                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1391                         1000));
1392                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1393                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1394         }
1395
1396         return 0;
1397 }
1398
1399 static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu,
1400                                              enum amd_pp_sensors sensor,
1401                                              uint32_t *value)
1402 {
1403         SmuMetrics_t metrics;
1404         int ret = 0;
1405
1406         if (!value)
1407                 return -EINVAL;
1408
1409         ret = sienna_cichlid_get_metrics_table(smu, &metrics);
1410         if (ret)
1411                 return ret;
1412
1413         switch (sensor) {
1414         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1415                 *value = metrics.TemperatureHotspot *
1416                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1417                 break;
1418         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1419                 *value = metrics.TemperatureEdge *
1420                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1421                 break;
1422         case AMDGPU_PP_SENSOR_MEM_TEMP:
1423                 *value = metrics.TemperatureMem *
1424                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1425                 break;
1426         default:
1427                 pr_err("Invalid sensor for retrieving temp\n");
1428                 return -EINVAL;
1429         }
1430
1431         return 0;
1432 }
1433
1434 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1435                                  enum amd_pp_sensors sensor,
1436                                  void *data, uint32_t *size)
1437 {
1438         int ret = 0;
1439         struct smu_table_context *table_context = &smu->smu_table;
1440         PPTable_t *pptable = table_context->driver_pptable;
1441
1442         if(!data || !size)
1443                 return -EINVAL;
1444
1445         mutex_lock(&smu->sensor_lock);
1446         switch (sensor) {
1447         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1448                 *(uint32_t *)data = pptable->FanMaximumRpm;
1449                 *size = 4;
1450                 break;
1451         case AMDGPU_PP_SENSOR_MEM_LOAD:
1452         case AMDGPU_PP_SENSOR_GPU_LOAD:
1453                 ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1454                 *size = 4;
1455                 break;
1456         case AMDGPU_PP_SENSOR_GPU_POWER:
1457                 ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data);
1458                 *size = 4;
1459                 break;
1460         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1461         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1462         case AMDGPU_PP_SENSOR_MEM_TEMP:
1463                 ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1464                 *size = 4;
1465                 break;
1466         default:
1467                 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1468         }
1469         mutex_unlock(&smu->sensor_lock);
1470
1471         return ret;
1472 }
1473
1474 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1475 {
1476         uint32_t num_discrete_levels = 0;
1477         uint16_t *dpm_levels = NULL;
1478         uint16_t i = 0;
1479         struct smu_table_context *table_context = &smu->smu_table;
1480         PPTable_t *driver_ppt = NULL;
1481
1482         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1483                 return -EINVAL;
1484
1485         driver_ppt = table_context->driver_pptable;
1486         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1487         dpm_levels = driver_ppt->FreqTableUclk;
1488
1489         if (num_discrete_levels == 0 || dpm_levels == NULL)
1490                 return -EINVAL;
1491
1492         *num_states = num_discrete_levels;
1493         for (i = 0; i < num_discrete_levels; i++) {
1494                 /* convert to khz */
1495                 *clocks_in_khz = (*dpm_levels) * 1000;
1496                 clocks_in_khz++;
1497                 dpm_levels++;
1498         }
1499
1500         return 0;
1501 }
1502
1503 static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1504                                         enum amd_dpm_forced_level level);
1505
1506 static int sienna_cichlid_set_standard_performance_level(struct smu_context *smu)
1507 {
1508         struct amdgpu_device *adev = smu->adev;
1509         int ret = 0;
1510         uint32_t sclk_freq = 0, uclk_freq = 0;
1511
1512         switch (adev->asic_type) {
1513         /* TODO: need to set specify clk value by asic type, not support yet*/
1514         default:
1515                 /* by default, this is same as auto performance level */
1516                 return sienna_cichlid_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
1517         }
1518
1519         ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
1520         if (ret)
1521                 return ret;
1522         ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
1523         if (ret)
1524                 return ret;
1525
1526         return ret;
1527 }
1528
1529 static int sienna_cichlid_set_peak_performance_level(struct smu_context *smu)
1530 {
1531         int ret = 0;
1532
1533         /* TODO: not support yet*/
1534         return ret;
1535 }
1536
1537 static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1538                                         enum amd_dpm_forced_level level)
1539 {
1540         int ret = 0;
1541         uint32_t sclk_mask, mclk_mask, soc_mask;
1542
1543         switch (level) {
1544         case AMD_DPM_FORCED_LEVEL_HIGH:
1545                 ret = smu_force_dpm_limit_value(smu, true);
1546                 break;
1547         case AMD_DPM_FORCED_LEVEL_LOW:
1548                 ret = smu_force_dpm_limit_value(smu, false);
1549                 break;
1550         case AMD_DPM_FORCED_LEVEL_AUTO:
1551                 ret = smu_unforce_dpm_levels(smu);
1552                 break;
1553         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1554                 ret = sienna_cichlid_set_standard_performance_level(smu);
1555                 break;
1556         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1557         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1558                 ret = smu_get_profiling_clk_mask(smu, level,
1559                                                  &sclk_mask,
1560                                                  &mclk_mask,
1561                                                  &soc_mask);
1562                 if (ret)
1563                         return ret;
1564                 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1565                 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1566                 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1567                 break;
1568         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1569                 ret = sienna_cichlid_set_peak_performance_level(smu);
1570                 break;
1571         case AMD_DPM_FORCED_LEVEL_MANUAL:
1572         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1573         default:
1574                 break;
1575         }
1576         return ret;
1577 }
1578
1579 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1580                                                 struct smu_temperature_range *range)
1581 {
1582         struct smu_table_context *table_context = &smu->smu_table;
1583         struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1584
1585         if (!range || !powerplay_table)
1586                 return -EINVAL;
1587
1588         range->max = powerplay_table->software_shutdown_temp *
1589                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1590
1591         return 0;
1592 }
1593
1594 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1595                                                 bool disable_memory_clock_switch)
1596 {
1597         int ret = 0;
1598         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1599                 (struct smu_11_0_max_sustainable_clocks *)
1600                         smu->smu_table.max_sustainable_clocks;
1601         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1602         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1603
1604         if(smu->disable_uclk_switch == disable_memory_clock_switch)
1605                 return 0;
1606
1607         if(disable_memory_clock_switch)
1608                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
1609         else
1610                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
1611
1612         if(!ret)
1613                 smu->disable_uclk_switch = disable_memory_clock_switch;
1614
1615         return ret;
1616 }
1617
1618 static uint32_t sienna_cichlid_get_pptable_power_limit(struct smu_context *smu)
1619 {
1620         PPTable_t *pptable = smu->smu_table.driver_pptable;
1621         return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1622 }
1623
1624 static int sienna_cichlid_get_power_limit(struct smu_context *smu,
1625                                      uint32_t *limit,
1626                                      bool cap)
1627 {
1628         PPTable_t *pptable = smu->smu_table.driver_pptable;
1629         uint32_t asic_default_power_limit = 0;
1630         int ret = 0;
1631         int power_src;
1632
1633         if (!smu->power_limit) {
1634                 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1635                         power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1636                         if (power_src < 0)
1637                                 return -EINVAL;
1638
1639                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1640                                                           power_src << 16, &asic_default_power_limit);
1641                         if (ret) {
1642                                 pr_err("[%s] get PPT limit failed!", __func__);
1643                                 return ret;
1644                         }
1645                 } else {
1646                         /* the last hope to figure out the ppt limit */
1647                         if (!pptable) {
1648                                 pr_err("Cannot get PPT limit due to pptable missing!");
1649                                 return -EINVAL;
1650                         }
1651                         asic_default_power_limit =
1652                                 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1653                 }
1654
1655                 smu->power_limit = asic_default_power_limit;
1656         }
1657
1658         if (cap)
1659                 *limit = smu_v11_0_get_max_power_limit(smu);
1660         else
1661                 *limit = smu->power_limit;
1662
1663         return 0;
1664 }
1665
1666 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1667                                          uint32_t pcie_gen_cap,
1668                                          uint32_t pcie_width_cap)
1669 {
1670         PPTable_t *pptable = smu->smu_table.driver_pptable;
1671         int ret, i;
1672         uint32_t smu_pcie_arg;
1673
1674         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1675         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1676
1677         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1678                 smu_pcie_arg = (i << 16) |
1679                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ?
1680                                         (pptable->PcieGenSpeed[i] << 8) :
1681                                         (pcie_gen_cap << 8)) |
1682                         ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1683                                         pptable->PcieLaneCount[i] :
1684                                         pcie_width_cap);
1685
1686                 ret = smu_send_smc_msg_with_param(smu,
1687                                                   SMU_MSG_OverridePcieParameters,
1688                                                   smu_pcie_arg, NULL);
1689                 if (ret)
1690                         return ret;
1691
1692                 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1693                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1694                 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1695                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1696         }
1697
1698         return 0;
1699 }
1700
1701 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
1702 {
1703         struct smu_table_context *table_context = &smu->smu_table;
1704         PPTable_t *pptable = table_context->driver_pptable;
1705         int i;
1706
1707         pr_info("Dumped PPTable:\n");
1708
1709         pr_info("Version = 0x%08x\n", pptable->Version);
1710         pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1711         pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1712
1713         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1714                 pr_info("SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
1715                 pr_info("SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
1716                 pr_info("SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
1717                 pr_info("SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
1718         }
1719
1720         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
1721                 pr_info("TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
1722                 pr_info("TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
1723         }
1724
1725         for (i = 0; i < TEMP_COUNT; i++) {
1726                 pr_info("TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
1727         }
1728
1729         pr_info("FitLimit = 0x%x\n", pptable->FitLimit);
1730         pr_info("TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
1731         pr_info("TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
1732         pr_info("TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
1733         pr_info("TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
1734
1735         pr_info("ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
1736         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
1737                 pr_info("SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
1738                 pr_info("SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
1739         }
1740         pr_info("PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]);
1741         pr_info("PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]);
1742         pr_info("PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]);
1743         pr_info("PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]);
1744
1745         pr_info("ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
1746
1747         pr_info("FwDStateMask = 0x%x\n", pptable->FwDStateMask);
1748
1749         pr_info("UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
1750         pr_info("UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
1751         pr_info("MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
1752         pr_info("MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
1753
1754         pr_info("SocLIVmin = 0x%x\n", pptable->SocLIVmin);
1755         pr_info("PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
1756
1757         pr_info("GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
1758         pr_info("paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
1759         pr_info("paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
1760         pr_info("paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
1761
1762         pr_info("MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
1763         pr_info("MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
1764         pr_info("MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
1765         pr_info("MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
1766
1767         pr_info("LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
1768         pr_info("LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
1769
1770         pr_info("VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
1771         pr_info("VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
1772         pr_info("VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
1773         pr_info("VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
1774         pr_info("VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
1775         pr_info("VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
1776         pr_info("VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
1777         pr_info("VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
1778
1779         pr_info("[PPCLK_GFXCLK]\n"
1780                         "  .VoltageMode          = 0x%02x\n"
1781                         "  .SnapToDiscrete       = 0x%02x\n"
1782                         "  .NumDiscreteLevels    = 0x%02x\n"
1783                         "  .padding              = 0x%02x\n"
1784                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1785                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1786                         "  .SsFmin               = 0x%04x\n"
1787                         "  .Padding_16           = 0x%04x\n",
1788                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1789                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1790                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1791                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
1792                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1793                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1794                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1795                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1796                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1797                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1798                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1799
1800         pr_info("[PPCLK_SOCCLK]\n"
1801                         "  .VoltageMode          = 0x%02x\n"
1802                         "  .SnapToDiscrete       = 0x%02x\n"
1803                         "  .NumDiscreteLevels    = 0x%02x\n"
1804                         "  .padding              = 0x%02x\n"
1805                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1806                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1807                         "  .SsFmin               = 0x%04x\n"
1808                         "  .Padding_16           = 0x%04x\n",
1809                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1810                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1811                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1812                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
1813                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1814                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1815                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1816                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1817                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1818                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1819                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1820
1821         pr_info("[PPCLK_UCLK]\n"
1822                         "  .VoltageMode          = 0x%02x\n"
1823                         "  .SnapToDiscrete       = 0x%02x\n"
1824                         "  .NumDiscreteLevels    = 0x%02x\n"
1825                         "  .padding              = 0x%02x\n"
1826                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1827                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1828                         "  .SsFmin               = 0x%04x\n"
1829                         "  .Padding_16           = 0x%04x\n",
1830                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1831                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1832                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1833                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
1834                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1835                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1836                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1837                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1838                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1839                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1840                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1841
1842         pr_info("[PPCLK_FCLK]\n"
1843                         "  .VoltageMode          = 0x%02x\n"
1844                         "  .SnapToDiscrete       = 0x%02x\n"
1845                         "  .NumDiscreteLevels    = 0x%02x\n"
1846                         "  .padding              = 0x%02x\n"
1847                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1848                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1849                         "  .SsFmin               = 0x%04x\n"
1850                         "  .Padding_16           = 0x%04x\n",
1851                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1852                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1853                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1854                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
1855                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1856                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1857                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1858                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1859                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1860                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1861                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1862
1863         pr_info("[PPCLK_DCLK_0]\n"
1864                         "  .VoltageMode          = 0x%02x\n"
1865                         "  .SnapToDiscrete       = 0x%02x\n"
1866                         "  .NumDiscreteLevels    = 0x%02x\n"
1867                         "  .padding              = 0x%02x\n"
1868                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1869                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1870                         "  .SsFmin               = 0x%04x\n"
1871                         "  .Padding_16           = 0x%04x\n",
1872                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
1873                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
1874                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
1875                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
1876                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
1877                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
1878                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
1879                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
1880                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
1881                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
1882                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
1883
1884         pr_info("[PPCLK_VCLK_0]\n"
1885                         "  .VoltageMode          = 0x%02x\n"
1886                         "  .SnapToDiscrete       = 0x%02x\n"
1887                         "  .NumDiscreteLevels    = 0x%02x\n"
1888                         "  .padding              = 0x%02x\n"
1889                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1890                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1891                         "  .SsFmin               = 0x%04x\n"
1892                         "  .Padding_16           = 0x%04x\n",
1893                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
1894                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
1895                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
1896                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
1897                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
1898                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
1899                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
1900                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
1901                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
1902                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
1903                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
1904
1905         pr_info("[PPCLK_DCLK_1]\n"
1906                         "  .VoltageMode          = 0x%02x\n"
1907                         "  .SnapToDiscrete       = 0x%02x\n"
1908                         "  .NumDiscreteLevels    = 0x%02x\n"
1909                         "  .padding              = 0x%02x\n"
1910                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1911                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1912                         "  .SsFmin               = 0x%04x\n"
1913                         "  .Padding_16           = 0x%04x\n",
1914                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
1915                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
1916                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
1917                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
1918                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
1919                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
1920                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
1921                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
1922                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
1923                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
1924                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
1925
1926         pr_info("[PPCLK_VCLK_1]\n"
1927                         "  .VoltageMode          = 0x%02x\n"
1928                         "  .SnapToDiscrete       = 0x%02x\n"
1929                         "  .NumDiscreteLevels    = 0x%02x\n"
1930                         "  .padding              = 0x%02x\n"
1931                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1932                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1933                         "  .SsFmin               = 0x%04x\n"
1934                         "  .Padding_16           = 0x%04x\n",
1935                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
1936                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
1937                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
1938                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
1939                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
1940                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
1941                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
1942                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
1943                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
1944                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
1945                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
1946
1947         pr_info("FreqTableGfx\n");
1948         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1949                 pr_info("  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
1950
1951         pr_info("FreqTableVclk\n");
1952         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1953                 pr_info("  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
1954
1955         pr_info("FreqTableDclk\n");
1956         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1957                 pr_info("  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
1958
1959         pr_info("FreqTableSocclk\n");
1960         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1961                 pr_info("  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
1962
1963         pr_info("FreqTableUclk\n");
1964         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1965                 pr_info("  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
1966
1967         pr_info("FreqTableFclk\n");
1968         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1969                 pr_info("  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
1970
1971         pr_info("Paddingclks[0] = 0x%x\n",  pptable->Paddingclks[0]);
1972         pr_info("Paddingclks[1] = 0x%x\n",  pptable->Paddingclks[1]);
1973         pr_info("Paddingclks[2] = 0x%x\n",  pptable->Paddingclks[2]);
1974         pr_info("Paddingclks[3] = 0x%x\n",  pptable->Paddingclks[3]);
1975         pr_info("Paddingclks[4] = 0x%x\n",  pptable->Paddingclks[4]);
1976         pr_info("Paddingclks[5] = 0x%x\n",  pptable->Paddingclks[5]);
1977         pr_info("Paddingclks[6] = 0x%x\n",  pptable->Paddingclks[6]);
1978         pr_info("Paddingclks[7] = 0x%x\n",  pptable->Paddingclks[7]);
1979         pr_info("Paddingclks[8] = 0x%x\n",  pptable->Paddingclks[8]);
1980         pr_info("Paddingclks[9] = 0x%x\n",  pptable->Paddingclks[9]);
1981         pr_info("Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]);
1982         pr_info("Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]);
1983         pr_info("Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]);
1984         pr_info("Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]);
1985         pr_info("Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]);
1986         pr_info("Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]);
1987
1988         pr_info("DcModeMaxFreq\n");
1989         pr_info("  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
1990         pr_info("  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
1991         pr_info("  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
1992         pr_info("  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
1993         pr_info("  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
1994         pr_info("  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
1995         pr_info("  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
1996         pr_info("  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
1997
1998         pr_info("FreqTableUclkDiv\n");
1999         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2000                 pr_info("  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2001
2002         pr_info("FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2003         pr_info("FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2004
2005         pr_info("Mp0clkFreq\n");
2006         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2007                 pr_info("  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2008
2009         pr_info("Mp0DpmVoltage\n");
2010         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2011                 pr_info("  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2012
2013         pr_info("MemVddciVoltage\n");
2014         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2015                 pr_info("  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2016
2017         pr_info("MemMvddVoltage\n");
2018         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2019                 pr_info("  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2020
2021         pr_info("GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2022         pr_info("GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2023         pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2024         pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2025         pr_info("GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2026
2027         pr_info("GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2028
2029         pr_info("GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2030         pr_info("GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2031         pr_info("GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2032         pr_info("GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2033         pr_info("GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2034         pr_info("GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2035         pr_info("GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2036         pr_info("GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2037         pr_info("GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2038         pr_info("GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2039         pr_info("GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2040
2041         pr_info("DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2042         pr_info("DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2043         pr_info("DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2044         pr_info("DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2045         pr_info("DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2046         pr_info("DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2047
2048         pr_info("DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2049         pr_info("DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2050         pr_info("DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2051         pr_info("DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2052         pr_info("DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2053
2054         pr_info("FlopsPerByteTable\n");
2055         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2056                 pr_info("  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2057
2058         pr_info("LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2059         pr_info("vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2060         pr_info("vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2061         pr_info("vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2062
2063         pr_info("UclkDpmPstates\n");
2064         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2065                 pr_info("  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2066
2067         pr_info("UclkDpmSrcFreqRange\n");
2068         pr_info("  .Fmin = 0x%x\n",
2069                 pptable->UclkDpmSrcFreqRange.Fmin);
2070         pr_info("  .Fmax = 0x%x\n",
2071                 pptable->UclkDpmSrcFreqRange.Fmax);
2072         pr_info("UclkDpmTargFreqRange\n");
2073         pr_info("  .Fmin = 0x%x\n",
2074                 pptable->UclkDpmTargFreqRange.Fmin);
2075         pr_info("  .Fmax = 0x%x\n",
2076                 pptable->UclkDpmTargFreqRange.Fmax);
2077         pr_info("UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2078         pr_info("UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2079
2080         pr_info("PcieGenSpeed\n");
2081         for (i = 0; i < NUM_LINK_LEVELS; i++)
2082                 pr_info("  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2083
2084         pr_info("PcieLaneCount\n");
2085         for (i = 0; i < NUM_LINK_LEVELS; i++)
2086                 pr_info("  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2087
2088         pr_info("LclkFreq\n");
2089         for (i = 0; i < NUM_LINK_LEVELS; i++)
2090                 pr_info("  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2091
2092         pr_info("FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2093         pr_info("FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2094
2095         pr_info("FanGain\n");
2096         for (i = 0; i < TEMP_COUNT; i++)
2097                 pr_info("  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2098
2099         pr_info("FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2100         pr_info("FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2101         pr_info("FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2102         pr_info("FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2103         pr_info("MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2104         pr_info("FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2105         pr_info("FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2106         pr_info("FanPadding16 = 0x%x\n", pptable->FanPadding16);
2107         pr_info("FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2108         pr_info("FanPadding = 0x%x\n", pptable->FanPadding);
2109         pr_info("FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2110         pr_info("FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2111
2112         pr_info("FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2113         pr_info("FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2114         pr_info("FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2115         pr_info("FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2116
2117         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2118         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2119         pr_info("dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2120         pr_info("Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2121
2122         pr_info("qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2123                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2124                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2125                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2126         pr_info("qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2127                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2128                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2129                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2130         pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2131                         pptable->dBtcGbGfxPll.a,
2132                         pptable->dBtcGbGfxPll.b,
2133                         pptable->dBtcGbGfxPll.c);
2134         pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2135                         pptable->dBtcGbGfxDfll.a,
2136                         pptable->dBtcGbGfxDfll.b,
2137                         pptable->dBtcGbGfxDfll.c);
2138         pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2139                         pptable->dBtcGbSoc.a,
2140                         pptable->dBtcGbSoc.b,
2141                         pptable->dBtcGbSoc.c);
2142         pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2143                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2144                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2145         pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2146                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2147                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2148
2149         pr_info("PiecewiseLinearDroopIntGfxDfll\n");
2150         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2151                 pr_info("               Fset[%d] = 0x%x\n",
2152                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2153                 pr_info("               Vdroop[%d] = 0x%x\n",
2154                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2155         }
2156
2157         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2158                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2159                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2160                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2161         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2162                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2163                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2164                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2165
2166         pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2167         pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2168
2169         pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2170         pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2171         pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2172         pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2173
2174         pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2175         pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2176         pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2177         pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2178
2179         pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2180         pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2181
2182         pr_info("XgmiDpmPstates\n");
2183         for (i = 0; i < NUM_XGMI_LEVELS; i++)
2184                 pr_info("  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2185         pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2186         pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2187
2188         pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2189         pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2190                         pptable->ReservedEquation0.a,
2191                         pptable->ReservedEquation0.b,
2192                         pptable->ReservedEquation0.c);
2193         pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2194                         pptable->ReservedEquation1.a,
2195                         pptable->ReservedEquation1.b,
2196                         pptable->ReservedEquation1.c);
2197         pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2198                         pptable->ReservedEquation2.a,
2199                         pptable->ReservedEquation2.b,
2200                         pptable->ReservedEquation2.c);
2201         pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2202                         pptable->ReservedEquation3.a,
2203                         pptable->ReservedEquation3.b,
2204                         pptable->ReservedEquation3.c);
2205
2206         pr_info("SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2207         pr_info("SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2208         pr_info("SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2209         pr_info("SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2210         pr_info("SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2211         pr_info("SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2212         pr_info("SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2213         pr_info("SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2214         pr_info("SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]);
2215         pr_info("SkuReserved[9] = 0x%x\n", pptable->SkuReserved[9]);
2216         pr_info("SkuReserved[10] = 0x%x\n", pptable->SkuReserved[10]);
2217         pr_info("SkuReserved[11] = 0x%x\n", pptable->SkuReserved[11]);
2218         pr_info("SkuReserved[12] = 0x%x\n", pptable->SkuReserved[12]);
2219         pr_info("SkuReserved[13] = 0x%x\n", pptable->SkuReserved[13]);
2220         pr_info("SkuReserved[14] = 0x%x\n", pptable->SkuReserved[14]);
2221
2222         pr_info("GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2223         pr_info("GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2224         pr_info("GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2225         pr_info("GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2226         pr_info("GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2227         pr_info("GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2228
2229         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2230                 pr_info("I2cControllers[%d]:\n", i);
2231                 pr_info("                   .Enabled = 0x%x\n",
2232                                 pptable->I2cControllers[i].Enabled);
2233                 pr_info("                   .Speed = 0x%x\n",
2234                                 pptable->I2cControllers[i].Speed);
2235                 pr_info("                   .SlaveAddress = 0x%x\n",
2236                                 pptable->I2cControllers[i].SlaveAddress);
2237                 pr_info("                   .ControllerPort = 0x%x\n",
2238                                 pptable->I2cControllers[i].ControllerPort);
2239                 pr_info("                   .ControllerName = 0x%x\n",
2240                                 pptable->I2cControllers[i].ControllerName);
2241                 pr_info("                   .ThermalThrottler = 0x%x\n",
2242                                 pptable->I2cControllers[i].ThermalThrotter);
2243                 pr_info("                   .I2cProtocol = 0x%x\n",
2244                                 pptable->I2cControllers[i].I2cProtocol);
2245                 pr_info("                   .PaddingConfig = 0x%x\n",
2246                                 pptable->I2cControllers[i].PaddingConfig);
2247         }
2248
2249         pr_info("GpioScl = 0x%x\n", pptable->GpioScl);
2250         pr_info("GpioSda = 0x%x\n", pptable->GpioSda);
2251         pr_info("FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2252         pr_info("I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2253
2254         pr_info("Board Parameters:\n");
2255         pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2256         pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2257         pr_info("VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2258         pr_info("VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2259         pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2260         pr_info("SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2261         pr_info("VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2262         pr_info("MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2263
2264         pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2265         pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
2266         pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2267
2268         pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2269         pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
2270         pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2271
2272         pr_info("Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2273         pr_info("Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2274         pr_info("Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2275
2276         pr_info("Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2277         pr_info("Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2278         pr_info("Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2279
2280         pr_info("MvddRatio = 0x%x\n", pptable->MvddRatio);
2281
2282         pr_info("AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2283         pr_info("AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2284         pr_info("VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2285         pr_info("VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2286         pr_info("VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2287         pr_info("VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2288         pr_info("GthrGpio = 0x%x\n", pptable->GthrGpio);
2289         pr_info("GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2290         pr_info("LedPin0 = 0x%x\n", pptable->LedPin0);
2291         pr_info("LedPin1 = 0x%x\n", pptable->LedPin1);
2292         pr_info("LedPin2 = 0x%x\n", pptable->LedPin2);
2293         pr_info("LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2294         pr_info("LedPcie = 0x%x\n", pptable->LedPcie);
2295         pr_info("LedError = 0x%x\n", pptable->LedError);
2296         pr_info("LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2297         pr_info("LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2298
2299         pr_info("PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2300         pr_info("PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2301         pr_info("PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
2302
2303         pr_info("DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2304         pr_info("DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2305         pr_info("DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
2306
2307         pr_info("UclkSpreadEnabled = 0x%x\n", pptable->UclkSpreadEnabled);
2308         pr_info("UclkSpreadPercent = 0x%x\n", pptable->UclkSpreadPercent);
2309         pr_info("UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2310
2311         pr_info("FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2312         pr_info("FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2313         pr_info("FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2314
2315         pr_info("MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2316         pr_info("DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2317         pr_info("PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2318         pr_info("PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2319         pr_info("PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2320
2321         pr_info("TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2322         pr_info("BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2323
2324         pr_info("XgmiLinkSpeed\n");
2325         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2326                 pr_info("  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2327         pr_info("XgmiLinkWidth\n");
2328         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2329                 pr_info("  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2330         pr_info("XgmiFclkFreq\n");
2331         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2332                 pr_info("  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2333         pr_info("XgmiSocVoltage\n");
2334         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2335                 pr_info("  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2336
2337         pr_info("HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2338         pr_info("VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2339         pr_info("PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2340         pr_info("PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2341
2342         pr_info("BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2343         pr_info("BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2344         pr_info("BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2345         pr_info("BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2346         pr_info("BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2347         pr_info("BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2348         pr_info("BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2349         pr_info("BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2350         pr_info("BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2351         pr_info("BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2352         pr_info("BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2353         pr_info("BoardReserved[11] = 0x%x\n", pptable->BoardReserved[11]);
2354         pr_info("BoardReserved[12] = 0x%x\n", pptable->BoardReserved[12]);
2355         pr_info("BoardReserved[13] = 0x%x\n", pptable->BoardReserved[13]);
2356         pr_info("BoardReserved[14] = 0x%x\n", pptable->BoardReserved[14]);
2357
2358         pr_info("MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2359         pr_info("MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2360         pr_info("MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2361         pr_info("MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2362         pr_info("MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2363         pr_info("MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2364         pr_info("MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2365         pr_info("MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2366 }
2367
2368 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
2369         .tables_init = sienna_cichlid_tables_init,
2370         .alloc_dpm_context = sienna_cichlid_allocate_dpm_context,
2371         .store_powerplay_table = sienna_cichlid_store_powerplay_table,
2372         .check_powerplay_table = sienna_cichlid_check_powerplay_table,
2373         .append_powerplay_table = sienna_cichlid_append_powerplay_table,
2374         .get_smu_msg_index = sienna_cichlid_get_smu_msg_index,
2375         .get_smu_clk_index = sienna_cichlid_get_smu_clk_index,
2376         .get_smu_feature_index = sienna_cichlid_get_smu_feature_index,
2377         .get_smu_table_index = sienna_cichlid_get_smu_table_index,
2378         .get_smu_power_index = sienna_cichlid_get_pwr_src_index,
2379         .get_workload_type = sienna_cichlid_get_workload_type,
2380         .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
2381         .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
2382         .dpm_set_uvd_enable = sienna_cichlid_dpm_set_uvd_enable,
2383         .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
2384         .get_current_clk_freq_by_table = sienna_cichlid_get_current_clk_freq_by_table,
2385         .print_clk_levels = sienna_cichlid_print_clk_levels,
2386         .force_clk_levels = sienna_cichlid_force_clk_levels,
2387         .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
2388         .get_clock_by_type_with_latency = sienna_cichlid_get_clock_by_type_with_latency,
2389         .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
2390         .display_config_changed = sienna_cichlid_display_config_changed,
2391         .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
2392         .force_dpm_limit_value = sienna_cichlid_force_dpm_limit_value,
2393         .unforce_dpm_levels = sienna_cichlid_unforce_dpm_levels,
2394         .is_dpm_running = sienna_cichlid_is_dpm_running,
2395         .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent,
2396         .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
2397         .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
2398         .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
2399         .get_profiling_clk_mask = sienna_cichlid_get_profiling_clk_mask,
2400         .set_watermarks_table = sienna_cichlid_set_watermarks_table,
2401         .read_sensor = sienna_cichlid_read_sensor,
2402         .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
2403         .set_performance_level = sienna_cichlid_set_performance_level,
2404         .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
2405         .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
2406         .get_power_limit = sienna_cichlid_get_power_limit,
2407         .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
2408         .dump_pptable = sienna_cichlid_dump_pptable,
2409         .init_microcode = smu_v11_0_init_microcode,
2410         .load_microcode = smu_v11_0_load_microcode,
2411         .init_smc_tables = smu_v11_0_init_smc_tables,
2412         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2413         .init_power = smu_v11_0_init_power,
2414         .fini_power = smu_v11_0_fini_power,
2415         .check_fw_status = smu_v11_0_check_fw_status,
2416         .setup_pptable = smu_v11_0_setup_pptable,
2417         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2418         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2419         .check_pptable = smu_v11_0_check_pptable,
2420         .parse_pptable = smu_v11_0_parse_pptable,
2421         .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2422         .check_fw_version = smu_v11_0_check_fw_version,
2423         .write_pptable = smu_v11_0_write_pptable,
2424         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2425         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2426         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2427         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2428         .system_features_control = smu_v11_0_system_features_control,
2429         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2430         .init_display_count = smu_v11_0_init_display_count,
2431         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2432         .get_enabled_mask = smu_v11_0_get_enabled_mask,
2433         .notify_display_change = smu_v11_0_notify_display_change,
2434         .set_power_limit = smu_v11_0_set_power_limit,
2435         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2436         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2437         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2438         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2439         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2440         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2441         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2442         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2443         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2444         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2445         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2446         .gfx_off_control = smu_v11_0_gfx_off_control,
2447         .register_irq_handler = smu_v11_0_register_irq_handler,
2448         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2449         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2450         .baco_is_support= smu_v11_0_baco_is_support,
2451         .baco_get_state = smu_v11_0_baco_get_state,
2452         .baco_set_state = smu_v11_0_baco_set_state,
2453         .baco_enter = smu_v11_0_baco_enter,
2454         .baco_exit = smu_v11_0_baco_exit,
2455         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2456         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2457         .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2458         .get_pptable_power_limit = sienna_cichlid_get_pptable_power_limit,
2459 };
2460
2461 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
2462 {
2463         smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
2464 }