drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include <linux/pci.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "smu_internal.h"
  30 #include "atomfirmware.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "smu_v11_0.h"
  33 #include "smu11_driver_if_sienna_cichlid.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "sienna_cichlid_ppt.h"
  37 #include "smu_v11_0_pptable.h"
  38 #include "smu_v11_0_7_ppsmc.h"
  39
  40 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  41
  42 #define FEATURE_MASK(feature) (1ULL << feature)
  43 #define SMC_DPM_FEATURE ( \
  44         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  45         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  46         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  47         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  48         FEATURE_MASK(FEATURE_DPM_FCLK_BIT))
  49
  50 #define MSG_MAP(msg, index) \
  51         [SMU_MSG_##msg] = {1, (index)}
  52
  53 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
  54         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
  55         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
  56         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion),
  57         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow),
  58         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  59         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures),
  60         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures),
  61         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow),
  62         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh),
  63         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow),
  64         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh),
  65         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow),
  66         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh),
  67         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask),
  68         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit),
  69         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh),
  70         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow),
  71         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh),
  72         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow),
  73         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram),
  74         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu),
  75         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable),
  76         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco),
  77         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq),
  78         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq),
  79         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq),
  80         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq),
  81         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq),
  82         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq),
  83         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex),
  84         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode),
  85         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh),
  86         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow),
  87         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters),
  88         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt),
  89         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource),
  90         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch),
  91         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps),
  92         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload),
  93         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff),
  94         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff),
  95         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit),
  96         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq),
  97         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco),
  98         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn),
  99         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn),
 100         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg),
 101         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg),
 102         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME),
 103 };
 104
 105 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
 106         CLK_MAP(GFXCLK,         PPCLK_GFXCLK),
 107         CLK_MAP(SCLK,           PPCLK_GFXCLK),
 108         CLK_MAP(SOCCLK,         PPCLK_SOCCLK),
 109         CLK_MAP(FCLK,           PPCLK_FCLK),
 110         CLK_MAP(UCLK,           PPCLK_UCLK),
 111         CLK_MAP(MCLK,           PPCLK_UCLK),
 112         CLK_MAP(DCLK,           PPCLK_DCLK_0),
 113         CLK_MAP(DCLK1,          PPCLK_DCLK_0),
 114         CLK_MAP(VCLK,           PPCLK_VCLK_1),
 115         CLK_MAP(VCLK1,          PPCLK_VCLK_1),
 116         CLK_MAP(DCEFCLK,        PPCLK_DCEFCLK),
 117         CLK_MAP(DISPCLK,        PPCLK_DISPCLK),
 118         CLK_MAP(PIXCLK,         PPCLK_PIXCLK),
 119         CLK_MAP(PHYCLK,         PPCLK_PHYCLK),
 120 };
 121
 122 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
 123         FEA_MAP(DPM_PREFETCHER),
 124         FEA_MAP(DPM_GFXCLK),
 125         FEA_MAP(DPM_UCLK),
 126         FEA_MAP(DPM_SOCCLK),
 127         FEA_MAP(DPM_MP0CLK),
 128         FEA_MAP(DPM_LINK),
 129         FEA_MAP(DPM_DCEFCLK),
 130         FEA_MAP(MEM_VDDCI_SCALING),
 131         FEA_MAP(MEM_MVDD_SCALING),
 132         FEA_MAP(DS_GFXCLK),
 133         FEA_MAP(DS_SOCCLK),
 134         FEA_MAP(DS_LCLK),
 135         FEA_MAP(DS_DCEFCLK),
 136         FEA_MAP(DS_UCLK),
 137         FEA_MAP(GFX_ULV),
 138         FEA_MAP(FW_DSTATE),
 139         FEA_MAP(GFXOFF),
 140         FEA_MAP(BACO),
 141         FEA_MAP(RSMU_SMN_CG),
 142         FEA_MAP(PPT),
 143         FEA_MAP(TDC),
 144         FEA_MAP(APCC_PLUS),
 145         FEA_MAP(GTHR),
 146         FEA_MAP(ACDC),
 147         FEA_MAP(VR0HOT),
 148         FEA_MAP(VR1HOT),
 149         FEA_MAP(FW_CTF),
 150         FEA_MAP(FAN_CONTROL),
 151         FEA_MAP(THERMAL),
 152         FEA_MAP(GFX_DCS),
 153         FEA_MAP(RM),
 154         FEA_MAP(LED_DISPLAY),
 155         FEA_MAP(GFX_SS),
 156         FEA_MAP(OUT_OF_BAND_MONITOR),
 157         FEA_MAP(TEMP_DEPENDENT_VMIN),
 158         FEA_MAP(MMHUB_PG),
 159         FEA_MAP(ATHUB_PG),
 160 };
 161
 162 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
 163         TAB_MAP(PPTABLE),
 164         TAB_MAP(WATERMARKS),
 165         TAB_MAP(AVFS_PSM_DEBUG),
 166         TAB_MAP(AVFS_FUSE_OVERRIDE),
 167         TAB_MAP(PMSTATUSLOG),
 168         TAB_MAP(SMU_METRICS),
 169         TAB_MAP(DRIVER_SMU_CONFIG),
 170         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 171         TAB_MAP(OVERDRIVE),
 172         TAB_MAP(I2C_COMMANDS),
 173         TAB_MAP(PACE),
 174 };
 175
 176 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 177         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 178         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 179         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 180         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 181         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 182         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_CUSTOM_BIT),
 183         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 184 };
 185
 186 static int sienna_cichlid_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 187 {
 188         struct smu_11_0_cmn2aisc_mapping mapping;
 189
 190         if (index >= SMU_MSG_MAX_COUNT)
 191                 return -EINVAL;
 192
 193         mapping = sienna_cichlid_message_map[index];
 194         if (!(mapping.valid_mapping)) {
 195                 return -EINVAL;
 196         }
 197
 198         return mapping.map_to;
 199 }
 200
 201 static int sienna_cichlid_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 202 {
 203         struct smu_11_0_cmn2aisc_mapping mapping;
 204
 205         if (index >= SMU_CLK_COUNT)
 206                 return -EINVAL;
 207
 208         mapping = sienna_cichlid_clk_map[index];
 209         if (!(mapping.valid_mapping)) {
 210                 return -EINVAL;
 211         }
 212
 213         return mapping.map_to;
 214 }
 215
 216 static int sienna_cichlid_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 217 {
 218         struct smu_11_0_cmn2aisc_mapping mapping;
 219
 220         if (index >= SMU_FEATURE_COUNT)
 221                 return -EINVAL;
 222
 223         mapping = sienna_cichlid_feature_mask_map[index];
 224         if (!(mapping.valid_mapping)) {
 225                 return -EINVAL;
 226         }
 227
 228         return mapping.map_to;
 229 }
 230
 231 static int sienna_cichlid_get_smu_table_index(struct smu_context *smc, uint32_t index)
 232 {
 233         struct smu_11_0_cmn2aisc_mapping mapping;
 234
 235         if (index >= SMU_TABLE_COUNT)
 236                 return -EINVAL;
 237
 238         mapping = sienna_cichlid_table_map[index];
 239         if (!(mapping.valid_mapping)) {
 240                 return -EINVAL;
 241         }
 242
 243         return mapping.map_to;
 244 }
 245
 246 static int sienna_cichlid_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 247 {
 248         struct smu_11_0_cmn2aisc_mapping mapping;
 249
 250         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 251                 return -EINVAL;
 252
 253         mapping = sienna_cichlid_workload_map[profile];
 254         if (!(mapping.valid_mapping)) {
 255                 return -EINVAL;
 256         }
 257
 258         return mapping.map_to;
 259 }
 260
 261 static int
 262 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 263                                   uint32_t *feature_mask, uint32_t num)
 264 {
 265         struct amdgpu_device *adev = smu->adev;
 266
 267         if (num > 2)
 268                 return -EINVAL;
 269
 270         memset(feature_mask, 0, sizeof(uint32_t) * num);
 271
 272         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 273                                 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
 274                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 275                                 | FEATURE_MASK(FEATURE_THERMAL_BIT);
 276
 277         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
 278                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 279
 280         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 281                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
 282
 283         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 284                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 285
 286         if (adev->pm.pp_feature & PP_ULV_MASK)
 287                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 288
 289         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 290                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 291
 292         return 0;
 293 }
 294
 295 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
 296 {
 297         return 0;
 298 }
 299
 300 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
 301 {
 302         return 0;
 303 }
 304
 305 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
 306 {
 307         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 308         struct smu_table_context *table_context = &smu->smu_table;
 309         struct smu_baco_context *smu_baco = &smu->smu_baco;
 310
 311         if (!table_context->power_play_table)
 312                 return -EINVAL;
 313
 314         powerplay_table = table_context->power_play_table;
 315
 316         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 317                sizeof(PPTable_t));
 318
 319         table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
 320
 321         mutex_lock(&smu_baco->mutex);
 322         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 323             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 324                 smu_baco->platform_support = true;
 325         mutex_unlock(&smu_baco->mutex);
 326
 327         return 0;
 328 }
 329
 330 static int sienna_cichlid_tables_init(struct smu_context *smu, struct smu_table *tables)
 331 {
 332         struct smu_table_context *smu_table = &smu->smu_table;
 333
 334         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 335                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 336         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 337                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 338         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 339                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 340         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 341                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 342         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 343                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 344         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 345                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 346                        AMDGPU_GEM_DOMAIN_VRAM);
 347
 348         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 349         if (!smu_table->metrics_table)
 350                 return -ENOMEM;
 351         smu_table->metrics_time = 0;
 352
 353         return 0;
 354 }
 355
 356 static int sienna_cichlid_get_metrics_table(struct smu_context *smu,
 357                                     SmuMetrics_t *metrics_table)
 358 {
 359         struct smu_table_context *smu_table= &smu->smu_table;
 360         int ret = 0;
 361
 362         mutex_lock(&smu->metrics_lock);
 363         if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
 364                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 365                                 (void *)smu_table->metrics_table, false);
 366                 if (ret) {
 367                         pr_info("Failed to export SMU metrics table!\n");
 368                         mutex_unlock(&smu->metrics_lock);
 369                         return ret;
 370                 }
 371                 smu_table->metrics_time = jiffies;
 372         }
 373
 374         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
 375         mutex_unlock(&smu->metrics_lock);
 376
 377         return ret;
 378 }
 379
 380 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
 381 {
 382         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 383
 384         if (smu_dpm->dpm_context)
 385                 return -EINVAL;
 386
 387         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 388                                        GFP_KERNEL);
 389         if (!smu_dpm->dpm_context)
 390                 return -ENOMEM;
 391
 392         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 393
 394         return 0;
 395 }
 396
 397 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 398 {
 399         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 400         struct smu_table_context *table_context = &smu->smu_table;
 401         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 402         PPTable_t *driver_ppt = NULL;
 403
 404         driver_ppt = table_context->driver_pptable;
 405
 406         dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
 407         dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
 408
 409         dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
 410         dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
 411
 412         dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
 413         dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
 414
 415         dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
 416         dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
 417
 418         dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
 419         dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
 420
 421         dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
 422         dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
 423
 424         dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
 425         dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
 426
 427         dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
 428         dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
 429
 430         dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
 431         dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
 432
 433         return 0;
 434 }
 435
 436 static int sienna_cichlid_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
 437 {
 438         struct smu_power_context *smu_power = &smu->smu_power;
 439         struct smu_power_gate *power_gate = &smu_power->power_gate;
 440         int ret = 0;
 441
 442         if (enable) {
 443                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 444                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 445                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
 446                         if (ret)
 447                                 return ret;
 448                 }
 449                 power_gate->vcn_gated = false;
 450         } else {
 451                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 452                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
 453                         if (ret)
 454                                 return ret;
 455                 }
 456                 power_gate->vcn_gated = true;
 457         }
 458
 459         return ret;
 460 }
 461
 462 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
 463                                        enum smu_clk_type clk_type,
 464                                        uint32_t *value)
 465 {
 466         int ret = 0, clk_id = 0;
 467         SmuMetrics_t metrics;
 468
 469         ret = sienna_cichlid_get_metrics_table(smu, &metrics);
 470         if (ret)
 471                 return ret;
 472
 473         clk_id = smu_clk_get_index(smu, clk_type);
 474         if (clk_id < 0)
 475                 return clk_id;
 476
 477         *value = metrics.CurrClock[clk_id];
 478
 479         return ret;
 480 }
 481
 482 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 483 {
 484         PPTable_t *pptable = smu->smu_table.driver_pptable;
 485         DpmDescriptor_t *dpm_desc = NULL;
 486         uint32_t clk_index = 0;
 487
 488         clk_index = smu_clk_get_index(smu, clk_type);
 489         dpm_desc = &pptable->DpmDescriptor[clk_index];
 490
 491         /* 0 - Fine grained DPM, 1 - Discrete DPM */
 492         return dpm_desc->SnapToDiscrete == 0 ? true : false;
 493 }
 494
 495 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
 496                         enum smu_clk_type clk_type, char *buf)
 497 {
 498         int i, size = 0, ret = 0;
 499         uint32_t cur_value = 0, value = 0, count = 0;
 500         uint32_t freq_values[3] = {0};
 501         uint32_t mark_index = 0;
 502
 503         switch (clk_type) {
 504         case SMU_GFXCLK:
 505         case SMU_SCLK:
 506         case SMU_SOCCLK:
 507         case SMU_MCLK:
 508         case SMU_UCLK:
 509         case SMU_FCLK:
 510         case SMU_DCEFCLK:
 511                 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
 512                 if (ret)
 513                         return size;
 514
 515                 /* 10KHz -> MHz */
 516                 cur_value = cur_value / 100;
 517
 518                 ret = smu_get_dpm_level_count(smu, clk_type, &count);
 519                 if (ret)
 520                         return size;
 521
 522                 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
 523                         for (i = 0; i < count; i++) {
 524                                 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
 525                                 if (ret)
 526                                         return size;
 527
 528                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 529                                                 cur_value == value ? "*" : "");
 530                         }
 531                 } else {
 532                         ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
 533                         if (ret)
 534                                 return size;
 535                         ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
 536                         if (ret)
 537                                 return size;
 538
 539                         freq_values[1] = cur_value;
 540                         mark_index = cur_value == freq_values[0] ? 0 :
 541                                      cur_value == freq_values[2] ? 2 : 1;
 542                         if (mark_index != 1)
 543                                 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
 544
 545                         for (i = 0; i < 3; i++) {
 546                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
 547                                                 i == mark_index ? "*" : "");
 548                         }
 549
 550                 }
 551                 break;
 552         default:
 553                 break;
 554         }
 555
 556         return size;
 557 }
 558
 559 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
 560                                    enum smu_clk_type clk_type, uint32_t mask)
 561 {
 562
 563         int ret = 0, size = 0;
 564         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
 565
 566         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 567         soft_max_level = mask ? (fls(mask) - 1) : 0;
 568
 569         switch (clk_type) {
 570         case SMU_GFXCLK:
 571         case SMU_SCLK:
 572         case SMU_SOCCLK:
 573         case SMU_MCLK:
 574         case SMU_UCLK:
 575         case SMU_DCEFCLK:
 576         case SMU_FCLK:
 577                 /* There is only 2 levels for fine grained DPM */
 578                 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
 579                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
 580                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
 581                 }
 582
 583                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
 584                 if (ret)
 585                         return size;
 586
 587                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
 588                 if (ret)
 589                         return size;
 590
 591                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
 592                 if (ret)
 593                         return size;
 594                 break;
 595         default:
 596                 break;
 597         }
 598
 599         return size;
 600 }
 601
 602 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
 603 {
 604         int ret = 0;
 605         uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
 606
 607         ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
 608         if (ret)
 609                 return ret;
 610
 611         smu->pstate_sclk = min_sclk_freq * 100;
 612
 613         ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
 614         if (ret)
 615                 return ret;
 616
 617         smu->pstate_mclk = min_mclk_freq * 100;
 618
 619         return ret;
 620 }
 621
 622 static int sienna_cichlid_get_clock_by_type_with_latency(struct smu_context *smu,
 623                                                  enum smu_clk_type clk_type,
 624                                                  struct pp_clock_levels_with_latency *clocks)
 625 {
 626         int ret = 0, i = 0;
 627         uint32_t level_count = 0, freq = 0;
 628
 629         switch (clk_type) {
 630         case SMU_GFXCLK:
 631         case SMU_DCEFCLK:
 632         case SMU_SOCCLK:
 633                 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
 634                 if (ret)
 635                         return ret;
 636
 637                 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
 638                 clocks->num_levels = level_count;
 639
 640                 for (i = 0; i < level_count; i++) {
 641                         ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
 642                         if (ret)
 643                                 return ret;
 644
 645                         clocks->data[i].clocks_in_khz = freq * 1000;
 646                         clocks->data[i].latency_in_us = 0;
 647                 }
 648                 break;
 649         default:
 650                 break;
 651         }
 652
 653         return ret;
 654 }
 655
 656 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
 657 {
 658         int ret = 0;
 659         uint32_t max_freq = 0;
 660
 661         /* Sienna_Cichlid do not support to change display num currently */
 662         return 0;
 663 #if 0
 664         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
 665         if (ret)
 666                 return ret;
 667 #endif
 668
 669         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 670                 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
 671                 if (ret)
 672                         return ret;
 673                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
 674                 if (ret)
 675                         return ret;
 676         }
 677
 678         return ret;
 679 }
 680
 681 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
 682 {
 683         int ret = 0;
 684
 685         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 686             !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 687                 ret = smu_write_watermarks_table(smu);
 688                 if (ret)
 689                         return ret;
 690
 691                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
 692         }
 693
 694         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 695             smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
 696             smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 697                 /* Sienna_Cichlid do not support to change display num currently */
 698                 ret = 0;
 699 #if 0
 700                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
 701                                                   smu->display_config->num_display, NULL);
 702 #endif
 703                 if (ret)
 704                         return ret;
 705         }
 706
 707         return ret;
 708 }
 709
 710 static int sienna_cichlid_force_dpm_limit_value(struct smu_context *smu, bool highest)
 711 {
 712         int ret = 0, i = 0;
 713         uint32_t min_freq, max_freq, force_freq;
 714         enum smu_clk_type clk_type;
 715
 716         enum smu_clk_type clks[] = {
 717                 SMU_GFXCLK,
 718         };
 719
 720         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 721                 clk_type = clks[i];
 722                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
 723                 if (ret)
 724                         return ret;
 725
 726                 force_freq = highest ? max_freq : min_freq;
 727                 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq, false);
 728                 if (ret)
 729                         return ret;
 730         }
 731
 732         return ret;
 733 }
 734
 735 static int sienna_cichlid_unforce_dpm_levels(struct smu_context *smu)
 736 {
 737         int ret = 0, i = 0;
 738         uint32_t min_freq, max_freq;
 739         enum smu_clk_type clk_type;
 740
 741         enum smu_clk_type clks[] = {
 742                 SMU_GFXCLK,
 743         };
 744
 745         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 746                 clk_type = clks[i];
 747                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
 748                 if (ret)
 749                         return ret;
 750
 751                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
 752                 if (ret)
 753                         return ret;
 754         }
 755
 756         return ret;
 757 }
 758
 759 static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)
 760 {
 761         int ret = 0;
 762         SmuMetrics_t metrics;
 763
 764         if (!value)
 765                 return -EINVAL;
 766
 767         ret = sienna_cichlid_get_metrics_table(smu, &metrics);
 768         if (ret)
 769                 return ret;
 770
 771         *value = metrics.AverageSocketPower << 8;
 772
 773         return 0;
 774 }
 775
 776 static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu,
 777                                                enum amd_pp_sensors sensor,
 778                                                uint32_t *value)
 779 {
 780         int ret = 0;
 781         SmuMetrics_t metrics;
 782
 783         if (!value)
 784                 return -EINVAL;
 785
 786         ret = sienna_cichlid_get_metrics_table(smu, &metrics);
 787         if (ret)
 788                 return ret;
 789
 790         switch (sensor) {
 791         case AMDGPU_PP_SENSOR_GPU_LOAD:
 792                 *value = metrics.AverageGfxActivity;
 793                 break;
 794         case AMDGPU_PP_SENSOR_MEM_LOAD:
 795                 *value = metrics.AverageUclkActivity;
 796                 break;
 797         default:
 798                 pr_err("Invalid sensor for retrieving clock activity\n");
 799                 return -EINVAL;
 800         }
 801
 802         return 0;
 803 }
 804
 805 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
 806 {
 807         int ret = 0;
 808         uint32_t feature_mask[2];
 809         unsigned long feature_enabled;
 810         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 811         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
 812                            ((uint64_t)feature_mask[1] << 32));
 813         return !!(feature_enabled & SMC_DPM_FEATURE);
 814 }
 815
 816 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
 817                                     uint32_t *speed)
 818 {
 819         SmuMetrics_t metrics;
 820         int ret = 0;
 821
 822         if (!speed)
 823                 return -EINVAL;
 824
 825         ret = sienna_cichlid_get_metrics_table(smu, &metrics);
 826         if (ret)
 827                 return ret;
 828
 829         *speed = metrics.CurrFanSpeed;
 830
 831         return ret;
 832 }
 833
 834 static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu,
 835                                         uint32_t *speed)
 836 {
 837         int ret = 0;
 838         uint32_t percent = 0;
 839         uint32_t current_rpm;
 840         PPTable_t *pptable = smu->smu_table.driver_pptable;
 841
 842         ret = sienna_cichlid_get_fan_speed_rpm(smu, &current_rpm);
 843         if (ret)
 844                 return ret;
 845
 846         percent = current_rpm * 100 / pptable->FanMaximumRpm;
 847         *speed = percent > 100 ? 100 : percent;
 848
 849         return ret;
 850 }
 851
 852 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
 853 {
 854         DpmActivityMonitorCoeffInt_t activity_monitor;
 855         uint32_t i, size = 0;
 856         int16_t workload_type = 0;
 857         static const char *profile_name[] = {
 858                                         "BOOTUP_DEFAULT",
 859                                         "3D_FULL_SCREEN",
 860                                         "POWER_SAVING",
 861                                         "VIDEO",
 862                                         "VR",
 863                                         "COMPUTE",
 864                                         "CUSTOM"};
 865         static const char *title[] = {
 866                         "PROFILE_INDEX(NAME)",
 867                         "CLOCK_TYPE(NAME)",
 868                         "FPS",
 869                         "MinFreqType",
 870                         "MinActiveFreqType",
 871                         "MinActiveFreq",
 872                         "BoosterFreqType",
 873                         "BoosterFreq",
 874                         "PD_Data_limit_c",
 875                         "PD_Data_error_coeff",
 876                         "PD_Data_error_rate_coeff"};
 877         int result = 0;
 878
 879         if (!buf)
 880                 return -EINVAL;
 881
 882         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
 883                         title[0], title[1], title[2], title[3], title[4], title[5],
 884                         title[6], title[7], title[8], title[9], title[10]);
 885
 886         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
 887                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
 888                 workload_type = smu_workload_get_type(smu, i);
 889                 if (workload_type < 0)
 890                         return -EINVAL;
 891
 892                 result = smu_update_table(smu,
 893                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
 894                                           (void *)(&activity_monitor), false);
 895                 if (result) {
 896                         pr_err("[%s] Failed to get activity monitor!", __func__);
 897                         return result;
 898                 }
 899
 900                 size += sprintf(buf + size, "%2d %14s%s:\n",
 901                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
 902
 903                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
 904                         " ",
 905                         0,
 906                         "GFXCLK",
 907                         activity_monitor.Gfx_FPS,
 908                         activity_monitor.Gfx_MinFreqStep,
 909                         activity_monitor.Gfx_MinActiveFreqType,
 910                         activity_monitor.Gfx_MinActiveFreq,
 911                         activity_monitor.Gfx_BoosterFreqType,
 912                         activity_monitor.Gfx_BoosterFreq,
 913                         activity_monitor.Gfx_PD_Data_limit_c,
 914                         activity_monitor.Gfx_PD_Data_error_coeff,
 915                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
 916
 917                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
 918                         " ",
 919                         1,
 920                         "SOCCLK",
 921                         activity_monitor.Fclk_FPS,
 922                         activity_monitor.Fclk_MinFreqStep,
 923                         activity_monitor.Fclk_MinActiveFreqType,
 924                         activity_monitor.Fclk_MinActiveFreq,
 925                         activity_monitor.Fclk_BoosterFreqType,
 926                         activity_monitor.Fclk_BoosterFreq,
 927                         activity_monitor.Fclk_PD_Data_limit_c,
 928                         activity_monitor.Fclk_PD_Data_error_coeff,
 929                         activity_monitor.Fclk_PD_Data_error_rate_coeff);
 930
 931                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
 932                         " ",
 933                         2,
 934                         "MEMLK",
 935                         activity_monitor.Mem_FPS,
 936                         activity_monitor.Mem_MinFreqStep,
 937                         activity_monitor.Mem_MinActiveFreqType,
 938                         activity_monitor.Mem_MinActiveFreq,
 939                         activity_monitor.Mem_BoosterFreqType,
 940                         activity_monitor.Mem_BoosterFreq,
 941                         activity_monitor.Mem_PD_Data_limit_c,
 942                         activity_monitor.Mem_PD_Data_error_coeff,
 943                         activity_monitor.Mem_PD_Data_error_rate_coeff);
 944         }
 945
 946         return size;
 947 }
 948
 949 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
 950 {
 951         DpmActivityMonitorCoeffInt_t activity_monitor;
 952         int workload_type, ret = 0;
 953
 954         smu->power_profile_mode = input[size];
 955
 956         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
 957                 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
 958                 return -EINVAL;
 959         }
 960
 961         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
 962                 if (size < 0)
 963                         return -EINVAL;
 964
 965                 ret = smu_update_table(smu,
 966                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
 967                                        (void *)(&activity_monitor), false);
 968                 if (ret) {
 969                         pr_err("[%s] Failed to get activity monitor!", __func__);
 970                         return ret;
 971                 }
 972
 973                 switch (input[0]) {
 974                 case 0: /* Gfxclk */
 975                         activity_monitor.Gfx_FPS = input[1];
 976                         activity_monitor.Gfx_MinFreqStep = input[2];
 977                         activity_monitor.Gfx_MinActiveFreqType = input[3];
 978                         activity_monitor.Gfx_MinActiveFreq = input[4];
 979                         activity_monitor.Gfx_BoosterFreqType = input[5];
 980                         activity_monitor.Gfx_BoosterFreq = input[6];
 981                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
 982                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
 983                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
 984                         break;
 985                 case 1: /* Socclk */
 986                         activity_monitor.Fclk_FPS = input[1];
 987                         activity_monitor.Fclk_MinFreqStep = input[2];
 988                         activity_monitor.Fclk_MinActiveFreqType = input[3];
 989                         activity_monitor.Fclk_MinActiveFreq = input[4];
 990                         activity_monitor.Fclk_BoosterFreqType = input[5];
 991                         activity_monitor.Fclk_BoosterFreq = input[6];
 992                         activity_monitor.Fclk_PD_Data_limit_c = input[7];
 993                         activity_monitor.Fclk_PD_Data_error_coeff = input[8];
 994                         activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
 995                         break;
 996                 case 2: /* Memlk */
 997                         activity_monitor.Mem_FPS = input[1];
 998                         activity_monitor.Mem_MinFreqStep = input[2];
 999                         activity_monitor.Mem_MinActiveFreqType = input[3];
1000                         activity_monitor.Mem_MinActiveFreq = input[4];
1001                         activity_monitor.Mem_BoosterFreqType = input[5];
1002                         activity_monitor.Mem_BoosterFreq = input[6];
1003                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1004                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1005                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1006                         break;
1007                 }
1008
1009                 ret = smu_update_table(smu,
1010                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1011                                        (void *)(&activity_monitor), true);
1012                 if (ret) {
1013                         pr_err("[%s] Failed to set activity monitor!", __func__);
1014                         return ret;
1015                 }
1016         }
1017
1018         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1019         workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1020         if (workload_type < 0)
1021                 return -EINVAL;
1022         smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1023                                     1 << workload_type, NULL);
1024
1025         return ret;
1026 }
1027
1028 static int sienna_cichlid_get_profiling_clk_mask(struct smu_context *smu,
1029                                          enum amd_dpm_forced_level level,
1030                                          uint32_t *sclk_mask,
1031                                          uint32_t *mclk_mask,
1032                                          uint32_t *soc_mask)
1033 {
1034         int ret = 0;
1035         uint32_t level_count = 0;
1036
1037         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1038                 if (sclk_mask)
1039                         *sclk_mask = 0;
1040         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1041                 if (mclk_mask)
1042                         *mclk_mask = 0;
1043         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1044                 if(sclk_mask) {
1045                         ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1046                         if (ret)
1047                                 return ret;
1048                         *sclk_mask = level_count - 1;
1049                 }
1050
1051                 if(mclk_mask) {
1052                         ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1053                         if (ret)
1054                                 return ret;
1055                         *mclk_mask = level_count - 1;
1056                 }
1057
1058                 if(soc_mask) {
1059                         ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1060                         if (ret)
1061                                 return ret;
1062                         *soc_mask = level_count - 1;
1063                 }
1064         }
1065
1066         return ret;
1067 }
1068
1069 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1070 {
1071         struct smu_clocks min_clocks = {0};
1072         struct pp_display_clock_request clock_req;
1073         int ret = 0;
1074
1075         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1076         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1077         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1078
1079         if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1080                 clock_req.clock_type = amd_pp_dcef_clock;
1081                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1082
1083                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1084                 if (!ret) {
1085                         if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1086                                 pr_err("Attempt to set divider for DCEFCLK Failed as it not support currently!");
1087                                 return ret;
1088                         }
1089                 } else {
1090                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1091                 }
1092         }
1093
1094         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1095                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1096                 if (ret) {
1097                         pr_err("[%s] Set hard min uclk failed!", __func__);
1098                         return ret;
1099                 }
1100         }
1101
1102         return 0;
1103 }
1104
1105 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1106                                        void *watermarks, struct
1107                                        dm_pp_wm_sets_with_clock_ranges_soc15
1108                                        *clock_ranges)
1109 {
1110         int i;
1111         Watermarks_t *table = watermarks;
1112
1113         if (!table || !clock_ranges)
1114                 return -EINVAL;
1115
1116         if (clock_ranges->num_wm_dmif_sets > 4 ||
1117             clock_ranges->num_wm_mcif_sets > 4)
1118                 return -EINVAL;
1119
1120         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1121                 table->WatermarkRow[1][i].MinClock =
1122                         cpu_to_le16((uint16_t)
1123                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1124                         1000));
1125                 table->WatermarkRow[1][i].MaxClock =
1126                         cpu_to_le16((uint16_t)
1127                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1128                         1000));
1129                 table->WatermarkRow[1][i].MinUclk =
1130                         cpu_to_le16((uint16_t)
1131                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1132                         1000));
1133                 table->WatermarkRow[1][i].MaxUclk =
1134                         cpu_to_le16((uint16_t)
1135                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1136                         1000));
1137                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1138                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1139         }
1140
1141         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1142                 table->WatermarkRow[0][i].MinClock =
1143                         cpu_to_le16((uint16_t)
1144                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1145                         1000));
1146                 table->WatermarkRow[0][i].MaxClock =
1147                         cpu_to_le16((uint16_t)
1148                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1149                         1000));
1150                 table->WatermarkRow[0][i].MinUclk =
1151                         cpu_to_le16((uint16_t)
1152                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1153                         1000));
1154                 table->WatermarkRow[0][i].MaxUclk =
1155                         cpu_to_le16((uint16_t)
1156                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1157                         1000));
1158                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1159                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1160         }
1161
1162         return 0;
1163 }
1164
1165 static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu,
1166                                              enum amd_pp_sensors sensor,
1167                                              uint32_t *value)
1168 {
1169         SmuMetrics_t metrics;
1170         int ret = 0;
1171
1172         if (!value)
1173                 return -EINVAL;
1174
1175         ret = sienna_cichlid_get_metrics_table(smu, &metrics);
1176         if (ret)
1177                 return ret;
1178
1179         switch (sensor) {
1180         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1181                 *value = metrics.TemperatureHotspot *
1182                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1183                 break;
1184         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1185                 *value = metrics.TemperatureEdge *
1186                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1187                 break;
1188         case AMDGPU_PP_SENSOR_MEM_TEMP:
1189                 *value = metrics.TemperatureMem *
1190                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1191                 break;
1192         default:
1193                 pr_err("Invalid sensor for retrieving temp\n");
1194                 return -EINVAL;
1195         }
1196
1197         return 0;
1198 }
1199
1200 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1201                                  enum amd_pp_sensors sensor,
1202                                  void *data, uint32_t *size)
1203 {
1204         int ret = 0;
1205         struct smu_table_context *table_context = &smu->smu_table;
1206         PPTable_t *pptable = table_context->driver_pptable;
1207
1208         if(!data || !size)
1209                 return -EINVAL;
1210
1211         mutex_lock(&smu->sensor_lock);
1212         switch (sensor) {
1213         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1214                 *(uint32_t *)data = pptable->FanMaximumRpm;
1215                 *size = 4;
1216                 break;
1217         case AMDGPU_PP_SENSOR_MEM_LOAD:
1218         case AMDGPU_PP_SENSOR_GPU_LOAD:
1219                 ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1220                 *size = 4;
1221                 break;
1222         case AMDGPU_PP_SENSOR_GPU_POWER:
1223                 ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data);
1224                 *size = 4;
1225                 break;
1226         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1227         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1228         case AMDGPU_PP_SENSOR_MEM_TEMP:
1229                 ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1230                 *size = 4;
1231                 break;
1232         default:
1233                 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1234         }
1235         mutex_unlock(&smu->sensor_lock);
1236
1237         return ret;
1238 }
1239
1240 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1241 {
1242         uint32_t num_discrete_levels = 0;
1243         uint16_t *dpm_levels = NULL;
1244         uint16_t i = 0;
1245         struct smu_table_context *table_context = &smu->smu_table;
1246         PPTable_t *driver_ppt = NULL;
1247
1248         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1249                 return -EINVAL;
1250
1251         driver_ppt = table_context->driver_pptable;
1252         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1253         dpm_levels = driver_ppt->FreqTableUclk;
1254
1255         if (num_discrete_levels == 0 || dpm_levels == NULL)
1256                 return -EINVAL;
1257
1258         *num_states = num_discrete_levels;
1259         for (i = 0; i < num_discrete_levels; i++) {
1260                 /* convert to khz */
1261                 *clocks_in_khz = (*dpm_levels) * 1000;
1262                 clocks_in_khz++;
1263                 dpm_levels++;
1264         }
1265
1266         return 0;
1267 }
1268
1269 static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1270                                         enum amd_dpm_forced_level level);
1271
1272 static int sienna_cichlid_set_standard_performance_level(struct smu_context *smu)
1273 {
1274         struct amdgpu_device *adev = smu->adev;
1275         int ret = 0;
1276         uint32_t sclk_freq = 0, uclk_freq = 0;
1277
1278         switch (adev->asic_type) {
1279         /* TODO: need to set specify clk value by asic type, not support yet*/
1280         default:
1281                 /* by default, this is same as auto performance level */
1282                 return sienna_cichlid_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
1283         }
1284
1285         ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
1286         if (ret)
1287                 return ret;
1288         ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
1289         if (ret)
1290                 return ret;
1291
1292         return ret;
1293 }
1294
1295 static int sienna_cichlid_set_peak_performance_level(struct smu_context *smu)
1296 {
1297         int ret = 0;
1298
1299         /* TODO: not support yet*/
1300         return ret;
1301 }
1302
1303 static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1304                                         enum amd_dpm_forced_level level)
1305 {
1306         int ret = 0;
1307         uint32_t sclk_mask, mclk_mask, soc_mask;
1308
1309         switch (level) {
1310         case AMD_DPM_FORCED_LEVEL_HIGH:
1311                 ret = smu_force_dpm_limit_value(smu, true);
1312                 break;
1313         case AMD_DPM_FORCED_LEVEL_LOW:
1314                 ret = smu_force_dpm_limit_value(smu, false);
1315                 break;
1316         case AMD_DPM_FORCED_LEVEL_AUTO:
1317                 ret = smu_unforce_dpm_levels(smu);
1318                 break;
1319         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1320                 ret = sienna_cichlid_set_standard_performance_level(smu);
1321                 break;
1322         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1323         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1324                 ret = smu_get_profiling_clk_mask(smu, level,
1325                                                  &sclk_mask,
1326                                                  &mclk_mask,
1327                                                  &soc_mask);
1328                 if (ret)
1329                         return ret;
1330                 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1331                 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1332                 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1333                 break;
1334         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1335                 ret = sienna_cichlid_set_peak_performance_level(smu);
1336                 break;
1337         case AMD_DPM_FORCED_LEVEL_MANUAL:
1338         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1339         default:
1340                 break;
1341         }
1342         return ret;
1343 }
1344
1345 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1346                                                 struct smu_temperature_range *range)
1347 {
1348         struct smu_table_context *table_context = &smu->smu_table;
1349         struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1350
1351         if (!range || !powerplay_table)
1352                 return -EINVAL;
1353
1354         range->max = powerplay_table->software_shutdown_temp *
1355                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1356
1357         return 0;
1358 }
1359
1360 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1361                                                 bool disable_memory_clock_switch)
1362 {
1363         int ret = 0;
1364         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1365                 (struct smu_11_0_max_sustainable_clocks *)
1366                         smu->smu_table.max_sustainable_clocks;
1367         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1368         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1369
1370         if(smu->disable_uclk_switch == disable_memory_clock_switch)
1371                 return 0;
1372
1373         if(disable_memory_clock_switch)
1374                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
1375         else
1376                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
1377
1378         if(!ret)
1379                 smu->disable_uclk_switch = disable_memory_clock_switch;
1380
1381         return ret;
1382 }
1383
1384 static int sienna_cichlid_get_power_limit(struct smu_context *smu,
1385                                      uint32_t *limit,
1386                                      bool cap)
1387 {
1388         PPTable_t *pptable = smu->smu_table.driver_pptable;
1389         uint32_t asic_default_power_limit = 0;
1390         int ret = 0;
1391         int power_src;
1392
1393         if (!smu->power_limit) {
1394                 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1395                         power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1396                         if (power_src < 0)
1397                                 return -EINVAL;
1398
1399                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1400                                                           power_src << 16, &asic_default_power_limit);
1401                         if (ret) {
1402                                 pr_err("[%s] get PPT limit failed!", __func__);
1403                                 return ret;
1404                         }
1405                 } else {
1406                         /* the last hope to figure out the ppt limit */
1407                         if (!pptable) {
1408                                 pr_err("Cannot get PPT limit due to pptable missing!");
1409                                 return -EINVAL;
1410                         }
1411                         asic_default_power_limit =
1412                                 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1413                 }
1414
1415                 smu->power_limit = asic_default_power_limit;
1416         }
1417
1418         if (cap)
1419                 *limit = smu_v11_0_get_max_power_limit(smu);
1420         else
1421                 *limit = smu->power_limit;
1422
1423         return 0;
1424 }
1425
1426 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
1427 {
1428         struct smu_table_context *table_context = &smu->smu_table;
1429         PPTable_t *pptable = table_context->driver_pptable;
1430         int i;
1431
1432         pr_info("Dumped PPTable:\n");
1433
1434         pr_info("Version = 0x%08x\n", pptable->Version);
1435         pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1436         pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1437
1438         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1439                 pr_info("SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
1440                 pr_info("SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
1441                 pr_info("SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
1442                 pr_info("SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
1443         }
1444
1445         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
1446                 pr_info("TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
1447                 pr_info("TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
1448         }
1449
1450         for (i = 0; i < TEMP_COUNT; i++) {
1451                 pr_info("TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
1452         }
1453
1454         pr_info("FitLimit = 0x%x\n", pptable->FitLimit);
1455         pr_info("TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
1456         pr_info("TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
1457         pr_info("TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
1458         pr_info("TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
1459
1460         pr_info("ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
1461         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
1462                 pr_info("SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
1463                 pr_info("SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
1464         }
1465         pr_info("PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]);
1466         pr_info("PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]);
1467         pr_info("PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]);
1468         pr_info("PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]);
1469
1470         pr_info("ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
1471
1472         pr_info("FwDStateMask = 0x%x\n", pptable->FwDStateMask);
1473
1474         pr_info("UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
1475         pr_info("UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
1476         pr_info("MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
1477         pr_info("MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
1478
1479         pr_info("SocLIVmin = 0x%x\n", pptable->SocLIVmin);
1480         pr_info("PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
1481
1482         pr_info("GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
1483         pr_info("paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
1484         pr_info("paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
1485         pr_info("paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
1486
1487         pr_info("MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
1488         pr_info("MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
1489         pr_info("MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
1490         pr_info("MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
1491
1492         pr_info("LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
1493         pr_info("LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
1494
1495         pr_info("VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
1496         pr_info("VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
1497         pr_info("VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
1498         pr_info("VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
1499         pr_info("VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
1500         pr_info("VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
1501         pr_info("VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
1502         pr_info("VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
1503
1504         pr_info("[PPCLK_GFXCLK]\n"
1505                         "  .VoltageMode          = 0x%02x\n"
1506                         "  .SnapToDiscrete       = 0x%02x\n"
1507                         "  .NumDiscreteLevels    = 0x%02x\n"
1508                         "  .padding              = 0x%02x\n"
1509                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1510                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1511                         "  .SsFmin               = 0x%04x\n"
1512                         "  .Padding_16           = 0x%04x\n",
1513                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1514                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1515                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1516                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
1517                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1518                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1519                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1520                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1521                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1522                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1523                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1524
1525         pr_info("[PPCLK_SOCCLK]\n"
1526                         "  .VoltageMode          = 0x%02x\n"
1527                         "  .SnapToDiscrete       = 0x%02x\n"
1528                         "  .NumDiscreteLevels    = 0x%02x\n"
1529                         "  .padding              = 0x%02x\n"
1530                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1531                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1532                         "  .SsFmin               = 0x%04x\n"
1533                         "  .Padding_16           = 0x%04x\n",
1534                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1535                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1536                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1537                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
1538                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1539                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1540                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1541                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1542                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1543                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1544                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1545
1546         pr_info("[PPCLK_UCLK]\n"
1547                         "  .VoltageMode          = 0x%02x\n"
1548                         "  .SnapToDiscrete       = 0x%02x\n"
1549                         "  .NumDiscreteLevels    = 0x%02x\n"
1550                         "  .padding              = 0x%02x\n"
1551                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1552                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1553                         "  .SsFmin               = 0x%04x\n"
1554                         "  .Padding_16           = 0x%04x\n",
1555                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1556                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1557                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1558                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
1559                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1560                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1561                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1562                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1563                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1564                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1565                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1566
1567         pr_info("[PPCLK_FCLK]\n"
1568                         "  .VoltageMode          = 0x%02x\n"
1569                         "  .SnapToDiscrete       = 0x%02x\n"
1570                         "  .NumDiscreteLevels    = 0x%02x\n"
1571                         "  .padding              = 0x%02x\n"
1572                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1573                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1574                         "  .SsFmin               = 0x%04x\n"
1575                         "  .Padding_16           = 0x%04x\n",
1576                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1577                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1578                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1579                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
1580                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1581                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1582                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1583                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1584                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1585                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1586                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1587
1588         pr_info("[PPCLK_DCLK_0]\n"
1589                         "  .VoltageMode          = 0x%02x\n"
1590                         "  .SnapToDiscrete       = 0x%02x\n"
1591                         "  .NumDiscreteLevels    = 0x%02x\n"
1592                         "  .padding              = 0x%02x\n"
1593                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1594                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1595                         "  .SsFmin               = 0x%04x\n"
1596                         "  .Padding_16           = 0x%04x\n",
1597                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
1598                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
1599                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
1600                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
1601                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
1602                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
1603                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
1604                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
1605                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
1606                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
1607                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
1608
1609         pr_info("[PPCLK_VCLK_0]\n"
1610                         "  .VoltageMode          = 0x%02x\n"
1611                         "  .SnapToDiscrete       = 0x%02x\n"
1612                         "  .NumDiscreteLevels    = 0x%02x\n"
1613                         "  .padding              = 0x%02x\n"
1614                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1615                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1616                         "  .SsFmin               = 0x%04x\n"
1617                         "  .Padding_16           = 0x%04x\n",
1618                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
1619                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
1620                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
1621                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
1622                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
1623                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
1624                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
1625                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
1626                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
1627                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
1628                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
1629
1630         pr_info("[PPCLK_DCLK_1]\n"
1631                         "  .VoltageMode          = 0x%02x\n"
1632                         "  .SnapToDiscrete       = 0x%02x\n"
1633                         "  .NumDiscreteLevels    = 0x%02x\n"
1634                         "  .padding              = 0x%02x\n"
1635                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1636                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1637                         "  .SsFmin               = 0x%04x\n"
1638                         "  .Padding_16           = 0x%04x\n",
1639                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
1640                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
1641                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
1642                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
1643                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
1644                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
1645                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
1646                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
1647                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
1648                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
1649                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
1650
1651         pr_info("[PPCLK_VCLK_1]\n"
1652                         "  .VoltageMode          = 0x%02x\n"
1653                         "  .SnapToDiscrete       = 0x%02x\n"
1654                         "  .NumDiscreteLevels    = 0x%02x\n"
1655                         "  .padding              = 0x%02x\n"
1656                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1657                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1658                         "  .SsFmin               = 0x%04x\n"
1659                         "  .Padding_16           = 0x%04x\n",
1660                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
1661                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
1662                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
1663                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
1664                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
1665                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
1666                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
1667                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
1668                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
1669                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
1670                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
1671
1672         pr_info("FreqTableGfx\n");
1673         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1674                 pr_info("  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
1675
1676         pr_info("FreqTableVclk\n");
1677         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1678                 pr_info("  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
1679
1680         pr_info("FreqTableDclk\n");
1681         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1682                 pr_info("  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
1683
1684         pr_info("FreqTableSocclk\n");
1685         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1686                 pr_info("  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
1687
1688         pr_info("FreqTableUclk\n");
1689         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1690                 pr_info("  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
1691
1692         pr_info("FreqTableFclk\n");
1693         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1694                 pr_info("  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
1695
1696         pr_info("Paddingclks[0] = 0x%x\n",  pptable->Paddingclks[0]);
1697         pr_info("Paddingclks[1] = 0x%x\n",  pptable->Paddingclks[1]);
1698         pr_info("Paddingclks[2] = 0x%x\n",  pptable->Paddingclks[2]);
1699         pr_info("Paddingclks[3] = 0x%x\n",  pptable->Paddingclks[3]);
1700         pr_info("Paddingclks[4] = 0x%x\n",  pptable->Paddingclks[4]);
1701         pr_info("Paddingclks[5] = 0x%x\n",  pptable->Paddingclks[5]);
1702         pr_info("Paddingclks[6] = 0x%x\n",  pptable->Paddingclks[6]);
1703         pr_info("Paddingclks[7] = 0x%x\n",  pptable->Paddingclks[7]);
1704         pr_info("Paddingclks[8] = 0x%x\n",  pptable->Paddingclks[8]);
1705         pr_info("Paddingclks[9] = 0x%x\n",  pptable->Paddingclks[9]);
1706         pr_info("Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]);
1707         pr_info("Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]);
1708         pr_info("Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]);
1709         pr_info("Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]);
1710         pr_info("Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]);
1711         pr_info("Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]);
1712
1713         pr_info("DcModeMaxFreq\n");
1714         pr_info("  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
1715         pr_info("  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
1716         pr_info("  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
1717         pr_info("  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
1718         pr_info("  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
1719         pr_info("  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
1720         pr_info("  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
1721         pr_info("  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
1722
1723         pr_info("FreqTableUclkDiv\n");
1724         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1725                 pr_info("  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
1726
1727         pr_info("FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
1728         pr_info("FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
1729
1730         pr_info("Mp0clkFreq\n");
1731         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1732                 pr_info("  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
1733
1734         pr_info("Mp0DpmVoltage\n");
1735         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1736                 pr_info("  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
1737
1738         pr_info("MemVddciVoltage\n");
1739         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1740                 pr_info("  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
1741
1742         pr_info("MemMvddVoltage\n");
1743         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1744                 pr_info("  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
1745
1746         pr_info("GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
1747         pr_info("GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
1748         pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1749         pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1750         pr_info("GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
1751
1752         pr_info("GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
1753
1754         pr_info("GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
1755         pr_info("GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
1756         pr_info("GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
1757         pr_info("GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
1758         pr_info("GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
1759         pr_info("GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
1760         pr_info("GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
1761         pr_info("GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
1762         pr_info("GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
1763         pr_info("GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
1764         pr_info("GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
1765
1766         pr_info("DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
1767         pr_info("DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
1768         pr_info("DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
1769         pr_info("DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
1770         pr_info("DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
1771         pr_info("DcsTimeout = 0x%x\n", pptable->DcsTimeout);
1772
1773         pr_info("DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
1774         pr_info("DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
1775         pr_info("DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
1776         pr_info("DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
1777         pr_info("DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
1778
1779         pr_info("FlopsPerByteTable\n");
1780         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
1781                 pr_info("  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
1782
1783         pr_info("LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
1784         pr_info("vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
1785         pr_info("vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
1786         pr_info("vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
1787
1788         pr_info("UclkDpmPstates\n");
1789         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1790                 pr_info("  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
1791
1792         pr_info("UclkDpmSrcFreqRange\n");
1793         pr_info("  .Fmin = 0x%x\n",
1794                 pptable->UclkDpmSrcFreqRange.Fmin);
1795         pr_info("  .Fmax = 0x%x\n",
1796                 pptable->UclkDpmSrcFreqRange.Fmax);
1797         pr_info("UclkDpmTargFreqRange\n");
1798         pr_info("  .Fmin = 0x%x\n",
1799                 pptable->UclkDpmTargFreqRange.Fmin);
1800         pr_info("  .Fmax = 0x%x\n",
1801                 pptable->UclkDpmTargFreqRange.Fmax);
1802         pr_info("UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
1803         pr_info("UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
1804
1805         pr_info("PcieGenSpeed\n");
1806         for (i = 0; i < NUM_LINK_LEVELS; i++)
1807                 pr_info("  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
1808
1809         pr_info("PcieLaneCount\n");
1810         for (i = 0; i < NUM_LINK_LEVELS; i++)
1811                 pr_info("  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
1812
1813         pr_info("LclkFreq\n");
1814         for (i = 0; i < NUM_LINK_LEVELS; i++)
1815                 pr_info("  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
1816
1817         pr_info("FanStopTemp = 0x%x\n", pptable->FanStopTemp);
1818         pr_info("FanStartTemp = 0x%x\n", pptable->FanStartTemp);
1819
1820         pr_info("FanGain\n");
1821         for (i = 0; i < TEMP_COUNT; i++)
1822                 pr_info("  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
1823
1824         pr_info("FanPwmMin = 0x%x\n", pptable->FanPwmMin);
1825         pr_info("FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
1826         pr_info("FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
1827         pr_info("FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
1828         pr_info("MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
1829         pr_info("FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
1830         pr_info("FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
1831         pr_info("FanPadding16 = 0x%x\n", pptable->FanPadding16);
1832         pr_info("FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
1833         pr_info("FanPadding = 0x%x\n", pptable->FanPadding);
1834         pr_info("FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
1835         pr_info("FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
1836
1837         pr_info("FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
1838         pr_info("FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
1839         pr_info("FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
1840         pr_info("FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
1841
1842         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1843         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1844         pr_info("dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
1845         pr_info("Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
1846
1847         pr_info("qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1848                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
1849                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
1850                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
1851         pr_info("qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1852                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
1853                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
1854                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
1855         pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1856                         pptable->dBtcGbGfxPll.a,
1857                         pptable->dBtcGbGfxPll.b,
1858                         pptable->dBtcGbGfxPll.c);
1859         pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1860                         pptable->dBtcGbGfxDfll.a,
1861                         pptable->dBtcGbGfxDfll.b,
1862                         pptable->dBtcGbGfxDfll.c);
1863         pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1864                         pptable->dBtcGbSoc.a,
1865                         pptable->dBtcGbSoc.b,
1866                         pptable->dBtcGbSoc.c);
1867         pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1868                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1869                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1870         pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1871                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1872                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1873
1874         pr_info("PiecewiseLinearDroopIntGfxDfll\n");
1875         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
1876                 pr_info("               Fset[%d] = 0x%x\n",
1877                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
1878                 pr_info("               Vdroop[%d] = 0x%x\n",
1879                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
1880         }
1881
1882         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1883                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1884                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1885                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1886         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1887                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1888                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1889                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1890
1891         pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1892         pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1893
1894         pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1895         pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1896         pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1897         pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1898
1899         pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1900         pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1901         pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1902         pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1903
1904         pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1905         pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1906
1907         pr_info("XgmiDpmPstates\n");
1908         for (i = 0; i < NUM_XGMI_LEVELS; i++)
1909                 pr_info("  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
1910         pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1911         pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1912
1913         pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1914         pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1915                         pptable->ReservedEquation0.a,
1916                         pptable->ReservedEquation0.b,
1917                         pptable->ReservedEquation0.c);
1918         pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1919                         pptable->ReservedEquation1.a,
1920                         pptable->ReservedEquation1.b,
1921                         pptable->ReservedEquation1.c);
1922         pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1923                         pptable->ReservedEquation2.a,
1924                         pptable->ReservedEquation2.b,
1925                         pptable->ReservedEquation2.c);
1926         pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1927                         pptable->ReservedEquation3.a,
1928                         pptable->ReservedEquation3.b,
1929                         pptable->ReservedEquation3.c);
1930
1931         pr_info("SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
1932         pr_info("SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
1933         pr_info("SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
1934         pr_info("SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
1935         pr_info("SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
1936         pr_info("SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
1937         pr_info("SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
1938         pr_info("SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
1939         pr_info("SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]);
1940         pr_info("SkuReserved[9] = 0x%x\n", pptable->SkuReserved[9]);
1941         pr_info("SkuReserved[10] = 0x%x\n", pptable->SkuReserved[10]);
1942         pr_info("SkuReserved[11] = 0x%x\n", pptable->SkuReserved[11]);
1943         pr_info("SkuReserved[12] = 0x%x\n", pptable->SkuReserved[12]);
1944         pr_info("SkuReserved[13] = 0x%x\n", pptable->SkuReserved[13]);
1945         pr_info("SkuReserved[14] = 0x%x\n", pptable->SkuReserved[14]);
1946
1947         pr_info("GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
1948         pr_info("GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
1949         pr_info("GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
1950         pr_info("GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
1951         pr_info("GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
1952         pr_info("GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
1953
1954         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1955                 pr_info("I2cControllers[%d]:\n", i);
1956                 pr_info("                   .Enabled = 0x%x\n",
1957                                 pptable->I2cControllers[i].Enabled);
1958                 pr_info("                   .Speed = 0x%x\n",
1959                                 pptable->I2cControllers[i].Speed);
1960                 pr_info("                   .SlaveAddress = 0x%x\n",
1961                                 pptable->I2cControllers[i].SlaveAddress);
1962                 pr_info("                   .ControllerPort = 0x%x\n",
1963                                 pptable->I2cControllers[i].ControllerPort);
1964                 pr_info("                   .ControllerName = 0x%x\n",
1965                                 pptable->I2cControllers[i].ControllerName);
1966                 pr_info("                   .ThermalThrottler = 0x%x\n",
1967                                 pptable->I2cControllers[i].ThermalThrotter);
1968                 pr_info("                   .I2cProtocol = 0x%x\n",
1969                                 pptable->I2cControllers[i].I2cProtocol);
1970                 pr_info("                   .PaddingConfig = 0x%x\n",
1971                                 pptable->I2cControllers[i].PaddingConfig);
1972         }
1973
1974         pr_info("GpioScl = 0x%x\n", pptable->GpioScl);
1975         pr_info("GpioSda = 0x%x\n", pptable->GpioSda);
1976         pr_info("FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
1977         pr_info("I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
1978
1979         pr_info("Board Parameters:\n");
1980         pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1981         pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1982         pr_info("VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
1983         pr_info("VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
1984         pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1985         pr_info("SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
1986         pr_info("VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
1987         pr_info("MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
1988
1989         pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1990         pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
1991         pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1992
1993         pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1994         pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
1995         pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1996
1997         pr_info("Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
1998         pr_info("Mem0Offset = 0x%x\n", pptable->Mem0Offset);
1999         pr_info("Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2000
2001         pr_info("Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2002         pr_info("Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2003         pr_info("Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2004
2005         pr_info("MvddRatio = 0x%x\n", pptable->MvddRatio);
2006
2007         pr_info("AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2008         pr_info("AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2009         pr_info("VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2010         pr_info("VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2011         pr_info("VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2012         pr_info("VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2013         pr_info("GthrGpio = 0x%x\n", pptable->GthrGpio);
2014         pr_info("GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2015         pr_info("LedPin0 = 0x%x\n", pptable->LedPin0);
2016         pr_info("LedPin1 = 0x%x\n", pptable->LedPin1);
2017         pr_info("LedPin2 = 0x%x\n", pptable->LedPin2);
2018         pr_info("LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2019         pr_info("LedPcie = 0x%x\n", pptable->LedPcie);
2020         pr_info("LedError = 0x%x\n", pptable->LedError);
2021         pr_info("LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2022         pr_info("LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2023
2024         pr_info("PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2025         pr_info("PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2026         pr_info("PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
2027
2028         pr_info("DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2029         pr_info("DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2030         pr_info("DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
2031
2032         pr_info("UclkSpreadEnabled = 0x%x\n", pptable->UclkSpreadEnabled);
2033         pr_info("UclkSpreadPercent = 0x%x\n", pptable->UclkSpreadPercent);
2034         pr_info("UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2035
2036         pr_info("FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2037         pr_info("FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2038         pr_info("FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2039
2040         pr_info("MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2041         pr_info("DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2042         pr_info("PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2043         pr_info("PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2044         pr_info("PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2045
2046         pr_info("TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2047         pr_info("BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2048
2049         pr_info("XgmiLinkSpeed\n");
2050         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2051                 pr_info("  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2052         pr_info("XgmiLinkWidth\n");
2053         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2054                 pr_info("  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2055         pr_info("XgmiFclkFreq\n");
2056         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2057                 pr_info("  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2058         pr_info("XgmiSocVoltage\n");
2059         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2060                 pr_info("  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2061
2062         pr_info("HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2063         pr_info("VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2064         pr_info("PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2065         pr_info("PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2066
2067         pr_info("BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2068         pr_info("BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2069         pr_info("BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2070         pr_info("BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2071         pr_info("BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2072         pr_info("BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2073         pr_info("BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2074         pr_info("BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2075         pr_info("BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2076         pr_info("BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2077         pr_info("BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2078         pr_info("BoardReserved[11] = 0x%x\n", pptable->BoardReserved[11]);
2079         pr_info("BoardReserved[12] = 0x%x\n", pptable->BoardReserved[12]);
2080         pr_info("BoardReserved[13] = 0x%x\n", pptable->BoardReserved[13]);
2081         pr_info("BoardReserved[14] = 0x%x\n", pptable->BoardReserved[14]);
2082
2083         pr_info("MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2084         pr_info("MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2085         pr_info("MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2086         pr_info("MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2087         pr_info("MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2088         pr_info("MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2089         pr_info("MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2090         pr_info("MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2091 }
2092
2093 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
2094         .tables_init = sienna_cichlid_tables_init,
2095         .alloc_dpm_context = sienna_cichlid_allocate_dpm_context,
2096         .store_powerplay_table = sienna_cichlid_store_powerplay_table,
2097         .check_powerplay_table = sienna_cichlid_check_powerplay_table,
2098         .append_powerplay_table = sienna_cichlid_append_powerplay_table,
2099         .get_smu_msg_index = sienna_cichlid_get_smu_msg_index,
2100         .get_smu_clk_index = sienna_cichlid_get_smu_clk_index,
2101         .get_smu_feature_index = sienna_cichlid_get_smu_feature_index,
2102         .get_smu_table_index = sienna_cichlid_get_smu_table_index,
2103         .get_workload_type = sienna_cichlid_get_workload_type,
2104         .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
2105         .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
2106         .dpm_set_uvd_enable = sienna_cichlid_dpm_set_uvd_enable,
2107         .get_current_clk_freq_by_table = sienna_cichlid_get_current_clk_freq_by_table,
2108         .print_clk_levels = sienna_cichlid_print_clk_levels,
2109         .force_clk_levels = sienna_cichlid_force_clk_levels,
2110         .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
2111         .get_clock_by_type_with_latency = sienna_cichlid_get_clock_by_type_with_latency,
2112         .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
2113         .display_config_changed = sienna_cichlid_display_config_changed,
2114         .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
2115         .force_dpm_limit_value = sienna_cichlid_force_dpm_limit_value,
2116         .unforce_dpm_levels = sienna_cichlid_unforce_dpm_levels,
2117         .is_dpm_running = sienna_cichlid_is_dpm_running,
2118         .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent,
2119         .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
2120         .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
2121         .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
2122         .get_profiling_clk_mask = sienna_cichlid_get_profiling_clk_mask,
2123         .set_watermarks_table = sienna_cichlid_set_watermarks_table,
2124         .read_sensor = sienna_cichlid_read_sensor,
2125         .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
2126         .set_performance_level = sienna_cichlid_set_performance_level,
2127         .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
2128         .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
2129         .get_power_limit = sienna_cichlid_get_power_limit,
2130         .dump_pptable = sienna_cichlid_dump_pptable,
2131         .init_microcode = smu_v11_0_init_microcode,
2132         .load_microcode = smu_v11_0_load_microcode,
2133         .init_smc_tables = smu_v11_0_init_smc_tables,
2134         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2135         .init_power = smu_v11_0_init_power,
2136         .fini_power = smu_v11_0_fini_power,
2137         .check_fw_status = smu_v11_0_check_fw_status,
2138         .setup_pptable = smu_v11_0_setup_pptable,
2139         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2140         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2141         .check_pptable = smu_v11_0_check_pptable,
2142         .parse_pptable = smu_v11_0_parse_pptable,
2143         .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2144         .check_fw_version = smu_v11_0_check_fw_version,
2145         .write_pptable = smu_v11_0_write_pptable,
2146         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2147         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2148         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2149         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2150         .system_features_control = smu_v11_0_system_features_control,
2151         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2152         .init_display_count = smu_v11_0_init_display_count,
2153         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2154         .get_enabled_mask = smu_v11_0_get_enabled_mask,
2155         .notify_display_change = smu_v11_0_notify_display_change,
2156         .set_power_limit = smu_v11_0_set_power_limit,
2157         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2158         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2159         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2160         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2161         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2162         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2163         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2164         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2165         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2166         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2167         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2168         .gfx_off_control = smu_v11_0_gfx_off_control,
2169         .register_irq_handler = smu_v11_0_register_irq_handler,
2170         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2171         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2172         .baco_is_support= smu_v11_0_baco_is_support,
2173         .baco_get_state = smu_v11_0_baco_get_state,
2174         .baco_set_state = smu_v11_0_baco_set_state,
2175         .baco_enter = smu_v11_0_baco_enter,
2176         .baco_exit = smu_v11_0_baco_exit,
2177         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2178         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2179         .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2180 };
2181
2182 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
2183 {
2184         smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
2185 }