drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include <linux/pci.h>
  28 #include <linux/i2c.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_smu.h"
  31 #include "atomfirmware.h"
  32 #include "amdgpu_atomfirmware.h"
  33 #include "amdgpu_atombios.h"
  34 #include "smu_v11_0.h"
  35 #include "smu11_driver_if_sienna_cichlid.h"
  36 #include "soc15_common.h"
  37 #include "atom.h"
  38 #include "sienna_cichlid_ppt.h"
  39 #include "smu_v11_0_7_pptable.h"
  40 #include "smu_v11_0_7_ppsmc.h"
  41 #include "nbio/nbio_2_3_offset.h"
  42 #include "nbio/nbio_2_3_sh_mask.h"
  43 #include "thm/thm_11_0_2_offset.h"
  44 #include "thm/thm_11_0_2_sh_mask.h"
  45 #include "mp/mp_11_0_offset.h"
  46 #include "mp/mp_11_0_sh_mask.h"
  47
  48 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  49 #include "smu_cmn.h"
  50
  51 /*
  52  * DO NOT use these for err/warn/info/debug messages.
  53  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  54  * They are more MGPU friendly.
  55  */
  56 #undef pr_err
  57 #undef pr_warn
  58 #undef pr_info
  59 #undef pr_debug
  60
  61 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  62
  63 #define FEATURE_MASK(feature) (1ULL << feature)
  64 #define SMC_DPM_FEATURE ( \
  65         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  66         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  67         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  68         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  69         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  70         FEATURE_MASK(FEATURE_DPM_FCLK_BIT)       | \
  71         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
  72
  73 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
  74
  75 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
  76         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                 1),
  77         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,               1),
  78         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,          1),
  79         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,   0),
  80         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,  0),
  81         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,        0),
  82         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,       0),
  83         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,        1),
  84         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,       1),
  85         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,       1),
  86         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,      1),
  87         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow,    1),
  88         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),
  89         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,             1),
  90         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                 0),
  91         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,       0),
  92         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,        0),
  93         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,        0),
  94         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,         0),
  95         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,       0),
  96         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,       0),
  97         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,           0),
  98         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                   0),
  99         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,            0),
 100         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,            0),
 101         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,            1),
 102         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,            0),
 103         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,               1),
 104         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,               1),
 105         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,           1),
 106         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode,               0),
 107         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh,       0),
 108         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow,        0),
 109         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,      0),
 110         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,       0),
 111         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,           0),
 112         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch,           0),
 113         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                 0),
 114         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,         1),
 115         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                 0),
 116         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,              0),
 117         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                 0),
 118         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,         1),
 119         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                    0),
 120         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                  0),
 121         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                0),
 122         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                 0),
 123         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,               0),
 124         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME,              0),
 125         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3,                       0),
 126         MSG_MAP(Mode1Reset,                     PPSMC_MSG_Mode1Reset,                  0),
 127         MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
 128 };
 129
 130 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
 131         CLK_MAP(GFXCLK,         PPCLK_GFXCLK),
 132         CLK_MAP(SCLK,           PPCLK_GFXCLK),
 133         CLK_MAP(SOCCLK,         PPCLK_SOCCLK),
 134         CLK_MAP(FCLK,           PPCLK_FCLK),
 135         CLK_MAP(UCLK,           PPCLK_UCLK),
 136         CLK_MAP(MCLK,           PPCLK_UCLK),
 137         CLK_MAP(DCLK,           PPCLK_DCLK_0),
 138         CLK_MAP(DCLK1,          PPCLK_DCLK_1),
 139         CLK_MAP(VCLK,           PPCLK_VCLK_0),
 140         CLK_MAP(VCLK1,          PPCLK_VCLK_1),
 141         CLK_MAP(DCEFCLK,        PPCLK_DCEFCLK),
 142         CLK_MAP(DISPCLK,        PPCLK_DISPCLK),
 143         CLK_MAP(PIXCLK,         PPCLK_PIXCLK),
 144         CLK_MAP(PHYCLK,         PPCLK_PHYCLK),
 145 };
 146
 147 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
 148         FEA_MAP(DPM_PREFETCHER),
 149         FEA_MAP(DPM_GFXCLK),
 150         FEA_MAP(DPM_GFX_GPO),
 151         FEA_MAP(DPM_UCLK),
 152         FEA_MAP(DPM_SOCCLK),
 153         FEA_MAP(DPM_MP0CLK),
 154         FEA_MAP(DPM_LINK),
 155         FEA_MAP(DPM_DCEFCLK),
 156         FEA_MAP(MEM_VDDCI_SCALING),
 157         FEA_MAP(MEM_MVDD_SCALING),
 158         FEA_MAP(DS_GFXCLK),
 159         FEA_MAP(DS_SOCCLK),
 160         FEA_MAP(DS_LCLK),
 161         FEA_MAP(DS_DCEFCLK),
 162         FEA_MAP(DS_UCLK),
 163         FEA_MAP(GFX_ULV),
 164         FEA_MAP(FW_DSTATE),
 165         FEA_MAP(GFXOFF),
 166         FEA_MAP(BACO),
 167         FEA_MAP(MM_DPM_PG),
 168         FEA_MAP(RSMU_SMN_CG),
 169         FEA_MAP(PPT),
 170         FEA_MAP(TDC),
 171         FEA_MAP(APCC_PLUS),
 172         FEA_MAP(GTHR),
 173         FEA_MAP(ACDC),
 174         FEA_MAP(VR0HOT),
 175         FEA_MAP(VR1HOT),
 176         FEA_MAP(FW_CTF),
 177         FEA_MAP(FAN_CONTROL),
 178         FEA_MAP(THERMAL),
 179         FEA_MAP(GFX_DCS),
 180         FEA_MAP(RM),
 181         FEA_MAP(LED_DISPLAY),
 182         FEA_MAP(GFX_SS),
 183         FEA_MAP(OUT_OF_BAND_MONITOR),
 184         FEA_MAP(TEMP_DEPENDENT_VMIN),
 185         FEA_MAP(MMHUB_PG),
 186         FEA_MAP(ATHUB_PG),
 187         FEA_MAP(APCC_DFLL),
 188 };
 189
 190 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
 191         TAB_MAP(PPTABLE),
 192         TAB_MAP(WATERMARKS),
 193         TAB_MAP(AVFS_PSM_DEBUG),
 194         TAB_MAP(AVFS_FUSE_OVERRIDE),
 195         TAB_MAP(PMSTATUSLOG),
 196         TAB_MAP(SMU_METRICS),
 197         TAB_MAP(DRIVER_SMU_CONFIG),
 198         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 199         TAB_MAP(OVERDRIVE),
 200         TAB_MAP(I2C_COMMANDS),
 201         TAB_MAP(PACE),
 202 };
 203
 204 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 205         PWR_MAP(AC),
 206         PWR_MAP(DC),
 207 };
 208
 209 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 210         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 211         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 212         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 213         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 214         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 215         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_CUSTOM_BIT),
 216         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 217 };
 218
 219 static int
 220 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 221                                   uint32_t *feature_mask, uint32_t num)
 222 {
 223         struct amdgpu_device *adev = smu->adev;
 224
 225         if (num > 2)
 226                 return -EINVAL;
 227
 228         memset(feature_mask, 0, sizeof(uint32_t) * num);
 229
 230         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 231                                 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
 232                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 233                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 234                                 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
 235                                 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
 236                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 237                                 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
 238                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 239                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 240                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 241                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 242                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 243                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 244                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 245                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 246                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 247                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 248                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 249
 250         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
 251                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 252                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
 253         }
 254
 255         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 256                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 257                                         | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 258                                         | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 259
 260         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 261                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 262
 263         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 264                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 265
 266         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 267                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 268
 269         if (adev->pm.pp_feature & PP_ULV_MASK)
 270                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 271
 272         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 273                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 274
 275         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 276                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 277
 278         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 279                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 280
 281         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 282                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 283
 284         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
 285             smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 286                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
 287
 288         return 0;
 289 }
 290
 291 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
 292 {
 293         struct smu_table_context *table_context = &smu->smu_table;
 294         struct smu_11_0_7_powerplay_table *powerplay_table =
 295                 table_context->power_play_table;
 296         struct smu_baco_context *smu_baco = &smu->smu_baco;
 297
 298         mutex_lock(&smu_baco->mutex);
 299         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO ||
 300             powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO)
 301                 smu_baco->platform_support = true;
 302         mutex_unlock(&smu_baco->mutex);
 303
 304         table_context->thermal_controller_type =
 305                 powerplay_table->thermal_controller_type;
 306
 307         return 0;
 308 }
 309
 310 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
 311 {
 312         struct smu_table_context *table_context = &smu->smu_table;
 313         PPTable_t *smc_pptable = table_context->driver_pptable;
 314         struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
 315         int index, ret;
 316
 317         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 318                                             smc_dpm_info);
 319
 320         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 321                                       (uint8_t **)&smc_dpm_table);
 322         if (ret)
 323                 return ret;
 324
 325         memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 326                sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
 327
 328         return 0;
 329 }
 330
 331 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
 332 {
 333         struct smu_table_context *table_context = &smu->smu_table;
 334         struct smu_11_0_7_powerplay_table *powerplay_table =
 335                 table_context->power_play_table;
 336
 337         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 338                sizeof(PPTable_t));
 339
 340         return 0;
 341 }
 342
 343 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
 344 {
 345         int ret = 0;
 346
 347         ret = smu_v11_0_setup_pptable(smu);
 348         if (ret)
 349                 return ret;
 350
 351         ret = sienna_cichlid_store_powerplay_table(smu);
 352         if (ret)
 353                 return ret;
 354
 355         ret = sienna_cichlid_append_powerplay_table(smu);
 356         if (ret)
 357                 return ret;
 358
 359         ret = sienna_cichlid_check_powerplay_table(smu);
 360         if (ret)
 361                 return ret;
 362
 363         return ret;
 364 }
 365
 366 static int sienna_cichlid_tables_init(struct smu_context *smu)
 367 {
 368         struct smu_table_context *smu_table = &smu->smu_table;
 369         struct smu_table *tables = smu_table->tables;
 370
 371         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 372                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 373         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 374                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 375         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 376                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 377         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 378                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 379         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 380                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 381         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 382                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 383         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 384                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 385                        AMDGPU_GEM_DOMAIN_VRAM);
 386
 387         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 388         if (!smu_table->metrics_table)
 389                 goto err0_out;
 390         smu_table->metrics_time = 0;
 391
 392         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0);
 393         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 394         if (!smu_table->gpu_metrics_table)
 395                 goto err1_out;
 396
 397         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 398         if (!smu_table->watermarks_table)
 399                 goto err2_out;
 400
 401         return 0;
 402
 403 err2_out:
 404         kfree(smu_table->gpu_metrics_table);
 405 err1_out:
 406         kfree(smu_table->metrics_table);
 407 err0_out:
 408         return -ENOMEM;
 409 }
 410
 411 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
 412                                                MetricsMember_t member,
 413                                                uint32_t *value)
 414 {
 415         struct smu_table_context *smu_table= &smu->smu_table;
 416         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 417         int ret = 0;
 418
 419         mutex_lock(&smu->metrics_lock);
 420
 421         ret = smu_cmn_get_metrics_table_locked(smu,
 422                                                NULL,
 423                                                false);
 424         if (ret) {
 425                 mutex_unlock(&smu->metrics_lock);
 426                 return ret;
 427         }
 428
 429         switch (member) {
 430         case METRICS_CURR_GFXCLK:
 431                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 432                 break;
 433         case METRICS_CURR_SOCCLK:
 434                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 435                 break;
 436         case METRICS_CURR_UCLK:
 437                 *value = metrics->CurrClock[PPCLK_UCLK];
 438                 break;
 439         case METRICS_CURR_VCLK:
 440                 *value = metrics->CurrClock[PPCLK_VCLK_0];
 441                 break;
 442         case METRICS_CURR_VCLK1:
 443                 *value = metrics->CurrClock[PPCLK_VCLK_1];
 444                 break;
 445         case METRICS_CURR_DCLK:
 446                 *value = metrics->CurrClock[PPCLK_DCLK_0];
 447                 break;
 448         case METRICS_CURR_DCLK1:
 449                 *value = metrics->CurrClock[PPCLK_DCLK_1];
 450                 break;
 451         case METRICS_CURR_DCEFCLK:
 452                 *value = metrics->CurrClock[PPCLK_DCEFCLK];
 453                 break;
 454         case METRICS_AVERAGE_GFXCLK:
 455                 if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
 456                         *value = metrics->AverageGfxclkFrequencyPostDs;
 457                 else
 458                         *value = metrics->AverageGfxclkFrequencyPreDs;
 459                 break;
 460         case METRICS_AVERAGE_FCLK:
 461                 *value = metrics->AverageFclkFrequencyPostDs;
 462                 break;
 463         case METRICS_AVERAGE_UCLK:
 464                 *value = metrics->AverageUclkFrequencyPostDs;
 465                 break;
 466         case METRICS_AVERAGE_GFXACTIVITY:
 467                 *value = metrics->AverageGfxActivity;
 468                 break;
 469         case METRICS_AVERAGE_MEMACTIVITY:
 470                 *value = metrics->AverageUclkActivity;
 471                 break;
 472         case METRICS_AVERAGE_SOCKETPOWER:
 473                 *value = metrics->AverageSocketPower << 8;
 474                 break;
 475         case METRICS_TEMPERATURE_EDGE:
 476                 *value = metrics->TemperatureEdge *
 477                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 478                 break;
 479         case METRICS_TEMPERATURE_HOTSPOT:
 480                 *value = metrics->TemperatureHotspot *
 481                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 482                 break;
 483         case METRICS_TEMPERATURE_MEM:
 484                 *value = metrics->TemperatureMem *
 485                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 486                 break;
 487         case METRICS_TEMPERATURE_VRGFX:
 488                 *value = metrics->TemperatureVrGfx *
 489                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 490                 break;
 491         case METRICS_TEMPERATURE_VRSOC:
 492                 *value = metrics->TemperatureVrSoc *
 493                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 494                 break;
 495         case METRICS_THROTTLER_STATUS:
 496                 *value = metrics->ThrottlerStatus;
 497                 break;
 498         case METRICS_CURR_FANSPEED:
 499                 *value = metrics->CurrFanSpeed;
 500                 break;
 501         default:
 502                 *value = UINT_MAX;
 503                 break;
 504         }
 505
 506         mutex_unlock(&smu->metrics_lock);
 507
 508         return ret;
 509
 510 }
 511
 512 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
 513 {
 514         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 515
 516         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 517                                        GFP_KERNEL);
 518         if (!smu_dpm->dpm_context)
 519                 return -ENOMEM;
 520
 521         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 522
 523         return 0;
 524 }
 525
 526 static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
 527 {
 528         int ret = 0;
 529
 530         ret = sienna_cichlid_tables_init(smu);
 531         if (ret)
 532                 return ret;
 533
 534         ret = sienna_cichlid_allocate_dpm_context(smu);
 535         if (ret)
 536                 return ret;
 537
 538         return smu_v11_0_init_smc_tables(smu);
 539 }
 540
 541 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 542 {
 543         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 544         PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 545         struct smu_11_0_dpm_table *dpm_table;
 546         struct amdgpu_device *adev = smu->adev;
 547         int ret = 0;
 548
 549         /* socclk dpm table setup */
 550         dpm_table = &dpm_context->dpm_tables.soc_table;
 551         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 552                 ret = smu_v11_0_set_single_dpm_table(smu,
 553                                                      SMU_SOCCLK,
 554                                                      dpm_table);
 555                 if (ret)
 556                         return ret;
 557                 dpm_table->is_fine_grained =
 558                         !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
 559         } else {
 560                 dpm_table->count = 1;
 561                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 562                 dpm_table->dpm_levels[0].enabled = true;
 563                 dpm_table->min = dpm_table->dpm_levels[0].value;
 564                 dpm_table->max = dpm_table->dpm_levels[0].value;
 565         }
 566
 567         /* gfxclk dpm table setup */
 568         dpm_table = &dpm_context->dpm_tables.gfx_table;
 569         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 570                 ret = smu_v11_0_set_single_dpm_table(smu,
 571                                                      SMU_GFXCLK,
 572                                                      dpm_table);
 573                 if (ret)
 574                         return ret;
 575                 dpm_table->is_fine_grained =
 576                         !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
 577         } else {
 578                 dpm_table->count = 1;
 579                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 580                 dpm_table->dpm_levels[0].enabled = true;
 581                 dpm_table->min = dpm_table->dpm_levels[0].value;
 582                 dpm_table->max = dpm_table->dpm_levels[0].value;
 583         }
 584
 585         /* uclk dpm table setup */
 586         dpm_table = &dpm_context->dpm_tables.uclk_table;
 587         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 588                 ret = smu_v11_0_set_single_dpm_table(smu,
 589                                                      SMU_UCLK,
 590                                                      dpm_table);
 591                 if (ret)
 592                         return ret;
 593                 dpm_table->is_fine_grained =
 594                         !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
 595         } else {
 596                 dpm_table->count = 1;
 597                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 598                 dpm_table->dpm_levels[0].enabled = true;
 599                 dpm_table->min = dpm_table->dpm_levels[0].value;
 600                 dpm_table->max = dpm_table->dpm_levels[0].value;
 601         }
 602
 603         /* fclk dpm table setup */
 604         dpm_table = &dpm_context->dpm_tables.fclk_table;
 605         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 606                 ret = smu_v11_0_set_single_dpm_table(smu,
 607                                                      SMU_FCLK,
 608                                                      dpm_table);
 609                 if (ret)
 610                         return ret;
 611                 dpm_table->is_fine_grained =
 612                         !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
 613         } else {
 614                 dpm_table->count = 1;
 615                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 616                 dpm_table->dpm_levels[0].enabled = true;
 617                 dpm_table->min = dpm_table->dpm_levels[0].value;
 618                 dpm_table->max = dpm_table->dpm_levels[0].value;
 619         }
 620
 621         /* vclk0 dpm table setup */
 622         dpm_table = &dpm_context->dpm_tables.vclk_table;
 623         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 624                 ret = smu_v11_0_set_single_dpm_table(smu,
 625                                                      SMU_VCLK,
 626                                                      dpm_table);
 627                 if (ret)
 628                         return ret;
 629                 dpm_table->is_fine_grained =
 630                         !driver_ppt->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete;
 631         } else {
 632                 dpm_table->count = 1;
 633                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
 634                 dpm_table->dpm_levels[0].enabled = true;
 635                 dpm_table->min = dpm_table->dpm_levels[0].value;
 636                 dpm_table->max = dpm_table->dpm_levels[0].value;
 637         }
 638
 639         /* vclk1 dpm table setup */
 640         if (adev->vcn.num_vcn_inst > 1) {
 641                 dpm_table = &dpm_context->dpm_tables.vclk1_table;
 642                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 643                         ret = smu_v11_0_set_single_dpm_table(smu,
 644                                                              SMU_VCLK1,
 645                                                              dpm_table);
 646                         if (ret)
 647                                 return ret;
 648                         dpm_table->is_fine_grained =
 649                                 !driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
 650                 } else {
 651                         dpm_table->count = 1;
 652                         dpm_table->dpm_levels[0].value =
 653                                 smu->smu_table.boot_values.vclk / 100;
 654                         dpm_table->dpm_levels[0].enabled = true;
 655                         dpm_table->min = dpm_table->dpm_levels[0].value;
 656                         dpm_table->max = dpm_table->dpm_levels[0].value;
 657                 }
 658         }
 659
 660         /* dclk0 dpm table setup */
 661         dpm_table = &dpm_context->dpm_tables.dclk_table;
 662         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 663                 ret = smu_v11_0_set_single_dpm_table(smu,
 664                                                      SMU_DCLK,
 665                                                      dpm_table);
 666                 if (ret)
 667                         return ret;
 668                 dpm_table->is_fine_grained =
 669                         !driver_ppt->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete;
 670         } else {
 671                 dpm_table->count = 1;
 672                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
 673                 dpm_table->dpm_levels[0].enabled = true;
 674                 dpm_table->min = dpm_table->dpm_levels[0].value;
 675                 dpm_table->max = dpm_table->dpm_levels[0].value;
 676         }
 677
 678         /* dclk1 dpm table setup */
 679         if (adev->vcn.num_vcn_inst > 1) {
 680                 dpm_table = &dpm_context->dpm_tables.dclk1_table;
 681                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 682                         ret = smu_v11_0_set_single_dpm_table(smu,
 683                                                              SMU_DCLK1,
 684                                                              dpm_table);
 685                         if (ret)
 686                                 return ret;
 687                         dpm_table->is_fine_grained =
 688                                 !driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
 689                 } else {
 690                         dpm_table->count = 1;
 691                         dpm_table->dpm_levels[0].value =
 692                                 smu->smu_table.boot_values.dclk / 100;
 693                         dpm_table->dpm_levels[0].enabled = true;
 694                         dpm_table->min = dpm_table->dpm_levels[0].value;
 695                         dpm_table->max = dpm_table->dpm_levels[0].value;
 696                 }
 697         }
 698
 699         /* dcefclk dpm table setup */
 700         dpm_table = &dpm_context->dpm_tables.dcef_table;
 701         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 702                 ret = smu_v11_0_set_single_dpm_table(smu,
 703                                                      SMU_DCEFCLK,
 704                                                      dpm_table);
 705                 if (ret)
 706                         return ret;
 707                 dpm_table->is_fine_grained =
 708                         !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
 709         } else {
 710                 dpm_table->count = 1;
 711                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 712                 dpm_table->dpm_levels[0].enabled = true;
 713                 dpm_table->min = dpm_table->dpm_levels[0].value;
 714                 dpm_table->max = dpm_table->dpm_levels[0].value;
 715         }
 716
 717         /* pixelclk dpm table setup */
 718         dpm_table = &dpm_context->dpm_tables.pixel_table;
 719         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 720                 ret = smu_v11_0_set_single_dpm_table(smu,
 721                                                      SMU_PIXCLK,
 722                                                      dpm_table);
 723                 if (ret)
 724                         return ret;
 725                 dpm_table->is_fine_grained =
 726                         !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
 727         } else {
 728                 dpm_table->count = 1;
 729                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 730                 dpm_table->dpm_levels[0].enabled = true;
 731                 dpm_table->min = dpm_table->dpm_levels[0].value;
 732                 dpm_table->max = dpm_table->dpm_levels[0].value;
 733         }
 734
 735         /* displayclk dpm table setup */
 736         dpm_table = &dpm_context->dpm_tables.display_table;
 737         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 738                 ret = smu_v11_0_set_single_dpm_table(smu,
 739                                                      SMU_DISPCLK,
 740                                                      dpm_table);
 741                 if (ret)
 742                         return ret;
 743                 dpm_table->is_fine_grained =
 744                         !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
 745         } else {
 746                 dpm_table->count = 1;
 747                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 748                 dpm_table->dpm_levels[0].enabled = true;
 749                 dpm_table->min = dpm_table->dpm_levels[0].value;
 750                 dpm_table->max = dpm_table->dpm_levels[0].value;
 751         }
 752
 753         /* phyclk dpm table setup */
 754         dpm_table = &dpm_context->dpm_tables.phy_table;
 755         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 756                 ret = smu_v11_0_set_single_dpm_table(smu,
 757                                                      SMU_PHYCLK,
 758                                                      dpm_table);
 759                 if (ret)
 760                         return ret;
 761                 dpm_table->is_fine_grained =
 762                         !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
 763         } else {
 764                 dpm_table->count = 1;
 765                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 766                 dpm_table->dpm_levels[0].enabled = true;
 767                 dpm_table->min = dpm_table->dpm_levels[0].value;
 768                 dpm_table->max = dpm_table->dpm_levels[0].value;
 769         }
 770
 771         return 0;
 772 }
 773
 774 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 775 {
 776         struct amdgpu_device *adev = smu->adev;
 777         int ret = 0;
 778
 779         if (enable) {
 780                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 781                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 782                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
 783                         if (ret)
 784                                 return ret;
 785                         if (adev->asic_type == CHIP_SIENNA_CICHLID) {
 786                                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
 787                                                                   0x10000, NULL);
 788                                 if (ret)
 789                                         return ret;
 790                         }
 791                 }
 792         } else {
 793                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 794                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
 795                         if (ret)
 796                                 return ret;
 797                         if (adev->asic_type == CHIP_SIENNA_CICHLID) {
 798                                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
 799                                                                   0x10000, NULL);
 800                                 if (ret)
 801                                         return ret;
 802                         }
 803                 }
 804         }
 805
 806         return ret;
 807 }
 808
 809 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 810 {
 811         int ret = 0;
 812
 813         if (enable) {
 814                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 815                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
 816                         if (ret)
 817                                 return ret;
 818                 }
 819         } else {
 820                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 821                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
 822                         if (ret)
 823                                 return ret;
 824                 }
 825         }
 826
 827         return ret;
 828 }
 829
 830 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
 831                                        enum smu_clk_type clk_type,
 832                                        uint32_t *value)
 833 {
 834         MetricsMember_t member_type;
 835         int clk_id = 0;
 836
 837         clk_id = smu_cmn_to_asic_specific_index(smu,
 838                                                 CMN2ASIC_MAPPING_CLK,
 839                                                 clk_type);
 840         if (clk_id < 0)
 841                 return clk_id;
 842
 843         switch (clk_id) {
 844         case PPCLK_GFXCLK:
 845                 member_type = METRICS_CURR_GFXCLK;
 846                 break;
 847         case PPCLK_UCLK:
 848                 member_type = METRICS_CURR_UCLK;
 849                 break;
 850         case PPCLK_SOCCLK:
 851                 member_type = METRICS_CURR_SOCCLK;
 852                 break;
 853         case PPCLK_FCLK:
 854                 member_type = METRICS_CURR_FCLK;
 855                 break;
 856         case PPCLK_VCLK_0:
 857                 member_type = METRICS_CURR_VCLK;
 858                 break;
 859         case PPCLK_VCLK_1:
 860                 member_type = METRICS_CURR_VCLK1;
 861                 break;
 862         case PPCLK_DCLK_0:
 863                 member_type = METRICS_CURR_DCLK;
 864                 break;
 865         case PPCLK_DCLK_1:
 866                 member_type = METRICS_CURR_DCLK1;
 867                 break;
 868         case PPCLK_DCEFCLK:
 869                 member_type = METRICS_CURR_DCEFCLK;
 870                 break;
 871         default:
 872                 return -EINVAL;
 873         }
 874
 875         return sienna_cichlid_get_smu_metrics_data(smu,
 876                                                    member_type,
 877                                                    value);
 878
 879 }
 880
 881 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 882 {
 883         PPTable_t *pptable = smu->smu_table.driver_pptable;
 884         DpmDescriptor_t *dpm_desc = NULL;
 885         uint32_t clk_index = 0;
 886
 887         clk_index = smu_cmn_to_asic_specific_index(smu,
 888                                                    CMN2ASIC_MAPPING_CLK,
 889                                                    clk_type);
 890         dpm_desc = &pptable->DpmDescriptor[clk_index];
 891
 892         /* 0 - Fine grained DPM, 1 - Discrete DPM */
 893         return dpm_desc->SnapToDiscrete == 0 ? true : false;
 894 }
 895
 896 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
 897                         enum smu_clk_type clk_type, char *buf)
 898 {
 899         struct amdgpu_device *adev = smu->adev;
 900         struct smu_table_context *table_context = &smu->smu_table;
 901         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 902         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 903         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 904         int i, size = 0, ret = 0;
 905         uint32_t cur_value = 0, value = 0, count = 0;
 906         uint32_t freq_values[3] = {0};
 907         uint32_t mark_index = 0;
 908         uint32_t gen_speed, lane_width;
 909
 910         switch (clk_type) {
 911         case SMU_GFXCLK:
 912         case SMU_SCLK:
 913         case SMU_SOCCLK:
 914         case SMU_MCLK:
 915         case SMU_UCLK:
 916         case SMU_FCLK:
 917         case SMU_DCEFCLK:
 918                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
 919                 if (ret)
 920                         goto print_clk_out;
 921
 922                 /* no need to disable gfxoff when retrieving the current gfxclk */
 923                 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
 924                         amdgpu_gfx_off_ctrl(adev, false);
 925
 926                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
 927                 if (ret)
 928                         goto print_clk_out;
 929
 930                 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
 931                         for (i = 0; i < count; i++) {
 932                                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
 933                                 if (ret)
 934                                         goto print_clk_out;
 935
 936                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 937                                                 cur_value == value ? "*" : "");
 938                         }
 939                 } else {
 940                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
 941                         if (ret)
 942                                 goto print_clk_out;
 943                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
 944                         if (ret)
 945                                 goto print_clk_out;
 946
 947                         freq_values[1] = cur_value;
 948                         mark_index = cur_value == freq_values[0] ? 0 :
 949                                      cur_value == freq_values[2] ? 2 : 1;
 950                         if (mark_index != 1)
 951                                 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
 952
 953                         for (i = 0; i < 3; i++) {
 954                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
 955                                                 i == mark_index ? "*" : "");
 956                         }
 957
 958                 }
 959                 break;
 960         case SMU_PCIE:
 961                 gen_speed = smu_v11_0_get_current_pcie_link_speed(smu);
 962                 lane_width = smu_v11_0_get_current_pcie_link_width(smu);
 963                 for (i = 0; i < NUM_LINK_LEVELS; i++)
 964                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
 965                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
 966                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
 967                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
 968                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
 969                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
 970                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
 971                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
 972                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
 973                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
 974                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
 975                                         pptable->LclkFreq[i],
 976                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
 977                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
 978                                         "*" : "");
 979                 break;
 980         default:
 981                 break;
 982         }
 983
 984 print_clk_out:
 985         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
 986                 amdgpu_gfx_off_ctrl(adev, true);
 987
 988         return size;
 989 }
 990
 991 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
 992                                    enum smu_clk_type clk_type, uint32_t mask)
 993 {
 994         struct amdgpu_device *adev = smu->adev;
 995         int ret = 0, size = 0;
 996         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
 997
 998         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 999         soft_max_level = mask ? (fls(mask) - 1) : 0;
1000
1001         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1002                 amdgpu_gfx_off_ctrl(adev, false);
1003
1004         switch (clk_type) {
1005         case SMU_GFXCLK:
1006         case SMU_SCLK:
1007         case SMU_SOCCLK:
1008         case SMU_MCLK:
1009         case SMU_UCLK:
1010         case SMU_DCEFCLK:
1011         case SMU_FCLK:
1012                 /* There is only 2 levels for fine grained DPM */
1013                 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1014                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1015                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1016                 }
1017
1018                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1019                 if (ret)
1020                         goto forec_level_out;
1021
1022                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1023                 if (ret)
1024                         goto forec_level_out;
1025
1026                 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1027                 if (ret)
1028                         goto forec_level_out;
1029                 break;
1030         default:
1031                 break;
1032         }
1033
1034 forec_level_out:
1035         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1036                 amdgpu_gfx_off_ctrl(adev, true);
1037
1038         return size;
1039 }
1040
1041 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1042 {
1043         struct smu_11_0_dpm_context *dpm_context =
1044                                 smu->smu_dpm.dpm_context;
1045         struct smu_11_0_dpm_table *gfx_table =
1046                                 &dpm_context->dpm_tables.gfx_table;
1047         struct smu_11_0_dpm_table *mem_table =
1048                                 &dpm_context->dpm_tables.uclk_table;
1049         struct smu_11_0_dpm_table *soc_table =
1050                                 &dpm_context->dpm_tables.soc_table;
1051         struct smu_umd_pstate_table *pstate_table =
1052                                 &smu->pstate_table;
1053
1054         pstate_table->gfxclk_pstate.min = gfx_table->min;
1055         pstate_table->gfxclk_pstate.peak = gfx_table->max;
1056
1057         pstate_table->uclk_pstate.min = mem_table->min;
1058         pstate_table->uclk_pstate.peak = mem_table->max;
1059
1060         pstate_table->socclk_pstate.min = soc_table->min;
1061         pstate_table->socclk_pstate.peak = soc_table->max;
1062
1063         return 0;
1064 }
1065
1066 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1067 {
1068         int ret = 0;
1069         uint32_t max_freq = 0;
1070
1071         /* Sienna_Cichlid do not support to change display num currently */
1072         return 0;
1073 #if 0
1074         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1075         if (ret)
1076                 return ret;
1077 #endif
1078
1079         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1080                 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1081                 if (ret)
1082                         return ret;
1083                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1084                 if (ret)
1085                         return ret;
1086         }
1087
1088         return ret;
1089 }
1090
1091 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1092 {
1093         int ret = 0;
1094
1095         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1096             smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1097             smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1098 #if 0
1099                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1100                                                   smu->display_config->num_display,
1101                                                   NULL);
1102 #endif
1103                 if (ret)
1104                         return ret;
1105         }
1106
1107         return ret;
1108 }
1109
1110 static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)
1111 {
1112         if (!value)
1113                 return -EINVAL;
1114
1115         return sienna_cichlid_get_smu_metrics_data(smu,
1116                                                    METRICS_AVERAGE_SOCKETPOWER,
1117                                                    value);
1118 }
1119
1120 static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu,
1121                                                enum amd_pp_sensors sensor,
1122                                                uint32_t *value)
1123 {
1124         int ret = 0;
1125
1126         if (!value)
1127                 return -EINVAL;
1128
1129         switch (sensor) {
1130         case AMDGPU_PP_SENSOR_GPU_LOAD:
1131                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1132                                                           METRICS_AVERAGE_GFXACTIVITY,
1133                                                           value);
1134                 break;
1135         case AMDGPU_PP_SENSOR_MEM_LOAD:
1136                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1137                                                           METRICS_AVERAGE_MEMACTIVITY,
1138                                                           value);
1139                 break;
1140         default:
1141                 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1142                 return -EINVAL;
1143         }
1144
1145         return ret;
1146 }
1147
1148 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1149 {
1150         int ret = 0;
1151         uint32_t feature_mask[2];
1152         unsigned long feature_enabled;
1153         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1154         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1155                            ((uint64_t)feature_mask[1] << 32));
1156         return !!(feature_enabled & SMC_DPM_FEATURE);
1157 }
1158
1159 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1160                                     uint32_t *speed)
1161 {
1162         if (!speed)
1163                 return -EINVAL;
1164
1165         return sienna_cichlid_get_smu_metrics_data(smu,
1166                                                    METRICS_CURR_FANSPEED,
1167                                                    speed);
1168 }
1169
1170 static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu,
1171                                         uint32_t *speed)
1172 {
1173         int ret = 0;
1174         uint32_t percent = 0;
1175         uint32_t current_rpm;
1176         PPTable_t *pptable = smu->smu_table.driver_pptable;
1177
1178         ret = sienna_cichlid_get_fan_speed_rpm(smu, &current_rpm);
1179         if (ret)
1180                 return ret;
1181
1182         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1183         *speed = percent > 100 ? 100 : percent;
1184
1185         return ret;
1186 }
1187
1188 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1189 {
1190         DpmActivityMonitorCoeffInt_t activity_monitor;
1191         uint32_t i, size = 0;
1192         int16_t workload_type = 0;
1193         static const char *profile_name[] = {
1194                                         "BOOTUP_DEFAULT",
1195                                         "3D_FULL_SCREEN",
1196                                         "POWER_SAVING",
1197                                         "VIDEO",
1198                                         "VR",
1199                                         "COMPUTE",
1200                                         "CUSTOM"};
1201         static const char *title[] = {
1202                         "PROFILE_INDEX(NAME)",
1203                         "CLOCK_TYPE(NAME)",
1204                         "FPS",
1205                         "MinFreqType",
1206                         "MinActiveFreqType",
1207                         "MinActiveFreq",
1208                         "BoosterFreqType",
1209                         "BoosterFreq",
1210                         "PD_Data_limit_c",
1211                         "PD_Data_error_coeff",
1212                         "PD_Data_error_rate_coeff"};
1213         int result = 0;
1214
1215         if (!buf)
1216                 return -EINVAL;
1217
1218         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1219                         title[0], title[1], title[2], title[3], title[4], title[5],
1220                         title[6], title[7], title[8], title[9], title[10]);
1221
1222         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1223                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1224                 workload_type = smu_cmn_to_asic_specific_index(smu,
1225                                                                CMN2ASIC_MAPPING_WORKLOAD,
1226                                                                i);
1227                 if (workload_type < 0)
1228                         return -EINVAL;
1229
1230                 result = smu_cmn_update_table(smu,
1231                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1232                                           (void *)(&activity_monitor), false);
1233                 if (result) {
1234                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1235                         return result;
1236                 }
1237
1238                 size += sprintf(buf + size, "%2d %14s%s:\n",
1239                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1240
1241                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1242                         " ",
1243                         0,
1244                         "GFXCLK",
1245                         activity_monitor.Gfx_FPS,
1246                         activity_monitor.Gfx_MinFreqStep,
1247                         activity_monitor.Gfx_MinActiveFreqType,
1248                         activity_monitor.Gfx_MinActiveFreq,
1249                         activity_monitor.Gfx_BoosterFreqType,
1250                         activity_monitor.Gfx_BoosterFreq,
1251                         activity_monitor.Gfx_PD_Data_limit_c,
1252                         activity_monitor.Gfx_PD_Data_error_coeff,
1253                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1254
1255                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1256                         " ",
1257                         1,
1258                         "SOCCLK",
1259                         activity_monitor.Fclk_FPS,
1260                         activity_monitor.Fclk_MinFreqStep,
1261                         activity_monitor.Fclk_MinActiveFreqType,
1262                         activity_monitor.Fclk_MinActiveFreq,
1263                         activity_monitor.Fclk_BoosterFreqType,
1264                         activity_monitor.Fclk_BoosterFreq,
1265                         activity_monitor.Fclk_PD_Data_limit_c,
1266                         activity_monitor.Fclk_PD_Data_error_coeff,
1267                         activity_monitor.Fclk_PD_Data_error_rate_coeff);
1268
1269                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1270                         " ",
1271                         2,
1272                         "MEMLK",
1273                         activity_monitor.Mem_FPS,
1274                         activity_monitor.Mem_MinFreqStep,
1275                         activity_monitor.Mem_MinActiveFreqType,
1276                         activity_monitor.Mem_MinActiveFreq,
1277                         activity_monitor.Mem_BoosterFreqType,
1278                         activity_monitor.Mem_BoosterFreq,
1279                         activity_monitor.Mem_PD_Data_limit_c,
1280                         activity_monitor.Mem_PD_Data_error_coeff,
1281                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1282         }
1283
1284         return size;
1285 }
1286
1287 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1288 {
1289         DpmActivityMonitorCoeffInt_t activity_monitor;
1290         int workload_type, ret = 0;
1291
1292         smu->power_profile_mode = input[size];
1293
1294         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1295                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1296                 return -EINVAL;
1297         }
1298
1299         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1300
1301                 ret = smu_cmn_update_table(smu,
1302                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1303                                        (void *)(&activity_monitor), false);
1304                 if (ret) {
1305                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1306                         return ret;
1307                 }
1308
1309                 switch (input[0]) {
1310                 case 0: /* Gfxclk */
1311                         activity_monitor.Gfx_FPS = input[1];
1312                         activity_monitor.Gfx_MinFreqStep = input[2];
1313                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1314                         activity_monitor.Gfx_MinActiveFreq = input[4];
1315                         activity_monitor.Gfx_BoosterFreqType = input[5];
1316                         activity_monitor.Gfx_BoosterFreq = input[6];
1317                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1318                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1319                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1320                         break;
1321                 case 1: /* Socclk */
1322                         activity_monitor.Fclk_FPS = input[1];
1323                         activity_monitor.Fclk_MinFreqStep = input[2];
1324                         activity_monitor.Fclk_MinActiveFreqType = input[3];
1325                         activity_monitor.Fclk_MinActiveFreq = input[4];
1326                         activity_monitor.Fclk_BoosterFreqType = input[5];
1327                         activity_monitor.Fclk_BoosterFreq = input[6];
1328                         activity_monitor.Fclk_PD_Data_limit_c = input[7];
1329                         activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1330                         activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1331                         break;
1332                 case 2: /* Memlk */
1333                         activity_monitor.Mem_FPS = input[1];
1334                         activity_monitor.Mem_MinFreqStep = input[2];
1335                         activity_monitor.Mem_MinActiveFreqType = input[3];
1336                         activity_monitor.Mem_MinActiveFreq = input[4];
1337                         activity_monitor.Mem_BoosterFreqType = input[5];
1338                         activity_monitor.Mem_BoosterFreq = input[6];
1339                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1340                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1341                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1342                         break;
1343                 }
1344
1345                 ret = smu_cmn_update_table(smu,
1346                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1347                                        (void *)(&activity_monitor), true);
1348                 if (ret) {
1349                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1350                         return ret;
1351                 }
1352         }
1353
1354         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1355         workload_type = smu_cmn_to_asic_specific_index(smu,
1356                                                        CMN2ASIC_MAPPING_WORKLOAD,
1357                                                        smu->power_profile_mode);
1358         if (workload_type < 0)
1359                 return -EINVAL;
1360         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1361                                     1 << workload_type, NULL);
1362
1363         return ret;
1364 }
1365
1366 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1367 {
1368         struct smu_clocks min_clocks = {0};
1369         struct pp_display_clock_request clock_req;
1370         int ret = 0;
1371
1372         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1373         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1374         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1375
1376         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1377                 clock_req.clock_type = amd_pp_dcef_clock;
1378                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1379
1380                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1381                 if (!ret) {
1382                         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1383                                 ret = smu_cmn_send_smc_msg_with_param(smu,
1384                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1385                                                                   min_clocks.dcef_clock_in_sr/100,
1386                                                                   NULL);
1387                                 if (ret) {
1388                                         dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1389                                         return ret;
1390                                 }
1391                         }
1392                 } else {
1393                         dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1394                 }
1395         }
1396
1397         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1398                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1399                 if (ret) {
1400                         dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1401                         return ret;
1402                 }
1403         }
1404
1405         return 0;
1406 }
1407
1408 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1409                                                struct dm_pp_wm_sets_with_clock_ranges_soc15
1410                                                *clock_ranges)
1411 {
1412         Watermarks_t *table = smu->smu_table.watermarks_table;
1413         int ret = 0;
1414         int i;
1415
1416         if (clock_ranges) {
1417                 if (clock_ranges->num_wm_dmif_sets > 4 ||
1418                     clock_ranges->num_wm_mcif_sets > 4)
1419                         return -EINVAL;
1420
1421                 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1422                         table->WatermarkRow[1][i].MinClock =
1423                                 cpu_to_le16((uint16_t)
1424                                 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1425                                 1000));
1426                         table->WatermarkRow[1][i].MaxClock =
1427                                 cpu_to_le16((uint16_t)
1428                                 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1429                                 1000));
1430                         table->WatermarkRow[1][i].MinUclk =
1431                                 cpu_to_le16((uint16_t)
1432                                 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1433                                 1000));
1434                         table->WatermarkRow[1][i].MaxUclk =
1435                                 cpu_to_le16((uint16_t)
1436                                 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1437                                 1000));
1438                         table->WatermarkRow[1][i].WmSetting = (uint8_t)
1439                                         clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1440                 }
1441
1442                 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1443                         table->WatermarkRow[0][i].MinClock =
1444                                 cpu_to_le16((uint16_t)
1445                                 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1446                                 1000));
1447                         table->WatermarkRow[0][i].MaxClock =
1448                                 cpu_to_le16((uint16_t)
1449                                 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1450                                 1000));
1451                         table->WatermarkRow[0][i].MinUclk =
1452                                 cpu_to_le16((uint16_t)
1453                                 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1454                                 1000));
1455                         table->WatermarkRow[0][i].MaxUclk =
1456                                 cpu_to_le16((uint16_t)
1457                                 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1458                                 1000));
1459                         table->WatermarkRow[0][i].WmSetting = (uint8_t)
1460                                         clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1461                 }
1462
1463                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1464         }
1465
1466         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1467              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1468                 ret = smu_cmn_write_watermarks_table(smu);
1469                 if (ret) {
1470                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1471                         return ret;
1472                 }
1473                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1474         }
1475
1476         return 0;
1477 }
1478
1479 static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu,
1480                                              enum amd_pp_sensors sensor,
1481                                              uint32_t *value)
1482 {
1483         int ret = 0;
1484
1485         if (!value)
1486                 return -EINVAL;
1487
1488         switch (sensor) {
1489         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1490                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1491                                                           METRICS_TEMPERATURE_HOTSPOT,
1492                                                           value);
1493                 break;
1494         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1495                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1496                                                           METRICS_TEMPERATURE_EDGE,
1497                                                           value);
1498                 break;
1499         case AMDGPU_PP_SENSOR_MEM_TEMP:
1500                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1501                                                           METRICS_TEMPERATURE_MEM,
1502                                                           value);
1503                 break;
1504         default:
1505                 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1506                 return -EINVAL;
1507         }
1508
1509         return ret;
1510 }
1511
1512 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1513                                  enum amd_pp_sensors sensor,
1514                                  void *data, uint32_t *size)
1515 {
1516         int ret = 0;
1517         struct smu_table_context *table_context = &smu->smu_table;
1518         PPTable_t *pptable = table_context->driver_pptable;
1519
1520         if(!data || !size)
1521                 return -EINVAL;
1522
1523         mutex_lock(&smu->sensor_lock);
1524         switch (sensor) {
1525         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1526                 *(uint32_t *)data = pptable->FanMaximumRpm;
1527                 *size = 4;
1528                 break;
1529         case AMDGPU_PP_SENSOR_MEM_LOAD:
1530         case AMDGPU_PP_SENSOR_GPU_LOAD:
1531                 ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1532                 *size = 4;
1533                 break;
1534         case AMDGPU_PP_SENSOR_GPU_POWER:
1535                 ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data);
1536                 *size = 4;
1537                 break;
1538         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1539         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1540         case AMDGPU_PP_SENSOR_MEM_TEMP:
1541                 ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1542                 *size = 4;
1543                 break;
1544         case AMDGPU_PP_SENSOR_GFX_MCLK:
1545                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1546                 *(uint32_t *)data *= 100;
1547                 *size = 4;
1548                 break;
1549         case AMDGPU_PP_SENSOR_GFX_SCLK:
1550                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1551                 *(uint32_t *)data *= 100;
1552                 *size = 4;
1553                 break;
1554         case AMDGPU_PP_SENSOR_VDDGFX:
1555                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1556                 *size = 4;
1557                 break;
1558         default:
1559                 ret = -EOPNOTSUPP;
1560                 break;
1561         }
1562         mutex_unlock(&smu->sensor_lock);
1563
1564         return ret;
1565 }
1566
1567 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1568 {
1569         uint32_t num_discrete_levels = 0;
1570         uint16_t *dpm_levels = NULL;
1571         uint16_t i = 0;
1572         struct smu_table_context *table_context = &smu->smu_table;
1573         PPTable_t *driver_ppt = NULL;
1574
1575         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1576                 return -EINVAL;
1577
1578         driver_ppt = table_context->driver_pptable;
1579         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1580         dpm_levels = driver_ppt->FreqTableUclk;
1581
1582         if (num_discrete_levels == 0 || dpm_levels == NULL)
1583                 return -EINVAL;
1584
1585         *num_states = num_discrete_levels;
1586         for (i = 0; i < num_discrete_levels; i++) {
1587                 /* convert to khz */
1588                 *clocks_in_khz = (*dpm_levels) * 1000;
1589                 clocks_in_khz++;
1590                 dpm_levels++;
1591         }
1592
1593         return 0;
1594 }
1595
1596 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1597                                                 struct smu_temperature_range *range)
1598 {
1599         struct smu_table_context *table_context = &smu->smu_table;
1600         struct smu_11_0_7_powerplay_table *powerplay_table =
1601                                 table_context->power_play_table;
1602         PPTable_t *pptable = smu->smu_table.driver_pptable;
1603
1604         if (!range)
1605                 return -EINVAL;
1606
1607         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1608
1609         range->max = pptable->TemperatureLimit[TEMP_EDGE] *
1610                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1611         range->edge_emergency_max = (pptable->TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
1612                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1613         range->hotspot_crit_max = pptable->TemperatureLimit[TEMP_HOTSPOT] *
1614                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1615         range->hotspot_emergency_max = (pptable->TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
1616                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1617         range->mem_crit_max = pptable->TemperatureLimit[TEMP_MEM] *
1618                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1619         range->mem_emergency_max = (pptable->TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
1620                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1621         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1622
1623         return 0;
1624 }
1625
1626 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1627                                                 bool disable_memory_clock_switch)
1628 {
1629         int ret = 0;
1630         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1631                 (struct smu_11_0_max_sustainable_clocks *)
1632                         smu->smu_table.max_sustainable_clocks;
1633         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1634         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1635
1636         if(smu->disable_uclk_switch == disable_memory_clock_switch)
1637                 return 0;
1638
1639         if(disable_memory_clock_switch)
1640                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
1641         else
1642                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
1643
1644         if(!ret)
1645                 smu->disable_uclk_switch = disable_memory_clock_switch;
1646
1647         return ret;
1648 }
1649
1650 static int sienna_cichlid_get_power_limit(struct smu_context *smu)
1651 {
1652         struct smu_11_0_7_powerplay_table *powerplay_table =
1653                 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
1654         PPTable_t *pptable = smu->smu_table.driver_pptable;
1655         uint32_t power_limit, od_percent;
1656
1657         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1658                 /* the last hope to figure out the ppt limit */
1659                 if (!pptable) {
1660                         dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1661                         return -EINVAL;
1662                 }
1663                 power_limit =
1664                         pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1665         }
1666         smu->current_power_limit = power_limit;
1667
1668         if (smu->od_enabled) {
1669                 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
1670
1671                 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1672
1673                 power_limit *= (100 + od_percent);
1674                 power_limit /= 100;
1675         }
1676         smu->max_power_limit = power_limit;
1677
1678         return 0;
1679 }
1680
1681 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1682                                          uint32_t pcie_gen_cap,
1683                                          uint32_t pcie_width_cap)
1684 {
1685         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1686         PPTable_t *pptable = smu->smu_table.driver_pptable;
1687         uint32_t smu_pcie_arg;
1688         int ret, i;
1689
1690         /* lclk dpm table setup */
1691         for (i = 0; i < MAX_PCIE_CONF; i++) {
1692                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
1693                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
1694         }
1695
1696         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1697                 smu_pcie_arg = (i << 16) |
1698                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ?
1699                                         (pptable->PcieGenSpeed[i] << 8) :
1700                                         (pcie_gen_cap << 8)) |
1701                         ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1702                                         pptable->PcieLaneCount[i] :
1703                                         pcie_width_cap);
1704
1705                 ret = smu_cmn_send_smc_msg_with_param(smu,
1706                                           SMU_MSG_OverridePcieParameters,
1707                                           smu_pcie_arg,
1708                                           NULL);
1709
1710                 if (ret)
1711                         return ret;
1712
1713                 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1714                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1715                 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1716                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1717         }
1718
1719         return 0;
1720 }
1721
1722 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
1723                                 enum smu_clk_type clk_type,
1724                                 uint32_t *min, uint32_t *max)
1725 {
1726         struct amdgpu_device *adev = smu->adev;
1727         int ret;
1728
1729         if (clk_type == SMU_GFXCLK)
1730                 amdgpu_gfx_off_ctrl(adev, false);
1731         ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
1732         if (clk_type == SMU_GFXCLK)
1733                 amdgpu_gfx_off_ctrl(adev, true);
1734
1735         return ret;
1736 }
1737
1738 static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)
1739 {
1740         struct amdgpu_device *adev = smu->adev;
1741         uint32_t val;
1742
1743         if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
1744                 return false;
1745
1746         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1747         return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
1748 }
1749
1750 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
1751 {
1752         struct amdgpu_device *adev = smu->adev;
1753         uint32_t val;
1754         u32 smu_version;
1755
1756         /**
1757          * SRIOV env will not support SMU mode1 reset
1758          * PM FW support mode1 reset from 58.26
1759          */
1760         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1761         if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
1762                 return false;
1763
1764         /**
1765          * mode1 reset relies on PSP, so we should check if
1766          * PSP is alive.
1767          */
1768         val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
1769         return val != 0x0;
1770 }
1771
1772 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
1773 {
1774         struct smu_table_context *table_context = &smu->smu_table;
1775         PPTable_t *pptable = table_context->driver_pptable;
1776         int i;
1777
1778         dev_info(smu->adev->dev, "Dumped PPTable:\n");
1779
1780         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1781         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1782         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1783
1784         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1785                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
1786                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
1787                 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
1788                 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
1789         }
1790
1791         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
1792                 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
1793                 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
1794         }
1795
1796         for (i = 0; i < TEMP_COUNT; i++) {
1797                 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
1798         }
1799
1800         dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
1801         dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
1802         dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
1803         dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
1804         dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
1805
1806         dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
1807         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
1808                 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
1809                 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
1810         }
1811         dev_info(smu->adev->dev, "PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]);
1812         dev_info(smu->adev->dev, "PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]);
1813         dev_info(smu->adev->dev, "PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]);
1814         dev_info(smu->adev->dev, "PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]);
1815
1816         dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
1817
1818         dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
1819
1820         dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
1821         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
1822         dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
1823         dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
1824
1825         dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
1826         dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
1827
1828         dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
1829         dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
1830         dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
1831         dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
1832
1833         dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
1834         dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
1835         dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
1836         dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
1837
1838         dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
1839         dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
1840
1841         dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
1842         dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
1843         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
1844         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
1845         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
1846         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
1847         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
1848         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
1849
1850         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1851                         "  .VoltageMode          = 0x%02x\n"
1852                         "  .SnapToDiscrete       = 0x%02x\n"
1853                         "  .NumDiscreteLevels    = 0x%02x\n"
1854                         "  .padding              = 0x%02x\n"
1855                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1856                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1857                         "  .SsFmin               = 0x%04x\n"
1858                         "  .Padding_16           = 0x%04x\n",
1859                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1860                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1861                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1862                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
1863                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1864                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1865                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1866                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1867                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1868                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1869                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1870
1871         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1872                         "  .VoltageMode          = 0x%02x\n"
1873                         "  .SnapToDiscrete       = 0x%02x\n"
1874                         "  .NumDiscreteLevels    = 0x%02x\n"
1875                         "  .padding              = 0x%02x\n"
1876                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1877                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1878                         "  .SsFmin               = 0x%04x\n"
1879                         "  .Padding_16           = 0x%04x\n",
1880                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1881                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1882                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1883                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
1884                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1885                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1886                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1887                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1888                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1889                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1890                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1891
1892         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
1893                         "  .VoltageMode          = 0x%02x\n"
1894                         "  .SnapToDiscrete       = 0x%02x\n"
1895                         "  .NumDiscreteLevels    = 0x%02x\n"
1896                         "  .padding              = 0x%02x\n"
1897                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1898                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1899                         "  .SsFmin               = 0x%04x\n"
1900                         "  .Padding_16           = 0x%04x\n",
1901                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1902                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1903                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1904                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
1905                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1906                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1907                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1908                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1909                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1910                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1911                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1912
1913         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
1914                         "  .VoltageMode          = 0x%02x\n"
1915                         "  .SnapToDiscrete       = 0x%02x\n"
1916                         "  .NumDiscreteLevels    = 0x%02x\n"
1917                         "  .padding              = 0x%02x\n"
1918                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1919                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1920                         "  .SsFmin               = 0x%04x\n"
1921                         "  .Padding_16           = 0x%04x\n",
1922                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1923                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1924                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1925                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
1926                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1927                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1928                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1929                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1930                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1931                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1932                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1933
1934         dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
1935                         "  .VoltageMode          = 0x%02x\n"
1936                         "  .SnapToDiscrete       = 0x%02x\n"
1937                         "  .NumDiscreteLevels    = 0x%02x\n"
1938                         "  .padding              = 0x%02x\n"
1939                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1940                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1941                         "  .SsFmin               = 0x%04x\n"
1942                         "  .Padding_16           = 0x%04x\n",
1943                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
1944                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
1945                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
1946                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
1947                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
1948                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
1949                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
1950                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
1951                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
1952                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
1953                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
1954
1955         dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
1956                         "  .VoltageMode          = 0x%02x\n"
1957                         "  .SnapToDiscrete       = 0x%02x\n"
1958                         "  .NumDiscreteLevels    = 0x%02x\n"
1959                         "  .padding              = 0x%02x\n"
1960                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1961                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1962                         "  .SsFmin               = 0x%04x\n"
1963                         "  .Padding_16           = 0x%04x\n",
1964                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
1965                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
1966                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
1967                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
1968                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
1969                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
1970                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
1971                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
1972                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
1973                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
1974                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
1975
1976         dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
1977                         "  .VoltageMode          = 0x%02x\n"
1978                         "  .SnapToDiscrete       = 0x%02x\n"
1979                         "  .NumDiscreteLevels    = 0x%02x\n"
1980                         "  .padding              = 0x%02x\n"
1981                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1982                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1983                         "  .SsFmin               = 0x%04x\n"
1984                         "  .Padding_16           = 0x%04x\n",
1985                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
1986                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
1987                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
1988                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
1989                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
1990                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
1991                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
1992                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
1993                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
1994                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
1995                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
1996
1997         dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
1998                         "  .VoltageMode          = 0x%02x\n"
1999                         "  .SnapToDiscrete       = 0x%02x\n"
2000                         "  .NumDiscreteLevels    = 0x%02x\n"
2001                         "  .padding              = 0x%02x\n"
2002                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2003                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2004                         "  .SsFmin               = 0x%04x\n"
2005                         "  .Padding_16           = 0x%04x\n",
2006                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2007                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2008                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2009                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2010                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2011                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2012                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2013                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2014                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2015                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2016                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2017
2018         dev_info(smu->adev->dev, "FreqTableGfx\n");
2019         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2020                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2021
2022         dev_info(smu->adev->dev, "FreqTableVclk\n");
2023         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2024                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2025
2026         dev_info(smu->adev->dev, "FreqTableDclk\n");
2027         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2028                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2029
2030         dev_info(smu->adev->dev, "FreqTableSocclk\n");
2031         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2032                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2033
2034         dev_info(smu->adev->dev, "FreqTableUclk\n");
2035         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2036                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2037
2038         dev_info(smu->adev->dev, "FreqTableFclk\n");
2039         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2040                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2041
2042         dev_info(smu->adev->dev, "Paddingclks[0] = 0x%x\n",  pptable->Paddingclks[0]);
2043         dev_info(smu->adev->dev, "Paddingclks[1] = 0x%x\n",  pptable->Paddingclks[1]);
2044         dev_info(smu->adev->dev, "Paddingclks[2] = 0x%x\n",  pptable->Paddingclks[2]);
2045         dev_info(smu->adev->dev, "Paddingclks[3] = 0x%x\n",  pptable->Paddingclks[3]);
2046         dev_info(smu->adev->dev, "Paddingclks[4] = 0x%x\n",  pptable->Paddingclks[4]);
2047         dev_info(smu->adev->dev, "Paddingclks[5] = 0x%x\n",  pptable->Paddingclks[5]);
2048         dev_info(smu->adev->dev, "Paddingclks[6] = 0x%x\n",  pptable->Paddingclks[6]);
2049         dev_info(smu->adev->dev, "Paddingclks[7] = 0x%x\n",  pptable->Paddingclks[7]);
2050         dev_info(smu->adev->dev, "Paddingclks[8] = 0x%x\n",  pptable->Paddingclks[8]);
2051         dev_info(smu->adev->dev, "Paddingclks[9] = 0x%x\n",  pptable->Paddingclks[9]);
2052         dev_info(smu->adev->dev, "Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]);
2053         dev_info(smu->adev->dev, "Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]);
2054         dev_info(smu->adev->dev, "Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]);
2055         dev_info(smu->adev->dev, "Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]);
2056         dev_info(smu->adev->dev, "Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]);
2057         dev_info(smu->adev->dev, "Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]);
2058
2059         dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2060         dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2061         dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2062         dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2063         dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2064         dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2065         dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2066         dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2067         dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2068
2069         dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2070         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2071                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2072
2073         dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2074         dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2075
2076         dev_info(smu->adev->dev, "Mp0clkFreq\n");
2077         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2078                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2079
2080         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2081         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2082                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2083
2084         dev_info(smu->adev->dev, "MemVddciVoltage\n");
2085         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2086                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2087
2088         dev_info(smu->adev->dev, "MemMvddVoltage\n");
2089         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2090                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2091
2092         dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2093         dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2094         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2095         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2096         dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2097
2098         dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2099
2100         dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2101         dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2102         dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2103         dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2104         dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2105         dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2106         dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2107         dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2108         dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2109         dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2110         dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2111
2112         dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2113         dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2114         dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2115         dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2116         dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2117         dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2118
2119         dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2120         dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2121         dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2122         dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2123         dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2124
2125         dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2126         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2127                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2128
2129         dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2130         dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2131         dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2132         dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2133
2134         dev_info(smu->adev->dev, "UclkDpmPstates\n");
2135         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2136                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2137
2138         dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2139         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2140                 pptable->UclkDpmSrcFreqRange.Fmin);
2141         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2142                 pptable->UclkDpmSrcFreqRange.Fmax);
2143         dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2144         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2145                 pptable->UclkDpmTargFreqRange.Fmin);
2146         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2147                 pptable->UclkDpmTargFreqRange.Fmax);
2148         dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2149         dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2150
2151         dev_info(smu->adev->dev, "PcieGenSpeed\n");
2152         for (i = 0; i < NUM_LINK_LEVELS; i++)
2153                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2154
2155         dev_info(smu->adev->dev, "PcieLaneCount\n");
2156         for (i = 0; i < NUM_LINK_LEVELS; i++)
2157                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2158
2159         dev_info(smu->adev->dev, "LclkFreq\n");
2160         for (i = 0; i < NUM_LINK_LEVELS; i++)
2161                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2162
2163         dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2164         dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2165
2166         dev_info(smu->adev->dev, "FanGain\n");
2167         for (i = 0; i < TEMP_COUNT; i++)
2168                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2169
2170         dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2171         dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2172         dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2173         dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2174         dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2175         dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2176         dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2177         dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2178         dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2179         dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2180         dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2181         dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2182
2183         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2184         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2185         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2186         dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2187
2188         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2189         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2190         dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2191         dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2192
2193         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2194                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2195                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2196                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2197         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2198                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2199                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2200                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2201         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2202                         pptable->dBtcGbGfxPll.a,
2203                         pptable->dBtcGbGfxPll.b,
2204                         pptable->dBtcGbGfxPll.c);
2205         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2206                         pptable->dBtcGbGfxDfll.a,
2207                         pptable->dBtcGbGfxDfll.b,
2208                         pptable->dBtcGbGfxDfll.c);
2209         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2210                         pptable->dBtcGbSoc.a,
2211                         pptable->dBtcGbSoc.b,
2212                         pptable->dBtcGbSoc.c);
2213         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2214                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2215                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2216         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2217                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2218                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2219
2220         dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2221         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2222                 dev_info(smu->adev->dev, "              Fset[%d] = 0x%x\n",
2223                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2224                 dev_info(smu->adev->dev, "              Vdroop[%d] = 0x%x\n",
2225                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2226         }
2227
2228         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2229                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2230                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2231                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2232         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2233                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2234                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2235                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2236
2237         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2238         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2239
2240         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2241         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2242         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2243         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2244
2245         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2246         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2247         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2248         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2249
2250         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2251         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2252
2253         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2254         for (i = 0; i < NUM_XGMI_LEVELS; i++)
2255                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2256         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2257         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2258
2259         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2260         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2261                         pptable->ReservedEquation0.a,
2262                         pptable->ReservedEquation0.b,
2263                         pptable->ReservedEquation0.c);
2264         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2265                         pptable->ReservedEquation1.a,
2266                         pptable->ReservedEquation1.b,
2267                         pptable->ReservedEquation1.c);
2268         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2269                         pptable->ReservedEquation2.a,
2270                         pptable->ReservedEquation2.b,
2271                         pptable->ReservedEquation2.c);
2272         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2273                         pptable->ReservedEquation3.a,
2274                         pptable->ReservedEquation3.b,
2275                         pptable->ReservedEquation3.c);
2276
2277         dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2278         dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2279         dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2280         dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2281         dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2282         dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2283         dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2284         dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2285         dev_info(smu->adev->dev, "SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]);
2286         dev_info(smu->adev->dev, "SkuReserved[9] = 0x%x\n", pptable->SkuReserved[9]);
2287         dev_info(smu->adev->dev, "SkuReserved[10] = 0x%x\n", pptable->SkuReserved[10]);
2288         dev_info(smu->adev->dev, "SkuReserved[11] = 0x%x\n", pptable->SkuReserved[11]);
2289         dev_info(smu->adev->dev, "SkuReserved[12] = 0x%x\n", pptable->SkuReserved[12]);
2290         dev_info(smu->adev->dev, "SkuReserved[13] = 0x%x\n", pptable->SkuReserved[13]);
2291
2292         dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2293         dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2294         dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2295         dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2296         dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2297         dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2298
2299         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2300                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2301                 dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
2302                                 pptable->I2cControllers[i].Enabled);
2303                 dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
2304                                 pptable->I2cControllers[i].Speed);
2305                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
2306                                 pptable->I2cControllers[i].SlaveAddress);
2307                 dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
2308                                 pptable->I2cControllers[i].ControllerPort);
2309                 dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
2310                                 pptable->I2cControllers[i].ControllerName);
2311                 dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
2312                                 pptable->I2cControllers[i].ThermalThrotter);
2313                 dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
2314                                 pptable->I2cControllers[i].I2cProtocol);
2315                 dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
2316                                 pptable->I2cControllers[i].PaddingConfig);
2317         }
2318
2319         dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2320         dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2321         dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2322         dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2323
2324         dev_info(smu->adev->dev, "Board Parameters:\n");
2325         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2326         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2327         dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2328         dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2329         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2330         dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2331         dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2332         dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2333
2334         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2335         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2336         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2337
2338         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2339         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2340         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2341
2342         dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2343         dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2344         dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2345
2346         dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2347         dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2348         dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2349
2350         dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2351
2352         dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2353         dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2354         dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2355         dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2356         dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2357         dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2358         dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2359         dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2360         dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2361         dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2362         dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2363         dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2364         dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2365         dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2366         dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2367         dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2368
2369         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2370         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2371         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
2372
2373         dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2374         dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2375         dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
2376
2377         dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2378         dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2379
2380         dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2381         dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2382         dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2383
2384         dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2385         dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2386         dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2387         dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2388         dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2389
2390         dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2391         dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2392
2393         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2394         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2395                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2396         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2397         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2398                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2399         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2400         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2401                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2402         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2403         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2404                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2405
2406         dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2407         dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2408         dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2409         dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2410
2411         dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2412         dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2413         dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2414         dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2415         dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2416         dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2417         dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2418         dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2419         dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2420         dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2421         dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2422
2423         dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2424         dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2425         dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2426         dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2427         dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2428         dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2429         dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2430         dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2431 }
2432
2433 static void sienna_cichlid_fill_i2c_req(SwI2cRequest_t  *req, bool write,
2434                                   uint8_t address, uint32_t numbytes,
2435                                   uint8_t *data)
2436 {
2437         int i;
2438
2439         BUG_ON(numbytes > MAX_SW_I2C_COMMANDS);
2440
2441         req->I2CcontrollerPort = 0;
2442         req->I2CSpeed = 2;
2443         req->SlaveAddress = address;
2444         req->NumCmds = numbytes;
2445
2446         for (i = 0; i < numbytes; i++) {
2447                 SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
2448
2449                 /* First 2 bytes are always write for lower 2b EEPROM address */
2450                 if (i < 2)
2451                         cmd->CmdConfig = CMDCONFIG_READWRITE_MASK;
2452                 else
2453                         cmd->CmdConfig = write ? CMDCONFIG_READWRITE_MASK : 0;
2454
2455
2456                 /* Add RESTART for read  after address filled */
2457                 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
2458
2459                 /* Add STOP in the end */
2460                 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
2461
2462                 /* Fill with data regardless if read or write to simplify code */
2463                 cmd->ReadWriteData = data[i];
2464         }
2465 }
2466
2467 static int sienna_cichlid_i2c_read_data(struct i2c_adapter *control,
2468                                                uint8_t address,
2469                                                uint8_t *data,
2470                                                uint32_t numbytes)
2471 {
2472         uint32_t  i, ret = 0;
2473         SwI2cRequest_t req;
2474         struct amdgpu_device *adev = to_amdgpu_device(control);
2475         struct smu_table_context *smu_table = &adev->smu.smu_table;
2476         struct smu_table *table = &smu_table->driver_table;
2477
2478         memset(&req, 0, sizeof(req));
2479         sienna_cichlid_fill_i2c_req(&req, false, address, numbytes, data);
2480
2481         mutex_lock(&adev->smu.mutex);
2482         /* Now read data starting with that address */
2483         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
2484                                         true);
2485         mutex_unlock(&adev->smu.mutex);
2486
2487         if (!ret) {
2488                 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
2489
2490                 /* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
2491                 for (i = 0; i < numbytes; i++)
2492                         data[i] = res->SwI2cCmds[i].ReadWriteData;
2493
2494                 dev_dbg(adev->dev, "sienna_cichlid_i2c_read_data, address = %x, bytes = %d, data :",
2495                                   (uint16_t)address, numbytes);
2496
2497                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2498                                8, 1, data, numbytes, false);
2499         } else
2500                 dev_err(adev->dev, "sienna_cichlid_i2c_read_data - error occurred :%x", ret);
2501
2502         return ret;
2503 }
2504
2505 static int sienna_cichlid_i2c_write_data(struct i2c_adapter *control,
2506                                                 uint8_t address,
2507                                                 uint8_t *data,
2508                                                 uint32_t numbytes)
2509 {
2510         uint32_t ret;
2511         SwI2cRequest_t req;
2512         struct amdgpu_device *adev = to_amdgpu_device(control);
2513
2514         memset(&req, 0, sizeof(req));
2515         sienna_cichlid_fill_i2c_req(&req, true, address, numbytes, data);
2516
2517         mutex_lock(&adev->smu.mutex);
2518         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
2519         mutex_unlock(&adev->smu.mutex);
2520
2521         if (!ret) {
2522                 dev_dbg(adev->dev, "sienna_cichlid_i2c_write(), address = %x, bytes = %d , data: ",
2523                                          (uint16_t)address, numbytes);
2524
2525                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2526                                8, 1, data, numbytes, false);
2527                 /*
2528                  * According to EEPROM spec there is a MAX of 10 ms required for
2529                  * EEPROM to flush internal RX buffer after STOP was issued at the
2530                  * end of write transaction. During this time the EEPROM will not be
2531                  * responsive to any more commands - so wait a bit more.
2532                  */
2533                 msleep(10);
2534
2535         } else
2536                 dev_err(adev->dev, "sienna_cichlid_i2c_write- error occurred :%x", ret);
2537
2538         return ret;
2539 }
2540
2541 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
2542                               struct i2c_msg *msgs, int num)
2543 {
2544         uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
2545         uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
2546
2547         for (i = 0; i < num; i++) {
2548                 /*
2549                  * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2550                  * once and hence the data needs to be spliced into chunks and sent each
2551                  * chunk separately
2552                  */
2553                 data_size = msgs[i].len - 2;
2554                 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
2555                 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2556                 data_ptr = msgs[i].buf + 2;
2557
2558                 for (j = 0; j < data_size / data_chunk_size; j++) {
2559                         /* Insert the EEPROM dest addess, bits 0-15 */
2560                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2561                         data_chunk[1] = (next_eeprom_addr & 0xff);
2562
2563                         if (msgs[i].flags & I2C_M_RD) {
2564                                 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2565                                                              (uint8_t)msgs[i].addr,
2566                                                              data_chunk, MAX_SW_I2C_COMMANDS);
2567
2568                                 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2569                         } else {
2570
2571                                 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2572
2573                                 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2574                                                               (uint8_t)msgs[i].addr,
2575                                                               data_chunk, MAX_SW_I2C_COMMANDS);
2576                         }
2577
2578                         if (ret) {
2579                                 num = -EIO;
2580                                 goto fail;
2581                         }
2582
2583                         next_eeprom_addr += data_chunk_size;
2584                         data_ptr += data_chunk_size;
2585                 }
2586
2587                 if (data_size % data_chunk_size) {
2588                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2589                         data_chunk[1] = (next_eeprom_addr & 0xff);
2590
2591                         if (msgs[i].flags & I2C_M_RD) {
2592                                 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2593                                                              (uint8_t)msgs[i].addr,
2594                                                              data_chunk, (data_size % data_chunk_size) + 2);
2595
2596                                 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2597                         } else {
2598                                 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2599
2600                                 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2601                                                               (uint8_t)msgs[i].addr,
2602                                                               data_chunk, (data_size % data_chunk_size) + 2);
2603                         }
2604
2605                         if (ret) {
2606                                 num = -EIO;
2607                                 goto fail;
2608                         }
2609                 }
2610         }
2611
2612 fail:
2613         return num;
2614 }
2615
2616 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
2617 {
2618         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2619 }
2620
2621
2622 static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
2623         .master_xfer = sienna_cichlid_i2c_xfer,
2624         .functionality = sienna_cichlid_i2c_func,
2625 };
2626
2627 static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2628 {
2629         struct amdgpu_device *adev = to_amdgpu_device(control);
2630         int res;
2631
2632         control->owner = THIS_MODULE;
2633         control->class = I2C_CLASS_SPD;
2634         control->dev.parent = &adev->pdev->dev;
2635         control->algo = &sienna_cichlid_i2c_algo;
2636         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2637
2638         res = i2c_add_adapter(control);
2639         if (res)
2640                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2641
2642         return res;
2643 }
2644
2645 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2646 {
2647         i2c_del_adapter(control);
2648 }
2649
2650 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
2651                                               void **table)
2652 {
2653         struct smu_table_context *smu_table = &smu->smu_table;
2654         struct gpu_metrics_v1_0 *gpu_metrics =
2655                 (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table;
2656         SmuMetrics_t metrics;
2657         int ret = 0;
2658
2659         ret = smu_cmn_get_metrics_table(smu,
2660                                         &metrics,
2661                                         true);
2662         if (ret)
2663                 return ret;
2664
2665         smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics);
2666
2667         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2668         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2669         gpu_metrics->temperature_mem = metrics.TemperatureMem;
2670         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2671         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2672         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2673
2674         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2675         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2676         gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2677
2678         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2679         gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2680
2681         if (metrics.AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
2682                 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
2683         else
2684                 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
2685         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
2686         gpu_metrics->average_vclk0_frequency = metrics.AverageVclk0Frequency;
2687         gpu_metrics->average_dclk0_frequency = metrics.AverageDclk0Frequency;
2688         gpu_metrics->average_vclk1_frequency = metrics.AverageVclk1Frequency;
2689         gpu_metrics->average_dclk1_frequency = metrics.AverageDclk1Frequency;
2690
2691         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2692         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2693         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2694         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK_0];
2695         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK_0];
2696         gpu_metrics->current_vclk1 = metrics.CurrClock[PPCLK_VCLK_1];
2697         gpu_metrics->current_dclk1 = metrics.CurrClock[PPCLK_DCLK_1];
2698
2699         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2700
2701         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2702
2703         gpu_metrics->pcie_link_width =
2704                         smu_v11_0_get_current_pcie_link_width(smu);
2705         gpu_metrics->pcie_link_speed =
2706                         smu_v11_0_get_current_pcie_link_speed(smu);
2707
2708         *table = (void *)gpu_metrics;
2709
2710         return sizeof(struct gpu_metrics_v1_0);
2711 }
2712
2713 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
2714 {
2715         return smu_cmn_send_smc_msg_with_param(smu,
2716                                                SMU_MSG_SetMGpuFanBoostLimitRpm,
2717                                                0,
2718                                                NULL);
2719 }
2720
2721 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
2722         .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
2723         .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
2724         .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
2725         .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
2726         .i2c_init = sienna_cichlid_i2c_control_init,
2727         .i2c_fini = sienna_cichlid_i2c_control_fini,
2728         .print_clk_levels = sienna_cichlid_print_clk_levels,
2729         .force_clk_levels = sienna_cichlid_force_clk_levels,
2730         .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
2731         .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
2732         .display_config_changed = sienna_cichlid_display_config_changed,
2733         .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
2734         .is_dpm_running = sienna_cichlid_is_dpm_running,
2735         .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent,
2736         .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
2737         .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
2738         .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
2739         .set_watermarks_table = sienna_cichlid_set_watermarks_table,
2740         .read_sensor = sienna_cichlid_read_sensor,
2741         .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
2742         .set_performance_level = smu_v11_0_set_performance_level,
2743         .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
2744         .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
2745         .get_power_limit = sienna_cichlid_get_power_limit,
2746         .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
2747         .dump_pptable = sienna_cichlid_dump_pptable,
2748         .init_microcode = smu_v11_0_init_microcode,
2749         .load_microcode = smu_v11_0_load_microcode,
2750         .init_smc_tables = sienna_cichlid_init_smc_tables,
2751         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2752         .init_power = smu_v11_0_init_power,
2753         .fini_power = smu_v11_0_fini_power,
2754         .check_fw_status = smu_v11_0_check_fw_status,
2755         .setup_pptable = sienna_cichlid_setup_pptable,
2756         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2757         .check_fw_version = smu_v11_0_check_fw_version,
2758         .write_pptable = smu_cmn_write_pptable,
2759         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2760         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2761         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2762         .system_features_control = smu_v11_0_system_features_control,
2763         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2764         .send_smc_msg = smu_cmn_send_smc_msg,
2765         .init_display_count = NULL,
2766         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2767         .get_enabled_mask = smu_cmn_get_enabled_mask,
2768         .feature_is_enabled = smu_cmn_feature_is_enabled,
2769         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2770         .notify_display_change = NULL,
2771         .set_power_limit = smu_v11_0_set_power_limit,
2772         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2773         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2774         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2775         .set_min_dcef_deep_sleep = NULL,
2776         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2777         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2778         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2779         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2780         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2781         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2782         .gfx_off_control = smu_v11_0_gfx_off_control,
2783         .register_irq_handler = smu_v11_0_register_irq_handler,
2784         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2785         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2786         .baco_is_support= sienna_cichlid_is_baco_supported,
2787         .baco_get_state = smu_v11_0_baco_get_state,
2788         .baco_set_state = smu_v11_0_baco_set_state,
2789         .baco_enter = smu_v11_0_baco_enter,
2790         .baco_exit = smu_v11_0_baco_exit,
2791         .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
2792         .mode1_reset = smu_v11_0_mode1_reset,
2793         .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
2794         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2795         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2796         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2797         .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
2798         .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
2799 };
2800
2801 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
2802 {
2803         smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
2804         smu->message_map = sienna_cichlid_message_map;
2805         smu->clock_map = sienna_cichlid_clk_map;
2806         smu->feature_map = sienna_cichlid_feature_mask_map;
2807         smu->table_map = sienna_cichlid_table_map;
2808         smu->pwr_src_map = sienna_cichlid_pwr_src_map;
2809         smu->workload_map = sienna_cichlid_workload_map;
2810 }