drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include <linux/pci.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "smu_internal.h"
  30 #include "atomfirmware.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "smu_v11_0.h"
  33 #include "smu11_driver_if_sienna_cichlid.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "sienna_cichlid_ppt.h"
  37 #include "smu_v11_0_pptable.h"
  38 #include "smu_v11_0_7_ppsmc.h"
  39
  40 #include "nbio/nbio_2_3_sh_mask.h"
  41 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  42
  43 #define FEATURE_MASK(feature) (1ULL << feature)
  44 #define SMC_DPM_FEATURE ( \
  45         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  46         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  47         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  48         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  49         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  50         FEATURE_MASK(FEATURE_DPM_FCLK_BIT)       | \
  51         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
  52
  53 #define MSG_MAP(msg, index) \
  54         [SMU_MSG_##msg] = {1, (index)}
  55
  56 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
  57         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
  58         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
  59         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion),
  60         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow),
  61         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  62         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures),
  63         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures),
  64         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow),
  65         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh),
  66         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow),
  67         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh),
  68         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow),
  69         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh),
  70         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask),
  71         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit),
  72         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh),
  73         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow),
  74         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh),
  75         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow),
  76         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram),
  77         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu),
  78         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable),
  79         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco),
  80         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq),
  81         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq),
  82         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq),
  83         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq),
  84         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq),
  85         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq),
  86         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex),
  87         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode),
  88         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh),
  89         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow),
  90         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters),
  91         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt),
  92         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource),
  93         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch),
  94         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps),
  95         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload),
  96         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff),
  97         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff),
  98         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit),
  99         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq),
 100         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco),
 101         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn),
 102         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn),
 103         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg),
 104         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg),
 105         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME),
 106         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3),
 107 };
 108
 109 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
 110         CLK_MAP(GFXCLK,         PPCLK_GFXCLK),
 111         CLK_MAP(SCLK,           PPCLK_GFXCLK),
 112         CLK_MAP(SOCCLK,         PPCLK_SOCCLK),
 113         CLK_MAP(FCLK,           PPCLK_FCLK),
 114         CLK_MAP(UCLK,           PPCLK_UCLK),
 115         CLK_MAP(MCLK,           PPCLK_UCLK),
 116         CLK_MAP(DCLK,           PPCLK_DCLK_0),
 117         CLK_MAP(DCLK1,          PPCLK_DCLK_0),
 118         CLK_MAP(VCLK,           PPCLK_VCLK_1),
 119         CLK_MAP(VCLK1,          PPCLK_VCLK_1),
 120         CLK_MAP(DCEFCLK,        PPCLK_DCEFCLK),
 121         CLK_MAP(DISPCLK,        PPCLK_DISPCLK),
 122         CLK_MAP(PIXCLK,         PPCLK_PIXCLK),
 123         CLK_MAP(PHYCLK,         PPCLK_PHYCLK),
 124 };
 125
 126 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
 127         FEA_MAP(DPM_PREFETCHER),
 128         FEA_MAP(DPM_GFXCLK),
 129         FEA_MAP(DPM_UCLK),
 130         FEA_MAP(DPM_SOCCLK),
 131         FEA_MAP(DPM_MP0CLK),
 132         FEA_MAP(DPM_LINK),
 133         FEA_MAP(DPM_DCEFCLK),
 134         FEA_MAP(MEM_VDDCI_SCALING),
 135         FEA_MAP(MEM_MVDD_SCALING),
 136         FEA_MAP(DS_GFXCLK),
 137         FEA_MAP(DS_SOCCLK),
 138         FEA_MAP(DS_LCLK),
 139         FEA_MAP(DS_DCEFCLK),
 140         FEA_MAP(DS_UCLK),
 141         FEA_MAP(GFX_ULV),
 142         FEA_MAP(FW_DSTATE),
 143         FEA_MAP(GFXOFF),
 144         FEA_MAP(BACO),
 145         FEA_MAP(MM_DPM_PG),
 146         FEA_MAP(RSMU_SMN_CG),
 147         FEA_MAP(PPT),
 148         FEA_MAP(TDC),
 149         FEA_MAP(APCC_PLUS),
 150         FEA_MAP(GTHR),
 151         FEA_MAP(ACDC),
 152         FEA_MAP(VR0HOT),
 153         FEA_MAP(VR1HOT),
 154         FEA_MAP(FW_CTF),
 155         FEA_MAP(FAN_CONTROL),
 156         FEA_MAP(THERMAL),
 157         FEA_MAP(GFX_DCS),
 158         FEA_MAP(RM),
 159         FEA_MAP(LED_DISPLAY),
 160         FEA_MAP(GFX_SS),
 161         FEA_MAP(OUT_OF_BAND_MONITOR),
 162         FEA_MAP(TEMP_DEPENDENT_VMIN),
 163         FEA_MAP(MMHUB_PG),
 164         FEA_MAP(ATHUB_PG),
 165         FEA_MAP(APCC_DFLL),
 166 };
 167
 168 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
 169         TAB_MAP(PPTABLE),
 170         TAB_MAP(WATERMARKS),
 171         TAB_MAP(AVFS_PSM_DEBUG),
 172         TAB_MAP(AVFS_FUSE_OVERRIDE),
 173         TAB_MAP(PMSTATUSLOG),
 174         TAB_MAP(SMU_METRICS),
 175         TAB_MAP(DRIVER_SMU_CONFIG),
 176         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 177         TAB_MAP(OVERDRIVE),
 178         TAB_MAP(I2C_COMMANDS),
 179         TAB_MAP(PACE),
 180 };
 181
 182 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 183         PWR_MAP(AC),
 184         PWR_MAP(DC),
 185 };
 186
 187 static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 188         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 189         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 190         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 191         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 192         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 193         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_CUSTOM_BIT),
 194         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 195 };
 196
 197 static int sienna_cichlid_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 198 {
 199         struct smu_11_0_cmn2aisc_mapping mapping;
 200
 201         if (index >= SMU_MSG_MAX_COUNT)
 202                 return -EINVAL;
 203
 204         mapping = sienna_cichlid_message_map[index];
 205         if (!(mapping.valid_mapping)) {
 206                 return -EINVAL;
 207         }
 208
 209         return mapping.map_to;
 210 }
 211
 212 static int sienna_cichlid_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 213 {
 214         struct smu_11_0_cmn2aisc_mapping mapping;
 215
 216         if (index >= SMU_CLK_COUNT)
 217                 return -EINVAL;
 218
 219         mapping = sienna_cichlid_clk_map[index];
 220         if (!(mapping.valid_mapping)) {
 221                 return -EINVAL;
 222         }
 223
 224         return mapping.map_to;
 225 }
 226
 227 static int sienna_cichlid_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 228 {
 229         struct smu_11_0_cmn2aisc_mapping mapping;
 230
 231         if (index >= SMU_FEATURE_COUNT)
 232                 return -EINVAL;
 233
 234         mapping = sienna_cichlid_feature_mask_map[index];
 235         if (!(mapping.valid_mapping)) {
 236                 return -EINVAL;
 237         }
 238
 239         return mapping.map_to;
 240 }
 241
 242 static int sienna_cichlid_get_smu_table_index(struct smu_context *smc, uint32_t index)
 243 {
 244         struct smu_11_0_cmn2aisc_mapping mapping;
 245
 246         if (index >= SMU_TABLE_COUNT)
 247                 return -EINVAL;
 248
 249         mapping = sienna_cichlid_table_map[index];
 250         if (!(mapping.valid_mapping)) {
 251                 return -EINVAL;
 252         }
 253
 254         return mapping.map_to;
 255 }
 256
 257 static int sienna_cichlid_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 258 {
 259         struct smu_11_0_cmn2aisc_mapping mapping;
 260
 261         if (index >= SMU_POWER_SOURCE_COUNT)
 262                 return -EINVAL;
 263
 264         mapping = sienna_cichlid_pwr_src_map[index];
 265         if (!(mapping.valid_mapping)) {
 266                 return -EINVAL;
 267         }
 268
 269         return mapping.map_to;
 270 }
 271
 272 static int sienna_cichlid_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 273 {
 274         struct smu_11_0_cmn2aisc_mapping mapping;
 275
 276         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 277                 return -EINVAL;
 278
 279         mapping = sienna_cichlid_workload_map[profile];
 280         if (!(mapping.valid_mapping)) {
 281                 return -EINVAL;
 282         }
 283
 284         return mapping.map_to;
 285 }
 286
 287 static int
 288 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 289                                   uint32_t *feature_mask, uint32_t num)
 290 {
 291         struct amdgpu_device *adev = smu->adev;
 292
 293         if (num > 2)
 294                 return -EINVAL;
 295
 296         memset(feature_mask, 0, sizeof(uint32_t) * num);
 297
 298         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 299                                 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
 300                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 301                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 302                                 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
 303                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 304                                 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
 305                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 306                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 307                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 308                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 309                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 310                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 311                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 312                                 | FEATURE_MASK(FEATURE_THERMAL_BIT);
 313
 314         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
 315                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 316
 317         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 318                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
 319
 320         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 321                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 322
 323         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 324                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 325
 326         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 327                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 328
 329         if (adev->pm.pp_feature & PP_ULV_MASK)
 330                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 331
 332         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 333                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 334
 335         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
 336             smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 337                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
 338
 339         return 0;
 340 }
 341
 342 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
 343 {
 344         return 0;
 345 }
 346
 347 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
 348 {
 349         return 0;
 350 }
 351
 352 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
 353 {
 354         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 355         struct smu_table_context *table_context = &smu->smu_table;
 356         struct smu_baco_context *smu_baco = &smu->smu_baco;
 357
 358         if (!table_context->power_play_table)
 359                 return -EINVAL;
 360
 361         powerplay_table = table_context->power_play_table;
 362
 363         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 364                sizeof(PPTable_t));
 365
 366         table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
 367
 368         mutex_lock(&smu_baco->mutex);
 369         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 370             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 371                 smu_baco->platform_support = true;
 372         mutex_unlock(&smu_baco->mutex);
 373
 374         return 0;
 375 }
 376
 377 static int sienna_cichlid_tables_init(struct smu_context *smu, struct smu_table *tables)
 378 {
 379         struct smu_table_context *smu_table = &smu->smu_table;
 380
 381         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 382                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 383         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 384                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 385         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 386                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 387         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 388                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 389         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 390                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 391         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 392                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 393                        AMDGPU_GEM_DOMAIN_VRAM);
 394
 395         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 396         if (!smu_table->metrics_table)
 397                 return -ENOMEM;
 398         smu_table->metrics_time = 0;
 399
 400         return 0;
 401 }
 402
 403 static int sienna_cichlid_get_metrics_table(struct smu_context *smu,
 404                                     SmuMetrics_t *metrics_table)
 405 {
 406         struct smu_table_context *smu_table= &smu->smu_table;
 407         int ret = 0;
 408
 409         mutex_lock(&smu->metrics_lock);
 410         if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
 411                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 412                                 (void *)smu_table->metrics_table, false);
 413                 if (ret) {
 414                         pr_info("Failed to export SMU metrics table!\n");
 415                         mutex_unlock(&smu->metrics_lock);
 416                         return ret;
 417                 }
 418                 smu_table->metrics_time = jiffies;
 419         }
 420
 421         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
 422         mutex_unlock(&smu->metrics_lock);
 423
 424         return ret;
 425 }
 426
 427 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
 428 {
 429         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 430
 431         if (smu_dpm->dpm_context)
 432                 return -EINVAL;
 433
 434         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 435                                        GFP_KERNEL);
 436         if (!smu_dpm->dpm_context)
 437                 return -ENOMEM;
 438
 439         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 440
 441         return 0;
 442 }
 443
 444 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 445 {
 446         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 447         struct smu_table_context *table_context = &smu->smu_table;
 448         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 449         PPTable_t *driver_ppt = NULL;
 450         int i;
 451
 452         driver_ppt = table_context->driver_pptable;
 453
 454         dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
 455         dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
 456
 457         dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
 458         dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
 459
 460         dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
 461         dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
 462
 463         dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
 464         dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
 465
 466         dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
 467         dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
 468
 469         dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
 470         dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
 471
 472         dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
 473         dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
 474
 475         dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
 476         dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
 477
 478         dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
 479         dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
 480
 481         for (i = 0; i < MAX_PCIE_CONF; i++) {
 482                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
 483                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
 484         }
 485
 486         return 0;
 487 }
 488
 489 static int sienna_cichlid_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
 490 {
 491         struct smu_power_context *smu_power = &smu->smu_power;
 492         struct smu_power_gate *power_gate = &smu_power->power_gate;
 493         int ret = 0;
 494
 495         if (enable) {
 496                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 497                 if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 498                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
 499                         if (ret)
 500                                 return ret;
 501                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0x10000, NULL);
 502                         if (ret)
 503                                 return ret;
 504                 }
 505                 power_gate->vcn_gated = false;
 506         } else {
 507                 if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 508                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
 509                         if (ret)
 510                                 return ret;
 511                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0x10000, NULL);
 512                         if (ret)
 513                                 return ret;
 514                 }
 515                 power_gate->vcn_gated = true;
 516         }
 517
 518         return ret;
 519 }
 520
 521 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 522 {
 523         struct smu_power_context *smu_power = &smu->smu_power;
 524         struct smu_power_gate *power_gate = &smu_power->power_gate;
 525         int ret = 0;
 526
 527         if (enable) {
 528                 if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 529                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
 530                         if (ret)
 531                                 return ret;
 532                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0x10000, NULL);
 533                         if (ret)
 534                                 return ret;
 535                 }
 536                 power_gate->jpeg_gated = false;
 537         } else {
 538                 if (smu_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 539                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
 540                         if (ret)
 541                                 return ret;
 542                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0x10000, NULL);
 543                         if (ret)
 544                                 return ret;
 545                 }
 546                 power_gate->jpeg_gated = true;
 547         }
 548
 549         return ret;
 550 }
 551
 552 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
 553                                        enum smu_clk_type clk_type,
 554                                        uint32_t *value)
 555 {
 556         int ret = 0, clk_id = 0;
 557         SmuMetrics_t metrics;
 558
 559         ret = sienna_cichlid_get_metrics_table(smu, &metrics);
 560         if (ret)
 561                 return ret;
 562
 563         clk_id = smu_clk_get_index(smu, clk_type);
 564         if (clk_id < 0)
 565                 return clk_id;
 566
 567         *value = metrics.CurrClock[clk_id];
 568
 569         return ret;
 570 }
 571
 572 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 573 {
 574         PPTable_t *pptable = smu->smu_table.driver_pptable;
 575         DpmDescriptor_t *dpm_desc = NULL;
 576         uint32_t clk_index = 0;
 577
 578         clk_index = smu_clk_get_index(smu, clk_type);
 579         dpm_desc = &pptable->DpmDescriptor[clk_index];
 580
 581         /* 0 - Fine grained DPM, 1 - Discrete DPM */
 582         return dpm_desc->SnapToDiscrete == 0 ? true : false;
 583 }
 584
 585 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
 586                         enum smu_clk_type clk_type, char *buf)
 587 {
 588         struct amdgpu_device *adev = smu->adev;
 589         struct smu_table_context *table_context = &smu->smu_table;
 590         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 591         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 592         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 593         int i, size = 0, ret = 0;
 594         uint32_t cur_value = 0, value = 0, count = 0;
 595         uint32_t freq_values[3] = {0};
 596         uint32_t mark_index = 0;
 597         uint32_t gen_speed, lane_width;
 598
 599         switch (clk_type) {
 600         case SMU_GFXCLK:
 601         case SMU_SCLK:
 602         case SMU_SOCCLK:
 603         case SMU_MCLK:
 604         case SMU_UCLK:
 605         case SMU_FCLK:
 606         case SMU_DCEFCLK:
 607                 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
 608                 if (ret)
 609                         return size;
 610
 611                 /* 10KHz -> MHz */
 612                 cur_value = cur_value / 100;
 613
 614                 ret = smu_get_dpm_level_count(smu, clk_type, &count);
 615                 if (ret)
 616                         return size;
 617
 618                 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
 619                         for (i = 0; i < count; i++) {
 620                                 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
 621                                 if (ret)
 622                                         return size;
 623
 624                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 625                                                 cur_value == value ? "*" : "");
 626                         }
 627                 } else {
 628                         ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
 629                         if (ret)
 630                                 return size;
 631                         ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
 632                         if (ret)
 633                                 return size;
 634
 635                         freq_values[1] = cur_value;
 636                         mark_index = cur_value == freq_values[0] ? 0 :
 637                                      cur_value == freq_values[2] ? 2 : 1;
 638                         if (mark_index != 1)
 639                                 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
 640
 641                         for (i = 0; i < 3; i++) {
 642                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
 643                                                 i == mark_index ? "*" : "");
 644                         }
 645
 646                 }
 647                 break;
 648         case SMU_PCIE:
 649                 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
 650                              PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
 651                         >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
 652                 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
 653                               PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
 654                         >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
 655                 for (i = 0; i < NUM_LINK_LEVELS; i++)
 656                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
 657                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
 658                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
 659                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
 660                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
 661                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
 662                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
 663                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
 664                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
 665                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
 666                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
 667                                         pptable->LclkFreq[i],
 668                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
 669                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
 670                                         "*" : "");
 671                 break;
 672         default:
 673                 break;
 674         }
 675
 676         return size;
 677 }
 678
 679 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
 680                                    enum smu_clk_type clk_type, uint32_t mask)
 681 {
 682
 683         int ret = 0, size = 0;
 684         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
 685
 686         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 687         soft_max_level = mask ? (fls(mask) - 1) : 0;
 688
 689         switch (clk_type) {
 690         case SMU_GFXCLK:
 691         case SMU_SCLK:
 692         case SMU_SOCCLK:
 693         case SMU_MCLK:
 694         case SMU_UCLK:
 695         case SMU_DCEFCLK:
 696         case SMU_FCLK:
 697                 /* There is only 2 levels for fine grained DPM */
 698                 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
 699                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
 700                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
 701                 }
 702
 703                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
 704                 if (ret)
 705                         return size;
 706
 707                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
 708                 if (ret)
 709                         return size;
 710
 711                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
 712                 if (ret)
 713                         return size;
 714                 break;
 715         default:
 716                 break;
 717         }
 718
 719         return size;
 720 }
 721
 722 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
 723 {
 724         int ret = 0;
 725         uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
 726
 727         ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
 728         if (ret)
 729                 return ret;
 730
 731         smu->pstate_sclk = min_sclk_freq * 100;
 732
 733         ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
 734         if (ret)
 735                 return ret;
 736
 737         smu->pstate_mclk = min_mclk_freq * 100;
 738
 739         return ret;
 740 }
 741
 742 static int sienna_cichlid_get_clock_by_type_with_latency(struct smu_context *smu,
 743                                                  enum smu_clk_type clk_type,
 744                                                  struct pp_clock_levels_with_latency *clocks)
 745 {
 746         int ret = 0, i = 0;
 747         uint32_t level_count = 0, freq = 0;
 748
 749         switch (clk_type) {
 750         case SMU_GFXCLK:
 751         case SMU_DCEFCLK:
 752         case SMU_SOCCLK:
 753                 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
 754                 if (ret)
 755                         return ret;
 756
 757                 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
 758                 clocks->num_levels = level_count;
 759
 760                 for (i = 0; i < level_count; i++) {
 761                         ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
 762                         if (ret)
 763                                 return ret;
 764
 765                         clocks->data[i].clocks_in_khz = freq * 1000;
 766                         clocks->data[i].latency_in_us = 0;
 767                 }
 768                 break;
 769         default:
 770                 break;
 771         }
 772
 773         return ret;
 774 }
 775
 776 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
 777 {
 778         int ret = 0;
 779         uint32_t max_freq = 0;
 780
 781         /* Sienna_Cichlid do not support to change display num currently */
 782         return 0;
 783 #if 0
 784         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
 785         if (ret)
 786                 return ret;
 787 #endif
 788
 789         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 790                 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
 791                 if (ret)
 792                         return ret;
 793                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
 794                 if (ret)
 795                         return ret;
 796         }
 797
 798         return ret;
 799 }
 800
 801 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
 802 {
 803         int ret = 0;
 804
 805         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 806             !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 807                 ret = smu_write_watermarks_table(smu);
 808                 if (ret)
 809                         return ret;
 810
 811                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
 812         }
 813
 814         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 815             smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
 816             smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 817                 /* Sienna_Cichlid do not support to change display num currently */
 818                 ret = 0;
 819 #if 0
 820                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
 821                                                   smu->display_config->num_display, NULL);
 822 #endif
 823                 if (ret)
 824                         return ret;
 825         }
 826
 827         return ret;
 828 }
 829
 830 static int sienna_cichlid_force_dpm_limit_value(struct smu_context *smu, bool highest)
 831 {
 832         int ret = 0, i = 0;
 833         uint32_t min_freq, max_freq, force_freq;
 834         enum smu_clk_type clk_type;
 835
 836         enum smu_clk_type clks[] = {
 837                 SMU_GFXCLK,
 838         };
 839
 840         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 841                 clk_type = clks[i];
 842                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
 843                 if (ret)
 844                         return ret;
 845
 846                 force_freq = highest ? max_freq : min_freq;
 847                 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq, false);
 848                 if (ret)
 849                         return ret;
 850         }
 851
 852         return ret;
 853 }
 854
 855 static int sienna_cichlid_unforce_dpm_levels(struct smu_context *smu)
 856 {
 857         int ret = 0, i = 0;
 858         uint32_t min_freq, max_freq;
 859         enum smu_clk_type clk_type;
 860
 861         enum smu_clk_type clks[] = {
 862                 SMU_GFXCLK,
 863         };
 864
 865         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 866                 clk_type = clks[i];
 867                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
 868                 if (ret)
 869                         return ret;
 870
 871                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
 872                 if (ret)
 873                         return ret;
 874         }
 875
 876         return ret;
 877 }
 878
 879 static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)
 880 {
 881         int ret = 0;
 882         SmuMetrics_t metrics;
 883
 884         if (!value)
 885                 return -EINVAL;
 886
 887         ret = sienna_cichlid_get_metrics_table(smu, &metrics);
 888         if (ret)
 889                 return ret;
 890
 891         *value = metrics.AverageSocketPower << 8;
 892
 893         return 0;
 894 }
 895
 896 static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu,
 897                                                enum amd_pp_sensors sensor,
 898                                                uint32_t *value)
 899 {
 900         int ret = 0;
 901         SmuMetrics_t metrics;
 902
 903         if (!value)
 904                 return -EINVAL;
 905
 906         ret = sienna_cichlid_get_metrics_table(smu, &metrics);
 907         if (ret)
 908                 return ret;
 909
 910         switch (sensor) {
 911         case AMDGPU_PP_SENSOR_GPU_LOAD:
 912                 *value = metrics.AverageGfxActivity;
 913                 break;
 914         case AMDGPU_PP_SENSOR_MEM_LOAD:
 915                 *value = metrics.AverageUclkActivity;
 916                 break;
 917         default:
 918                 pr_err("Invalid sensor for retrieving clock activity\n");
 919                 return -EINVAL;
 920         }
 921
 922         return 0;
 923 }
 924
 925 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
 926 {
 927         int ret = 0;
 928         uint32_t feature_mask[2];
 929         unsigned long feature_enabled;
 930         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 931         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
 932                            ((uint64_t)feature_mask[1] << 32));
 933         return !!(feature_enabled & SMC_DPM_FEATURE);
 934 }
 935
 936 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
 937                                     uint32_t *speed)
 938 {
 939         SmuMetrics_t metrics;
 940         int ret = 0;
 941
 942         if (!speed)
 943                 return -EINVAL;
 944
 945         ret = sienna_cichlid_get_metrics_table(smu, &metrics);
 946         if (ret)
 947                 return ret;
 948
 949         *speed = metrics.CurrFanSpeed;
 950
 951         return ret;
 952 }
 953
 954 static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu,
 955                                         uint32_t *speed)
 956 {
 957         int ret = 0;
 958         uint32_t percent = 0;
 959         uint32_t current_rpm;
 960         PPTable_t *pptable = smu->smu_table.driver_pptable;
 961
 962         ret = sienna_cichlid_get_fan_speed_rpm(smu, &current_rpm);
 963         if (ret)
 964                 return ret;
 965
 966         percent = current_rpm * 100 / pptable->FanMaximumRpm;
 967         *speed = percent > 100 ? 100 : percent;
 968
 969         return ret;
 970 }
 971
 972 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
 973 {
 974         DpmActivityMonitorCoeffInt_t activity_monitor;
 975         uint32_t i, size = 0;
 976         int16_t workload_type = 0;
 977         static const char *profile_name[] = {
 978                                         "BOOTUP_DEFAULT",
 979                                         "3D_FULL_SCREEN",
 980                                         "POWER_SAVING",
 981                                         "VIDEO",
 982                                         "VR",
 983                                         "COMPUTE",
 984                                         "CUSTOM"};
 985         static const char *title[] = {
 986                         "PROFILE_INDEX(NAME)",
 987                         "CLOCK_TYPE(NAME)",
 988                         "FPS",
 989                         "MinFreqType",
 990                         "MinActiveFreqType",
 991                         "MinActiveFreq",
 992                         "BoosterFreqType",
 993                         "BoosterFreq",
 994                         "PD_Data_limit_c",
 995                         "PD_Data_error_coeff",
 996                         "PD_Data_error_rate_coeff"};
 997         int result = 0;
 998
 999         if (!buf)
1000                 return -EINVAL;
1001
1002         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1003                         title[0], title[1], title[2], title[3], title[4], title[5],
1004                         title[6], title[7], title[8], title[9], title[10]);
1005
1006         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1007                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1008                 workload_type = smu_workload_get_type(smu, i);
1009                 if (workload_type < 0)
1010                         return -EINVAL;
1011
1012                 result = smu_update_table(smu,
1013                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1014                                           (void *)(&activity_monitor), false);
1015                 if (result) {
1016                         pr_err("[%s] Failed to get activity monitor!", __func__);
1017                         return result;
1018                 }
1019
1020                 size += sprintf(buf + size, "%2d %14s%s:\n",
1021                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1022
1023                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1024                         " ",
1025                         0,
1026                         "GFXCLK",
1027                         activity_monitor.Gfx_FPS,
1028                         activity_monitor.Gfx_MinFreqStep,
1029                         activity_monitor.Gfx_MinActiveFreqType,
1030                         activity_monitor.Gfx_MinActiveFreq,
1031                         activity_monitor.Gfx_BoosterFreqType,
1032                         activity_monitor.Gfx_BoosterFreq,
1033                         activity_monitor.Gfx_PD_Data_limit_c,
1034                         activity_monitor.Gfx_PD_Data_error_coeff,
1035                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1036
1037                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1038                         " ",
1039                         1,
1040                         "SOCCLK",
1041                         activity_monitor.Fclk_FPS,
1042                         activity_monitor.Fclk_MinFreqStep,
1043                         activity_monitor.Fclk_MinActiveFreqType,
1044                         activity_monitor.Fclk_MinActiveFreq,
1045                         activity_monitor.Fclk_BoosterFreqType,
1046                         activity_monitor.Fclk_BoosterFreq,
1047                         activity_monitor.Fclk_PD_Data_limit_c,
1048                         activity_monitor.Fclk_PD_Data_error_coeff,
1049                         activity_monitor.Fclk_PD_Data_error_rate_coeff);
1050
1051                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1052                         " ",
1053                         2,
1054                         "MEMLK",
1055                         activity_monitor.Mem_FPS,
1056                         activity_monitor.Mem_MinFreqStep,
1057                         activity_monitor.Mem_MinActiveFreqType,
1058                         activity_monitor.Mem_MinActiveFreq,
1059                         activity_monitor.Mem_BoosterFreqType,
1060                         activity_monitor.Mem_BoosterFreq,
1061                         activity_monitor.Mem_PD_Data_limit_c,
1062                         activity_monitor.Mem_PD_Data_error_coeff,
1063                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1064         }
1065
1066         return size;
1067 }
1068
1069 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1070 {
1071         DpmActivityMonitorCoeffInt_t activity_monitor;
1072         int workload_type, ret = 0;
1073
1074         smu->power_profile_mode = input[size];
1075
1076         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1077                 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1078                 return -EINVAL;
1079         }
1080
1081         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1082                 if (size < 0)
1083                         return -EINVAL;
1084
1085                 ret = smu_update_table(smu,
1086                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1087                                        (void *)(&activity_monitor), false);
1088                 if (ret) {
1089                         pr_err("[%s] Failed to get activity monitor!", __func__);
1090                         return ret;
1091                 }
1092
1093                 switch (input[0]) {
1094                 case 0: /* Gfxclk */
1095                         activity_monitor.Gfx_FPS = input[1];
1096                         activity_monitor.Gfx_MinFreqStep = input[2];
1097                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1098                         activity_monitor.Gfx_MinActiveFreq = input[4];
1099                         activity_monitor.Gfx_BoosterFreqType = input[5];
1100                         activity_monitor.Gfx_BoosterFreq = input[6];
1101                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1102                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1103                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1104                         break;
1105                 case 1: /* Socclk */
1106                         activity_monitor.Fclk_FPS = input[1];
1107                         activity_monitor.Fclk_MinFreqStep = input[2];
1108                         activity_monitor.Fclk_MinActiveFreqType = input[3];
1109                         activity_monitor.Fclk_MinActiveFreq = input[4];
1110                         activity_monitor.Fclk_BoosterFreqType = input[5];
1111                         activity_monitor.Fclk_BoosterFreq = input[6];
1112                         activity_monitor.Fclk_PD_Data_limit_c = input[7];
1113                         activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1114                         activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1115                         break;
1116                 case 2: /* Memlk */
1117                         activity_monitor.Mem_FPS = input[1];
1118                         activity_monitor.Mem_MinFreqStep = input[2];
1119                         activity_monitor.Mem_MinActiveFreqType = input[3];
1120                         activity_monitor.Mem_MinActiveFreq = input[4];
1121                         activity_monitor.Mem_BoosterFreqType = input[5];
1122                         activity_monitor.Mem_BoosterFreq = input[6];
1123                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1124                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1125                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1126                         break;
1127                 }
1128
1129                 ret = smu_update_table(smu,
1130                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1131                                        (void *)(&activity_monitor), true);
1132                 if (ret) {
1133                         pr_err("[%s] Failed to set activity monitor!", __func__);
1134                         return ret;
1135                 }
1136         }
1137
1138         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1139         workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1140         if (workload_type < 0)
1141                 return -EINVAL;
1142         smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1143                                     1 << workload_type, NULL);
1144
1145         return ret;
1146 }
1147
1148 static int sienna_cichlid_get_profiling_clk_mask(struct smu_context *smu,
1149                                          enum amd_dpm_forced_level level,
1150                                          uint32_t *sclk_mask,
1151                                          uint32_t *mclk_mask,
1152                                          uint32_t *soc_mask)
1153 {
1154         int ret = 0;
1155         uint32_t level_count = 0;
1156
1157         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1158                 if (sclk_mask)
1159                         *sclk_mask = 0;
1160         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1161                 if (mclk_mask)
1162                         *mclk_mask = 0;
1163         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1164                 if(sclk_mask) {
1165                         ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1166                         if (ret)
1167                                 return ret;
1168                         *sclk_mask = level_count - 1;
1169                 }
1170
1171                 if(mclk_mask) {
1172                         ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1173                         if (ret)
1174                                 return ret;
1175                         *mclk_mask = level_count - 1;
1176                 }
1177
1178                 if(soc_mask) {
1179                         ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1180                         if (ret)
1181                                 return ret;
1182                         *soc_mask = level_count - 1;
1183                 }
1184         }
1185
1186         return ret;
1187 }
1188
1189 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1190 {
1191         struct smu_clocks min_clocks = {0};
1192         struct pp_display_clock_request clock_req;
1193         int ret = 0;
1194
1195         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1196         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1197         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1198
1199         if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1200                 clock_req.clock_type = amd_pp_dcef_clock;
1201                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1202
1203                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1204                 if (!ret) {
1205                         if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1206                                 pr_err("Attempt to set divider for DCEFCLK Failed as it not support currently!");
1207                                 return ret;
1208                         }
1209                 } else {
1210                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1211                 }
1212         }
1213
1214         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1215                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1216                 if (ret) {
1217                         pr_err("[%s] Set hard min uclk failed!", __func__);
1218                         return ret;
1219                 }
1220         }
1221
1222         return 0;
1223 }
1224
1225 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1226                                        void *watermarks, struct
1227                                        dm_pp_wm_sets_with_clock_ranges_soc15
1228                                        *clock_ranges)
1229 {
1230         int i;
1231         Watermarks_t *table = watermarks;
1232
1233         if (!table || !clock_ranges)
1234                 return -EINVAL;
1235
1236         if (clock_ranges->num_wm_dmif_sets > 4 ||
1237             clock_ranges->num_wm_mcif_sets > 4)
1238                 return -EINVAL;
1239
1240         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1241                 table->WatermarkRow[1][i].MinClock =
1242                         cpu_to_le16((uint16_t)
1243                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1244                         1000));
1245                 table->WatermarkRow[1][i].MaxClock =
1246                         cpu_to_le16((uint16_t)
1247                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1248                         1000));
1249                 table->WatermarkRow[1][i].MinUclk =
1250                         cpu_to_le16((uint16_t)
1251                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1252                         1000));
1253                 table->WatermarkRow[1][i].MaxUclk =
1254                         cpu_to_le16((uint16_t)
1255                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1256                         1000));
1257                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1258                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1259         }
1260
1261         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1262                 table->WatermarkRow[0][i].MinClock =
1263                         cpu_to_le16((uint16_t)
1264                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1265                         1000));
1266                 table->WatermarkRow[0][i].MaxClock =
1267                         cpu_to_le16((uint16_t)
1268                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1269                         1000));
1270                 table->WatermarkRow[0][i].MinUclk =
1271                         cpu_to_le16((uint16_t)
1272                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1273                         1000));
1274                 table->WatermarkRow[0][i].MaxUclk =
1275                         cpu_to_le16((uint16_t)
1276                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1277                         1000));
1278                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1279                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1280         }
1281
1282         return 0;
1283 }
1284
1285 static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu,
1286                                              enum amd_pp_sensors sensor,
1287                                              uint32_t *value)
1288 {
1289         SmuMetrics_t metrics;
1290         int ret = 0;
1291
1292         if (!value)
1293                 return -EINVAL;
1294
1295         ret = sienna_cichlid_get_metrics_table(smu, &metrics);
1296         if (ret)
1297                 return ret;
1298
1299         switch (sensor) {
1300         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1301                 *value = metrics.TemperatureHotspot *
1302                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1303                 break;
1304         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1305                 *value = metrics.TemperatureEdge *
1306                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1307                 break;
1308         case AMDGPU_PP_SENSOR_MEM_TEMP:
1309                 *value = metrics.TemperatureMem *
1310                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1311                 break;
1312         default:
1313                 pr_err("Invalid sensor for retrieving temp\n");
1314                 return -EINVAL;
1315         }
1316
1317         return 0;
1318 }
1319
1320 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1321                                  enum amd_pp_sensors sensor,
1322                                  void *data, uint32_t *size)
1323 {
1324         int ret = 0;
1325         struct smu_table_context *table_context = &smu->smu_table;
1326         PPTable_t *pptable = table_context->driver_pptable;
1327
1328         if(!data || !size)
1329                 return -EINVAL;
1330
1331         mutex_lock(&smu->sensor_lock);
1332         switch (sensor) {
1333         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1334                 *(uint32_t *)data = pptable->FanMaximumRpm;
1335                 *size = 4;
1336                 break;
1337         case AMDGPU_PP_SENSOR_MEM_LOAD:
1338         case AMDGPU_PP_SENSOR_GPU_LOAD:
1339                 ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1340                 *size = 4;
1341                 break;
1342         case AMDGPU_PP_SENSOR_GPU_POWER:
1343                 ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data);
1344                 *size = 4;
1345                 break;
1346         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1347         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1348         case AMDGPU_PP_SENSOR_MEM_TEMP:
1349                 ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1350                 *size = 4;
1351                 break;
1352         default:
1353                 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1354         }
1355         mutex_unlock(&smu->sensor_lock);
1356
1357         return ret;
1358 }
1359
1360 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1361 {
1362         uint32_t num_discrete_levels = 0;
1363         uint16_t *dpm_levels = NULL;
1364         uint16_t i = 0;
1365         struct smu_table_context *table_context = &smu->smu_table;
1366         PPTable_t *driver_ppt = NULL;
1367
1368         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1369                 return -EINVAL;
1370
1371         driver_ppt = table_context->driver_pptable;
1372         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1373         dpm_levels = driver_ppt->FreqTableUclk;
1374
1375         if (num_discrete_levels == 0 || dpm_levels == NULL)
1376                 return -EINVAL;
1377
1378         *num_states = num_discrete_levels;
1379         for (i = 0; i < num_discrete_levels; i++) {
1380                 /* convert to khz */
1381                 *clocks_in_khz = (*dpm_levels) * 1000;
1382                 clocks_in_khz++;
1383                 dpm_levels++;
1384         }
1385
1386         return 0;
1387 }
1388
1389 static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1390                                         enum amd_dpm_forced_level level);
1391
1392 static int sienna_cichlid_set_standard_performance_level(struct smu_context *smu)
1393 {
1394         struct amdgpu_device *adev = smu->adev;
1395         int ret = 0;
1396         uint32_t sclk_freq = 0, uclk_freq = 0;
1397
1398         switch (adev->asic_type) {
1399         /* TODO: need to set specify clk value by asic type, not support yet*/
1400         default:
1401                 /* by default, this is same as auto performance level */
1402                 return sienna_cichlid_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
1403         }
1404
1405         ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
1406         if (ret)
1407                 return ret;
1408         ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
1409         if (ret)
1410                 return ret;
1411
1412         return ret;
1413 }
1414
1415 static int sienna_cichlid_set_peak_performance_level(struct smu_context *smu)
1416 {
1417         int ret = 0;
1418
1419         /* TODO: not support yet*/
1420         return ret;
1421 }
1422
1423 static int sienna_cichlid_set_performance_level(struct smu_context *smu,
1424                                         enum amd_dpm_forced_level level)
1425 {
1426         int ret = 0;
1427         uint32_t sclk_mask, mclk_mask, soc_mask;
1428
1429         switch (level) {
1430         case AMD_DPM_FORCED_LEVEL_HIGH:
1431                 ret = smu_force_dpm_limit_value(smu, true);
1432                 break;
1433         case AMD_DPM_FORCED_LEVEL_LOW:
1434                 ret = smu_force_dpm_limit_value(smu, false);
1435                 break;
1436         case AMD_DPM_FORCED_LEVEL_AUTO:
1437                 ret = smu_unforce_dpm_levels(smu);
1438                 break;
1439         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1440                 ret = sienna_cichlid_set_standard_performance_level(smu);
1441                 break;
1442         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1443         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1444                 ret = smu_get_profiling_clk_mask(smu, level,
1445                                                  &sclk_mask,
1446                                                  &mclk_mask,
1447                                                  &soc_mask);
1448                 if (ret)
1449                         return ret;
1450                 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1451                 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1452                 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1453                 break;
1454         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1455                 ret = sienna_cichlid_set_peak_performance_level(smu);
1456                 break;
1457         case AMD_DPM_FORCED_LEVEL_MANUAL:
1458         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1459         default:
1460                 break;
1461         }
1462         return ret;
1463 }
1464
1465 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1466                                                 struct smu_temperature_range *range)
1467 {
1468         struct smu_table_context *table_context = &smu->smu_table;
1469         struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1470
1471         if (!range || !powerplay_table)
1472                 return -EINVAL;
1473
1474         range->max = powerplay_table->software_shutdown_temp *
1475                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1476
1477         return 0;
1478 }
1479
1480 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1481                                                 bool disable_memory_clock_switch)
1482 {
1483         int ret = 0;
1484         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1485                 (struct smu_11_0_max_sustainable_clocks *)
1486                         smu->smu_table.max_sustainable_clocks;
1487         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1488         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1489
1490         if(smu->disable_uclk_switch == disable_memory_clock_switch)
1491                 return 0;
1492
1493         if(disable_memory_clock_switch)
1494                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
1495         else
1496                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
1497
1498         if(!ret)
1499                 smu->disable_uclk_switch = disable_memory_clock_switch;
1500
1501         return ret;
1502 }
1503
1504 static int sienna_cichlid_get_power_limit(struct smu_context *smu,
1505                                      uint32_t *limit,
1506                                      bool cap)
1507 {
1508         PPTable_t *pptable = smu->smu_table.driver_pptable;
1509         uint32_t asic_default_power_limit = 0;
1510         int ret = 0;
1511         int power_src;
1512
1513         if (!smu->power_limit) {
1514                 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1515                         power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1516                         if (power_src < 0)
1517                                 return -EINVAL;
1518
1519                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1520                                                           power_src << 16, &asic_default_power_limit);
1521                         if (ret) {
1522                                 pr_err("[%s] get PPT limit failed!", __func__);
1523                                 return ret;
1524                         }
1525                 } else {
1526                         /* the last hope to figure out the ppt limit */
1527                         if (!pptable) {
1528                                 pr_err("Cannot get PPT limit due to pptable missing!");
1529                                 return -EINVAL;
1530                         }
1531                         asic_default_power_limit =
1532                                 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1533                 }
1534
1535                 smu->power_limit = asic_default_power_limit;
1536         }
1537
1538         if (cap)
1539                 *limit = smu_v11_0_get_max_power_limit(smu);
1540         else
1541                 *limit = smu->power_limit;
1542
1543         return 0;
1544 }
1545
1546 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1547                                          uint32_t pcie_gen_cap,
1548                                          uint32_t pcie_width_cap)
1549 {
1550         PPTable_t *pptable = smu->smu_table.driver_pptable;
1551         int ret, i;
1552         uint32_t smu_pcie_arg;
1553
1554         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1555         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1556
1557         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1558                 smu_pcie_arg = (i << 16) |
1559                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ?
1560                                         (pptable->PcieGenSpeed[i] << 8) :
1561                                         (pcie_gen_cap << 8)) |
1562                         ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1563                                         pptable->PcieLaneCount[i] :
1564                                         pcie_width_cap);
1565
1566                 ret = smu_send_smc_msg_with_param(smu,
1567                                                   SMU_MSG_OverridePcieParameters,
1568                                                   smu_pcie_arg, NULL);
1569                 if (ret)
1570                         return ret;
1571
1572                 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1573                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1574                 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1575                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1576         }
1577
1578         return 0;
1579 }
1580
1581 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
1582 {
1583         struct smu_table_context *table_context = &smu->smu_table;
1584         PPTable_t *pptable = table_context->driver_pptable;
1585         int i;
1586
1587         pr_info("Dumped PPTable:\n");
1588
1589         pr_info("Version = 0x%08x\n", pptable->Version);
1590         pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1591         pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1592
1593         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1594                 pr_info("SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
1595                 pr_info("SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
1596                 pr_info("SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
1597                 pr_info("SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
1598         }
1599
1600         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
1601                 pr_info("TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
1602                 pr_info("TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
1603         }
1604
1605         for (i = 0; i < TEMP_COUNT; i++) {
1606                 pr_info("TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
1607         }
1608
1609         pr_info("FitLimit = 0x%x\n", pptable->FitLimit);
1610         pr_info("TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
1611         pr_info("TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
1612         pr_info("TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
1613         pr_info("TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
1614
1615         pr_info("ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
1616         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
1617                 pr_info("SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
1618                 pr_info("SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
1619         }
1620         pr_info("PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]);
1621         pr_info("PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]);
1622         pr_info("PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]);
1623         pr_info("PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]);
1624
1625         pr_info("ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
1626
1627         pr_info("FwDStateMask = 0x%x\n", pptable->FwDStateMask);
1628
1629         pr_info("UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
1630         pr_info("UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
1631         pr_info("MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
1632         pr_info("MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
1633
1634         pr_info("SocLIVmin = 0x%x\n", pptable->SocLIVmin);
1635         pr_info("PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
1636
1637         pr_info("GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
1638         pr_info("paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
1639         pr_info("paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
1640         pr_info("paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
1641
1642         pr_info("MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
1643         pr_info("MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
1644         pr_info("MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
1645         pr_info("MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
1646
1647         pr_info("LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
1648         pr_info("LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
1649
1650         pr_info("VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
1651         pr_info("VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
1652         pr_info("VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
1653         pr_info("VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
1654         pr_info("VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
1655         pr_info("VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
1656         pr_info("VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
1657         pr_info("VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
1658
1659         pr_info("[PPCLK_GFXCLK]\n"
1660                         "  .VoltageMode          = 0x%02x\n"
1661                         "  .SnapToDiscrete       = 0x%02x\n"
1662                         "  .NumDiscreteLevels    = 0x%02x\n"
1663                         "  .padding              = 0x%02x\n"
1664                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1665                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1666                         "  .SsFmin               = 0x%04x\n"
1667                         "  .Padding_16           = 0x%04x\n",
1668                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1669                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1670                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1671                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
1672                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1673                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1674                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1675                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1676                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1677                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1678                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1679
1680         pr_info("[PPCLK_SOCCLK]\n"
1681                         "  .VoltageMode          = 0x%02x\n"
1682                         "  .SnapToDiscrete       = 0x%02x\n"
1683                         "  .NumDiscreteLevels    = 0x%02x\n"
1684                         "  .padding              = 0x%02x\n"
1685                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1686                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1687                         "  .SsFmin               = 0x%04x\n"
1688                         "  .Padding_16           = 0x%04x\n",
1689                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1690                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1691                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1692                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
1693                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1694                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1695                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1696                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1697                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1698                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1699                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1700
1701         pr_info("[PPCLK_UCLK]\n"
1702                         "  .VoltageMode          = 0x%02x\n"
1703                         "  .SnapToDiscrete       = 0x%02x\n"
1704                         "  .NumDiscreteLevels    = 0x%02x\n"
1705                         "  .padding              = 0x%02x\n"
1706                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1707                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1708                         "  .SsFmin               = 0x%04x\n"
1709                         "  .Padding_16           = 0x%04x\n",
1710                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1711                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1712                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1713                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
1714                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1715                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1716                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1717                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1718                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1719                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1720                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1721
1722         pr_info("[PPCLK_FCLK]\n"
1723                         "  .VoltageMode          = 0x%02x\n"
1724                         "  .SnapToDiscrete       = 0x%02x\n"
1725                         "  .NumDiscreteLevels    = 0x%02x\n"
1726                         "  .padding              = 0x%02x\n"
1727                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1728                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1729                         "  .SsFmin               = 0x%04x\n"
1730                         "  .Padding_16           = 0x%04x\n",
1731                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1732                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1733                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1734                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
1735                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1736                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1737                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1738                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1739                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1740                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1741                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1742
1743         pr_info("[PPCLK_DCLK_0]\n"
1744                         "  .VoltageMode          = 0x%02x\n"
1745                         "  .SnapToDiscrete       = 0x%02x\n"
1746                         "  .NumDiscreteLevels    = 0x%02x\n"
1747                         "  .padding              = 0x%02x\n"
1748                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1749                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1750                         "  .SsFmin               = 0x%04x\n"
1751                         "  .Padding_16           = 0x%04x\n",
1752                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
1753                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
1754                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
1755                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
1756                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
1757                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
1758                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
1759                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
1760                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
1761                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
1762                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
1763
1764         pr_info("[PPCLK_VCLK_0]\n"
1765                         "  .VoltageMode          = 0x%02x\n"
1766                         "  .SnapToDiscrete       = 0x%02x\n"
1767                         "  .NumDiscreteLevels    = 0x%02x\n"
1768                         "  .padding              = 0x%02x\n"
1769                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1770                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1771                         "  .SsFmin               = 0x%04x\n"
1772                         "  .Padding_16           = 0x%04x\n",
1773                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
1774                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
1775                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
1776                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
1777                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
1778                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
1779                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
1780                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
1781                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
1782                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
1783                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
1784
1785         pr_info("[PPCLK_DCLK_1]\n"
1786                         "  .VoltageMode          = 0x%02x\n"
1787                         "  .SnapToDiscrete       = 0x%02x\n"
1788                         "  .NumDiscreteLevels    = 0x%02x\n"
1789                         "  .padding              = 0x%02x\n"
1790                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1791                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1792                         "  .SsFmin               = 0x%04x\n"
1793                         "  .Padding_16           = 0x%04x\n",
1794                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
1795                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
1796                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
1797                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
1798                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
1799                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
1800                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
1801                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
1802                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
1803                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
1804                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
1805
1806         pr_info("[PPCLK_VCLK_1]\n"
1807                         "  .VoltageMode          = 0x%02x\n"
1808                         "  .SnapToDiscrete       = 0x%02x\n"
1809                         "  .NumDiscreteLevels    = 0x%02x\n"
1810                         "  .padding              = 0x%02x\n"
1811                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1812                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1813                         "  .SsFmin               = 0x%04x\n"
1814                         "  .Padding_16           = 0x%04x\n",
1815                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
1816                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
1817                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
1818                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
1819                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
1820                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
1821                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
1822                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
1823                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
1824                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
1825                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
1826
1827         pr_info("FreqTableGfx\n");
1828         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1829                 pr_info("  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
1830
1831         pr_info("FreqTableVclk\n");
1832         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1833                 pr_info("  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
1834
1835         pr_info("FreqTableDclk\n");
1836         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1837                 pr_info("  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
1838
1839         pr_info("FreqTableSocclk\n");
1840         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1841                 pr_info("  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
1842
1843         pr_info("FreqTableUclk\n");
1844         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1845                 pr_info("  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
1846
1847         pr_info("FreqTableFclk\n");
1848         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1849                 pr_info("  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
1850
1851         pr_info("Paddingclks[0] = 0x%x\n",  pptable->Paddingclks[0]);
1852         pr_info("Paddingclks[1] = 0x%x\n",  pptable->Paddingclks[1]);
1853         pr_info("Paddingclks[2] = 0x%x\n",  pptable->Paddingclks[2]);
1854         pr_info("Paddingclks[3] = 0x%x\n",  pptable->Paddingclks[3]);
1855         pr_info("Paddingclks[4] = 0x%x\n",  pptable->Paddingclks[4]);
1856         pr_info("Paddingclks[5] = 0x%x\n",  pptable->Paddingclks[5]);
1857         pr_info("Paddingclks[6] = 0x%x\n",  pptable->Paddingclks[6]);
1858         pr_info("Paddingclks[7] = 0x%x\n",  pptable->Paddingclks[7]);
1859         pr_info("Paddingclks[8] = 0x%x\n",  pptable->Paddingclks[8]);
1860         pr_info("Paddingclks[9] = 0x%x\n",  pptable->Paddingclks[9]);
1861         pr_info("Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]);
1862         pr_info("Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]);
1863         pr_info("Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]);
1864         pr_info("Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]);
1865         pr_info("Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]);
1866         pr_info("Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]);
1867
1868         pr_info("DcModeMaxFreq\n");
1869         pr_info("  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
1870         pr_info("  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
1871         pr_info("  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
1872         pr_info("  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
1873         pr_info("  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
1874         pr_info("  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
1875         pr_info("  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
1876         pr_info("  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
1877
1878         pr_info("FreqTableUclkDiv\n");
1879         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1880                 pr_info("  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
1881
1882         pr_info("FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
1883         pr_info("FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
1884
1885         pr_info("Mp0clkFreq\n");
1886         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1887                 pr_info("  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
1888
1889         pr_info("Mp0DpmVoltage\n");
1890         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1891                 pr_info("  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
1892
1893         pr_info("MemVddciVoltage\n");
1894         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1895                 pr_info("  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
1896
1897         pr_info("MemMvddVoltage\n");
1898         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1899                 pr_info("  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
1900
1901         pr_info("GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
1902         pr_info("GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
1903         pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1904         pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1905         pr_info("GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
1906
1907         pr_info("GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
1908
1909         pr_info("GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
1910         pr_info("GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
1911         pr_info("GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
1912         pr_info("GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
1913         pr_info("GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
1914         pr_info("GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
1915         pr_info("GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
1916         pr_info("GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
1917         pr_info("GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
1918         pr_info("GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
1919         pr_info("GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
1920
1921         pr_info("DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
1922         pr_info("DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
1923         pr_info("DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
1924         pr_info("DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
1925         pr_info("DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
1926         pr_info("DcsTimeout = 0x%x\n", pptable->DcsTimeout);
1927
1928         pr_info("DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
1929         pr_info("DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
1930         pr_info("DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
1931         pr_info("DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
1932         pr_info("DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
1933
1934         pr_info("FlopsPerByteTable\n");
1935         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
1936                 pr_info("  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
1937
1938         pr_info("LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
1939         pr_info("vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
1940         pr_info("vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
1941         pr_info("vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
1942
1943         pr_info("UclkDpmPstates\n");
1944         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1945                 pr_info("  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
1946
1947         pr_info("UclkDpmSrcFreqRange\n");
1948         pr_info("  .Fmin = 0x%x\n",
1949                 pptable->UclkDpmSrcFreqRange.Fmin);
1950         pr_info("  .Fmax = 0x%x\n",
1951                 pptable->UclkDpmSrcFreqRange.Fmax);
1952         pr_info("UclkDpmTargFreqRange\n");
1953         pr_info("  .Fmin = 0x%x\n",
1954                 pptable->UclkDpmTargFreqRange.Fmin);
1955         pr_info("  .Fmax = 0x%x\n",
1956                 pptable->UclkDpmTargFreqRange.Fmax);
1957         pr_info("UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
1958         pr_info("UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
1959
1960         pr_info("PcieGenSpeed\n");
1961         for (i = 0; i < NUM_LINK_LEVELS; i++)
1962                 pr_info("  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
1963
1964         pr_info("PcieLaneCount\n");
1965         for (i = 0; i < NUM_LINK_LEVELS; i++)
1966                 pr_info("  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
1967
1968         pr_info("LclkFreq\n");
1969         for (i = 0; i < NUM_LINK_LEVELS; i++)
1970                 pr_info("  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
1971
1972         pr_info("FanStopTemp = 0x%x\n", pptable->FanStopTemp);
1973         pr_info("FanStartTemp = 0x%x\n", pptable->FanStartTemp);
1974
1975         pr_info("FanGain\n");
1976         for (i = 0; i < TEMP_COUNT; i++)
1977                 pr_info("  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
1978
1979         pr_info("FanPwmMin = 0x%x\n", pptable->FanPwmMin);
1980         pr_info("FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
1981         pr_info("FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
1982         pr_info("FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
1983         pr_info("MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
1984         pr_info("FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
1985         pr_info("FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
1986         pr_info("FanPadding16 = 0x%x\n", pptable->FanPadding16);
1987         pr_info("FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
1988         pr_info("FanPadding = 0x%x\n", pptable->FanPadding);
1989         pr_info("FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
1990         pr_info("FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
1991
1992         pr_info("FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
1993         pr_info("FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
1994         pr_info("FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
1995         pr_info("FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
1996
1997         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1998         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1999         pr_info("dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2000         pr_info("Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2001
2002         pr_info("qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2003                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2004                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2005                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2006         pr_info("qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2007                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2008                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2009                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2010         pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2011                         pptable->dBtcGbGfxPll.a,
2012                         pptable->dBtcGbGfxPll.b,
2013                         pptable->dBtcGbGfxPll.c);
2014         pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2015                         pptable->dBtcGbGfxDfll.a,
2016                         pptable->dBtcGbGfxDfll.b,
2017                         pptable->dBtcGbGfxDfll.c);
2018         pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2019                         pptable->dBtcGbSoc.a,
2020                         pptable->dBtcGbSoc.b,
2021                         pptable->dBtcGbSoc.c);
2022         pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2023                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2024                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2025         pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2026                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2027                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2028
2029         pr_info("PiecewiseLinearDroopIntGfxDfll\n");
2030         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2031                 pr_info("               Fset[%d] = 0x%x\n",
2032                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2033                 pr_info("               Vdroop[%d] = 0x%x\n",
2034                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2035         }
2036
2037         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2038                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2039                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2040                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2041         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2042                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2043                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2044                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2045
2046         pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2047         pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2048
2049         pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2050         pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2051         pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2052         pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2053
2054         pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2055         pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2056         pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2057         pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2058
2059         pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2060         pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2061
2062         pr_info("XgmiDpmPstates\n");
2063         for (i = 0; i < NUM_XGMI_LEVELS; i++)
2064                 pr_info("  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2065         pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2066         pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2067
2068         pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2069         pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2070                         pptable->ReservedEquation0.a,
2071                         pptable->ReservedEquation0.b,
2072                         pptable->ReservedEquation0.c);
2073         pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2074                         pptable->ReservedEquation1.a,
2075                         pptable->ReservedEquation1.b,
2076                         pptable->ReservedEquation1.c);
2077         pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2078                         pptable->ReservedEquation2.a,
2079                         pptable->ReservedEquation2.b,
2080                         pptable->ReservedEquation2.c);
2081         pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2082                         pptable->ReservedEquation3.a,
2083                         pptable->ReservedEquation3.b,
2084                         pptable->ReservedEquation3.c);
2085
2086         pr_info("SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2087         pr_info("SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2088         pr_info("SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2089         pr_info("SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2090         pr_info("SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2091         pr_info("SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2092         pr_info("SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2093         pr_info("SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2094         pr_info("SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]);
2095         pr_info("SkuReserved[9] = 0x%x\n", pptable->SkuReserved[9]);
2096         pr_info("SkuReserved[10] = 0x%x\n", pptable->SkuReserved[10]);
2097         pr_info("SkuReserved[11] = 0x%x\n", pptable->SkuReserved[11]);
2098         pr_info("SkuReserved[12] = 0x%x\n", pptable->SkuReserved[12]);
2099         pr_info("SkuReserved[13] = 0x%x\n", pptable->SkuReserved[13]);
2100         pr_info("SkuReserved[14] = 0x%x\n", pptable->SkuReserved[14]);
2101
2102         pr_info("GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2103         pr_info("GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2104         pr_info("GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2105         pr_info("GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2106         pr_info("GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2107         pr_info("GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2108
2109         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2110                 pr_info("I2cControllers[%d]:\n", i);
2111                 pr_info("                   .Enabled = 0x%x\n",
2112                                 pptable->I2cControllers[i].Enabled);
2113                 pr_info("                   .Speed = 0x%x\n",
2114                                 pptable->I2cControllers[i].Speed);
2115                 pr_info("                   .SlaveAddress = 0x%x\n",
2116                                 pptable->I2cControllers[i].SlaveAddress);
2117                 pr_info("                   .ControllerPort = 0x%x\n",
2118                                 pptable->I2cControllers[i].ControllerPort);
2119                 pr_info("                   .ControllerName = 0x%x\n",
2120                                 pptable->I2cControllers[i].ControllerName);
2121                 pr_info("                   .ThermalThrottler = 0x%x\n",
2122                                 pptable->I2cControllers[i].ThermalThrotter);
2123                 pr_info("                   .I2cProtocol = 0x%x\n",
2124                                 pptable->I2cControllers[i].I2cProtocol);
2125                 pr_info("                   .PaddingConfig = 0x%x\n",
2126                                 pptable->I2cControllers[i].PaddingConfig);
2127         }
2128
2129         pr_info("GpioScl = 0x%x\n", pptable->GpioScl);
2130         pr_info("GpioSda = 0x%x\n", pptable->GpioSda);
2131         pr_info("FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2132         pr_info("I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2133
2134         pr_info("Board Parameters:\n");
2135         pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2136         pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2137         pr_info("VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2138         pr_info("VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2139         pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2140         pr_info("SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2141         pr_info("VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2142         pr_info("MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2143
2144         pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2145         pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
2146         pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2147
2148         pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2149         pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
2150         pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2151
2152         pr_info("Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2153         pr_info("Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2154         pr_info("Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2155
2156         pr_info("Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2157         pr_info("Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2158         pr_info("Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2159
2160         pr_info("MvddRatio = 0x%x\n", pptable->MvddRatio);
2161
2162         pr_info("AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2163         pr_info("AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2164         pr_info("VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2165         pr_info("VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2166         pr_info("VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2167         pr_info("VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2168         pr_info("GthrGpio = 0x%x\n", pptable->GthrGpio);
2169         pr_info("GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2170         pr_info("LedPin0 = 0x%x\n", pptable->LedPin0);
2171         pr_info("LedPin1 = 0x%x\n", pptable->LedPin1);
2172         pr_info("LedPin2 = 0x%x\n", pptable->LedPin2);
2173         pr_info("LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2174         pr_info("LedPcie = 0x%x\n", pptable->LedPcie);
2175         pr_info("LedError = 0x%x\n", pptable->LedError);
2176         pr_info("LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2177         pr_info("LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2178
2179         pr_info("PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2180         pr_info("PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2181         pr_info("PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
2182
2183         pr_info("DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2184         pr_info("DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2185         pr_info("DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
2186
2187         pr_info("UclkSpreadEnabled = 0x%x\n", pptable->UclkSpreadEnabled);
2188         pr_info("UclkSpreadPercent = 0x%x\n", pptable->UclkSpreadPercent);
2189         pr_info("UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2190
2191         pr_info("FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2192         pr_info("FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2193         pr_info("FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2194
2195         pr_info("MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2196         pr_info("DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2197         pr_info("PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2198         pr_info("PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2199         pr_info("PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2200
2201         pr_info("TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2202         pr_info("BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2203
2204         pr_info("XgmiLinkSpeed\n");
2205         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2206                 pr_info("  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2207         pr_info("XgmiLinkWidth\n");
2208         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2209                 pr_info("  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2210         pr_info("XgmiFclkFreq\n");
2211         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2212                 pr_info("  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2213         pr_info("XgmiSocVoltage\n");
2214         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2215                 pr_info("  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2216
2217         pr_info("HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2218         pr_info("VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2219         pr_info("PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2220         pr_info("PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2221
2222         pr_info("BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2223         pr_info("BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2224         pr_info("BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2225         pr_info("BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2226         pr_info("BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2227         pr_info("BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2228         pr_info("BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2229         pr_info("BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2230         pr_info("BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2231         pr_info("BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2232         pr_info("BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2233         pr_info("BoardReserved[11] = 0x%x\n", pptable->BoardReserved[11]);
2234         pr_info("BoardReserved[12] = 0x%x\n", pptable->BoardReserved[12]);
2235         pr_info("BoardReserved[13] = 0x%x\n", pptable->BoardReserved[13]);
2236         pr_info("BoardReserved[14] = 0x%x\n", pptable->BoardReserved[14]);
2237
2238         pr_info("MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2239         pr_info("MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2240         pr_info("MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2241         pr_info("MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2242         pr_info("MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2243         pr_info("MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2244         pr_info("MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2245         pr_info("MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2246 }
2247
2248 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
2249         .tables_init = sienna_cichlid_tables_init,
2250         .alloc_dpm_context = sienna_cichlid_allocate_dpm_context,
2251         .store_powerplay_table = sienna_cichlid_store_powerplay_table,
2252         .check_powerplay_table = sienna_cichlid_check_powerplay_table,
2253         .append_powerplay_table = sienna_cichlid_append_powerplay_table,
2254         .get_smu_msg_index = sienna_cichlid_get_smu_msg_index,
2255         .get_smu_clk_index = sienna_cichlid_get_smu_clk_index,
2256         .get_smu_feature_index = sienna_cichlid_get_smu_feature_index,
2257         .get_smu_table_index = sienna_cichlid_get_smu_table_index,
2258         .get_smu_power_index = sienna_cichlid_get_pwr_src_index,
2259         .get_workload_type = sienna_cichlid_get_workload_type,
2260         .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
2261         .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
2262         .dpm_set_uvd_enable = sienna_cichlid_dpm_set_uvd_enable,
2263         .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
2264         .get_current_clk_freq_by_table = sienna_cichlid_get_current_clk_freq_by_table,
2265         .print_clk_levels = sienna_cichlid_print_clk_levels,
2266         .force_clk_levels = sienna_cichlid_force_clk_levels,
2267         .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
2268         .get_clock_by_type_with_latency = sienna_cichlid_get_clock_by_type_with_latency,
2269         .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
2270         .display_config_changed = sienna_cichlid_display_config_changed,
2271         .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
2272         .force_dpm_limit_value = sienna_cichlid_force_dpm_limit_value,
2273         .unforce_dpm_levels = sienna_cichlid_unforce_dpm_levels,
2274         .is_dpm_running = sienna_cichlid_is_dpm_running,
2275         .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent,
2276         .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
2277         .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
2278         .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
2279         .get_profiling_clk_mask = sienna_cichlid_get_profiling_clk_mask,
2280         .set_watermarks_table = sienna_cichlid_set_watermarks_table,
2281         .read_sensor = sienna_cichlid_read_sensor,
2282         .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
2283         .set_performance_level = sienna_cichlid_set_performance_level,
2284         .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
2285         .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
2286         .get_power_limit = sienna_cichlid_get_power_limit,
2287         .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
2288         .dump_pptable = sienna_cichlid_dump_pptable,
2289         .init_microcode = smu_v11_0_init_microcode,
2290         .load_microcode = smu_v11_0_load_microcode,
2291         .init_smc_tables = smu_v11_0_init_smc_tables,
2292         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2293         .init_power = smu_v11_0_init_power,
2294         .fini_power = smu_v11_0_fini_power,
2295         .check_fw_status = smu_v11_0_check_fw_status,
2296         .setup_pptable = smu_v11_0_setup_pptable,
2297         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2298         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2299         .check_pptable = smu_v11_0_check_pptable,
2300         .parse_pptable = smu_v11_0_parse_pptable,
2301         .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2302         .check_fw_version = smu_v11_0_check_fw_version,
2303         .write_pptable = smu_v11_0_write_pptable,
2304         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2305         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2306         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2307         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2308         .system_features_control = smu_v11_0_system_features_control,
2309         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2310         .init_display_count = smu_v11_0_init_display_count,
2311         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2312         .get_enabled_mask = smu_v11_0_get_enabled_mask,
2313         .notify_display_change = smu_v11_0_notify_display_change,
2314         .set_power_limit = smu_v11_0_set_power_limit,
2315         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2316         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2317         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2318         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2319         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2320         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2321         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2322         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2323         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2324         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2325         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2326         .gfx_off_control = smu_v11_0_gfx_off_control,
2327         .register_irq_handler = smu_v11_0_register_irq_handler,
2328         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2329         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2330         .baco_is_support= smu_v11_0_baco_is_support,
2331         .baco_get_state = smu_v11_0_baco_get_state,
2332         .baco_set_state = smu_v11_0_baco_set_state,
2333         .baco_enter = smu_v11_0_baco_enter,
2334         .baco_exit = smu_v11_0_baco_exit,
2335         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2336         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2337         .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2338 };
2339
2340 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
2341 {
2342         smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
2343 }