drivers/gpu/drm/amd/powerplay/renoir_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_v12_0_ppsmc.h"
  29 #include "smu12_driver_if.h"
  30 #include "smu_v12_0.h"
  31 #include "renoir_ppt.h"
  32 #include "smu_cmn.h"
  33
  34 /*
  35  * DO NOT use these for err/warn/info/debug messages.
  36  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  37  * They are more MGPU friendly.
  38  */
  39 #undef pr_err
  40 #undef pr_warn
  41 #undef pr_info
  42 #undef pr_debug
  43
  44 static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = {
  45         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                  1),
  46         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,                1),
  47         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,           1),
  48         MSG_MAP(PowerUpGfx,                     PPSMC_MSG_PowerUpGfx,                   1),
  49         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_EnableGfxOff,                 1),
  50         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisableGfxOff,                1),
  51         MSG_MAP(PowerDownIspByTile,             PPSMC_MSG_PowerDownIspByTile,           1),
  52         MSG_MAP(PowerUpIspByTile,               PPSMC_MSG_PowerUpIspByTile,             1),
  53         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                 1),
  54         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                   1),
  55         MSG_MAP(PowerDownSdma,                  PPSMC_MSG_PowerDownSdma,                1),
  56         MSG_MAP(PowerUpSdma,                    PPSMC_MSG_PowerUpSdma,                  1),
  57         MSG_MAP(SetHardMinIspclkByFreq,         PPSMC_MSG_SetHardMinIspclkByFreq,       1),
  58         MSG_MAP(SetHardMinVcn,                  PPSMC_MSG_SetHardMinVcn,                1),
  59         MSG_MAP(Spare1,                         PPSMC_MSG_spare1,                       1),
  60         MSG_MAP(Spare2,                         PPSMC_MSG_spare2,                       1),
  61         MSG_MAP(SetAllowFclkSwitch,             PPSMC_MSG_SetAllowFclkSwitch,           1),
  62         MSG_MAP(SetMinVideoGfxclkFreq,          PPSMC_MSG_SetMinVideoGfxclkFreq,        1),
  63         MSG_MAP(ActiveProcessNotify,            PPSMC_MSG_ActiveProcessNotify,          1),
  64         MSG_MAP(SetCustomPolicy,                PPSMC_MSG_SetCustomPolicy,              1),
  65         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                  1),
  66         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_SetDisplayCount,              1),
  67         MSG_MAP(QueryPowerLimit,                PPSMC_MSG_QueryPowerLimit,              1),
  68         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,        1),
  69         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,         1),
  70         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,        1),
  71         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,        1),
  72         MSG_MAP(GfxDeviceDriverReset,           PPSMC_MSG_GfxDeviceDriverReset,         1),
  73         MSG_MAP(SetGfxclkOverdriveByFreqVid,    PPSMC_MSG_SetGfxclkOverdriveByFreqVid,  1),
  74         MSG_MAP(SetHardMinDcfclkByFreq,         PPSMC_MSG_SetHardMinDcfclkByFreq,       1),
  75         MSG_MAP(SetHardMinSocclkByFreq,         PPSMC_MSG_SetHardMinSocclkByFreq,       1),
  76         MSG_MAP(ControlIgpuATS,                 PPSMC_MSG_ControlIgpuATS,               1),
  77         MSG_MAP(SetMinVideoFclkFreq,            PPSMC_MSG_SetMinVideoFclkFreq,          1),
  78         MSG_MAP(SetMinDeepSleepDcfclk,          PPSMC_MSG_SetMinDeepSleepDcfclk,        1),
  79         MSG_MAP(ForcePowerDownGfx,              PPSMC_MSG_ForcePowerDownGfx,            1),
  80         MSG_MAP(SetPhyclkVoltageByFreq,         PPSMC_MSG_SetPhyclkVoltageByFreq,       1),
  81         MSG_MAP(SetDppclkVoltageByFreq,         PPSMC_MSG_SetDppclkVoltageByFreq,       1),
  82         MSG_MAP(SetSoftMinVcn,                  PPSMC_MSG_SetSoftMinVcn,                1),
  83         MSG_MAP(EnablePostCode,                 PPSMC_MSG_EnablePostCode,               1),
  84         MSG_MAP(GetGfxclkFrequency,             PPSMC_MSG_GetGfxclkFrequency,           1),
  85         MSG_MAP(GetFclkFrequency,               PPSMC_MSG_GetFclkFrequency,             1),
  86         MSG_MAP(GetMinGfxclkFrequency,          PPSMC_MSG_GetMinGfxclkFrequency,        1),
  87         MSG_MAP(GetMaxGfxclkFrequency,          PPSMC_MSG_GetMaxGfxclkFrequency,        1),
  88         MSG_MAP(SoftReset,                      PPSMC_MSG_SoftReset,                    1),
  89         MSG_MAP(SetGfxCGPG,                     PPSMC_MSG_SetGfxCGPG,                   1),
  90         MSG_MAP(SetSoftMaxGfxClk,               PPSMC_MSG_SetSoftMaxGfxClk,             1),
  91         MSG_MAP(SetHardMinGfxClk,               PPSMC_MSG_SetHardMinGfxClk,             1),
  92         MSG_MAP(SetSoftMaxSocclkByFreq,         PPSMC_MSG_SetSoftMaxSocclkByFreq,       1),
  93         MSG_MAP(SetSoftMaxFclkByFreq,           PPSMC_MSG_SetSoftMaxFclkByFreq,         1),
  94         MSG_MAP(SetSoftMaxVcn,                  PPSMC_MSG_SetSoftMaxVcn,                1),
  95         MSG_MAP(PowerGateMmHub,                 PPSMC_MSG_PowerGateMmHub,               1),
  96         MSG_MAP(UpdatePmeRestore,               PPSMC_MSG_UpdatePmeRestore,             1),
  97         MSG_MAP(GpuChangeState,                 PPSMC_MSG_GpuChangeState,               1),
  98         MSG_MAP(SetPowerLimitPercentage,        PPSMC_MSG_SetPowerLimitPercentage,      1),
  99         MSG_MAP(ForceGfxContentSave,            PPSMC_MSG_ForceGfxContentSave,          1),
 100         MSG_MAP(EnableTmdp48MHzRefclkPwrDown,   PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown, 1),
 101         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,                1),
 102         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                  1),
 103         MSG_MAP(PowerGateAtHub,                 PPSMC_MSG_PowerGateAtHub,               1),
 104         MSG_MAP(SetSoftMinJpeg,                 PPSMC_MSG_SetSoftMinJpeg,               1),
 105         MSG_MAP(SetHardMinFclkByFreq,           PPSMC_MSG_SetHardMinFclkByFreq,         1),
 106 };
 107
 108 static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = {
 109         CLK_MAP(GFXCLK, CLOCK_GFXCLK),
 110         CLK_MAP(SCLK,   CLOCK_GFXCLK),
 111         CLK_MAP(SOCCLK, CLOCK_SOCCLK),
 112         CLK_MAP(UCLK, CLOCK_FCLK),
 113         CLK_MAP(MCLK, CLOCK_FCLK),
 114 };
 115
 116 static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = {
 117         TAB_MAP_VALID(WATERMARKS),
 118         TAB_MAP_INVALID(CUSTOM_DPM),
 119         TAB_MAP_VALID(DPMCLOCKS),
 120         TAB_MAP_VALID(SMU_METRICS),
 121 };
 122
 123 static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 124         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 125         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 126         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 127         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 128         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 129 };
 130
 131 static int renoir_get_metrics_table(struct smu_context *smu,
 132                                     SmuMetrics_t *metrics_table,
 133                                     bool bypass_cache)
 134 {
 135         struct smu_table_context *smu_table= &smu->smu_table;
 136         int ret = 0;
 137
 138         mutex_lock(&smu->metrics_lock);
 139
 140         if (bypass_cache ||
 141             !smu_table->metrics_time ||
 142             time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(1))) {
 143                 ret = smu_cmn_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 144                                 (void *)smu_table->metrics_table, false);
 145                 if (ret) {
 146                         dev_info(smu->adev->dev, "Failed to export SMU metrics table!\n");
 147                         mutex_unlock(&smu->metrics_lock);
 148                         return ret;
 149                 }
 150                 smu_table->metrics_time = jiffies;
 151         }
 152
 153         if (metrics_table)
 154                 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
 155
 156         mutex_unlock(&smu->metrics_lock);
 157
 158         return ret;
 159 }
 160
 161 static int renoir_init_smc_tables(struct smu_context *smu)
 162 {
 163         struct smu_table_context *smu_table = &smu->smu_table;
 164         struct smu_table *tables = smu_table->tables;
 165
 166         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 167                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 168         SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
 169                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 170         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 171                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 172
 173         smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
 174         if (!smu_table->clocks_table)
 175                 goto err0_out;
 176
 177         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 178         if (!smu_table->metrics_table)
 179                 goto err1_out;
 180         smu_table->metrics_time = 0;
 181
 182         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 183         if (!smu_table->watermarks_table)
 184                 goto err2_out;
 185
 186         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_0);
 187         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 188         if (!smu_table->gpu_metrics_table)
 189                 goto err3_out;
 190
 191         return 0;
 192
 193 err3_out:
 194         kfree(smu_table->watermarks_table);
 195 err2_out:
 196         kfree(smu_table->metrics_table);
 197 err1_out:
 198         kfree(smu_table->clocks_table);
 199 err0_out:
 200         return -ENOMEM;
 201 }
 202
 203 /**
 204  * This interface just for getting uclk ultimate freq and should't introduce
 205  * other likewise function result in overmuch callback.
 206  */
 207 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
 208                                                 uint32_t dpm_level, uint32_t *freq)
 209 {
 210         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 211
 212         if (!clk_table || clk_type >= SMU_CLK_COUNT)
 213                 return -EINVAL;
 214
 215         switch (clk_type) {
 216         case SMU_SOCCLK:
 217                 if (dpm_level >= NUM_SOCCLK_DPM_LEVELS)
 218                         return -EINVAL;
 219                 *freq = clk_table->SocClocks[dpm_level].Freq;
 220                 break;
 221         case SMU_MCLK:
 222                 if (dpm_level >= NUM_FCLK_DPM_LEVELS)
 223                         return -EINVAL;
 224                 *freq = clk_table->FClocks[dpm_level].Freq;
 225                 break;
 226         case SMU_DCEFCLK:
 227                 if (dpm_level >= NUM_DCFCLK_DPM_LEVELS)
 228                         return -EINVAL;
 229                 *freq = clk_table->DcfClocks[dpm_level].Freq;
 230                 break;
 231         case SMU_FCLK:
 232                 if (dpm_level >= NUM_FCLK_DPM_LEVELS)
 233                         return -EINVAL;
 234                 *freq = clk_table->FClocks[dpm_level].Freq;
 235                 break;
 236         default:
 237                 return -EINVAL;
 238         }
 239
 240         return 0;
 241 }
 242
 243 static int renoir_get_profiling_clk_mask(struct smu_context *smu,
 244                                          enum amd_dpm_forced_level level,
 245                                          uint32_t *sclk_mask,
 246                                          uint32_t *mclk_mask,
 247                                          uint32_t *soc_mask)
 248 {
 249
 250         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
 251                 if (sclk_mask)
 252                         *sclk_mask = 0;
 253         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
 254                 if (mclk_mask)
 255                         *mclk_mask = 0;
 256         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
 257                 if(sclk_mask)
 258                         /* The sclk as gfxclk and has three level about max/min/current */
 259                         *sclk_mask = 3 - 1;
 260
 261                 if(mclk_mask)
 262                         *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;
 263
 264                 if(soc_mask)
 265                         *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;
 266         }
 267
 268         return 0;
 269 }
 270
 271 static int renoir_get_dpm_ultimate_freq(struct smu_context *smu,
 272                                         enum smu_clk_type clk_type,
 273                                         uint32_t *min,
 274                                         uint32_t *max)
 275 {
 276         int ret = 0;
 277         uint32_t mclk_mask, soc_mask;
 278         uint32_t clock_limit;
 279
 280         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
 281                 switch (clk_type) {
 282                 case SMU_MCLK:
 283                 case SMU_UCLK:
 284                         clock_limit = smu->smu_table.boot_values.uclk;
 285                         break;
 286                 case SMU_GFXCLK:
 287                 case SMU_SCLK:
 288                         clock_limit = smu->smu_table.boot_values.gfxclk;
 289                         break;
 290                 case SMU_SOCCLK:
 291                         clock_limit = smu->smu_table.boot_values.socclk;
 292                         break;
 293                 default:
 294                         clock_limit = 0;
 295                         break;
 296                 }
 297
 298                 /* clock in Mhz unit */
 299                 if (min)
 300                         *min = clock_limit / 100;
 301                 if (max)
 302                         *max = clock_limit / 100;
 303
 304                 return 0;
 305         }
 306
 307         if (max) {
 308                 ret = renoir_get_profiling_clk_mask(smu,
 309                                                     AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
 310                                                     NULL,
 311                                                     &mclk_mask,
 312                                                     &soc_mask);
 313                 if (ret)
 314                         goto failed;
 315
 316                 switch (clk_type) {
 317                 case SMU_GFXCLK:
 318                 case SMU_SCLK:
 319                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max);
 320                         if (ret) {
 321                                 dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n");
 322                                 goto failed;
 323                         }
 324                         break;
 325                 case SMU_UCLK:
 326                 case SMU_FCLK:
 327                 case SMU_MCLK:
 328                         ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
 329                         if (ret)
 330                                 goto failed;
 331                         break;
 332                 case SMU_SOCCLK:
 333                         ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
 334                         if (ret)
 335                                 goto failed;
 336                         break;
 337                 default:
 338                         ret = -EINVAL;
 339                         goto failed;
 340                 }
 341         }
 342
 343         if (min) {
 344                 switch (clk_type) {
 345                 case SMU_GFXCLK:
 346                 case SMU_SCLK:
 347                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min);
 348                         if (ret) {
 349                                 dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n");
 350                                 goto failed;
 351                         }
 352                         break;
 353                 case SMU_UCLK:
 354                 case SMU_FCLK:
 355                 case SMU_MCLK:
 356                         ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min);
 357                         if (ret)
 358                                 goto failed;
 359                         break;
 360                 case SMU_SOCCLK:
 361                         ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min);
 362                         if (ret)
 363                                 goto failed;
 364                         break;
 365                 default:
 366                         ret = -EINVAL;
 367                         goto failed;
 368                 }
 369         }
 370 failed:
 371         return ret;
 372 }
 373
 374 static int renoir_print_clk_levels(struct smu_context *smu,
 375                         enum smu_clk_type clk_type, char *buf)
 376 {
 377         int i, size = 0, ret = 0;
 378         uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
 379         SmuMetrics_t metrics;
 380         bool cur_value_match_level = false;
 381
 382         memset(&metrics, 0, sizeof(metrics));
 383
 384         ret = renoir_get_metrics_table(smu, &metrics, false);
 385         if (ret)
 386                 return ret;
 387
 388         switch (clk_type) {
 389         case SMU_GFXCLK:
 390         case SMU_SCLK:
 391                 /* retirve table returned paramters unit is MHz */
 392                 cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
 393                 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max);
 394                 if (!ret) {
 395                         /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
 396                         if (cur_value  == max)
 397                                 i = 2;
 398                         else if (cur_value == min)
 399                                 i = 0;
 400                         else
 401                                 i = 1;
 402
 403                         size += sprintf(buf + size, "0: %uMhz %s\n", min,
 404                                         i == 0 ? "*" : "");
 405                         size += sprintf(buf + size, "1: %uMhz %s\n",
 406                                         i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK,
 407                                         i == 1 ? "*" : "");
 408                         size += sprintf(buf + size, "2: %uMhz %s\n", max,
 409                                         i == 2 ? "*" : "");
 410                 }
 411                 return size;
 412         case SMU_SOCCLK:
 413                 count = NUM_SOCCLK_DPM_LEVELS;
 414                 cur_value = metrics.ClockFrequency[CLOCK_SOCCLK];
 415                 break;
 416         case SMU_MCLK:
 417                 count = NUM_MEMCLK_DPM_LEVELS;
 418                 cur_value = metrics.ClockFrequency[CLOCK_FCLK];
 419                 break;
 420         case SMU_DCEFCLK:
 421                 count = NUM_DCFCLK_DPM_LEVELS;
 422                 cur_value = metrics.ClockFrequency[CLOCK_DCFCLK];
 423                 break;
 424         case SMU_FCLK:
 425                 count = NUM_FCLK_DPM_LEVELS;
 426                 cur_value = metrics.ClockFrequency[CLOCK_FCLK];
 427                 break;
 428         default:
 429                 return -EINVAL;
 430         }
 431
 432         for (i = 0; i < count; i++) {
 433                 ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value);
 434                 if (ret)
 435                         return ret;
 436                 if (!value)
 437                         continue;
 438                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 439                                 cur_value == value ? "*" : "");
 440                 if (cur_value == value)
 441                         cur_value_match_level = true;
 442         }
 443
 444         if (!cur_value_match_level)
 445                 size += sprintf(buf + size, "   %uMhz *\n", cur_value);
 446
 447         return size;
 448 }
 449
 450 static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu)
 451 {
 452         enum amd_pm_state_type pm_type;
 453         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
 454
 455         if (!smu_dpm_ctx->dpm_context ||
 456             !smu_dpm_ctx->dpm_current_power_state)
 457                 return -EINVAL;
 458
 459         switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
 460         case SMU_STATE_UI_LABEL_BATTERY:
 461                 pm_type = POWER_STATE_TYPE_BATTERY;
 462                 break;
 463         case SMU_STATE_UI_LABEL_BALLANCED:
 464                 pm_type = POWER_STATE_TYPE_BALANCED;
 465                 break;
 466         case SMU_STATE_UI_LABEL_PERFORMANCE:
 467                 pm_type = POWER_STATE_TYPE_PERFORMANCE;
 468                 break;
 469         default:
 470                 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
 471                         pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
 472                 else
 473                         pm_type = POWER_STATE_TYPE_DEFAULT;
 474                 break;
 475         }
 476
 477         return pm_type;
 478 }
 479
 480 static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 481 {
 482         int ret = 0;
 483
 484         if (enable) {
 485                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 486                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 487                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
 488                         if (ret)
 489                                 return ret;
 490                 }
 491         } else {
 492                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 493                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
 494                         if (ret)
 495                                 return ret;
 496                 }
 497         }
 498
 499         return ret;
 500 }
 501
 502 static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 503 {
 504         int ret = 0;
 505
 506         if (enable) {
 507                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 508                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
 509                         if (ret)
 510                                 return ret;
 511                 }
 512         } else {
 513                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 514                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
 515                         if (ret)
 516                                 return ret;
 517                 }
 518         }
 519
 520         return ret;
 521 }
 522
 523 static int renoir_get_current_clk_freq_by_table(struct smu_context *smu,
 524                                        enum smu_clk_type clk_type,
 525                                        uint32_t *value)
 526 {
 527         int ret = 0, clk_id = 0;
 528         SmuMetrics_t metrics;
 529
 530         ret = renoir_get_metrics_table(smu, &metrics, false);
 531         if (ret)
 532                 return ret;
 533
 534         clk_id = smu_cmn_to_asic_specific_index(smu,
 535                                                 CMN2ASIC_MAPPING_CLK,
 536                                                 clk_type);
 537         if (clk_id < 0)
 538                 return clk_id;
 539
 540         *value = metrics.ClockFrequency[clk_id];
 541
 542         return ret;
 543 }
 544
 545 static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
 546 {
 547         int ret = 0, i = 0;
 548         uint32_t min_freq, max_freq, force_freq;
 549         enum smu_clk_type clk_type;
 550
 551         enum smu_clk_type clks[] = {
 552                 SMU_GFXCLK,
 553                 SMU_MCLK,
 554                 SMU_SOCCLK,
 555         };
 556
 557         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 558                 clk_type = clks[i];
 559                 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
 560                 if (ret)
 561                         return ret;
 562
 563                 force_freq = highest ? max_freq : min_freq;
 564                 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
 565                 if (ret)
 566                         return ret;
 567         }
 568
 569         return ret;
 570 }
 571
 572 static int renoir_unforce_dpm_levels(struct smu_context *smu) {
 573
 574         int ret = 0, i = 0;
 575         uint32_t min_freq, max_freq;
 576         enum smu_clk_type clk_type;
 577
 578         struct clk_feature_map {
 579                 enum smu_clk_type clk_type;
 580                 uint32_t        feature;
 581         } clk_feature_map[] = {
 582                 {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},
 583                 {SMU_MCLK,   SMU_FEATURE_DPM_UCLK_BIT},
 584                 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
 585         };
 586
 587         for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
 588                 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
 589                     continue;
 590
 591                 clk_type = clk_feature_map[i].clk_type;
 592
 593                 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
 594                 if (ret)
 595                         return ret;
 596
 597                 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
 598                 if (ret)
 599                         return ret;
 600         }
 601
 602         return ret;
 603 }
 604
 605 static int renoir_get_gpu_temperature(struct smu_context *smu, uint32_t *value)
 606 {
 607         int ret = 0;
 608         SmuMetrics_t metrics;
 609
 610         if (!value)
 611                 return -EINVAL;
 612
 613         ret = renoir_get_metrics_table(smu, &metrics, false);
 614         if (ret)
 615                 return ret;
 616
 617         *value = (metrics.GfxTemperature / 100) *
 618                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 619
 620         return 0;
 621 }
 622
 623 static int renoir_get_current_activity_percent(struct smu_context *smu,
 624                                                enum amd_pp_sensors sensor,
 625                                                uint32_t *value)
 626 {
 627         int ret = 0;
 628         SmuMetrics_t metrics;
 629
 630         if (!value)
 631                 return -EINVAL;
 632
 633         ret = renoir_get_metrics_table(smu, &metrics, false);
 634         if (ret)
 635                 return ret;
 636
 637         switch (sensor) {
 638         case AMDGPU_PP_SENSOR_GPU_LOAD:
 639                 *value = metrics.AverageGfxActivity / 100;
 640                 break;
 641         default:
 642                 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
 643                 return -EINVAL;
 644         }
 645
 646         return 0;
 647 }
 648
 649 /**
 650  * This interface get dpm clock table for dc
 651  */
 652 static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
 653 {
 654         DpmClocks_t *table = smu->smu_table.clocks_table;
 655         int i;
 656
 657         if (!clock_table || !table)
 658                 return -EINVAL;
 659
 660         for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) {
 661                 clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq;
 662                 clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol;
 663         }
 664
 665         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
 666                 clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq;
 667                 clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol;
 668         }
 669
 670         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
 671                 clock_table->FClocks[i].Freq = table->FClocks[i].Freq;
 672                 clock_table->FClocks[i].Vol = table->FClocks[i].Vol;
 673         }
 674
 675         for (i = 0; i<  NUM_MEMCLK_DPM_LEVELS; i++) {
 676                 clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq;
 677                 clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol;
 678         }
 679
 680         return 0;
 681 }
 682
 683 static int renoir_force_clk_levels(struct smu_context *smu,
 684                                    enum smu_clk_type clk_type, uint32_t mask)
 685 {
 686
 687         int ret = 0 ;
 688         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
 689
 690         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 691         soft_max_level = mask ? (fls(mask) - 1) : 0;
 692
 693         switch (clk_type) {
 694         case SMU_GFXCLK:
 695         case SMU_SCLK:
 696                 if (soft_min_level > 2 || soft_max_level > 2) {
 697                         dev_info(smu->adev->dev, "Currently sclk only support 3 levels on APU\n");
 698                         return -EINVAL;
 699                 }
 700
 701                 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq);
 702                 if (ret)
 703                         return ret;
 704                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
 705                                         soft_max_level == 0 ? min_freq :
 706                                         soft_max_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : max_freq,
 707                                         NULL);
 708                 if (ret)
 709                         return ret;
 710                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
 711                                         soft_min_level == 2 ? max_freq :
 712                                         soft_min_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : min_freq,
 713                                         NULL);
 714                 if (ret)
 715                         return ret;
 716                 break;
 717         case SMU_SOCCLK:
 718                 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
 719                 if (ret)
 720                         return ret;
 721                 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
 722                 if (ret)
 723                         return ret;
 724                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL);
 725                 if (ret)
 726                         return ret;
 727                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL);
 728                 if (ret)
 729                         return ret;
 730                 break;
 731         case SMU_MCLK:
 732         case SMU_FCLK:
 733                 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
 734                 if (ret)
 735                         return ret;
 736                 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
 737                 if (ret)
 738                         return ret;
 739                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL);
 740                 if (ret)
 741                         return ret;
 742                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL);
 743                 if (ret)
 744                         return ret;
 745                 break;
 746         default:
 747                 break;
 748         }
 749
 750         return ret;
 751 }
 752
 753 static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
 754 {
 755         int workload_type, ret;
 756         uint32_t profile_mode = input[size];
 757
 758         if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
 759                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
 760                 return -EINVAL;
 761         }
 762
 763         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
 764         workload_type = smu_cmn_to_asic_specific_index(smu,
 765                                                        CMN2ASIC_MAPPING_WORKLOAD,
 766                                                        profile_mode);
 767         if (workload_type < 0) {
 768                 /*
 769                  * TODO: If some case need switch to powersave/default power mode
 770                  * then can consider enter WORKLOAD_COMPUTE/WORKLOAD_CUSTOM for power saving.
 771                  */
 772                 dev_err_once(smu->adev->dev, "Unsupported power profile mode %d on RENOIR\n", profile_mode);
 773                 return -EINVAL;
 774         }
 775
 776         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
 777                                     1 << workload_type,
 778                                     NULL);
 779         if (ret) {
 780                 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
 781                 return ret;
 782         }
 783
 784         smu->power_profile_mode = profile_mode;
 785
 786         return 0;
 787 }
 788
 789 static int renoir_set_peak_clock_by_device(struct smu_context *smu)
 790 {
 791         int ret = 0;
 792         uint32_t sclk_freq = 0, uclk_freq = 0;
 793
 794         ret = renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq);
 795         if (ret)
 796                 return ret;
 797
 798         ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
 799         if (ret)
 800                 return ret;
 801
 802         ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq);
 803         if (ret)
 804                 return ret;
 805
 806         ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
 807         if (ret)
 808                 return ret;
 809
 810         return ret;
 811 }
 812
 813 static int renoir_set_performance_level(struct smu_context *smu,
 814                                         enum amd_dpm_forced_level level)
 815 {
 816         int ret = 0;
 817         uint32_t sclk_mask, mclk_mask, soc_mask;
 818
 819         switch (level) {
 820         case AMD_DPM_FORCED_LEVEL_HIGH:
 821                 ret = renoir_force_dpm_limit_value(smu, true);
 822                 break;
 823         case AMD_DPM_FORCED_LEVEL_LOW:
 824                 ret = renoir_force_dpm_limit_value(smu, false);
 825                 break;
 826         case AMD_DPM_FORCED_LEVEL_AUTO:
 827         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
 828                 ret = renoir_unforce_dpm_levels(smu);
 829                 break;
 830         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
 831         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
 832                 ret = renoir_get_profiling_clk_mask(smu, level,
 833                                                     &sclk_mask,
 834                                                     &mclk_mask,
 835                                                     &soc_mask);
 836                 if (ret)
 837                         return ret;
 838                 renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
 839                 renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
 840                 renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
 841                 break;
 842         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
 843                 ret = renoir_set_peak_clock_by_device(smu);
 844                 break;
 845         case AMD_DPM_FORCED_LEVEL_MANUAL:
 846         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
 847         default:
 848                 break;
 849         }
 850         return ret;
 851 }
 852
 853 /* save watermark settings into pplib smu structure,
 854  * also pass data to smu controller
 855  */
 856 static int renoir_set_watermarks_table(
 857                 struct smu_context *smu,
 858                 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
 859 {
 860         Watermarks_t *table = smu->smu_table.watermarks_table;
 861         int ret = 0;
 862         int i;
 863
 864         if (clock_ranges) {
 865                 if (clock_ranges->num_wm_dmif_sets > 4 ||
 866                                 clock_ranges->num_wm_mcif_sets > 4)
 867                         return -EINVAL;
 868
 869                 /* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/
 870                 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
 871                         table->WatermarkRow[WM_DCFCLK][i].MinClock =
 872                                 cpu_to_le16((uint16_t)
 873                                 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz));
 874                         table->WatermarkRow[WM_DCFCLK][i].MaxClock =
 875                                 cpu_to_le16((uint16_t)
 876                                 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz));
 877                         table->WatermarkRow[WM_DCFCLK][i].MinMclk =
 878                                 cpu_to_le16((uint16_t)
 879                                 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz));
 880                         table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
 881                                 cpu_to_le16((uint16_t)
 882                                 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz));
 883                         table->WatermarkRow[WM_DCFCLK][i].WmSetting = (uint8_t)
 884                                         clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
 885                 }
 886
 887                 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
 888                         table->WatermarkRow[WM_SOCCLK][i].MinClock =
 889                                 cpu_to_le16((uint16_t)
 890                                 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz));
 891                         table->WatermarkRow[WM_SOCCLK][i].MaxClock =
 892                                 cpu_to_le16((uint16_t)
 893                                 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz));
 894                         table->WatermarkRow[WM_SOCCLK][i].MinMclk =
 895                                 cpu_to_le16((uint16_t)
 896                                 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz));
 897                         table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
 898                                 cpu_to_le16((uint16_t)
 899                                 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz));
 900                         table->WatermarkRow[WM_SOCCLK][i].WmSetting = (uint8_t)
 901                                         clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
 902                 }
 903
 904                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
 905         }
 906
 907         /* pass data to smu controller */
 908         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 909              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 910                 ret = smu_cmn_write_watermarks_table(smu);
 911                 if (ret) {
 912                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
 913                         return ret;
 914                 }
 915                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
 916         }
 917
 918         return 0;
 919 }
 920
 921 static int renoir_get_power_profile_mode(struct smu_context *smu,
 922                                            char *buf)
 923 {
 924         static const char *profile_name[] = {
 925                                         "BOOTUP_DEFAULT",
 926                                         "3D_FULL_SCREEN",
 927                                         "POWER_SAVING",
 928                                         "VIDEO",
 929                                         "VR",
 930                                         "COMPUTE",
 931                                         "CUSTOM"};
 932         uint32_t i, size = 0;
 933         int16_t workload_type = 0;
 934
 935         if (!buf)
 936                 return -EINVAL;
 937
 938         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
 939                 /*
 940                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
 941                  * Not all profile modes are supported on arcturus.
 942                  */
 943                 workload_type = smu_cmn_to_asic_specific_index(smu,
 944                                                                CMN2ASIC_MAPPING_WORKLOAD,
 945                                                                i);
 946                 if (workload_type < 0)
 947                         continue;
 948
 949                 size += sprintf(buf + size, "%2d %14s%s\n",
 950                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
 951         }
 952
 953         return size;
 954 }
 955
 956 static int renoir_read_sensor(struct smu_context *smu,
 957                                  enum amd_pp_sensors sensor,
 958                                  void *data, uint32_t *size)
 959 {
 960         int ret = 0;
 961
 962         if (!data || !size)
 963                 return -EINVAL;
 964
 965         mutex_lock(&smu->sensor_lock);
 966         switch (sensor) {
 967         case AMDGPU_PP_SENSOR_GPU_LOAD:
 968                 ret = renoir_get_current_activity_percent(smu, sensor, (uint32_t *)data);
 969                 *size = 4;
 970                 break;
 971         case AMDGPU_PP_SENSOR_GPU_TEMP:
 972                 ret = renoir_get_gpu_temperature(smu, (uint32_t *)data);
 973                 *size = 4;
 974                 break;
 975         case AMDGPU_PP_SENSOR_GFX_MCLK:
 976                 ret = renoir_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
 977                 *(uint32_t *)data *= 100;
 978                 *size = 4;
 979                 break;
 980         case AMDGPU_PP_SENSOR_GFX_SCLK:
 981                 ret = renoir_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
 982                 *(uint32_t *)data *= 100;
 983                 *size = 4;
 984                 break;
 985         default:
 986                 ret = -EOPNOTSUPP;
 987                 break;
 988         }
 989         mutex_unlock(&smu->sensor_lock);
 990
 991         return ret;
 992 }
 993
 994 static bool renoir_is_dpm_running(struct smu_context *smu)
 995 {
 996         struct amdgpu_device *adev = smu->adev;
 997
 998         /*
 999          * Until now, the pmfw hasn't exported the interface of SMU
1000          * feature mask to APU SKU so just force on all the feature
1001          * at early initial stage.
1002          */
1003         if (adev->in_suspend)
1004                 return false;
1005         else
1006                 return true;
1007
1008 }
1009
1010 static ssize_t renoir_get_gpu_metrics(struct smu_context *smu,
1011                                       void **table)
1012 {
1013         struct smu_table_context *smu_table = &smu->smu_table;
1014         struct gpu_metrics_v2_0 *gpu_metrics =
1015                 (struct gpu_metrics_v2_0 *)smu_table->gpu_metrics_table;
1016         SmuMetrics_t metrics;
1017         int ret = 0;
1018
1019         ret = renoir_get_metrics_table(smu, &metrics, true);
1020         if (ret)
1021                 return ret;
1022
1023         smu_v12_0_init_gpu_metrics_v2_0(gpu_metrics);
1024
1025         gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1026         gpu_metrics->temperature_soc = metrics.SocTemperature;
1027         memcpy(&gpu_metrics->temperature_core[0],
1028                 &metrics.CoreTemperature[0],
1029                 sizeof(uint16_t) * 8);
1030         gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1031         gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1];
1032
1033         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1034         gpu_metrics->average_mm_activity = metrics.AverageUvdActivity;
1035
1036         gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1037         gpu_metrics->average_cpu_power = metrics.Power[0];
1038         gpu_metrics->average_soc_power = metrics.Power[1];
1039         memcpy(&gpu_metrics->average_core_power[0],
1040                 &metrics.CorePower[0],
1041                 sizeof(uint16_t) * 8);
1042
1043         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1044         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1045         gpu_metrics->average_fclk_frequency = metrics.AverageFclkFrequency;
1046         gpu_metrics->average_vclk_frequency = metrics.AverageVclkFrequency;
1047
1048         gpu_metrics->current_gfxclk = metrics.ClockFrequency[CLOCK_GFXCLK];
1049         gpu_metrics->current_socclk = metrics.ClockFrequency[CLOCK_SOCCLK];
1050         gpu_metrics->current_uclk = metrics.ClockFrequency[CLOCK_UMCCLK];
1051         gpu_metrics->current_fclk = metrics.ClockFrequency[CLOCK_FCLK];
1052         gpu_metrics->current_vclk = metrics.ClockFrequency[CLOCK_VCLK];
1053         gpu_metrics->current_dclk = metrics.ClockFrequency[CLOCK_DCLK];
1054         memcpy(&gpu_metrics->current_coreclk[0],
1055                 &metrics.CoreFrequency[0],
1056                 sizeof(uint16_t) * 8);
1057         gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1058         gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1];
1059
1060         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1061
1062         gpu_metrics->fan_pwm = metrics.FanPwm;
1063
1064         *table = (void *)gpu_metrics;
1065
1066         return sizeof(struct gpu_metrics_v2_0);
1067 }
1068
1069 static const struct pptable_funcs renoir_ppt_funcs = {
1070         .set_power_state = NULL,
1071         .print_clk_levels = renoir_print_clk_levels,
1072         .get_current_power_state = renoir_get_current_power_state,
1073         .dpm_set_vcn_enable = renoir_dpm_set_vcn_enable,
1074         .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
1075         .force_clk_levels = renoir_force_clk_levels,
1076         .set_power_profile_mode = renoir_set_power_profile_mode,
1077         .set_performance_level = renoir_set_performance_level,
1078         .get_dpm_clock_table = renoir_get_dpm_clock_table,
1079         .set_watermarks_table = renoir_set_watermarks_table,
1080         .get_power_profile_mode = renoir_get_power_profile_mode,
1081         .read_sensor = renoir_read_sensor,
1082         .check_fw_status = smu_v12_0_check_fw_status,
1083         .check_fw_version = smu_v12_0_check_fw_version,
1084         .powergate_sdma = smu_v12_0_powergate_sdma,
1085         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1086         .send_smc_msg = smu_cmn_send_smc_msg,
1087         .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
1088         .gfx_off_control = smu_v12_0_gfx_off_control,
1089         .get_gfx_off_status = smu_v12_0_get_gfxoff_status,
1090         .init_smc_tables = renoir_init_smc_tables,
1091         .fini_smc_tables = smu_v12_0_fini_smc_tables,
1092         .set_default_dpm_table = smu_v12_0_set_default_dpm_tables,
1093         .get_enabled_mask = smu_cmn_get_enabled_mask,
1094         .feature_is_enabled = smu_cmn_feature_is_enabled,
1095         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
1096         .get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq,
1097         .mode2_reset = smu_v12_0_mode2_reset,
1098         .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
1099         .set_driver_table_location = smu_v12_0_set_driver_table_location,
1100         .is_dpm_running = renoir_is_dpm_running,
1101         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1102         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1103         .get_gpu_metrics = renoir_get_gpu_metrics,
1104 };
1105
1106 void renoir_set_ppt_funcs(struct smu_context *smu)
1107 {
1108         smu->ppt_funcs = &renoir_ppt_funcs;
1109         smu->message_map = renoir_message_map;
1110         smu->clock_map = renoir_clk_map;
1111         smu->table_map = renoir_table_map;
1112         smu->workload_map = renoir_workload_map;
1113         smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION;
1114         smu->is_apu = true;
1115 }