drivers/gpu/drm/amd/powerplay/navi10_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/pci.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_internal.h"
  29 #include "atomfirmware.h"
  30 #include "amdgpu_atomfirmware.h"
  31 #include "soc15_common.h"
  32 #include "smu_v11_0.h"
  33 #include "smu11_driver_if_navi10.h"
  34 #include "atom.h"
  35 #include "navi10_ppt.h"
  36 #include "smu_v11_0_pptable.h"
  37 #include "smu_v11_0_ppsmc.h"
  38 #include "nbio/nbio_2_3_offset.h"
  39 #include "nbio/nbio_2_3_sh_mask.h"
  40 #include "thm/thm_11_0_2_offset.h"
  41 #include "thm/thm_11_0_2_sh_mask.h"
  42
  43 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  44
  45 #define FEATURE_MASK(feature) (1ULL << feature)
  46 #define SMC_DPM_FEATURE ( \
  47         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  48         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  49         FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT)   | \
  50         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  51         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  52         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)     | \
  53         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  54         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
  55
  56 #define MSG_MAP(msg, index, valid_in_vf) \
  57         [SMU_MSG_##msg] = {1, (index), (valid_in_vf)}
  58
  59 static struct smu_11_0_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
  60         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                  1),
  61         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,                1),
  62         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,           1),
  63         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,    0),
  64         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,   0),
  65         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,         0),
  66         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,        0),
  67         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,         1),
  68         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,        1),
  69         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,        1),
  70         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,       1),
  71         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetEnabledSmuFeaturesLow,     1),
  72         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetEnabledSmuFeaturesHigh,    1),
  73         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,              1),
  74         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                  0),
  75         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,        0),
  76         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,         0),
  77         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,         0),
  78         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,          0),
  79         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,        0),
  80         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,        0),
  81         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,            0),
  82         MSG_MAP(UseBackupPPTable,               PPSMC_MSG_UseBackupPPTable,             0),
  83         MSG_MAP(RunBtc,                         PPSMC_MSG_RunBtc,                       0),
  84         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                    0),
  85         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,             0),
  86         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,             0),
  87         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,             1),
  88         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,             0),
  89         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,                1),
  90         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,                1),
  91         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,            1),
  92         MSG_MAP(SetMemoryChannelConfig,         PPSMC_MSG_SetMemoryChannelConfig,       0),
  93         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode,                0),
  94         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh,        0),
  95         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow,         0),
  96         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,       0),
  97         MSG_MAP(SetMinDeepSleepDcefclk,         PPSMC_MSG_SetMinDeepSleepDcefclk,       0),
  98         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,        0),
  99         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,            0),
 100         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch,            0),
 101         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                  0),
 102         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,          1),
 103         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh,       0),
 104         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow,        0),
 105         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize,           0),
 106         MSG_MAP(ConfigureGfxDidt,               PPSMC_MSG_ConfigureGfxDidt,             0),
 107         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_NumOfDisplays,                0),
 108         MSG_MAP(SetSystemVirtualDramAddrHigh,   PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
 109         MSG_MAP(SetSystemVirtualDramAddrLow,    PPSMC_MSG_SetSystemVirtualDramAddrLow,  0),
 110         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                  0),
 111         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,               0),
 112         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                  0),
 113         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,          1),
 114         MSG_MAP(GetDebugData,                   PPSMC_MSG_GetDebugData,                 0),
 115         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                     0),
 116         MSG_MAP(PrepareMp1ForReset,             PPSMC_MSG_PrepareMp1ForReset,           0),
 117         MSG_MAP(PrepareMp1ForShutdown,          PPSMC_MSG_PrepareMp1ForShutdown,        0),
 118         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                   0),
 119         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                 0),
 120         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                  0),
 121         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,                0),
 122         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME,               0),
 123         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3,                        0),
 124         MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE,PPSMC_MSG_DALDisableDummyPstateChange,  0),
 125         MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange,   0),
 126         MSG_MAP(GetVoltageByDpm,                PPSMC_MSG_GetVoltageByDpm,              0),
 127         MSG_MAP(GetVoltageByDpmOverdrive,       PPSMC_MSG_GetVoltageByDpmOverdrive,     0),
 128 };
 129
 130 static struct smu_11_0_cmn2aisc_mapping navi10_clk_map[SMU_CLK_COUNT] = {
 131         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 132         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 133         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 134         CLK_MAP(FCLK, PPCLK_SOCCLK),
 135         CLK_MAP(UCLK, PPCLK_UCLK),
 136         CLK_MAP(MCLK, PPCLK_UCLK),
 137         CLK_MAP(DCLK, PPCLK_DCLK),
 138         CLK_MAP(VCLK, PPCLK_VCLK),
 139         CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
 140         CLK_MAP(DISPCLK, PPCLK_DISPCLK),
 141         CLK_MAP(PIXCLK, PPCLK_PIXCLK),
 142         CLK_MAP(PHYCLK, PPCLK_PHYCLK),
 143 };
 144
 145 static struct smu_11_0_cmn2aisc_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
 146         FEA_MAP(DPM_PREFETCHER),
 147         FEA_MAP(DPM_GFXCLK),
 148         FEA_MAP(DPM_GFX_PACE),
 149         FEA_MAP(DPM_UCLK),
 150         FEA_MAP(DPM_SOCCLK),
 151         FEA_MAP(DPM_MP0CLK),
 152         FEA_MAP(DPM_LINK),
 153         FEA_MAP(DPM_DCEFCLK),
 154         FEA_MAP(MEM_VDDCI_SCALING),
 155         FEA_MAP(MEM_MVDD_SCALING),
 156         FEA_MAP(DS_GFXCLK),
 157         FEA_MAP(DS_SOCCLK),
 158         FEA_MAP(DS_LCLK),
 159         FEA_MAP(DS_DCEFCLK),
 160         FEA_MAP(DS_UCLK),
 161         FEA_MAP(GFX_ULV),
 162         FEA_MAP(FW_DSTATE),
 163         FEA_MAP(GFXOFF),
 164         FEA_MAP(BACO),
 165         FEA_MAP(VCN_PG),
 166         FEA_MAP(JPEG_PG),
 167         FEA_MAP(USB_PG),
 168         FEA_MAP(RSMU_SMN_CG),
 169         FEA_MAP(PPT),
 170         FEA_MAP(TDC),
 171         FEA_MAP(GFX_EDC),
 172         FEA_MAP(APCC_PLUS),
 173         FEA_MAP(GTHR),
 174         FEA_MAP(ACDC),
 175         FEA_MAP(VR0HOT),
 176         FEA_MAP(VR1HOT),
 177         FEA_MAP(FW_CTF),
 178         FEA_MAP(FAN_CONTROL),
 179         FEA_MAP(THERMAL),
 180         FEA_MAP(GFX_DCS),
 181         FEA_MAP(RM),
 182         FEA_MAP(LED_DISPLAY),
 183         FEA_MAP(GFX_SS),
 184         FEA_MAP(OUT_OF_BAND_MONITOR),
 185         FEA_MAP(TEMP_DEPENDENT_VMIN),
 186         FEA_MAP(MMHUB_PG),
 187         FEA_MAP(ATHUB_PG),
 188         FEA_MAP(APCC_DFLL),
 189 };
 190
 191 static struct smu_11_0_cmn2aisc_mapping navi10_table_map[SMU_TABLE_COUNT] = {
 192         TAB_MAP(PPTABLE),
 193         TAB_MAP(WATERMARKS),
 194         TAB_MAP(AVFS),
 195         TAB_MAP(AVFS_PSM_DEBUG),
 196         TAB_MAP(AVFS_FUSE_OVERRIDE),
 197         TAB_MAP(PMSTATUSLOG),
 198         TAB_MAP(SMU_METRICS),
 199         TAB_MAP(DRIVER_SMU_CONFIG),
 200         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 201         TAB_MAP(OVERDRIVE),
 202         TAB_MAP(I2C_COMMANDS),
 203         TAB_MAP(PACE),
 204 };
 205
 206 static struct smu_11_0_cmn2aisc_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 207         PWR_MAP(AC),
 208         PWR_MAP(DC),
 209 };
 210
 211 static struct smu_11_0_cmn2aisc_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 212         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 213         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 214         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 215         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 216         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 217         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 218         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 219 };
 220
 221 static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 222 {
 223         struct smu_11_0_msg_mapping mapping;
 224
 225         if (index >= SMU_MSG_MAX_COUNT)
 226                 return -EINVAL;
 227
 228         mapping = navi10_message_map[index];
 229         if (!(mapping.valid_mapping)) {
 230                 return -EINVAL;
 231         }
 232
 233         if (amdgpu_sriov_vf(smc->adev) && !mapping.valid_in_vf)
 234                 return -EACCES;
 235
 236         return mapping.map_to;
 237 }
 238
 239 static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 240 {
 241         struct smu_11_0_cmn2aisc_mapping mapping;
 242
 243         if (index >= SMU_CLK_COUNT)
 244                 return -EINVAL;
 245
 246         mapping = navi10_clk_map[index];
 247         if (!(mapping.valid_mapping)) {
 248                 return -EINVAL;
 249         }
 250
 251         return mapping.map_to;
 252 }
 253
 254 static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 255 {
 256         struct smu_11_0_cmn2aisc_mapping mapping;
 257
 258         if (index >= SMU_FEATURE_COUNT)
 259                 return -EINVAL;
 260
 261         mapping = navi10_feature_mask_map[index];
 262         if (!(mapping.valid_mapping)) {
 263                 return -EINVAL;
 264         }
 265
 266         return mapping.map_to;
 267 }
 268
 269 static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
 270 {
 271         struct smu_11_0_cmn2aisc_mapping mapping;
 272
 273         if (index >= SMU_TABLE_COUNT)
 274                 return -EINVAL;
 275
 276         mapping = navi10_table_map[index];
 277         if (!(mapping.valid_mapping)) {
 278                 return -EINVAL;
 279         }
 280
 281         return mapping.map_to;
 282 }
 283
 284 static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 285 {
 286         struct smu_11_0_cmn2aisc_mapping mapping;
 287
 288         if (index >= SMU_POWER_SOURCE_COUNT)
 289                 return -EINVAL;
 290
 291         mapping = navi10_pwr_src_map[index];
 292         if (!(mapping.valid_mapping)) {
 293                 return -EINVAL;
 294         }
 295
 296         return mapping.map_to;
 297 }
 298
 299
 300 static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 301 {
 302         struct smu_11_0_cmn2aisc_mapping mapping;
 303
 304         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 305                 return -EINVAL;
 306
 307         mapping = navi10_workload_map[profile];
 308         if (!(mapping.valid_mapping)) {
 309                 return -EINVAL;
 310         }
 311
 312         return mapping.map_to;
 313 }
 314
 315 static bool is_asic_secure(struct smu_context *smu)
 316 {
 317         struct amdgpu_device *adev = smu->adev;
 318         bool is_secure = true;
 319         uint32_t mp0_fw_intf;
 320
 321         mp0_fw_intf = RREG32_PCIE(MP0_Public |
 322                                    (smnMP0_FW_INTF & 0xffffffff));
 323
 324         if (!(mp0_fw_intf & (1 << 19)))
 325                 is_secure = false;
 326
 327         return is_secure;
 328 }
 329
 330 static int
 331 navi10_get_allowed_feature_mask(struct smu_context *smu,
 332                                   uint32_t *feature_mask, uint32_t num)
 333 {
 334         struct amdgpu_device *adev = smu->adev;
 335
 336         if (num > 2)
 337                 return -EINVAL;
 338
 339         memset(feature_mask, 0, sizeof(uint32_t) * num);
 340
 341         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 342                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 343                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 344                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 345                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 346                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 347                                 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
 348                                 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
 349                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 350                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 351                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 352                                 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
 353                                 | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
 354                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 355                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 356                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 357                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 358                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 359                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 360                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 361
 362         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 363                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 364
 365         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
 366                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 367
 368         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 369                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 370
 371         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 372                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 373
 374         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 375                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 376                                 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 377                                 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 378
 379         if (adev->pm.pp_feature & PP_ULV_MASK)
 380                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 381
 382         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 383                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 384
 385         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 386                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 387
 388         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 389                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 390
 391         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 392                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 393
 394         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
 395                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
 396
 397         if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 398                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
 399
 400         if (smu->dc_controlled_by_gpio)
 401                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
 402
 403         /* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
 404         if (is_asic_secure(smu)) {
 405                 /* only for navi10 A0 */
 406                 if ((adev->asic_type == CHIP_NAVI10) &&
 407                         (adev->rev_id == 0)) {
 408                         *(uint64_t *)feature_mask &=
 409                                         ~(FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 410                                           | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 411                                           | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT));
 412                         *(uint64_t *)feature_mask &=
 413                                         ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
 414                 }
 415         }
 416
 417         return 0;
 418 }
 419
 420 static int navi10_check_powerplay_table(struct smu_context *smu)
 421 {
 422         struct smu_table_context *table_context = &smu->smu_table;
 423         struct smu_11_0_powerplay_table *powerplay_table =
 424                 table_context->power_play_table;
 425         struct smu_baco_context *smu_baco = &smu->smu_baco;
 426
 427         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC)
 428                 smu->dc_controlled_by_gpio = true;
 429
 430         mutex_lock(&smu_baco->mutex);
 431         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 432             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 433                 smu_baco->platform_support = true;
 434         mutex_unlock(&smu_baco->mutex);
 435
 436         table_context->thermal_controller_type =
 437                 powerplay_table->thermal_controller_type;
 438
 439         /*
 440          * Instead of having its own buffer space and get overdrive_table copied,
 441          * smu->od_settings just points to the actual overdrive_table
 442          */
 443         smu->od_settings = &powerplay_table->overdrive_table;
 444
 445         return 0;
 446 }
 447
 448 static int navi10_append_powerplay_table(struct smu_context *smu)
 449 {
 450         struct amdgpu_device *adev = smu->adev;
 451         struct smu_table_context *table_context = &smu->smu_table;
 452         PPTable_t *smc_pptable = table_context->driver_pptable;
 453         struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
 454         struct atom_smc_dpm_info_v4_7 *smc_dpm_table_v4_7;
 455         int index, ret;
 456
 457         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 458                                            smc_dpm_info);
 459
 460         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 461                                       (uint8_t **)&smc_dpm_table);
 462         if (ret)
 463                 return ret;
 464
 465         pr_info("smc_dpm_info table revision(format.content): %d.%d\n",
 466                         smc_dpm_table->table_header.format_revision,
 467                         smc_dpm_table->table_header.content_revision);
 468
 469         if (smc_dpm_table->table_header.format_revision != 4) {
 470                 pr_err("smc_dpm_info table format revision is not 4!\n");
 471                 return -EINVAL;
 472         }
 473
 474         switch (smc_dpm_table->table_header.content_revision) {
 475         case 5: /* nv10 and nv14 */
 476                 memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 477                         sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
 478                 break;
 479         case 7: /* nv12 */
 480                 ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 481                                               (uint8_t **)&smc_dpm_table_v4_7);
 482                 if (ret)
 483                         return ret;
 484                 memcpy(smc_pptable->I2cControllers, smc_dpm_table_v4_7->I2cControllers,
 485                         sizeof(*smc_dpm_table_v4_7) - sizeof(smc_dpm_table_v4_7->table_header));
 486                 break;
 487         default:
 488                 pr_err("smc_dpm_info with unsupported content revision %d!\n",
 489                                 smc_dpm_table->table_header.content_revision);
 490                 return -EINVAL;
 491         }
 492
 493         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 494                 /* TODO: remove it once SMU fw fix it */
 495                 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
 496         }
 497
 498         return 0;
 499 }
 500
 501 static int navi10_store_powerplay_table(struct smu_context *smu)
 502 {
 503         struct smu_table_context *table_context = &smu->smu_table;
 504         struct smu_11_0_powerplay_table *powerplay_table =
 505                 table_context->power_play_table;
 506
 507         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 508                sizeof(PPTable_t));
 509
 510         return 0;
 511 }
 512
 513 static int navi10_setup_pptable(struct smu_context *smu)
 514 {
 515         int ret = 0;
 516
 517         ret = smu_v11_0_setup_pptable(smu);
 518         if (ret)
 519                 return ret;
 520
 521         ret = navi10_store_powerplay_table(smu);
 522         if (ret)
 523                 return ret;
 524
 525         ret = navi10_append_powerplay_table(smu);
 526         if (ret)
 527                 return ret;
 528
 529         ret = navi10_check_powerplay_table(smu);
 530         if (ret)
 531                 return ret;
 532
 533         return ret;
 534 }
 535
 536 static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
 537 {
 538         struct smu_table_context *smu_table = &smu->smu_table;
 539
 540         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 541                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 542         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 543                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 544         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 545                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 546         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 547                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 548         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 549                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 550         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 551                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 552                        AMDGPU_GEM_DOMAIN_VRAM);
 553
 554         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 555         if (!smu_table->metrics_table)
 556                 return -ENOMEM;
 557         smu_table->metrics_time = 0;
 558
 559         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 560         if (!smu_table->watermarks_table)
 561                 return -ENOMEM;
 562
 563         return 0;
 564 }
 565
 566 static int navi10_get_smu_metrics_data(struct smu_context *smu,
 567                                        MetricsMember_t member,
 568                                        uint32_t *value)
 569 {
 570         struct smu_table_context *smu_table= &smu->smu_table;
 571         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 572         int ret = 0;
 573
 574         mutex_lock(&smu->metrics_lock);
 575         if (!smu_table->metrics_time ||
 576              time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(1))) {
 577                 ret = smu_update_table(smu,
 578                                        SMU_TABLE_SMU_METRICS,
 579                                        0,
 580                                        smu_table->metrics_table,
 581                                        false);
 582                 if (ret) {
 583                         pr_info("Failed to export SMU metrics table!\n");
 584                         mutex_unlock(&smu->metrics_lock);
 585                         return ret;
 586                 }
 587                 smu_table->metrics_time = jiffies;
 588         }
 589
 590         switch (member) {
 591         case METRICS_CURR_GFXCLK:
 592                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 593                 break;
 594         case METRICS_CURR_SOCCLK:
 595                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 596                 break;
 597         case METRICS_CURR_UCLK:
 598                 *value = metrics->CurrClock[PPCLK_UCLK];
 599                 break;
 600         case METRICS_CURR_VCLK:
 601                 *value = metrics->CurrClock[PPCLK_VCLK];
 602                 break;
 603         case METRICS_CURR_DCLK:
 604                 *value = metrics->CurrClock[PPCLK_DCLK];
 605                 break;
 606         case METRICS_AVERAGE_GFXCLK:
 607                 *value = metrics->AverageGfxclkFrequency;
 608                 break;
 609         case METRICS_AVERAGE_SOCCLK:
 610                 *value = metrics->AverageSocclkFrequency;
 611                 break;
 612         case METRICS_AVERAGE_UCLK:
 613                 *value = metrics->AverageUclkFrequency;
 614                 break;
 615         case METRICS_AVERAGE_GFXACTIVITY:
 616                 *value = metrics->AverageGfxActivity;
 617                 break;
 618         case METRICS_AVERAGE_MEMACTIVITY:
 619                 *value = metrics->AverageUclkActivity;
 620                 break;
 621         case METRICS_AVERAGE_SOCKETPOWER:
 622                 *value = metrics->AverageSocketPower << 8;
 623                 break;
 624         case METRICS_TEMPERATURE_EDGE:
 625                 *value = metrics->TemperatureEdge *
 626                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 627                 break;
 628         case METRICS_TEMPERATURE_HOTSPOT:
 629                 *value = metrics->TemperatureHotspot *
 630                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 631                 break;
 632         case METRICS_TEMPERATURE_MEM:
 633                 *value = metrics->TemperatureMem *
 634                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 635                 break;
 636         case METRICS_TEMPERATURE_VRGFX:
 637                 *value = metrics->TemperatureVrGfx *
 638                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 639                 break;
 640         case METRICS_TEMPERATURE_VRSOC:
 641                 *value = metrics->TemperatureVrSoc *
 642                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 643                 break;
 644         case METRICS_THROTTLER_STATUS:
 645                 *value = metrics->ThrottlerStatus;
 646                 break;
 647         case METRICS_CURR_FANSPEED:
 648                 *value = metrics->CurrFanSpeed;
 649                 break;
 650         default:
 651                 *value = UINT_MAX;
 652                 break;
 653         }
 654
 655         mutex_unlock(&smu->metrics_lock);
 656
 657         return ret;
 658 }
 659
 660 static int navi10_allocate_dpm_context(struct smu_context *smu)
 661 {
 662         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 663
 664         if (smu_dpm->dpm_context)
 665                 return -EINVAL;
 666
 667         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 668                                        GFP_KERNEL);
 669         if (!smu_dpm->dpm_context)
 670                 return -ENOMEM;
 671
 672         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 673
 674         return 0;
 675 }
 676
 677 static int navi10_set_default_dpm_table(struct smu_context *smu)
 678 {
 679         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 680         struct smu_table_context *table_context = &smu->smu_table;
 681         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 682         PPTable_t *driver_ppt = NULL;
 683         int i;
 684
 685         driver_ppt = table_context->driver_pptable;
 686
 687         dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
 688         dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
 689
 690         dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
 691         dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
 692
 693         dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
 694         dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
 695
 696         dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
 697         dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
 698
 699         dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
 700         dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
 701
 702         dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
 703         dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
 704
 705         dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
 706         dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
 707
 708         dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
 709         dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
 710
 711         dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
 712         dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
 713
 714         for (i = 0; i < MAX_PCIE_CONF; i++) {
 715                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
 716                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
 717         }
 718
 719         return 0;
 720 }
 721
 722 static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
 723 {
 724         struct smu_power_context *smu_power = &smu->smu_power;
 725         struct smu_power_gate *power_gate = &smu_power->power_gate;
 726         int ret = 0;
 727
 728         if (enable) {
 729                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 730                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 731                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
 732                         if (ret)
 733                                 return ret;
 734                 }
 735                 power_gate->vcn_gated = false;
 736         } else {
 737                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 738                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
 739                         if (ret)
 740                                 return ret;
 741                 }
 742                 power_gate->vcn_gated = true;
 743         }
 744
 745         return ret;
 746 }
 747
 748 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 749 {
 750         struct smu_power_context *smu_power = &smu->smu_power;
 751         struct smu_power_gate *power_gate = &smu_power->power_gate;
 752         int ret = 0;
 753
 754         if (enable) {
 755                 if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 756                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL);
 757                         if (ret)
 758                                 return ret;
 759                 }
 760                 power_gate->jpeg_gated = false;
 761         } else {
 762                 if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 763                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL);
 764                         if (ret)
 765                                 return ret;
 766                 }
 767                 power_gate->jpeg_gated = true;
 768         }
 769
 770         return ret;
 771 }
 772
 773 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
 774                                        enum smu_clk_type clk_type,
 775                                        uint32_t *value)
 776 {
 777         MetricsMember_t member_type;
 778         int clk_id = 0;
 779
 780         clk_id = smu_clk_get_index(smu, clk_type);
 781         if (clk_id < 0)
 782                 return clk_id;
 783
 784         switch (clk_id) {
 785         case PPCLK_GFXCLK:
 786                 member_type = METRICS_CURR_GFXCLK;
 787                 break;
 788         case PPCLK_UCLK:
 789                 member_type = METRICS_CURR_UCLK;
 790                 break;
 791         case PPCLK_SOCCLK:
 792                 member_type = METRICS_CURR_SOCCLK;
 793                 break;
 794         case PPCLK_VCLK:
 795                 member_type = METRICS_CURR_VCLK;
 796                 break;
 797         case PPCLK_DCLK:
 798                 member_type = METRICS_CURR_DCLK;
 799                 break;
 800         case PPCLK_DCEFCLK:
 801                 member_type = METRICS_CURR_DCEFCLK;
 802                 break;
 803         default:
 804                 return -EINVAL;
 805         }
 806
 807         return navi10_get_smu_metrics_data(smu,
 808                                            member_type,
 809                                            value);
 810 }
 811
 812 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 813 {
 814         PPTable_t *pptable = smu->smu_table.driver_pptable;
 815         DpmDescriptor_t *dpm_desc = NULL;
 816         uint32_t clk_index = 0;
 817
 818         clk_index = smu_clk_get_index(smu, clk_type);
 819         dpm_desc = &pptable->DpmDescriptor[clk_index];
 820
 821         /* 0 - Fine grained DPM, 1 - Discrete DPM */
 822         return dpm_desc->SnapToDiscrete == 0 ? true : false;
 823 }
 824
 825 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap)
 826 {
 827         return od_table->cap[cap];
 828 }
 829
 830 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table,
 831                                         enum SMU_11_0_ODSETTING_ID setting,
 832                                         uint32_t *min, uint32_t *max)
 833 {
 834         if (min)
 835                 *min = od_table->min[setting];
 836         if (max)
 837                 *max = od_table->max[setting];
 838 }
 839
 840 static int navi10_print_clk_levels(struct smu_context *smu,
 841                         enum smu_clk_type clk_type, char *buf)
 842 {
 843         uint16_t *curve_settings;
 844         int i, size = 0, ret = 0;
 845         uint32_t cur_value = 0, value = 0, count = 0;
 846         uint32_t freq_values[3] = {0};
 847         uint32_t mark_index = 0;
 848         struct smu_table_context *table_context = &smu->smu_table;
 849         uint32_t gen_speed, lane_width;
 850         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 851         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 852         struct amdgpu_device *adev = smu->adev;
 853         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 854         OverDriveTable_t *od_table =
 855                 (OverDriveTable_t *)table_context->overdrive_table;
 856         struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
 857         uint32_t min_value, max_value;
 858
 859         switch (clk_type) {
 860         case SMU_GFXCLK:
 861         case SMU_SCLK:
 862         case SMU_SOCCLK:
 863         case SMU_MCLK:
 864         case SMU_UCLK:
 865         case SMU_FCLK:
 866         case SMU_DCEFCLK:
 867                 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
 868                 if (ret)
 869                         return size;
 870
 871                 /* 10KHz -> MHz */
 872                 cur_value = cur_value / 100;
 873
 874                 ret = smu_get_dpm_level_count(smu, clk_type, &count);
 875                 if (ret)
 876                         return size;
 877
 878                 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
 879                         for (i = 0; i < count; i++) {
 880                                 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
 881                                 if (ret)
 882                                         return size;
 883
 884                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 885                                                 cur_value == value ? "*" : "");
 886                         }
 887                 } else {
 888                         ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
 889                         if (ret)
 890                                 return size;
 891                         ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
 892                         if (ret)
 893                                 return size;
 894
 895                         freq_values[1] = cur_value;
 896                         mark_index = cur_value == freq_values[0] ? 0 :
 897                                      cur_value == freq_values[2] ? 2 : 1;
 898                         if (mark_index != 1)
 899                                 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
 900
 901                         for (i = 0; i < 3; i++) {
 902                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
 903                                                 i == mark_index ? "*" : "");
 904                         }
 905
 906                 }
 907                 break;
 908         case SMU_PCIE:
 909                 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
 910                              PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
 911                         >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
 912                 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
 913                               PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
 914                         >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
 915                 for (i = 0; i < NUM_LINK_LEVELS; i++)
 916                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
 917                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
 918                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
 919                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
 920                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
 921                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
 922                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
 923                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
 924                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
 925                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
 926                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
 927                                         pptable->LclkFreq[i],
 928                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
 929                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
 930                                         "*" : "");
 931                 break;
 932         case SMU_OD_SCLK:
 933                 if (!smu->od_enabled || !od_table || !od_settings)
 934                         break;
 935                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS))
 936                         break;
 937                 size += sprintf(buf + size, "OD_SCLK:\n");
 938                 size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
 939                 break;
 940         case SMU_OD_MCLK:
 941                 if (!smu->od_enabled || !od_table || !od_settings)
 942                         break;
 943                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX))
 944                         break;
 945                 size += sprintf(buf + size, "OD_MCLK:\n");
 946                 size += sprintf(buf + size, "1: %uMHz\n", od_table->UclkFmax);
 947                 break;
 948         case SMU_OD_VDDC_CURVE:
 949                 if (!smu->od_enabled || !od_table || !od_settings)
 950                         break;
 951                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE))
 952                         break;
 953                 size += sprintf(buf + size, "OD_VDDC_CURVE:\n");
 954                 for (i = 0; i < 3; i++) {
 955                         switch (i) {
 956                         case 0:
 957                                 curve_settings = &od_table->GfxclkFreq1;
 958                                 break;
 959                         case 1:
 960                                 curve_settings = &od_table->GfxclkFreq2;
 961                                 break;
 962                         case 2:
 963                                 curve_settings = &od_table->GfxclkFreq3;
 964                                 break;
 965                         default:
 966                                 break;
 967                         }
 968                         size += sprintf(buf + size, "%d: %uMHz @ %umV\n", i, curve_settings[0], curve_settings[1] / NAVI10_VOLTAGE_SCALE);
 969                 }
 970                 break;
 971         case SMU_OD_RANGE:
 972                 if (!smu->od_enabled || !od_table || !od_settings)
 973                         break;
 974                 size = sprintf(buf, "%s:\n", "OD_RANGE");
 975
 976                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
 977                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
 978                                                     &min_value, NULL);
 979                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
 980                                                     NULL, &max_value);
 981                         size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
 982                                         min_value, max_value);
 983                 }
 984
 985                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
 986                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
 987                                                     &min_value, &max_value);
 988                         size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
 989                                         min_value, max_value);
 990                 }
 991
 992                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
 993                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
 994                                                     &min_value, &max_value);
 995                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
 996                                         min_value, max_value);
 997                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
 998                                                     &min_value, &max_value);
 999                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1000                                         min_value, max_value);
1001                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
1002                                                     &min_value, &max_value);
1003                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1004                                         min_value, max_value);
1005                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
1006                                                     &min_value, &max_value);
1007                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1008                                         min_value, max_value);
1009                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
1010                                                     &min_value, &max_value);
1011                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1012                                         min_value, max_value);
1013                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
1014                                                     &min_value, &max_value);
1015                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1016                                         min_value, max_value);
1017                 }
1018
1019                 break;
1020         default:
1021                 break;
1022         }
1023
1024         return size;
1025 }
1026
1027 static int navi10_force_clk_levels(struct smu_context *smu,
1028                                    enum smu_clk_type clk_type, uint32_t mask)
1029 {
1030
1031         int ret = 0, size = 0;
1032         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1033
1034         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1035         soft_max_level = mask ? (fls(mask) - 1) : 0;
1036
1037         switch (clk_type) {
1038         case SMU_GFXCLK:
1039         case SMU_SCLK:
1040         case SMU_SOCCLK:
1041         case SMU_MCLK:
1042         case SMU_UCLK:
1043         case SMU_DCEFCLK:
1044         case SMU_FCLK:
1045                 /* There is only 2 levels for fine grained DPM */
1046                 if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1047                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1048                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1049                 }
1050
1051                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1052                 if (ret)
1053                         return size;
1054
1055                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1056                 if (ret)
1057                         return size;
1058
1059                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
1060                 if (ret)
1061                         return size;
1062                 break;
1063         default:
1064                 break;
1065         }
1066
1067         return size;
1068 }
1069
1070 static int navi10_populate_umd_state_clk(struct smu_context *smu)
1071 {
1072         int ret = 0;
1073         uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
1074
1075         ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
1076         if (ret)
1077                 return ret;
1078
1079         smu->pstate_sclk = min_sclk_freq * 100;
1080
1081         ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
1082         if (ret)
1083                 return ret;
1084
1085         smu->pstate_mclk = min_mclk_freq * 100;
1086
1087         return ret;
1088 }
1089
1090 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
1091                                                  enum smu_clk_type clk_type,
1092                                                  struct pp_clock_levels_with_latency *clocks)
1093 {
1094         int ret = 0, i = 0;
1095         uint32_t level_count = 0, freq = 0;
1096
1097         switch (clk_type) {
1098         case SMU_GFXCLK:
1099         case SMU_DCEFCLK:
1100         case SMU_SOCCLK:
1101         case SMU_MCLK:
1102         case SMU_UCLK:
1103                 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
1104                 if (ret)
1105                         return ret;
1106
1107                 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
1108                 clocks->num_levels = level_count;
1109
1110                 for (i = 0; i < level_count; i++) {
1111                         ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
1112                         if (ret)
1113                                 return ret;
1114
1115                         clocks->data[i].clocks_in_khz = freq * 1000;
1116                         clocks->data[i].latency_in_us = 0;
1117                 }
1118                 break;
1119         default:
1120                 break;
1121         }
1122
1123         return ret;
1124 }
1125
1126 static int navi10_pre_display_config_changed(struct smu_context *smu)
1127 {
1128         int ret = 0;
1129         uint32_t max_freq = 0;
1130
1131         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1132         if (ret)
1133                 return ret;
1134
1135         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1136                 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
1137                 if (ret)
1138                         return ret;
1139                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
1140                 if (ret)
1141                         return ret;
1142         }
1143
1144         return ret;
1145 }
1146
1147 static int navi10_display_config_changed(struct smu_context *smu)
1148 {
1149         int ret = 0;
1150
1151         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1152             smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1153             smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1154                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1155                                                   smu->display_config->num_display,
1156                                                   NULL);
1157                 if (ret)
1158                         return ret;
1159         }
1160
1161         return ret;
1162 }
1163
1164 static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
1165 {
1166         int ret = 0, i = 0;
1167         uint32_t min_freq, max_freq, force_freq;
1168         enum smu_clk_type clk_type;
1169
1170         enum smu_clk_type clks[] = {
1171                 SMU_GFXCLK,
1172                 SMU_MCLK,
1173                 SMU_SOCCLK,
1174         };
1175
1176         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1177                 clk_type = clks[i];
1178                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
1179                 if (ret)
1180                         return ret;
1181
1182                 force_freq = highest ? max_freq : min_freq;
1183                 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq, false);
1184                 if (ret)
1185                         return ret;
1186         }
1187
1188         return ret;
1189 }
1190
1191 static int navi10_unforce_dpm_levels(struct smu_context *smu)
1192 {
1193         int ret = 0, i = 0;
1194         uint32_t min_freq, max_freq;
1195         enum smu_clk_type clk_type;
1196
1197         enum smu_clk_type clks[] = {
1198                 SMU_GFXCLK,
1199                 SMU_MCLK,
1200                 SMU_SOCCLK,
1201         };
1202
1203         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1204                 clk_type = clks[i];
1205                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
1206                 if (ret)
1207                         return ret;
1208
1209                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
1210                 if (ret)
1211                         return ret;
1212         }
1213
1214         return ret;
1215 }
1216
1217 static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
1218 {
1219         if (!value)
1220                 return -EINVAL;
1221
1222         return navi10_get_smu_metrics_data(smu,
1223                                            METRICS_AVERAGE_SOCKETPOWER,
1224                                            value);
1225 }
1226
1227 static int navi10_get_current_activity_percent(struct smu_context *smu,
1228                                                enum amd_pp_sensors sensor,
1229                                                uint32_t *value)
1230 {
1231         int ret = 0;
1232
1233         if (!value)
1234                 return -EINVAL;
1235
1236         switch (sensor) {
1237         case AMDGPU_PP_SENSOR_GPU_LOAD:
1238                 ret = navi10_get_smu_metrics_data(smu,
1239                                                   METRICS_AVERAGE_GFXACTIVITY,
1240                                                   value);
1241                 break;
1242         case AMDGPU_PP_SENSOR_MEM_LOAD:
1243                 ret = navi10_get_smu_metrics_data(smu,
1244                                                   METRICS_AVERAGE_MEMACTIVITY,
1245                                                   value);
1246                 break;
1247         default:
1248                 pr_err("Invalid sensor for retrieving clock activity\n");
1249                 return -EINVAL;
1250         }
1251
1252         return ret;
1253 }
1254
1255 static bool navi10_is_dpm_running(struct smu_context *smu)
1256 {
1257         int ret = 0;
1258         uint32_t feature_mask[2];
1259         unsigned long feature_enabled;
1260         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1261         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1262                            ((uint64_t)feature_mask[1] << 32));
1263         return !!(feature_enabled & SMC_DPM_FEATURE);
1264 }
1265
1266 static int navi10_get_fan_speed_rpm(struct smu_context *smu,
1267                                     uint32_t *speed)
1268 {
1269         if (!speed)
1270                 return -EINVAL;
1271
1272         return navi10_get_smu_metrics_data(smu,
1273                                            METRICS_CURR_FANSPEED,
1274                                            speed);
1275 }
1276
1277 static int navi10_get_fan_speed_percent(struct smu_context *smu,
1278                                         uint32_t *speed)
1279 {
1280         int ret = 0;
1281         uint32_t percent = 0;
1282         uint32_t current_rpm;
1283         PPTable_t *pptable = smu->smu_table.driver_pptable;
1284
1285         ret = navi10_get_fan_speed_rpm(smu, &current_rpm);
1286         if (ret)
1287                 return ret;
1288
1289         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1290         *speed = percent > 100 ? 100 : percent;
1291
1292         return ret;
1293 }
1294
1295 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1296 {
1297         DpmActivityMonitorCoeffInt_t activity_monitor;
1298         uint32_t i, size = 0;
1299         int16_t workload_type = 0;
1300         static const char *profile_name[] = {
1301                                         "BOOTUP_DEFAULT",
1302                                         "3D_FULL_SCREEN",
1303                                         "POWER_SAVING",
1304                                         "VIDEO",
1305                                         "VR",
1306                                         "COMPUTE",
1307                                         "CUSTOM"};
1308         static const char *title[] = {
1309                         "PROFILE_INDEX(NAME)",
1310                         "CLOCK_TYPE(NAME)",
1311                         "FPS",
1312                         "MinFreqType",
1313                         "MinActiveFreqType",
1314                         "MinActiveFreq",
1315                         "BoosterFreqType",
1316                         "BoosterFreq",
1317                         "PD_Data_limit_c",
1318                         "PD_Data_error_coeff",
1319                         "PD_Data_error_rate_coeff"};
1320         int result = 0;
1321
1322         if (!buf)
1323                 return -EINVAL;
1324
1325         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1326                         title[0], title[1], title[2], title[3], title[4], title[5],
1327                         title[6], title[7], title[8], title[9], title[10]);
1328
1329         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1330                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1331                 workload_type = smu_workload_get_type(smu, i);
1332                 if (workload_type < 0)
1333                         return -EINVAL;
1334
1335                 result = smu_update_table(smu,
1336                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1337                                           (void *)(&activity_monitor), false);
1338                 if (result) {
1339                         pr_err("[%s] Failed to get activity monitor!", __func__);
1340                         return result;
1341                 }
1342
1343                 size += sprintf(buf + size, "%2d %14s%s:\n",
1344                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1345
1346                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1347                         " ",
1348                         0,
1349                         "GFXCLK",
1350                         activity_monitor.Gfx_FPS,
1351                         activity_monitor.Gfx_MinFreqStep,
1352                         activity_monitor.Gfx_MinActiveFreqType,
1353                         activity_monitor.Gfx_MinActiveFreq,
1354                         activity_monitor.Gfx_BoosterFreqType,
1355                         activity_monitor.Gfx_BoosterFreq,
1356                         activity_monitor.Gfx_PD_Data_limit_c,
1357                         activity_monitor.Gfx_PD_Data_error_coeff,
1358                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1359
1360                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1361                         " ",
1362                         1,
1363                         "SOCCLK",
1364                         activity_monitor.Soc_FPS,
1365                         activity_monitor.Soc_MinFreqStep,
1366                         activity_monitor.Soc_MinActiveFreqType,
1367                         activity_monitor.Soc_MinActiveFreq,
1368                         activity_monitor.Soc_BoosterFreqType,
1369                         activity_monitor.Soc_BoosterFreq,
1370                         activity_monitor.Soc_PD_Data_limit_c,
1371                         activity_monitor.Soc_PD_Data_error_coeff,
1372                         activity_monitor.Soc_PD_Data_error_rate_coeff);
1373
1374                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1375                         " ",
1376                         2,
1377                         "MEMLK",
1378                         activity_monitor.Mem_FPS,
1379                         activity_monitor.Mem_MinFreqStep,
1380                         activity_monitor.Mem_MinActiveFreqType,
1381                         activity_monitor.Mem_MinActiveFreq,
1382                         activity_monitor.Mem_BoosterFreqType,
1383                         activity_monitor.Mem_BoosterFreq,
1384                         activity_monitor.Mem_PD_Data_limit_c,
1385                         activity_monitor.Mem_PD_Data_error_coeff,
1386                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1387         }
1388
1389         return size;
1390 }
1391
1392 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1393 {
1394         DpmActivityMonitorCoeffInt_t activity_monitor;
1395         int workload_type, ret = 0;
1396
1397         smu->power_profile_mode = input[size];
1398
1399         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1400                 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1401                 return -EINVAL;
1402         }
1403
1404         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1405
1406                 ret = smu_update_table(smu,
1407                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1408                                        (void *)(&activity_monitor), false);
1409                 if (ret) {
1410                         pr_err("[%s] Failed to get activity monitor!", __func__);
1411                         return ret;
1412                 }
1413
1414                 switch (input[0]) {
1415                 case 0: /* Gfxclk */
1416                         activity_monitor.Gfx_FPS = input[1];
1417                         activity_monitor.Gfx_MinFreqStep = input[2];
1418                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1419                         activity_monitor.Gfx_MinActiveFreq = input[4];
1420                         activity_monitor.Gfx_BoosterFreqType = input[5];
1421                         activity_monitor.Gfx_BoosterFreq = input[6];
1422                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1423                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1424                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1425                         break;
1426                 case 1: /* Socclk */
1427                         activity_monitor.Soc_FPS = input[1];
1428                         activity_monitor.Soc_MinFreqStep = input[2];
1429                         activity_monitor.Soc_MinActiveFreqType = input[3];
1430                         activity_monitor.Soc_MinActiveFreq = input[4];
1431                         activity_monitor.Soc_BoosterFreqType = input[5];
1432                         activity_monitor.Soc_BoosterFreq = input[6];
1433                         activity_monitor.Soc_PD_Data_limit_c = input[7];
1434                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
1435                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1436                         break;
1437                 case 2: /* Memlk */
1438                         activity_monitor.Mem_FPS = input[1];
1439                         activity_monitor.Mem_MinFreqStep = input[2];
1440                         activity_monitor.Mem_MinActiveFreqType = input[3];
1441                         activity_monitor.Mem_MinActiveFreq = input[4];
1442                         activity_monitor.Mem_BoosterFreqType = input[5];
1443                         activity_monitor.Mem_BoosterFreq = input[6];
1444                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1445                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1446                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1447                         break;
1448                 }
1449
1450                 ret = smu_update_table(smu,
1451                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1452                                        (void *)(&activity_monitor), true);
1453                 if (ret) {
1454                         pr_err("[%s] Failed to set activity monitor!", __func__);
1455                         return ret;
1456                 }
1457         }
1458
1459         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1460         workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1461         if (workload_type < 0)
1462                 return -EINVAL;
1463         smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1464                                     1 << workload_type, NULL);
1465
1466         return ret;
1467 }
1468
1469 static int navi10_get_profiling_clk_mask(struct smu_context *smu,
1470                                          enum amd_dpm_forced_level level,
1471                                          uint32_t *sclk_mask,
1472                                          uint32_t *mclk_mask,
1473                                          uint32_t *soc_mask)
1474 {
1475         int ret = 0;
1476         uint32_t level_count = 0;
1477
1478         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1479                 if (sclk_mask)
1480                         *sclk_mask = 0;
1481         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1482                 if (mclk_mask)
1483                         *mclk_mask = 0;
1484         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1485                 if(sclk_mask) {
1486                         ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1487                         if (ret)
1488                                 return ret;
1489                         *sclk_mask = level_count - 1;
1490                 }
1491
1492                 if(mclk_mask) {
1493                         ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1494                         if (ret)
1495                                 return ret;
1496                         *mclk_mask = level_count - 1;
1497                 }
1498
1499                 if(soc_mask) {
1500                         ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1501                         if (ret)
1502                                 return ret;
1503                         *soc_mask = level_count - 1;
1504                 }
1505         }
1506
1507         return ret;
1508 }
1509
1510 static int navi10_notify_smc_display_config(struct smu_context *smu)
1511 {
1512         struct smu_clocks min_clocks = {0};
1513         struct pp_display_clock_request clock_req;
1514         int ret = 0;
1515
1516         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1517         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1518         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1519
1520         if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1521                 clock_req.clock_type = amd_pp_dcef_clock;
1522                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1523
1524                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1525                 if (!ret) {
1526                         if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1527                                 ret = smu_send_smc_msg_with_param(smu,
1528                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1529                                                                   min_clocks.dcef_clock_in_sr/100,
1530                                                                   NULL);
1531                                 if (ret) {
1532                                         pr_err("Attempt to set divider for DCEFCLK Failed!");
1533                                         return ret;
1534                                 }
1535                         }
1536                 } else {
1537                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1538                 }
1539         }
1540
1541         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1542                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1543                 if (ret) {
1544                         pr_err("[%s] Set hard min uclk failed!", __func__);
1545                         return ret;
1546                 }
1547         }
1548
1549         return 0;
1550 }
1551
1552 static int navi10_set_watermarks_table(struct smu_context *smu,
1553                                        void *watermarks, struct
1554                                        dm_pp_wm_sets_with_clock_ranges_soc15
1555                                        *clock_ranges)
1556 {
1557         int i;
1558         int ret = 0;
1559         Watermarks_t *table = watermarks;
1560
1561         if (!table || !clock_ranges)
1562                 return -EINVAL;
1563
1564         if (clock_ranges->num_wm_dmif_sets > 4 ||
1565             clock_ranges->num_wm_mcif_sets > 4)
1566                 return -EINVAL;
1567
1568         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1569                 table->WatermarkRow[1][i].MinClock =
1570                         cpu_to_le16((uint16_t)
1571                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1572                         1000));
1573                 table->WatermarkRow[1][i].MaxClock =
1574                         cpu_to_le16((uint16_t)
1575                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1576                         1000));
1577                 table->WatermarkRow[1][i].MinUclk =
1578                         cpu_to_le16((uint16_t)
1579                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1580                         1000));
1581                 table->WatermarkRow[1][i].MaxUclk =
1582                         cpu_to_le16((uint16_t)
1583                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1584                         1000));
1585                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1586                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1587         }
1588
1589         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1590                 table->WatermarkRow[0][i].MinClock =
1591                         cpu_to_le16((uint16_t)
1592                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1593                         1000));
1594                 table->WatermarkRow[0][i].MaxClock =
1595                         cpu_to_le16((uint16_t)
1596                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1597                         1000));
1598                 table->WatermarkRow[0][i].MinUclk =
1599                         cpu_to_le16((uint16_t)
1600                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1601                         1000));
1602                 table->WatermarkRow[0][i].MaxUclk =
1603                         cpu_to_le16((uint16_t)
1604                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1605                         1000));
1606                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1607                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1608         }
1609
1610         smu->watermarks_bitmap |= WATERMARKS_EXIST;
1611
1612         /* pass data to smu controller */
1613         if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1614                 ret = smu_write_watermarks_table(smu);
1615                 if (ret) {
1616                         pr_err("Failed to update WMTABLE!");
1617                         return ret;
1618                 }
1619                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1620         }
1621
1622         return 0;
1623 }
1624
1625 static int navi10_thermal_get_temperature(struct smu_context *smu,
1626                                              enum amd_pp_sensors sensor,
1627                                              uint32_t *value)
1628 {
1629         int ret = 0;
1630
1631         if (!value)
1632                 return -EINVAL;
1633
1634         switch (sensor) {
1635         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1636                 ret = navi10_get_smu_metrics_data(smu,
1637                                                   METRICS_TEMPERATURE_HOTSPOT,
1638                                                   value);
1639                 break;
1640         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1641                 ret = navi10_get_smu_metrics_data(smu,
1642                                                   METRICS_TEMPERATURE_EDGE,
1643                                                   value);
1644                 break;
1645         case AMDGPU_PP_SENSOR_MEM_TEMP:
1646                 ret = navi10_get_smu_metrics_data(smu,
1647                                                   METRICS_TEMPERATURE_MEM,
1648                                                   value);
1649                 break;
1650         default:
1651                 pr_err("Invalid sensor for retrieving temp\n");
1652                 return -EINVAL;
1653         }
1654
1655         return ret;
1656 }
1657
1658 static int navi10_read_sensor(struct smu_context *smu,
1659                                  enum amd_pp_sensors sensor,
1660                                  void *data, uint32_t *size)
1661 {
1662         int ret = 0;
1663         struct smu_table_context *table_context = &smu->smu_table;
1664         PPTable_t *pptable = table_context->driver_pptable;
1665
1666         if(!data || !size)
1667                 return -EINVAL;
1668
1669         mutex_lock(&smu->sensor_lock);
1670         switch (sensor) {
1671         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1672                 *(uint32_t *)data = pptable->FanMaximumRpm;
1673                 *size = 4;
1674                 break;
1675         case AMDGPU_PP_SENSOR_MEM_LOAD:
1676         case AMDGPU_PP_SENSOR_GPU_LOAD:
1677                 ret = navi10_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1678                 *size = 4;
1679                 break;
1680         case AMDGPU_PP_SENSOR_GPU_POWER:
1681                 ret = navi10_get_gpu_power(smu, (uint32_t *)data);
1682                 *size = 4;
1683                 break;
1684         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1685         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1686         case AMDGPU_PP_SENSOR_MEM_TEMP:
1687                 ret = navi10_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1688                 *size = 4;
1689                 break;
1690         default:
1691                 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1692         }
1693         mutex_unlock(&smu->sensor_lock);
1694
1695         return ret;
1696 }
1697
1698 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1699 {
1700         uint32_t num_discrete_levels = 0;
1701         uint16_t *dpm_levels = NULL;
1702         uint16_t i = 0;
1703         struct smu_table_context *table_context = &smu->smu_table;
1704         PPTable_t *driver_ppt = NULL;
1705
1706         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1707                 return -EINVAL;
1708
1709         driver_ppt = table_context->driver_pptable;
1710         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1711         dpm_levels = driver_ppt->FreqTableUclk;
1712
1713         if (num_discrete_levels == 0 || dpm_levels == NULL)
1714                 return -EINVAL;
1715
1716         *num_states = num_discrete_levels;
1717         for (i = 0; i < num_discrete_levels; i++) {
1718                 /* convert to khz */
1719                 *clocks_in_khz = (*dpm_levels) * 1000;
1720                 clocks_in_khz++;
1721                 dpm_levels++;
1722         }
1723
1724         return 0;
1725 }
1726
1727 static int navi10_set_performance_level(struct smu_context *smu,
1728                                         enum amd_dpm_forced_level level);
1729
1730 static int navi10_set_standard_performance_level(struct smu_context *smu)
1731 {
1732         struct amdgpu_device *adev = smu->adev;
1733         int ret = 0;
1734         uint32_t sclk_freq = 0, uclk_freq = 0;
1735
1736         switch (adev->asic_type) {
1737         case CHIP_NAVI10:
1738                 sclk_freq = NAVI10_UMD_PSTATE_PROFILING_GFXCLK;
1739                 uclk_freq = NAVI10_UMD_PSTATE_PROFILING_MEMCLK;
1740                 break;
1741         case CHIP_NAVI14:
1742                 sclk_freq = NAVI14_UMD_PSTATE_PROFILING_GFXCLK;
1743                 uclk_freq = NAVI14_UMD_PSTATE_PROFILING_MEMCLK;
1744                 break;
1745         default:
1746                 /* by default, this is same as auto performance level */
1747                 return navi10_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
1748         }
1749
1750         ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
1751         if (ret)
1752                 return ret;
1753         ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
1754         if (ret)
1755                 return ret;
1756
1757         return ret;
1758 }
1759
1760 static int navi10_set_peak_performance_level(struct smu_context *smu)
1761 {
1762         struct amdgpu_device *adev = smu->adev;
1763         int ret = 0;
1764         uint32_t sclk_freq = 0, uclk_freq = 0;
1765
1766         switch (adev->asic_type) {
1767         case CHIP_NAVI10:
1768                 switch (adev->pdev->revision) {
1769                 case 0xf0: /* XTX */
1770                 case 0xc0:
1771                         sclk_freq = NAVI10_PEAK_SCLK_XTX;
1772                         break;
1773                 case 0xf1: /* XT */
1774                 case 0xc1:
1775                         sclk_freq = NAVI10_PEAK_SCLK_XT;
1776                         break;
1777                 default: /* XL */
1778                         sclk_freq = NAVI10_PEAK_SCLK_XL;
1779                         break;
1780                 }
1781                 break;
1782         case CHIP_NAVI14:
1783                 switch (adev->pdev->revision) {
1784                 case 0xc7: /* XT */
1785                 case 0xf4:
1786                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
1787                         break;
1788                 case 0xc1: /* XTM */
1789                 case 0xf2:
1790                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
1791                         break;
1792                 case 0xc3: /* XLM */
1793                 case 0xf3:
1794                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1795                         break;
1796                 case 0xc5: /* XTX */
1797                 case 0xf6:
1798                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1799                         break;
1800                 default: /* XL */
1801                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
1802                         break;
1803                 }
1804                 break;
1805         case CHIP_NAVI12:
1806                 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
1807                 break;
1808         default:
1809                 ret = smu_get_dpm_level_range(smu, SMU_SCLK, NULL, &sclk_freq);
1810                 if (ret)
1811                         return ret;
1812         }
1813
1814         ret = smu_get_dpm_level_range(smu, SMU_UCLK, NULL, &uclk_freq);
1815         if (ret)
1816                 return ret;
1817
1818         ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
1819         if (ret)
1820                 return ret;
1821         ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
1822         if (ret)
1823                 return ret;
1824
1825         return ret;
1826 }
1827
1828 static int navi10_set_performance_level(struct smu_context *smu,
1829                                         enum amd_dpm_forced_level level)
1830 {
1831         int ret = 0;
1832         uint32_t sclk_mask, mclk_mask, soc_mask;
1833
1834         switch (level) {
1835         case AMD_DPM_FORCED_LEVEL_HIGH:
1836                 ret = smu_force_dpm_limit_value(smu, true);
1837                 break;
1838         case AMD_DPM_FORCED_LEVEL_LOW:
1839                 ret = smu_force_dpm_limit_value(smu, false);
1840                 break;
1841         case AMD_DPM_FORCED_LEVEL_AUTO:
1842                 ret = smu_unforce_dpm_levels(smu);
1843                 break;
1844         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1845                 ret = navi10_set_standard_performance_level(smu);
1846                 break;
1847         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1848         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1849                 ret = smu_get_profiling_clk_mask(smu, level,
1850                                                  &sclk_mask,
1851                                                  &mclk_mask,
1852                                                  &soc_mask);
1853                 if (ret)
1854                         return ret;
1855                 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1856                 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1857                 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1858                 break;
1859         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1860                 ret = navi10_set_peak_performance_level(smu);
1861                 break;
1862         case AMD_DPM_FORCED_LEVEL_MANUAL:
1863         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1864         default:
1865                 break;
1866         }
1867         return ret;
1868 }
1869
1870 static int navi10_get_thermal_temperature_range(struct smu_context *smu,
1871                                                 struct smu_temperature_range *range)
1872 {
1873         struct smu_table_context *table_context = &smu->smu_table;
1874         struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1875
1876         if (!range || !powerplay_table)
1877                 return -EINVAL;
1878
1879         range->max = powerplay_table->software_shutdown_temp *
1880                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1881
1882         return 0;
1883 }
1884
1885 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
1886                                                 bool disable_memory_clock_switch)
1887 {
1888         int ret = 0;
1889         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1890                 (struct smu_11_0_max_sustainable_clocks *)
1891                         smu->smu_table.max_sustainable_clocks;
1892         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1893         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1894
1895         if(smu->disable_uclk_switch == disable_memory_clock_switch)
1896                 return 0;
1897
1898         if(disable_memory_clock_switch)
1899                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
1900         else
1901                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
1902
1903         if(!ret)
1904                 smu->disable_uclk_switch = disable_memory_clock_switch;
1905
1906         return ret;
1907 }
1908
1909 static uint32_t navi10_get_pptable_power_limit(struct smu_context *smu)
1910 {
1911         PPTable_t *pptable = smu->smu_table.driver_pptable;
1912         return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1913 }
1914
1915 static int navi10_get_power_limit(struct smu_context *smu,
1916                                      uint32_t *limit,
1917                                      bool cap)
1918 {
1919         PPTable_t *pptable = smu->smu_table.driver_pptable;
1920         uint32_t asic_default_power_limit = 0;
1921         int ret = 0;
1922         int power_src;
1923
1924         if (!smu->power_limit) {
1925                 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1926                         power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1927                         if (power_src < 0)
1928                                 return -EINVAL;
1929
1930                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1931                                 power_src << 16, &asic_default_power_limit);
1932                         if (ret) {
1933                                 pr_err("[%s] get PPT limit failed!", __func__);
1934                                 return ret;
1935                         }
1936                 } else {
1937                         /* the last hope to figure out the ppt limit */
1938                         if (!pptable) {
1939                                 pr_err("Cannot get PPT limit due to pptable missing!");
1940                                 return -EINVAL;
1941                         }
1942                         asic_default_power_limit =
1943                                 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1944                 }
1945
1946                 smu->power_limit = asic_default_power_limit;
1947         }
1948
1949         if (cap)
1950                 *limit = smu_get_max_power_limit(smu);
1951         else
1952                 *limit = smu->power_limit;
1953
1954         return 0;
1955 }
1956
1957 static int navi10_update_pcie_parameters(struct smu_context *smu,
1958                                      uint32_t pcie_gen_cap,
1959                                      uint32_t pcie_width_cap)
1960 {
1961         PPTable_t *pptable = smu->smu_table.driver_pptable;
1962         int ret, i;
1963         uint32_t smu_pcie_arg;
1964
1965         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1966         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1967
1968         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1969                 smu_pcie_arg = (i << 16) |
1970                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
1971                                 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1972                                         pptable->PcieLaneCount[i] : pcie_width_cap);
1973                 ret = smu_send_smc_msg_with_param(smu,
1974                                           SMU_MSG_OverridePcieParameters,
1975                                           smu_pcie_arg,
1976                                           NULL);
1977
1978                 if (ret)
1979                         return ret;
1980
1981                 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1982                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1983                 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1984                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1985         }
1986
1987         return 0;
1988 }
1989
1990 static inline void navi10_dump_od_table(OverDriveTable_t *od_table) {
1991         pr_debug("OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1992         pr_debug("OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
1993         pr_debug("OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
1994         pr_debug("OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
1995         pr_debug("OD: UclkFmax: %d\n", od_table->UclkFmax);
1996         pr_debug("OD: OverDrivePct: %d\n", od_table->OverDrivePct);
1997 }
1998
1999 static int navi10_od_setting_check_range(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODSETTING_ID setting, uint32_t value)
2000 {
2001         if (value < od_table->min[setting]) {
2002                 pr_warn("OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
2003                 return -EINVAL;
2004         }
2005         if (value > od_table->max[setting]) {
2006                 pr_warn("OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
2007                 return -EINVAL;
2008         }
2009         return 0;
2010 }
2011
2012 static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
2013                                                      uint16_t *voltage,
2014                                                      uint32_t freq)
2015 {
2016         uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16);
2017         uint32_t value = 0;
2018         int ret;
2019
2020         ret = smu_send_smc_msg_with_param(smu,
2021                                           SMU_MSG_GetVoltageByDpm,
2022                                           param,
2023                                           &value);
2024         if (ret) {
2025                 pr_err("[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
2026                 return ret;
2027         }
2028
2029         *voltage = (uint16_t)value;
2030
2031         return 0;
2032 }
2033
2034 static bool navi10_is_baco_supported(struct smu_context *smu)
2035 {
2036         struct amdgpu_device *adev = smu->adev;
2037         uint32_t val;
2038
2039         if (!smu_v11_0_baco_is_support(smu))
2040                 return false;
2041
2042         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
2043         return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
2044 }
2045
2046 static int navi10_set_default_od_settings(struct smu_context *smu)
2047 {
2048         OverDriveTable_t *od_table =
2049                 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2050         OverDriveTable_t *boot_od_table =
2051                 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2052         int ret = 0;
2053
2054         ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, false);
2055         if (ret) {
2056                 pr_err("Failed to get overdrive table!\n");
2057                 return ret;
2058         }
2059
2060         if (!od_table->GfxclkVolt1) {
2061                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2062                                                                 &od_table->GfxclkVolt1,
2063                                                                 od_table->GfxclkFreq1);
2064                 if (ret)
2065                         return ret;
2066         }
2067
2068         if (!od_table->GfxclkVolt2) {
2069                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2070                                                                 &od_table->GfxclkVolt2,
2071                                                                 od_table->GfxclkFreq2);
2072                 if (ret)
2073                         return ret;
2074         }
2075
2076         if (!od_table->GfxclkVolt3) {
2077                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2078                                                                 &od_table->GfxclkVolt3,
2079                                                                 od_table->GfxclkFreq3);
2080                 if (ret)
2081                         return ret;
2082         }
2083
2084         memcpy(boot_od_table, od_table, sizeof(OverDriveTable_t));
2085
2086         navi10_dump_od_table(od_table);
2087
2088         return 0;
2089 }
2090
2091 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) {
2092         int i;
2093         int ret = 0;
2094         struct smu_table_context *table_context = &smu->smu_table;
2095         OverDriveTable_t *od_table;
2096         struct smu_11_0_overdrive_table *od_settings;
2097         enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting;
2098         uint16_t *freq_ptr, *voltage_ptr;
2099         od_table = (OverDriveTable_t *)table_context->overdrive_table;
2100
2101         if (!smu->od_enabled) {
2102                 pr_warn("OverDrive is not enabled!\n");
2103                 return -EINVAL;
2104         }
2105
2106         if (!smu->od_settings) {
2107                 pr_err("OD board limits are not set!\n");
2108                 return -ENOENT;
2109         }
2110
2111         od_settings = smu->od_settings;
2112
2113         switch (type) {
2114         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2115                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
2116                         pr_warn("GFXCLK_LIMITS not supported!\n");
2117                         return -ENOTSUPP;
2118                 }
2119                 if (!table_context->overdrive_table) {
2120                         pr_err("Overdrive is not initialized\n");
2121                         return -EINVAL;
2122                 }
2123                 for (i = 0; i < size; i += 2) {
2124                         if (i + 2 > size) {
2125                                 pr_info("invalid number of input parameters %d\n", size);
2126                                 return -EINVAL;
2127                         }
2128                         switch (input[i]) {
2129                         case 0:
2130                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
2131                                 freq_ptr = &od_table->GfxclkFmin;
2132                                 if (input[i + 1] > od_table->GfxclkFmax) {
2133                                         pr_info("GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2134                                                 input[i + 1],
2135                                                 od_table->GfxclkFmin);
2136                                         return -EINVAL;
2137                                 }
2138                                 break;
2139                         case 1:
2140                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
2141                                 freq_ptr = &od_table->GfxclkFmax;
2142                                 if (input[i + 1] < od_table->GfxclkFmin) {
2143                                         pr_info("GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2144                                                 input[i + 1],
2145                                                 od_table->GfxclkFmax);
2146                                         return -EINVAL;
2147                                 }
2148                                 break;
2149                         default:
2150                                 pr_info("Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2151                                 pr_info("Supported indices: [0:min,1:max]\n");
2152                                 return -EINVAL;
2153                         }
2154                         ret = navi10_od_setting_check_range(od_settings, freq_setting, input[i + 1]);
2155                         if (ret)
2156                                 return ret;
2157                         *freq_ptr = input[i + 1];
2158                 }
2159                 break;
2160         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2161                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
2162                         pr_warn("UCLK_MAX not supported!\n");
2163                         return -ENOTSUPP;
2164                 }
2165                 if (size < 2) {
2166                         pr_info("invalid number of parameters: %d\n", size);
2167                         return -EINVAL;
2168                 }
2169                 if (input[0] != 1) {
2170                         pr_info("Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
2171                         pr_info("Supported indices: [1:max]\n");
2172                         return -EINVAL;
2173                 }
2174                 ret = navi10_od_setting_check_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
2175                 if (ret)
2176                         return ret;
2177                 od_table->UclkFmax = input[1];
2178                 break;
2179         case PP_OD_RESTORE_DEFAULT_TABLE:
2180                 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2181                         pr_err("Overdrive table was not initialized!\n");
2182                         return -EINVAL;
2183                 }
2184                 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t));
2185                 break;
2186         case PP_OD_COMMIT_DPM_TABLE:
2187                 navi10_dump_od_table(od_table);
2188                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2189                 if (ret) {
2190                         pr_err("Failed to import overdrive table!\n");
2191                         return ret;
2192                 }
2193                 // no lock needed because smu_od_edit_dpm_table has it
2194                 ret = smu_handle_task(smu, smu->smu_dpm.dpm_level,
2195                         AMD_PP_TASK_READJUST_POWER_STATE,
2196                         false);
2197                 if (ret) {
2198                         return ret;
2199                 }
2200                 break;
2201         case PP_OD_EDIT_VDDC_CURVE:
2202                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
2203                         pr_warn("GFXCLK_CURVE not supported!\n");
2204                         return -ENOTSUPP;
2205                 }
2206                 if (size < 3) {
2207                         pr_info("invalid number of parameters: %d\n", size);
2208                         return -EINVAL;
2209                 }
2210                 if (!od_table) {
2211                         pr_info("Overdrive is not initialized\n");
2212                         return -EINVAL;
2213                 }
2214
2215                 switch (input[0]) {
2216                 case 0:
2217                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1;
2218                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1;
2219                         freq_ptr = &od_table->GfxclkFreq1;
2220                         voltage_ptr = &od_table->GfxclkVolt1;
2221                         break;
2222                 case 1:
2223                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2;
2224                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2;
2225                         freq_ptr = &od_table->GfxclkFreq2;
2226                         voltage_ptr = &od_table->GfxclkVolt2;
2227                         break;
2228                 case 2:
2229                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3;
2230                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3;
2231                         freq_ptr = &od_table->GfxclkFreq3;
2232                         voltage_ptr = &od_table->GfxclkVolt3;
2233                         break;
2234                 default:
2235                         pr_info("Invalid VDDC_CURVE index: %ld\n", input[0]);
2236                         pr_info("Supported indices: [0, 1, 2]\n");
2237                         return -EINVAL;
2238                 }
2239                 ret = navi10_od_setting_check_range(od_settings, freq_setting, input[1]);
2240                 if (ret)
2241                         return ret;
2242                 // Allow setting zero to disable the OverDrive VDDC curve
2243                 if (input[2] != 0) {
2244                         ret = navi10_od_setting_check_range(od_settings, voltage_setting, input[2]);
2245                         if (ret)
2246                                 return ret;
2247                         *freq_ptr = input[1];
2248                         *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
2249                         pr_debug("OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
2250                 } else {
2251                         // If setting 0, disable all voltage curve settings
2252                         od_table->GfxclkVolt1 = 0;
2253                         od_table->GfxclkVolt2 = 0;
2254                         od_table->GfxclkVolt3 = 0;
2255                 }
2256                 navi10_dump_od_table(od_table);
2257                 break;
2258         default:
2259                 return -ENOSYS;
2260         }
2261         return ret;
2262 }
2263
2264 static int navi10_run_btc(struct smu_context *smu)
2265 {
2266         int ret = 0;
2267
2268         ret = smu_send_smc_msg(smu, SMU_MSG_RunBtc, NULL);
2269         if (ret)
2270                 pr_err("RunBtc failed!\n");
2271
2272         return ret;
2273 }
2274
2275 static int navi10_dummy_pstate_control(struct smu_context *smu, bool enable)
2276 {
2277         int result = 0;
2278
2279         if (!enable)
2280                 result = smu_send_smc_msg(smu, SMU_MSG_DAL_DISABLE_DUMMY_PSTATE_CHANGE, NULL);
2281         else
2282                 result = smu_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL);
2283
2284         return result;
2285 }
2286
2287 static inline bool navi10_need_umc_cdr_12gbps_workaround(struct amdgpu_device *adev)
2288 {
2289         if (adev->asic_type != CHIP_NAVI10)
2290                 return false;
2291
2292         if (adev->pdev->device == 0x731f &&
2293             (adev->pdev->revision == 0xc2 ||
2294              adev->pdev->revision == 0xc3 ||
2295              adev->pdev->revision == 0xca ||
2296              adev->pdev->revision == 0xcb))
2297                 return true;
2298         else
2299                 return false;
2300 }
2301
2302 static int navi10_disable_umc_cdr_12gbps_workaround(struct smu_context *smu)
2303 {
2304         uint32_t uclk_count, uclk_min, uclk_max;
2305         uint32_t smu_version;
2306         int ret = 0;
2307
2308         if (!navi10_need_umc_cdr_12gbps_workaround(smu->adev))
2309                 return 0;
2310
2311         ret = smu_get_smc_version(smu, NULL, &smu_version);
2312         if (ret)
2313                 return ret;
2314
2315         /* This workaround is available only for 42.50 or later SMC firmwares */
2316         if (smu_version < 0x2A3200)
2317                 return 0;
2318
2319         ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_count);
2320         if (ret)
2321                 return ret;
2322
2323         ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min);
2324         if (ret)
2325                 return ret;
2326
2327         ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max);
2328         if (ret)
2329                 return ret;
2330
2331         /* Force UCLK out of the highest DPM */
2332         ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, uclk_min);
2333         if (ret)
2334                 return ret;
2335
2336         /* Revert the UCLK Hardmax */
2337         ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, uclk_max);
2338         if (ret)
2339                 return ret;
2340
2341         /*
2342          * In this case, SMU already disabled dummy pstate during enablement
2343          * of UCLK DPM, we have to re-enabled it.
2344          * */
2345         return navi10_dummy_pstate_control(smu, true);
2346 }
2347
2348 static int navi10_set_thermal_range(struct smu_context *smu,
2349                                        struct smu_temperature_range range)
2350 {
2351         struct amdgpu_device *adev = smu->adev;
2352         int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
2353         int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
2354         uint32_t val;
2355         struct smu_table_context *table_context = &smu->smu_table;
2356         struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
2357
2358         low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
2359                         range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
2360         high = min((uint16_t)SMU_THERMAL_MAXIMUM_ALERT_TEMP, powerplay_table->software_shutdown_temp);
2361
2362         if (low > high)
2363                 return -EINVAL;
2364
2365         val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
2366         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
2367         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
2368         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
2369         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
2370         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
2371         val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
2372         val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
2373
2374         WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
2375
2376         return 0;
2377 }
2378
2379 static uint32_t navi10_get_max_power_limit(struct smu_context *smu) {
2380         uint32_t od_limit, max_power_limit;
2381         struct smu_11_0_powerplay_table *powerplay_table = NULL;
2382         struct smu_table_context *table_context = &smu->smu_table;
2383         powerplay_table = table_context->power_play_table;
2384
2385         max_power_limit = smu_get_pptable_power_limit(smu);
2386
2387         if (!max_power_limit) {
2388                 // If we couldn't get the table limit, fall back on first-read value
2389                 if (!smu->default_power_limit)
2390                         smu->default_power_limit = smu->power_limit;
2391                 max_power_limit = smu->default_power_limit;
2392         }
2393
2394         if (smu->od_enabled) {
2395                 od_limit = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
2396
2397                 pr_debug("ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_limit, smu->default_power_limit);
2398
2399                 max_power_limit *= (100 + od_limit);
2400                 max_power_limit /= 100;
2401         }
2402
2403         return max_power_limit;
2404 }
2405
2406 static const struct pptable_funcs navi10_ppt_funcs = {
2407         .tables_init = navi10_tables_init,
2408         .alloc_dpm_context = navi10_allocate_dpm_context,
2409         .get_smu_msg_index = navi10_get_smu_msg_index,
2410         .get_smu_clk_index = navi10_get_smu_clk_index,
2411         .get_smu_feature_index = navi10_get_smu_feature_index,
2412         .get_smu_table_index = navi10_get_smu_table_index,
2413         .get_smu_power_index = navi10_get_pwr_src_index,
2414         .get_workload_type = navi10_get_workload_type,
2415         .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
2416         .set_default_dpm_table = navi10_set_default_dpm_table,
2417         .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
2418         .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
2419         .get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
2420         .print_clk_levels = navi10_print_clk_levels,
2421         .force_clk_levels = navi10_force_clk_levels,
2422         .populate_umd_state_clk = navi10_populate_umd_state_clk,
2423         .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
2424         .pre_display_config_changed = navi10_pre_display_config_changed,
2425         .display_config_changed = navi10_display_config_changed,
2426         .notify_smc_display_config = navi10_notify_smc_display_config,
2427         .force_dpm_limit_value = navi10_force_dpm_limit_value,
2428         .unforce_dpm_levels = navi10_unforce_dpm_levels,
2429         .is_dpm_running = navi10_is_dpm_running,
2430         .get_fan_speed_percent = navi10_get_fan_speed_percent,
2431         .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
2432         .get_power_profile_mode = navi10_get_power_profile_mode,
2433         .set_power_profile_mode = navi10_set_power_profile_mode,
2434         .get_profiling_clk_mask = navi10_get_profiling_clk_mask,
2435         .set_watermarks_table = navi10_set_watermarks_table,
2436         .read_sensor = navi10_read_sensor,
2437         .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
2438         .set_performance_level = navi10_set_performance_level,
2439         .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
2440         .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
2441         .get_power_limit = navi10_get_power_limit,
2442         .update_pcie_parameters = navi10_update_pcie_parameters,
2443         .init_microcode = smu_v11_0_init_microcode,
2444         .load_microcode = smu_v11_0_load_microcode,
2445         .fini_microcode = smu_v11_0_fini_microcode,
2446         .init_smc_tables = smu_v11_0_init_smc_tables,
2447         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2448         .init_power = smu_v11_0_init_power,
2449         .fini_power = smu_v11_0_fini_power,
2450         .check_fw_status = smu_v11_0_check_fw_status,
2451         .setup_pptable = navi10_setup_pptable,
2452         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2453         .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2454         .check_fw_version = smu_v11_0_check_fw_version,
2455         .write_pptable = smu_v11_0_write_pptable,
2456         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2457         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2458         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2459         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2460         .system_features_control = smu_v11_0_system_features_control,
2461         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2462         .init_display_count = smu_v11_0_init_display_count,
2463         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2464         .get_enabled_mask = smu_v11_0_get_enabled_mask,
2465         .notify_display_change = smu_v11_0_notify_display_change,
2466         .set_power_limit = smu_v11_0_set_power_limit,
2467         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2468         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2469         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2470         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2471         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2472         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2473         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2474         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2475         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2476         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2477         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2478         .gfx_off_control = smu_v11_0_gfx_off_control,
2479         .register_irq_handler = smu_v11_0_register_irq_handler,
2480         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2481         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2482         .baco_is_support= navi10_is_baco_supported,
2483         .baco_get_state = smu_v11_0_baco_get_state,
2484         .baco_set_state = smu_v11_0_baco_set_state,
2485         .baco_enter = smu_v11_0_baco_enter,
2486         .baco_exit = smu_v11_0_baco_exit,
2487         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2488         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2489         .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2490         .set_default_od_settings = navi10_set_default_od_settings,
2491         .od_edit_dpm_table = navi10_od_edit_dpm_table,
2492         .get_pptable_power_limit = navi10_get_pptable_power_limit,
2493         .run_btc = navi10_run_btc,
2494         .disable_umc_cdr_12gbps_workaround = navi10_disable_umc_cdr_12gbps_workaround,
2495         .set_power_source = smu_v11_0_set_power_source,
2496         .set_thermal_range = navi10_set_thermal_range,
2497         .get_max_power_limit = navi10_get_max_power_limit,
2498 };
2499
2500 void navi10_set_ppt_funcs(struct smu_context *smu)
2501 {
2502         smu->ppt_funcs = &navi10_ppt_funcs;
2503 }