2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/firmware.h>
26 #include <linux/pci.h>
28 #include "amdgpu_smu.h"
29 #include "atomfirmware.h"
30 #include "amdgpu_atomfirmware.h"
31 #include "smu_v11_0.h"
32 #include "smu11_driver_if_navi10.h"
33 #include "soc15_common.h"
35 #include "navi10_ppt.h"
36 #include "smu_v11_0_pptable.h"
37 #include "smu_v11_0_ppsmc.h"
39 #include "asic_reg/mp/mp_11_0_sh_mask.h"
41 #define FEATURE_MASK(feature) (1ULL << feature)
42 #define SMC_DPM_FEATURE ( \
43 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
44 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
45 FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \
46 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
47 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
48 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \
49 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
50 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
52 #define MSG_MAP(msg, index) \
53 [SMU_MSG_##msg] = index
55 static int navi10_message_map[SMU_MSG_MAX_COUNT] = {
56 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage),
57 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion),
58 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion),
59 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow),
60 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh),
61 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures),
62 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures),
63 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow),
64 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh),
65 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow),
66 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh),
67 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow),
68 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh),
69 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask),
70 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit),
71 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh),
72 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow),
73 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh),
74 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow),
75 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram),
76 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu),
77 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable),
78 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable),
79 MSG_MAP(RunBtc, PPSMC_MSG_RunBtc),
80 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco),
81 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq),
82 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq),
83 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq),
84 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq),
85 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq),
86 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq),
87 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex),
88 MSG_MAP(SetMemoryChannelConfig, PPSMC_MSG_SetMemoryChannelConfig),
89 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode),
90 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh),
91 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow),
92 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters),
93 MSG_MAP(SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk),
94 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt),
95 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource),
96 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch),
97 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps),
98 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload),
99 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh),
100 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow),
101 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize),
102 MSG_MAP(ConfigureGfxDidt, PPSMC_MSG_ConfigureGfxDidt),
103 MSG_MAP(NumOfDisplays, PPSMC_MSG_NumOfDisplays),
104 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh),
105 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow),
106 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff),
107 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff),
108 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit),
109 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq),
110 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData),
111 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco),
112 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset),
113 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown),
114 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn),
115 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn),
116 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg),
117 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg),
118 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME),
119 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3),
122 static int navi10_clk_map[SMU_CLK_COUNT] = {
123 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
124 CLK_MAP(SCLK, PPCLK_GFXCLK),
125 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
126 CLK_MAP(FCLK, PPCLK_SOCCLK),
127 CLK_MAP(UCLK, PPCLK_UCLK),
128 CLK_MAP(MCLK, PPCLK_UCLK),
129 CLK_MAP(DCLK, PPCLK_DCLK),
130 CLK_MAP(VCLK, PPCLK_VCLK),
131 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
132 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
133 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
134 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
137 static int navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
138 FEA_MAP(DPM_PREFETCHER),
140 FEA_MAP(DPM_GFX_PACE),
145 FEA_MAP(DPM_DCEFCLK),
146 FEA_MAP(MEM_VDDCI_SCALING),
147 FEA_MAP(MEM_MVDD_SCALING),
160 FEA_MAP(RSMU_SMN_CG),
170 FEA_MAP(FAN_CONTROL),
174 FEA_MAP(LED_DISPLAY),
176 FEA_MAP(OUT_OF_BAND_MONITOR),
177 FEA_MAP(TEMP_DEPENDENT_VMIN),
182 static int navi10_table_map[SMU_TABLE_COUNT] = {
186 TAB_MAP(AVFS_PSM_DEBUG),
187 TAB_MAP(AVFS_FUSE_OVERRIDE),
188 TAB_MAP(PMSTATUSLOG),
189 TAB_MAP(SMU_METRICS),
190 TAB_MAP(DRIVER_SMU_CONFIG),
191 TAB_MAP(ACTIVITY_MONITOR_COEFF),
193 TAB_MAP(I2C_COMMANDS),
197 static int navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
202 static int navi10_workload_map[] = {
203 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
204 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
205 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
206 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
208 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
209 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
212 static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
215 if (index > SMU_MSG_MAX_COUNT)
218 val = navi10_message_map[index];
219 if (val > PPSMC_Message_Count)
225 static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
228 if (index >= SMU_CLK_COUNT)
231 val = navi10_clk_map[index];
232 if (val >= PPCLK_COUNT)
238 static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
241 if (index >= SMU_FEATURE_COUNT)
244 val = navi10_feature_mask_map[index];
251 static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
254 if (index >= SMU_TABLE_COUNT)
257 val = navi10_table_map[index];
258 if (val >= TABLE_COUNT)
264 static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
267 if (index >= SMU_POWER_SOURCE_COUNT)
270 val = navi10_pwr_src_map[index];
271 if (val >= POWER_SOURCE_COUNT)
278 static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
281 if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
284 val = navi10_workload_map[profile];
289 static bool is_asic_secure(struct smu_context *smu)
291 struct amdgpu_device *adev = smu->adev;
292 bool is_secure = true;
293 uint32_t mp0_fw_intf;
295 mp0_fw_intf = RREG32_PCIE(MP0_Public |
296 (smnMP0_FW_INTF & 0xffffffff));
298 if (!(mp0_fw_intf & (1 << 19)))
305 navi10_get_allowed_feature_mask(struct smu_context *smu,
306 uint32_t *feature_mask, uint32_t num)
308 struct amdgpu_device *adev = smu->adev;
313 memset(feature_mask, 0, sizeof(uint32_t) * num);
315 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
316 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
317 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
318 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
319 | FEATURE_MASK(FEATURE_DPM_LINK_BIT)
320 | FEATURE_MASK(FEATURE_GFX_ULV_BIT)
321 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
322 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
323 | FEATURE_MASK(FEATURE_PPT_BIT)
324 | FEATURE_MASK(FEATURE_TDC_BIT)
325 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
326 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
327 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
328 | FEATURE_MASK(FEATURE_THERMAL_BIT)
329 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
330 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
331 | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT)
332 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
333 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
334 | FEATURE_MASK(FEATURE_BACO_BIT)
335 | FEATURE_MASK(FEATURE_ACDC_BIT)
336 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
337 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
338 | FEATURE_MASK(FEATURE_FW_CTF_BIT);
340 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
341 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
342 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
343 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
345 if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
346 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
347 /* TODO: remove it once fw fix the bug */
348 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
351 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
352 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
354 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
355 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
357 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
358 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
360 /* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
361 if (is_asic_secure(smu)) {
362 /* only for navi10 A0 */
363 if ((adev->asic_type == CHIP_NAVI10) &&
364 (adev->rev_id == 0)) {
365 *(uint64_t *)feature_mask &=
366 ~(FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
367 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
368 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT));
369 *(uint64_t *)feature_mask &=
370 ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
377 static int navi10_check_powerplay_table(struct smu_context *smu)
382 static int navi10_append_powerplay_table(struct smu_context *smu)
384 struct amdgpu_device *adev = smu->adev;
385 struct smu_table_context *table_context = &smu->smu_table;
386 PPTable_t *smc_pptable = table_context->driver_pptable;
387 struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
390 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
393 ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
394 (uint8_t **)&smc_dpm_table);
398 memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
399 sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS);
401 /* SVI2 Board Parameters */
402 smc_pptable->MaxVoltageStepGfx = smc_dpm_table->MaxVoltageStepGfx;
403 smc_pptable->MaxVoltageStepSoc = smc_dpm_table->MaxVoltageStepSoc;
404 smc_pptable->VddGfxVrMapping = smc_dpm_table->VddGfxVrMapping;
405 smc_pptable->VddSocVrMapping = smc_dpm_table->VddSocVrMapping;
406 smc_pptable->VddMem0VrMapping = smc_dpm_table->VddMem0VrMapping;
407 smc_pptable->VddMem1VrMapping = smc_dpm_table->VddMem1VrMapping;
408 smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->GfxUlvPhaseSheddingMask;
409 smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->SocUlvPhaseSheddingMask;
410 smc_pptable->ExternalSensorPresent = smc_dpm_table->ExternalSensorPresent;
411 smc_pptable->Padding8_V = smc_dpm_table->Padding8_V;
413 /* Telemetry Settings */
414 smc_pptable->GfxMaxCurrent = smc_dpm_table->GfxMaxCurrent;
415 smc_pptable->GfxOffset = smc_dpm_table->GfxOffset;
416 smc_pptable->Padding_TelemetryGfx = smc_dpm_table->Padding_TelemetryGfx;
417 smc_pptable->SocMaxCurrent = smc_dpm_table->SocMaxCurrent;
418 smc_pptable->SocOffset = smc_dpm_table->SocOffset;
419 smc_pptable->Padding_TelemetrySoc = smc_dpm_table->Padding_TelemetrySoc;
420 smc_pptable->Mem0MaxCurrent = smc_dpm_table->Mem0MaxCurrent;
421 smc_pptable->Mem0Offset = smc_dpm_table->Mem0Offset;
422 smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->Padding_TelemetryMem0;
423 smc_pptable->Mem1MaxCurrent = smc_dpm_table->Mem1MaxCurrent;
424 smc_pptable->Mem1Offset = smc_dpm_table->Mem1Offset;
425 smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->Padding_TelemetryMem1;
428 smc_pptable->AcDcGpio = smc_dpm_table->AcDcGpio;
429 smc_pptable->AcDcPolarity = smc_dpm_table->AcDcPolarity;
430 smc_pptable->VR0HotGpio = smc_dpm_table->VR0HotGpio;
431 smc_pptable->VR0HotPolarity = smc_dpm_table->VR0HotPolarity;
432 smc_pptable->VR1HotGpio = smc_dpm_table->VR1HotGpio;
433 smc_pptable->VR1HotPolarity = smc_dpm_table->VR1HotPolarity;
434 smc_pptable->GthrGpio = smc_dpm_table->GthrGpio;
435 smc_pptable->GthrPolarity = smc_dpm_table->GthrPolarity;
437 /* LED Display Settings */
438 smc_pptable->LedPin0 = smc_dpm_table->LedPin0;
439 smc_pptable->LedPin1 = smc_dpm_table->LedPin1;
440 smc_pptable->LedPin2 = smc_dpm_table->LedPin2;
441 smc_pptable->padding8_4 = smc_dpm_table->padding8_4;
443 /* GFXCLK PLL Spread Spectrum */
444 smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->PllGfxclkSpreadEnabled;
445 smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->PllGfxclkSpreadPercent;
446 smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->PllGfxclkSpreadFreq;
448 /* GFXCLK DFLL Spread Spectrum */
449 smc_pptable->DfllGfxclkSpreadEnabled = smc_dpm_table->DfllGfxclkSpreadEnabled;
450 smc_pptable->DfllGfxclkSpreadPercent = smc_dpm_table->DfllGfxclkSpreadPercent;
451 smc_pptable->DfllGfxclkSpreadFreq = smc_dpm_table->DfllGfxclkSpreadFreq;
453 /* UCLK Spread Spectrum */
454 smc_pptable->UclkSpreadEnabled = smc_dpm_table->UclkSpreadEnabled;
455 smc_pptable->UclkSpreadPercent = smc_dpm_table->UclkSpreadPercent;
456 smc_pptable->UclkSpreadFreq = smc_dpm_table->UclkSpreadFreq;
458 /* SOCCLK Spread Spectrum */
459 smc_pptable->SoclkSpreadEnabled = smc_dpm_table->SoclkSpreadEnabled;
460 smc_pptable->SocclkSpreadPercent = smc_dpm_table->SocclkSpreadPercent;
461 smc_pptable->SocclkSpreadFreq = smc_dpm_table->SocclkSpreadFreq;
463 /* Total board power */
464 smc_pptable->TotalBoardPower = smc_dpm_table->TotalBoardPower;
465 smc_pptable->BoardPadding = smc_dpm_table->BoardPadding;
467 /* Mvdd Svi2 Div Ratio Setting */
468 smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
470 if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
471 /* TODO: remove it once SMU fw fix it */
472 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
478 static int navi10_store_powerplay_table(struct smu_context *smu)
480 struct smu_11_0_powerplay_table *powerplay_table = NULL;
481 struct smu_table_context *table_context = &smu->smu_table;
482 struct smu_baco_context *smu_baco = &smu->smu_baco;
484 if (!table_context->power_play_table)
487 powerplay_table = table_context->power_play_table;
489 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
492 table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
494 mutex_lock(&smu_baco->mutex);
495 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
496 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
497 smu_baco->platform_support = true;
498 mutex_unlock(&smu_baco->mutex);
503 static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
505 struct smu_table_context *smu_table = &smu->smu_table;
507 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
508 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
509 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
510 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
511 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
512 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
513 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
514 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
515 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
516 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
517 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
518 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
519 AMDGPU_GEM_DOMAIN_VRAM);
521 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
522 if (!smu_table->metrics_table)
524 smu_table->metrics_time = 0;
529 static int navi10_get_metrics_table(struct smu_context *smu,
530 SmuMetrics_t *metrics_table)
532 struct smu_table_context *smu_table= &smu->smu_table;
535 if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
536 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
537 (void *)smu_table->metrics_table, false);
539 pr_info("Failed to export SMU metrics table!\n");
542 smu_table->metrics_time = jiffies;
545 memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
550 static int navi10_allocate_dpm_context(struct smu_context *smu)
552 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
554 if (smu_dpm->dpm_context)
557 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
559 if (!smu_dpm->dpm_context)
562 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
567 static int navi10_set_default_dpm_table(struct smu_context *smu)
569 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
570 struct smu_table_context *table_context = &smu->smu_table;
571 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
572 PPTable_t *driver_ppt = NULL;
574 driver_ppt = table_context->driver_pptable;
576 dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
577 dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
579 dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
580 dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
582 dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
583 dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
585 dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
586 dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
588 dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
589 dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
591 dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
592 dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
594 dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
595 dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
597 dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
598 dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
600 dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
601 dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
606 static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
608 struct smu_power_context *smu_power = &smu->smu_power;
609 struct smu_power_gate *power_gate = &smu_power->power_gate;
613 /* vcn dpm on is a prerequisite for vcn power gate messages */
614 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
615 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
619 power_gate->vcn_gated = false;
621 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
622 ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
626 power_gate->vcn_gated = true;
632 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
633 enum smu_clk_type clk_type,
636 int ret = 0, clk_id = 0;
637 SmuMetrics_t metrics;
639 ret = navi10_get_metrics_table(smu, &metrics);
643 clk_id = smu_clk_get_index(smu, clk_type);
647 *value = metrics.CurrClock[clk_id];
652 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
654 PPTable_t *pptable = smu->smu_table.driver_pptable;
655 DpmDescriptor_t *dpm_desc = NULL;
656 uint32_t clk_index = 0;
658 clk_index = smu_clk_get_index(smu, clk_type);
659 dpm_desc = &pptable->DpmDescriptor[clk_index];
661 /* 0 - Fine grained DPM, 1 - Discrete DPM */
662 return dpm_desc->SnapToDiscrete == 0 ? true : false;
665 static int navi10_print_clk_levels(struct smu_context *smu,
666 enum smu_clk_type clk_type, char *buf)
668 int i, size = 0, ret = 0;
669 uint32_t cur_value = 0, value = 0, count = 0;
670 uint32_t freq_values[3] = {0};
671 uint32_t mark_index = 0;
681 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
686 cur_value = cur_value / 100;
688 ret = smu_get_dpm_level_count(smu, clk_type, &count);
692 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
693 for (i = 0; i < count; i++) {
694 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
698 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
699 cur_value == value ? "*" : "");
702 ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
705 ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
709 freq_values[1] = cur_value;
710 mark_index = cur_value == freq_values[0] ? 0 :
711 cur_value == freq_values[2] ? 2 : 1;
713 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
715 for (i = 0; i < 3; i++) {
716 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
717 i == mark_index ? "*" : "");
729 static int navi10_force_clk_levels(struct smu_context *smu,
730 enum smu_clk_type clk_type, uint32_t mask)
733 int ret = 0, size = 0;
734 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
736 soft_min_level = mask ? (ffs(mask) - 1) : 0;
737 soft_max_level = mask ? (fls(mask) - 1) : 0;
747 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
751 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
755 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
766 static int navi10_populate_umd_state_clk(struct smu_context *smu)
769 uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
771 ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL);
775 smu->pstate_sclk = min_sclk_freq * 100;
777 ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL);
781 smu->pstate_mclk = min_mclk_freq * 100;
786 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
787 enum smu_clk_type clk_type,
788 struct pp_clock_levels_with_latency *clocks)
791 uint32_t level_count = 0, freq = 0;
797 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
801 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
802 clocks->num_levels = level_count;
804 for (i = 0; i < level_count; i++) {
805 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
809 clocks->data[i].clocks_in_khz = freq * 1000;
810 clocks->data[i].latency_in_us = 0;
820 static int navi10_pre_display_config_changed(struct smu_context *smu)
823 uint32_t max_freq = 0;
825 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
829 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
830 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq);
833 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
841 static int navi10_display_config_changed(struct smu_context *smu)
845 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
846 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
847 ret = smu_write_watermarks_table(smu);
851 smu->watermarks_bitmap |= WATERMARKS_LOADED;
854 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
855 smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
856 smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
857 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
858 smu->display_config->num_display);
866 static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
869 uint32_t min_freq, max_freq, force_freq;
870 enum smu_clk_type clk_type;
872 enum smu_clk_type clks[] = {
878 for (i = 0; i < ARRAY_SIZE(clks); i++) {
880 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
884 force_freq = highest ? max_freq : min_freq;
885 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq);
893 static int navi10_unforce_dpm_levels(struct smu_context *smu)
896 uint32_t min_freq, max_freq;
897 enum smu_clk_type clk_type;
899 enum smu_clk_type clks[] = {
905 for (i = 0; i < ARRAY_SIZE(clks); i++) {
907 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
911 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
919 static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
922 SmuMetrics_t metrics;
927 ret = navi10_get_metrics_table(smu, &metrics);
933 *value = metrics.AverageSocketPower << 8;
938 static int navi10_get_current_activity_percent(struct smu_context *smu,
939 enum amd_pp_sensors sensor,
943 SmuMetrics_t metrics;
948 ret = navi10_get_metrics_table(smu, &metrics);
953 case AMDGPU_PP_SENSOR_GPU_LOAD:
954 *value = metrics.AverageGfxActivity;
956 case AMDGPU_PP_SENSOR_MEM_LOAD:
957 *value = metrics.AverageUclkActivity;
960 pr_err("Invalid sensor for retrieving clock activity\n");
967 static bool navi10_is_dpm_running(struct smu_context *smu)
970 uint32_t feature_mask[2];
971 unsigned long feature_enabled;
972 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
973 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
974 ((uint64_t)feature_mask[1] << 32));
975 return !!(feature_enabled & SMC_DPM_FEATURE);
978 static int navi10_get_fan_speed_rpm(struct smu_context *smu,
981 SmuMetrics_t metrics;
987 ret = navi10_get_metrics_table(smu, &metrics);
993 *speed = metrics.CurrFanSpeed;
998 static int navi10_get_fan_speed_percent(struct smu_context *smu,
1002 uint32_t percent = 0;
1003 uint32_t current_rpm;
1004 PPTable_t *pptable = smu->smu_table.driver_pptable;
1006 ret = navi10_get_fan_speed_rpm(smu, ¤t_rpm);
1010 percent = current_rpm * 100 / pptable->FanMaximumRpm;
1011 *speed = percent > 100 ? 100 : percent;
1016 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1018 DpmActivityMonitorCoeffInt_t activity_monitor;
1019 uint32_t i, size = 0;
1020 uint16_t workload_type = 0;
1021 static const char *profile_name[] = {
1029 static const char *title[] = {
1030 "PROFILE_INDEX(NAME)",
1034 "MinActiveFreqType",
1039 "PD_Data_error_coeff",
1040 "PD_Data_error_rate_coeff"};
1046 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1047 title[0], title[1], title[2], title[3], title[4], title[5],
1048 title[6], title[7], title[8], title[9], title[10]);
1050 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1051 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1052 workload_type = smu_workload_get_type(smu, i);
1053 result = smu_update_table(smu,
1054 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1055 (void *)(&activity_monitor), false);
1057 pr_err("[%s] Failed to get activity monitor!", __func__);
1061 size += sprintf(buf + size, "%2d %14s%s:\n",
1062 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1064 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1068 activity_monitor.Gfx_FPS,
1069 activity_monitor.Gfx_MinFreqStep,
1070 activity_monitor.Gfx_MinActiveFreqType,
1071 activity_monitor.Gfx_MinActiveFreq,
1072 activity_monitor.Gfx_BoosterFreqType,
1073 activity_monitor.Gfx_BoosterFreq,
1074 activity_monitor.Gfx_PD_Data_limit_c,
1075 activity_monitor.Gfx_PD_Data_error_coeff,
1076 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1078 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1082 activity_monitor.Soc_FPS,
1083 activity_monitor.Soc_MinFreqStep,
1084 activity_monitor.Soc_MinActiveFreqType,
1085 activity_monitor.Soc_MinActiveFreq,
1086 activity_monitor.Soc_BoosterFreqType,
1087 activity_monitor.Soc_BoosterFreq,
1088 activity_monitor.Soc_PD_Data_limit_c,
1089 activity_monitor.Soc_PD_Data_error_coeff,
1090 activity_monitor.Soc_PD_Data_error_rate_coeff);
1092 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1096 activity_monitor.Mem_FPS,
1097 activity_monitor.Mem_MinFreqStep,
1098 activity_monitor.Mem_MinActiveFreqType,
1099 activity_monitor.Mem_MinActiveFreq,
1100 activity_monitor.Mem_BoosterFreqType,
1101 activity_monitor.Mem_BoosterFreq,
1102 activity_monitor.Mem_PD_Data_limit_c,
1103 activity_monitor.Mem_PD_Data_error_coeff,
1104 activity_monitor.Mem_PD_Data_error_rate_coeff);
1110 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1112 DpmActivityMonitorCoeffInt_t activity_monitor;
1113 int workload_type, ret = 0;
1115 smu->power_profile_mode = input[size];
1117 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1118 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1122 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1126 ret = smu_update_table(smu,
1127 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1128 (void *)(&activity_monitor), false);
1130 pr_err("[%s] Failed to get activity monitor!", __func__);
1135 case 0: /* Gfxclk */
1136 activity_monitor.Gfx_FPS = input[1];
1137 activity_monitor.Gfx_MinFreqStep = input[2];
1138 activity_monitor.Gfx_MinActiveFreqType = input[3];
1139 activity_monitor.Gfx_MinActiveFreq = input[4];
1140 activity_monitor.Gfx_BoosterFreqType = input[5];
1141 activity_monitor.Gfx_BoosterFreq = input[6];
1142 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1143 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1144 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1146 case 1: /* Socclk */
1147 activity_monitor.Soc_FPS = input[1];
1148 activity_monitor.Soc_MinFreqStep = input[2];
1149 activity_monitor.Soc_MinActiveFreqType = input[3];
1150 activity_monitor.Soc_MinActiveFreq = input[4];
1151 activity_monitor.Soc_BoosterFreqType = input[5];
1152 activity_monitor.Soc_BoosterFreq = input[6];
1153 activity_monitor.Soc_PD_Data_limit_c = input[7];
1154 activity_monitor.Soc_PD_Data_error_coeff = input[8];
1155 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1158 activity_monitor.Mem_FPS = input[1];
1159 activity_monitor.Mem_MinFreqStep = input[2];
1160 activity_monitor.Mem_MinActiveFreqType = input[3];
1161 activity_monitor.Mem_MinActiveFreq = input[4];
1162 activity_monitor.Mem_BoosterFreqType = input[5];
1163 activity_monitor.Mem_BoosterFreq = input[6];
1164 activity_monitor.Mem_PD_Data_limit_c = input[7];
1165 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1166 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1170 ret = smu_update_table(smu,
1171 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1172 (void *)(&activity_monitor), true);
1174 pr_err("[%s] Failed to set activity monitor!", __func__);
1179 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1180 workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1181 smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1182 1 << workload_type);
1187 static int navi10_get_profiling_clk_mask(struct smu_context *smu,
1188 enum amd_dpm_forced_level level,
1189 uint32_t *sclk_mask,
1190 uint32_t *mclk_mask,
1194 uint32_t level_count = 0;
1196 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1199 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1202 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1204 ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1207 *sclk_mask = level_count - 1;
1211 ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1214 *mclk_mask = level_count - 1;
1218 ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1221 *soc_mask = level_count - 1;
1228 static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
1230 struct smu_clocks min_clocks = {0};
1231 struct pp_display_clock_request clock_req;
1234 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1235 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1236 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1238 if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1239 clock_req.clock_type = amd_pp_dcef_clock;
1240 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1241 if (!smu_display_clock_voltage_request(smu, &clock_req)) {
1242 if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1243 ret = smu_send_smc_msg_with_param(smu,
1244 SMU_MSG_SetMinDeepSleepDcefclk,
1245 min_clocks.dcef_clock_in_sr/100);
1247 pr_err("Attempt to set divider for DCEFCLK Failed!");
1252 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1256 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1257 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1259 pr_err("[%s] Set hard min uclk failed!", __func__);
1267 static int navi10_set_watermarks_table(struct smu_context *smu,
1268 void *watermarks, struct
1269 dm_pp_wm_sets_with_clock_ranges_soc15
1273 Watermarks_t *table = watermarks;
1275 if (!table || !clock_ranges)
1278 if (clock_ranges->num_wm_dmif_sets > 4 ||
1279 clock_ranges->num_wm_mcif_sets > 4)
1282 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1283 table->WatermarkRow[1][i].MinClock =
1284 cpu_to_le16((uint16_t)
1285 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1287 table->WatermarkRow[1][i].MaxClock =
1288 cpu_to_le16((uint16_t)
1289 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1291 table->WatermarkRow[1][i].MinUclk =
1292 cpu_to_le16((uint16_t)
1293 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1295 table->WatermarkRow[1][i].MaxUclk =
1296 cpu_to_le16((uint16_t)
1297 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1299 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1300 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1303 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1304 table->WatermarkRow[0][i].MinClock =
1305 cpu_to_le16((uint16_t)
1306 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1308 table->WatermarkRow[0][i].MaxClock =
1309 cpu_to_le16((uint16_t)
1310 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1312 table->WatermarkRow[0][i].MinUclk =
1313 cpu_to_le16((uint16_t)
1314 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1316 table->WatermarkRow[0][i].MaxUclk =
1317 cpu_to_le16((uint16_t)
1318 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1320 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1321 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1327 static int navi10_thermal_get_temperature(struct smu_context *smu,
1328 enum amd_pp_sensors sensor,
1331 SmuMetrics_t metrics;
1337 ret = navi10_get_metrics_table(smu, &metrics);
1342 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1343 *value = metrics.TemperatureHotspot *
1344 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1346 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1347 *value = metrics.TemperatureEdge *
1348 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1350 case AMDGPU_PP_SENSOR_MEM_TEMP:
1351 *value = metrics.TemperatureMem *
1352 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1355 pr_err("Invalid sensor for retrieving temp\n");
1362 static int navi10_read_sensor(struct smu_context *smu,
1363 enum amd_pp_sensors sensor,
1364 void *data, uint32_t *size)
1367 struct smu_table_context *table_context = &smu->smu_table;
1368 PPTable_t *pptable = table_context->driver_pptable;
1371 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1372 *(uint32_t *)data = pptable->FanMaximumRpm;
1375 case AMDGPU_PP_SENSOR_MEM_LOAD:
1376 case AMDGPU_PP_SENSOR_GPU_LOAD:
1377 ret = navi10_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1380 case AMDGPU_PP_SENSOR_GPU_POWER:
1381 ret = navi10_get_gpu_power(smu, (uint32_t *)data);
1384 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1385 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1386 case AMDGPU_PP_SENSOR_MEM_TEMP:
1387 ret = navi10_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1397 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1399 uint32_t num_discrete_levels = 0;
1400 uint16_t *dpm_levels = NULL;
1402 struct smu_table_context *table_context = &smu->smu_table;
1403 PPTable_t *driver_ppt = NULL;
1405 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1408 driver_ppt = table_context->driver_pptable;
1409 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1410 dpm_levels = driver_ppt->FreqTableUclk;
1412 if (num_discrete_levels == 0 || dpm_levels == NULL)
1415 *num_states = num_discrete_levels;
1416 for (i = 0; i < num_discrete_levels; i++) {
1417 /* convert to khz */
1418 *clocks_in_khz = (*dpm_levels) * 1000;
1426 static int navi10_get_ppfeature_status(struct smu_context *smu,
1429 static const char *ppfeature_name[] = {
1438 "MEM_VDDCI_SCALING",
1468 "OUT_OF_BAND_MONITOR",
1469 "TEMP_DEPENDENT_VMIN",
1472 static const char *output_title[] = {
1476 uint64_t features_enabled;
1477 uint32_t feature_mask[2];
1482 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1483 PP_ASSERT_WITH_CODE(!ret,
1484 "[GetPPfeatureStatus] Failed to get enabled smc features!",
1486 features_enabled = (uint64_t)feature_mask[0] |
1487 (uint64_t)feature_mask[1] << 32;
1489 size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
1490 size += sprintf(buf + size, "%-19s %-22s %s\n",
1494 for (i = 0; i < (sizeof(ppfeature_name) / sizeof(ppfeature_name[0])); i++) {
1495 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
1498 (features_enabled & (1ULL << i)) ? "Y" : "N");
1504 static int navi10_enable_smc_features(struct smu_context *smu,
1506 uint64_t feature_masks)
1508 struct smu_feature *feature = &smu->smu_feature;
1509 uint32_t feature_low, feature_high;
1510 uint32_t feature_mask[2];
1513 feature_low = (uint32_t)(feature_masks & 0xFFFFFFFF);
1514 feature_high = (uint32_t)((feature_masks & 0xFFFFFFFF00000000ULL) >> 32);
1517 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
1521 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
1526 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
1530 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
1536 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1540 mutex_lock(&feature->mutex);
1541 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
1542 feature->feature_num);
1543 mutex_unlock(&feature->mutex);
1548 static int navi10_set_ppfeature_status(struct smu_context *smu,
1549 uint64_t new_ppfeature_masks)
1551 uint64_t features_enabled;
1552 uint32_t feature_mask[2];
1553 uint64_t features_to_enable;
1554 uint64_t features_to_disable;
1557 ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1558 PP_ASSERT_WITH_CODE(!ret,
1559 "[SetPPfeatureStatus] Failed to get enabled smc features!",
1561 features_enabled = (uint64_t)feature_mask[0] |
1562 (uint64_t)feature_mask[1] << 32;
1564 features_to_disable =
1565 features_enabled & ~new_ppfeature_masks;
1566 features_to_enable =
1567 ~features_enabled & new_ppfeature_masks;
1569 pr_debug("features_to_disable 0x%llx\n", features_to_disable);
1570 pr_debug("features_to_enable 0x%llx\n", features_to_enable);
1572 if (features_to_disable) {
1573 ret = navi10_enable_smc_features(smu, false, features_to_disable);
1574 PP_ASSERT_WITH_CODE(!ret,
1575 "[SetPPfeatureStatus] Failed to disable smc features!",
1579 if (features_to_enable) {
1580 ret = navi10_enable_smc_features(smu, true, features_to_enable);
1581 PP_ASSERT_WITH_CODE(!ret,
1582 "[SetPPfeatureStatus] Failed to enable smc features!",
1589 static int navi10_set_peak_clock_by_device(struct smu_context *smu)
1591 struct amdgpu_device *adev = smu->adev;
1593 uint32_t sclk_freq = 0, uclk_freq = 0;
1594 uint32_t uclk_level = 0;
1596 switch (adev->pdev->revision) {
1597 case 0xf0: /* XTX */
1599 sclk_freq = NAVI10_PEAK_SCLK_XTX;
1603 sclk_freq = NAVI10_PEAK_SCLK_XT;
1606 sclk_freq = NAVI10_PEAK_SCLK_XL;
1610 ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_level);
1613 ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, uclk_level - 1, &uclk_freq);
1617 ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
1620 ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
1627 static int navi10_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1632 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1633 ret = navi10_set_peak_clock_by_device(smu);
1643 static int navi10_get_thermal_temperature_range(struct smu_context *smu,
1644 struct smu_temperature_range *range)
1646 struct smu_table_context *table_context = &smu->smu_table;
1647 struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1649 if (!range || !powerplay_table)
1652 /* The unit is temperature */
1654 range->max = powerplay_table->software_shutdown_temp;
1659 static const struct pptable_funcs navi10_ppt_funcs = {
1660 .tables_init = navi10_tables_init,
1661 .alloc_dpm_context = navi10_allocate_dpm_context,
1662 .store_powerplay_table = navi10_store_powerplay_table,
1663 .check_powerplay_table = navi10_check_powerplay_table,
1664 .append_powerplay_table = navi10_append_powerplay_table,
1665 .get_smu_msg_index = navi10_get_smu_msg_index,
1666 .get_smu_clk_index = navi10_get_smu_clk_index,
1667 .get_smu_feature_index = navi10_get_smu_feature_index,
1668 .get_smu_table_index = navi10_get_smu_table_index,
1669 .get_smu_power_index = navi10_get_pwr_src_index,
1670 .get_workload_type = navi10_get_workload_type,
1671 .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
1672 .set_default_dpm_table = navi10_set_default_dpm_table,
1673 .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
1674 .get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
1675 .print_clk_levels = navi10_print_clk_levels,
1676 .force_clk_levels = navi10_force_clk_levels,
1677 .populate_umd_state_clk = navi10_populate_umd_state_clk,
1678 .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
1679 .pre_display_config_changed = navi10_pre_display_config_changed,
1680 .display_config_changed = navi10_display_config_changed,
1681 .notify_smc_dispaly_config = navi10_notify_smc_dispaly_config,
1682 .force_dpm_limit_value = navi10_force_dpm_limit_value,
1683 .unforce_dpm_levels = navi10_unforce_dpm_levels,
1684 .is_dpm_running = navi10_is_dpm_running,
1685 .get_fan_speed_percent = navi10_get_fan_speed_percent,
1686 .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
1687 .get_power_profile_mode = navi10_get_power_profile_mode,
1688 .set_power_profile_mode = navi10_set_power_profile_mode,
1689 .get_profiling_clk_mask = navi10_get_profiling_clk_mask,
1690 .set_watermarks_table = navi10_set_watermarks_table,
1691 .read_sensor = navi10_read_sensor,
1692 .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
1693 .get_ppfeature_status = navi10_get_ppfeature_status,
1694 .set_ppfeature_status = navi10_set_ppfeature_status,
1695 .set_performance_level = navi10_set_performance_level,
1696 .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
1699 void navi10_set_ppt_funcs(struct smu_context *smu)
1701 struct smu_table_context *smu_table = &smu->smu_table;
1703 smu->ppt_funcs = &navi10_ppt_funcs;
1704 smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
1705 smu_table->table_count = TABLE_COUNT;