drivers/gpu/drm/amd/powerplay/navi10_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "atomfirmware.h"
  29 #include "amdgpu_atomfirmware.h"
  30 #include "smu_v11_0.h"
  31 #include "smu11_driver_if_navi10.h"
  32 #include "soc15_common.h"
  33 #include "atom.h"
  34 #include "navi10_ppt.h"
  35 #include "smu_v11_0_pptable.h"
  36 #include "smu_v11_0_ppsmc.h"
  37
  38 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  39
  40 #define FEATURE_MASK(feature) (1ULL << feature)
  41 #define SMC_DPM_FEATURE ( \
  42         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  43         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  44         FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT)   | \
  45         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  46         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  47         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)     | \
  48         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  49         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
  50
  51 #define MSG_MAP(msg, index) \
  52         [SMU_MSG_##msg] = index
  53
  54 static int navi10_message_map[SMU_MSG_MAX_COUNT] = {
  55         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
  56         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
  57         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion),
  58         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow),
  59         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  60         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures),
  61         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures),
  62         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow),
  63         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh),
  64         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow),
  65         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh),
  66         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetEnabledSmuFeaturesLow),
  67         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetEnabledSmuFeaturesHigh),
  68         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask),
  69         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit),
  70         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh),
  71         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow),
  72         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh),
  73         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow),
  74         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram),
  75         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu),
  76         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable),
  77         MSG_MAP(UseBackupPPTable,               PPSMC_MSG_UseBackupPPTable),
  78         MSG_MAP(RunBtc,                         PPSMC_MSG_RunBtc),
  79         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco),
  80         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq),
  81         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq),
  82         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq),
  83         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq),
  84         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq),
  85         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq),
  86         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex),
  87         MSG_MAP(SetMemoryChannelConfig,         PPSMC_MSG_SetMemoryChannelConfig),
  88         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode),
  89         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh),
  90         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow),
  91         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters),
  92         MSG_MAP(SetMinDeepSleepDcefclk,         PPSMC_MSG_SetMinDeepSleepDcefclk),
  93         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt),
  94         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource),
  95         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch),
  96         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps),
  97         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload),
  98         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh),
  99         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow),
 100         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize),
 101         MSG_MAP(ConfigureGfxDidt,               PPSMC_MSG_ConfigureGfxDidt),
 102         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_NumOfDisplays),
 103         MSG_MAP(SetSystemVirtualDramAddrHigh,   PPSMC_MSG_SetSystemVirtualDramAddrHigh),
 104         MSG_MAP(SetSystemVirtualDramAddrLow,    PPSMC_MSG_SetSystemVirtualDramAddrLow),
 105         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff),
 106         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff),
 107         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit),
 108         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq),
 109         MSG_MAP(GetDebugData,                   PPSMC_MSG_GetDebugData),
 110         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco),
 111         MSG_MAP(PrepareMp1ForReset,             PPSMC_MSG_PrepareMp1ForReset),
 112         MSG_MAP(PrepareMp1ForShutdown,          PPSMC_MSG_PrepareMp1ForShutdown),
 113         MSG_MAP(PowerUpVcn,             PPSMC_MSG_PowerUpVcn),
 114         MSG_MAP(PowerDownVcn,           PPSMC_MSG_PowerDownVcn),
 115         MSG_MAP(PowerUpJpeg,            PPSMC_MSG_PowerUpJpeg),
 116         MSG_MAP(PowerDownJpeg,          PPSMC_MSG_PowerDownJpeg),
 117         MSG_MAP(BacoAudioD3PME,         PPSMC_MSG_BacoAudioD3PME),
 118         MSG_MAP(ArmD3,                  PPSMC_MSG_ArmD3),
 119 };
 120
 121 static int navi10_clk_map[SMU_CLK_COUNT] = {
 122         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 123         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 124         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 125         CLK_MAP(FCLK, PPCLK_SOCCLK),
 126         CLK_MAP(UCLK, PPCLK_UCLK),
 127         CLK_MAP(MCLK, PPCLK_UCLK),
 128         CLK_MAP(DCLK, PPCLK_DCLK),
 129         CLK_MAP(VCLK, PPCLK_VCLK),
 130         CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
 131         CLK_MAP(DISPCLK, PPCLK_DISPCLK),
 132         CLK_MAP(PIXCLK, PPCLK_PIXCLK),
 133         CLK_MAP(PHYCLK, PPCLK_PHYCLK),
 134 };
 135
 136 static int navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
 137         FEA_MAP(DPM_PREFETCHER),
 138         FEA_MAP(DPM_GFXCLK),
 139         FEA_MAP(DPM_GFX_PACE),
 140         FEA_MAP(DPM_UCLK),
 141         FEA_MAP(DPM_SOCCLK),
 142         FEA_MAP(DPM_MP0CLK),
 143         FEA_MAP(DPM_LINK),
 144         FEA_MAP(DPM_DCEFCLK),
 145         FEA_MAP(MEM_VDDCI_SCALING),
 146         FEA_MAP(MEM_MVDD_SCALING),
 147         FEA_MAP(DS_GFXCLK),
 148         FEA_MAP(DS_SOCCLK),
 149         FEA_MAP(DS_LCLK),
 150         FEA_MAP(DS_DCEFCLK),
 151         FEA_MAP(DS_UCLK),
 152         FEA_MAP(GFX_ULV),
 153         FEA_MAP(FW_DSTATE),
 154         FEA_MAP(GFXOFF),
 155         FEA_MAP(BACO),
 156         FEA_MAP(VCN_PG),
 157         FEA_MAP(JPEG_PG),
 158         FEA_MAP(USB_PG),
 159         FEA_MAP(RSMU_SMN_CG),
 160         FEA_MAP(PPT),
 161         FEA_MAP(TDC),
 162         FEA_MAP(GFX_EDC),
 163         FEA_MAP(APCC_PLUS),
 164         FEA_MAP(GTHR),
 165         FEA_MAP(ACDC),
 166         FEA_MAP(VR0HOT),
 167         FEA_MAP(VR1HOT),
 168         FEA_MAP(FW_CTF),
 169         FEA_MAP(FAN_CONTROL),
 170         FEA_MAP(THERMAL),
 171         FEA_MAP(GFX_DCS),
 172         FEA_MAP(RM),
 173         FEA_MAP(LED_DISPLAY),
 174         FEA_MAP(GFX_SS),
 175         FEA_MAP(OUT_OF_BAND_MONITOR),
 176         FEA_MAP(TEMP_DEPENDENT_VMIN),
 177         FEA_MAP(MMHUB_PG),
 178         FEA_MAP(ATHUB_PG),
 179 };
 180
 181 static int navi10_table_map[SMU_TABLE_COUNT] = {
 182         TAB_MAP(PPTABLE),
 183         TAB_MAP(WATERMARKS),
 184         TAB_MAP(AVFS),
 185         TAB_MAP(AVFS_PSM_DEBUG),
 186         TAB_MAP(AVFS_FUSE_OVERRIDE),
 187         TAB_MAP(PMSTATUSLOG),
 188         TAB_MAP(SMU_METRICS),
 189         TAB_MAP(DRIVER_SMU_CONFIG),
 190         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 191         TAB_MAP(OVERDRIVE),
 192         TAB_MAP(I2C_COMMANDS),
 193         TAB_MAP(PACE),
 194 };
 195
 196 static int navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 197         PWR_MAP(AC),
 198         PWR_MAP(DC),
 199 };
 200
 201 static int navi10_workload_map[] = {
 202         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 203         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 204         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 205         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 206         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 207         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_CUSTOM_BIT),
 208         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 209 };
 210
 211 static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 212 {
 213         int val;
 214         if (index > SMU_MSG_MAX_COUNT)
 215                 return -EINVAL;
 216
 217         val = navi10_message_map[index];
 218         if (val > PPSMC_Message_Count)
 219                 return -EINVAL;
 220
 221         return val;
 222 }
 223
 224 static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 225 {
 226         int val;
 227         if (index >= SMU_CLK_COUNT)
 228                 return -EINVAL;
 229
 230         val = navi10_clk_map[index];
 231         if (val >= PPCLK_COUNT)
 232                 return -EINVAL;
 233
 234         return val;
 235 }
 236
 237 static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 238 {
 239         int val;
 240         if (index >= SMU_FEATURE_COUNT)
 241                 return -EINVAL;
 242
 243         val = navi10_feature_mask_map[index];
 244         if (val > 64)
 245                 return -EINVAL;
 246
 247         return val;
 248 }
 249
 250 static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
 251 {
 252         int val;
 253         if (index >= SMU_TABLE_COUNT)
 254                 return -EINVAL;
 255
 256         val = navi10_table_map[index];
 257         if (val >= TABLE_COUNT)
 258                 return -EINVAL;
 259
 260         return val;
 261 }
 262
 263 static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 264 {
 265         int val;
 266         if (index >= SMU_POWER_SOURCE_COUNT)
 267                 return -EINVAL;
 268
 269         val = navi10_pwr_src_map[index];
 270         if (val >= POWER_SOURCE_COUNT)
 271                 return -EINVAL;
 272
 273         return val;
 274 }
 275
 276
 277 static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 278 {
 279         int val;
 280         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 281                 return -EINVAL;
 282
 283         val = navi10_workload_map[profile];
 284
 285         return val;
 286 }
 287
 288 static bool is_asic_secure(struct smu_context *smu)
 289 {
 290         struct amdgpu_device *adev = smu->adev;
 291         bool is_secure = true;
 292         uint32_t mp0_fw_intf;
 293
 294         mp0_fw_intf = RREG32_PCIE(MP0_Public |
 295                                    (smnMP0_FW_INTF & 0xffffffff));
 296
 297         if (!(mp0_fw_intf & (1 << 19)))
 298                 is_secure = false;
 299
 300         return is_secure;
 301 }
 302
 303 static int
 304 navi10_get_allowed_feature_mask(struct smu_context *smu,
 305                                   uint32_t *feature_mask, uint32_t num)
 306 {
 307         struct amdgpu_device *adev = smu->adev;
 308
 309         if (num > 2)
 310                 return -EINVAL;
 311
 312         memset(feature_mask, 0, sizeof(uint32_t) * num);
 313
 314         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 315                                 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
 316                                 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
 317                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 318                                 | FEATURE_MASK(FEATURE_DPM_LINK_BIT)
 319                                 | FEATURE_MASK(FEATURE_GFX_ULV_BIT)
 320                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 321                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 322                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 323                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 324                                 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
 325                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 326                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 327                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 328                                 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
 329                                 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
 330                                 | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT)
 331                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 332                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 333                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 334                                 | FEATURE_MASK(FEATURE_ACDC_BIT)
 335                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 336                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 337                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT);
 338
 339         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 340                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 341                                 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 342                                 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 343
 344         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 345                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 346                 /* TODO: remove it once fw fix the bug */
 347                 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
 348         }
 349
 350         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 351                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 352
 353         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 354                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 355
 356         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
 357                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
 358
 359         /* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
 360         if (is_asic_secure(smu)) {
 361                 /* only for navi10 A0 */
 362                 if ((adev->asic_type == CHIP_NAVI10) &&
 363                         (adev->rev_id == 0)) {
 364                         *(uint64_t *)feature_mask &=
 365                                         ~(FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 366                                           | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 367                                           | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT));
 368                         *(uint64_t *)feature_mask &=
 369                                         ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
 370                 }
 371         }
 372
 373         return 0;
 374 }
 375
 376 static int navi10_check_powerplay_table(struct smu_context *smu)
 377 {
 378         return 0;
 379 }
 380
 381 static int navi10_append_powerplay_table(struct smu_context *smu)
 382 {
 383         struct amdgpu_device *adev = smu->adev;
 384         struct smu_table_context *table_context = &smu->smu_table;
 385         PPTable_t *smc_pptable = table_context->driver_pptable;
 386         struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
 387         int index, ret;
 388
 389         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 390                                            smc_dpm_info);
 391
 392         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 393                                       (uint8_t **)&smc_dpm_table);
 394         if (ret)
 395                 return ret;
 396
 397         memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 398                sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS);
 399
 400         /* SVI2 Board Parameters */
 401         smc_pptable->MaxVoltageStepGfx = smc_dpm_table->MaxVoltageStepGfx;
 402         smc_pptable->MaxVoltageStepSoc = smc_dpm_table->MaxVoltageStepSoc;
 403         smc_pptable->VddGfxVrMapping = smc_dpm_table->VddGfxVrMapping;
 404         smc_pptable->VddSocVrMapping = smc_dpm_table->VddSocVrMapping;
 405         smc_pptable->VddMem0VrMapping = smc_dpm_table->VddMem0VrMapping;
 406         smc_pptable->VddMem1VrMapping = smc_dpm_table->VddMem1VrMapping;
 407         smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->GfxUlvPhaseSheddingMask;
 408         smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->SocUlvPhaseSheddingMask;
 409         smc_pptable->ExternalSensorPresent = smc_dpm_table->ExternalSensorPresent;
 410         smc_pptable->Padding8_V = smc_dpm_table->Padding8_V;
 411
 412         /* Telemetry Settings */
 413         smc_pptable->GfxMaxCurrent = smc_dpm_table->GfxMaxCurrent;
 414         smc_pptable->GfxOffset = smc_dpm_table->GfxOffset;
 415         smc_pptable->Padding_TelemetryGfx = smc_dpm_table->Padding_TelemetryGfx;
 416         smc_pptable->SocMaxCurrent = smc_dpm_table->SocMaxCurrent;
 417         smc_pptable->SocOffset = smc_dpm_table->SocOffset;
 418         smc_pptable->Padding_TelemetrySoc = smc_dpm_table->Padding_TelemetrySoc;
 419         smc_pptable->Mem0MaxCurrent = smc_dpm_table->Mem0MaxCurrent;
 420         smc_pptable->Mem0Offset = smc_dpm_table->Mem0Offset;
 421         smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->Padding_TelemetryMem0;
 422         smc_pptable->Mem1MaxCurrent = smc_dpm_table->Mem1MaxCurrent;
 423         smc_pptable->Mem1Offset = smc_dpm_table->Mem1Offset;
 424         smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->Padding_TelemetryMem1;
 425
 426         /* GPIO Settings */
 427         smc_pptable->AcDcGpio = smc_dpm_table->AcDcGpio;
 428         smc_pptable->AcDcPolarity = smc_dpm_table->AcDcPolarity;
 429         smc_pptable->VR0HotGpio = smc_dpm_table->VR0HotGpio;
 430         smc_pptable->VR0HotPolarity = smc_dpm_table->VR0HotPolarity;
 431         smc_pptable->VR1HotGpio = smc_dpm_table->VR1HotGpio;
 432         smc_pptable->VR1HotPolarity = smc_dpm_table->VR1HotPolarity;
 433         smc_pptable->GthrGpio = smc_dpm_table->GthrGpio;
 434         smc_pptable->GthrPolarity = smc_dpm_table->GthrPolarity;
 435
 436         /* LED Display Settings */
 437         smc_pptable->LedPin0 = smc_dpm_table->LedPin0;
 438         smc_pptable->LedPin1 = smc_dpm_table->LedPin1;
 439         smc_pptable->LedPin2 = smc_dpm_table->LedPin2;
 440         smc_pptable->padding8_4 = smc_dpm_table->padding8_4;
 441
 442         /* GFXCLK PLL Spread Spectrum */
 443         smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->PllGfxclkSpreadEnabled;
 444         smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->PllGfxclkSpreadPercent;
 445         smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->PllGfxclkSpreadFreq;
 446
 447         /* GFXCLK DFLL Spread Spectrum */
 448         smc_pptable->DfllGfxclkSpreadEnabled = smc_dpm_table->DfllGfxclkSpreadEnabled;
 449         smc_pptable->DfllGfxclkSpreadPercent = smc_dpm_table->DfllGfxclkSpreadPercent;
 450         smc_pptable->DfllGfxclkSpreadFreq = smc_dpm_table->DfllGfxclkSpreadFreq;
 451
 452         /* UCLK Spread Spectrum */
 453         smc_pptable->UclkSpreadEnabled = smc_dpm_table->UclkSpreadEnabled;
 454         smc_pptable->UclkSpreadPercent = smc_dpm_table->UclkSpreadPercent;
 455         smc_pptable->UclkSpreadFreq = smc_dpm_table->UclkSpreadFreq;
 456
 457         /* SOCCLK Spread Spectrum */
 458         smc_pptable->SoclkSpreadEnabled = smc_dpm_table->SoclkSpreadEnabled;
 459         smc_pptable->SocclkSpreadPercent = smc_dpm_table->SocclkSpreadPercent;
 460         smc_pptable->SocclkSpreadFreq = smc_dpm_table->SocclkSpreadFreq;
 461
 462         /* Total board power */
 463         smc_pptable->TotalBoardPower = smc_dpm_table->TotalBoardPower;
 464         smc_pptable->BoardPadding = smc_dpm_table->BoardPadding;
 465
 466         /* Mvdd Svi2 Div Ratio Setting */
 467         smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
 468
 469         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 470                 /* TODO: remove it once SMU fw fix it */
 471                 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
 472         }
 473
 474         return 0;
 475 }
 476
 477 static int navi10_store_powerplay_table(struct smu_context *smu)
 478 {
 479         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 480         struct smu_table_context *table_context = &smu->smu_table;
 481         struct smu_baco_context *smu_baco = &smu->smu_baco;
 482
 483         if (!table_context->power_play_table)
 484                 return -EINVAL;
 485
 486         powerplay_table = table_context->power_play_table;
 487
 488         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 489                sizeof(PPTable_t));
 490
 491         table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
 492
 493         mutex_lock(&smu_baco->mutex);
 494         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 495             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 496                 smu_baco->platform_support = true;
 497         mutex_unlock(&smu_baco->mutex);
 498
 499         return 0;
 500 }
 501
 502 static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
 503 {
 504         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 505                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 506         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 507                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 508         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 509                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 510         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 511                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 512         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 513                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 514         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 515                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 516                        AMDGPU_GEM_DOMAIN_VRAM);
 517
 518         return 0;
 519 }
 520
 521 static int navi10_allocate_dpm_context(struct smu_context *smu)
 522 {
 523         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 524
 525         if (smu_dpm->dpm_context)
 526                 return -EINVAL;
 527
 528         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 529                                        GFP_KERNEL);
 530         if (!smu_dpm->dpm_context)
 531                 return -ENOMEM;
 532
 533         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 534
 535         return 0;
 536 }
 537
 538 static int navi10_set_default_dpm_table(struct smu_context *smu)
 539 {
 540         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 541         struct smu_table_context *table_context = &smu->smu_table;
 542         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 543         PPTable_t *driver_ppt = NULL;
 544
 545         driver_ppt = table_context->driver_pptable;
 546
 547         dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
 548         dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
 549
 550         dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
 551         dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
 552
 553         dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
 554         dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
 555
 556         dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
 557         dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
 558
 559         dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
 560         dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
 561
 562         dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
 563         dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
 564
 565         dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
 566         dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
 567
 568         dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
 569         dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
 570
 571         dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
 572         dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
 573
 574         return 0;
 575 }
 576
 577 static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
 578 {
 579         int ret = 0;
 580         struct smu_power_context *smu_power = &smu->smu_power;
 581         struct smu_power_gate *power_gate = &smu_power->power_gate;
 582
 583         if (enable && power_gate->uvd_gated) {
 584                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
 585                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
 586                         if (ret)
 587                                 return ret;
 588                 }
 589                 power_gate->uvd_gated = false;
 590         } else {
 591                 if (!enable && !power_gate->uvd_gated) {
 592                         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
 593                                 ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
 594                                 if (ret)
 595                                         return ret;
 596                         }
 597                         power_gate->uvd_gated = true;
 598                 }
 599         }
 600
 601         return 0;
 602 }
 603
 604 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
 605                                        enum smu_clk_type clk_type,
 606                                        uint32_t *value)
 607 {
 608         static SmuMetrics_t metrics;
 609         int ret = 0, clk_id = 0;
 610
 611         if (!value)
 612                 return -EINVAL;
 613
 614         memset(&metrics, 0, sizeof(metrics));
 615
 616         ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false);
 617         if (ret)
 618                 return ret;
 619
 620         clk_id = smu_clk_get_index(smu, clk_type);
 621         if (clk_id < 0)
 622                 return clk_id;
 623
 624         *value = metrics.CurrClock[clk_id];
 625
 626         return ret;
 627 }
 628
 629 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 630 {
 631         PPTable_t *pptable = smu->smu_table.driver_pptable;
 632         DpmDescriptor_t *dpm_desc = NULL;
 633         uint32_t clk_index = 0;
 634
 635         clk_index = smu_clk_get_index(smu, clk_type);
 636         dpm_desc = &pptable->DpmDescriptor[clk_index];
 637
 638         /* 0 - Fine grained DPM, 1 - Discrete DPM */
 639         return dpm_desc->SnapToDiscrete == 0 ? true : false;
 640 }
 641
 642 static int navi10_print_clk_levels(struct smu_context *smu,
 643                         enum smu_clk_type clk_type, char *buf)
 644 {
 645         int i, size = 0, ret = 0;
 646         uint32_t cur_value = 0, value = 0, count = 0;
 647         uint32_t freq_values[3] = {0};
 648         uint32_t mark_index = 0;
 649
 650         switch (clk_type) {
 651         case SMU_GFXCLK:
 652         case SMU_SCLK:
 653         case SMU_SOCCLK:
 654         case SMU_MCLK:
 655         case SMU_UCLK:
 656         case SMU_FCLK:
 657         case SMU_DCEFCLK:
 658                 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
 659                 if (ret)
 660                         return size;
 661
 662                 /* 10KHz -> MHz */
 663                 cur_value = cur_value / 100;
 664
 665                 ret = smu_get_dpm_level_count(smu, clk_type, &count);
 666                 if (ret)
 667                         return size;
 668
 669                 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
 670                         for (i = 0; i < count; i++) {
 671                                 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
 672                                 if (ret)
 673                                         return size;
 674
 675                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 676                                                 cur_value == value ? "*" : "");
 677                         }
 678                 } else {
 679                         ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
 680                         if (ret)
 681                                 return size;
 682                         ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
 683                         if (ret)
 684                                 return size;
 685
 686                         freq_values[1] = cur_value;
 687                         mark_index = cur_value == freq_values[0] ? 0 :
 688                                      cur_value == freq_values[2] ? 2 : 1;
 689                         if (mark_index != 1)
 690                                 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
 691
 692                         for (i = 0; i < 3; i++) {
 693                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
 694                                                 i == mark_index ? "*" : "");
 695                         }
 696
 697                 }
 698                 break;
 699         default:
 700                 break;
 701         }
 702
 703         return size;
 704 }
 705
 706 static int navi10_force_clk_levels(struct smu_context *smu,
 707                                    enum smu_clk_type clk_type, uint32_t mask)
 708 {
 709
 710         int ret = 0, size = 0;
 711         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
 712
 713         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 714         soft_max_level = mask ? (fls(mask) - 1) : 0;
 715
 716         switch (clk_type) {
 717         case SMU_GFXCLK:
 718         case SMU_SCLK:
 719         case SMU_SOCCLK:
 720         case SMU_MCLK:
 721         case SMU_UCLK:
 722         case SMU_DCEFCLK:
 723         case SMU_FCLK:
 724                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
 725                 if (ret)
 726                         return size;
 727
 728                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
 729                 if (ret)
 730                         return size;
 731
 732                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
 733                 if (ret)
 734                         return size;
 735                 break;
 736         default:
 737                 break;
 738         }
 739
 740         return size;
 741 }
 742
 743 static int navi10_populate_umd_state_clk(struct smu_context *smu)
 744 {
 745         int ret = 0;
 746         uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
 747
 748         ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL);
 749         if (ret)
 750                 return ret;
 751
 752         smu->pstate_sclk = min_sclk_freq * 100;
 753
 754         ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL);
 755         if (ret)
 756                 return ret;
 757
 758         smu->pstate_mclk = min_mclk_freq * 100;
 759
 760         return ret;
 761 }
 762
 763 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
 764                                                  enum smu_clk_type clk_type,
 765                                                  struct pp_clock_levels_with_latency *clocks)
 766 {
 767         int ret = 0, i = 0;
 768         uint32_t level_count = 0, freq = 0;
 769
 770         switch (clk_type) {
 771         case SMU_GFXCLK:
 772         case SMU_DCEFCLK:
 773         case SMU_SOCCLK:
 774                 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
 775                 if (ret)
 776                         return ret;
 777
 778                 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
 779                 clocks->num_levels = level_count;
 780
 781                 for (i = 0; i < level_count; i++) {
 782                         ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
 783                         if (ret)
 784                                 return ret;
 785
 786                         clocks->data[i].clocks_in_khz = freq * 1000;
 787                         clocks->data[i].latency_in_us = 0;
 788                 }
 789                 break;
 790         default:
 791                 break;
 792         }
 793
 794         return ret;
 795 }
 796
 797 static int navi10_pre_display_config_changed(struct smu_context *smu)
 798 {
 799         int ret = 0;
 800         uint32_t max_freq = 0;
 801
 802         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
 803         if (ret)
 804                 return ret;
 805
 806         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 807                 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq);
 808                 if (ret)
 809                         return ret;
 810                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
 811                 if (ret)
 812                         return ret;
 813         }
 814
 815         return ret;
 816 }
 817
 818 static int navi10_display_config_changed(struct smu_context *smu)
 819 {
 820         int ret = 0;
 821
 822         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 823             !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 824                 ret = smu_write_watermarks_table(smu);
 825                 if (ret)
 826                         return ret;
 827
 828                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
 829         }
 830
 831         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 832             smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
 833             smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 834                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
 835                                                   smu->display_config->num_display);
 836                 if (ret)
 837                         return ret;
 838         }
 839
 840         return ret;
 841 }
 842
 843 static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
 844 {
 845         int ret = 0, i = 0;
 846         uint32_t min_freq, max_freq, force_freq;
 847         enum smu_clk_type clk_type;
 848
 849         enum smu_clk_type clks[] = {
 850                 SMU_GFXCLK,
 851                 SMU_MCLK,
 852                 SMU_SOCCLK,
 853         };
 854
 855         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 856                 clk_type = clks[i];
 857                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
 858                 if (ret)
 859                         return ret;
 860
 861                 force_freq = highest ? max_freq : min_freq;
 862                 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq);
 863                 if (ret)
 864                         return ret;
 865         }
 866
 867         return ret;
 868 }
 869
 870 static int navi10_unforce_dpm_levels(struct smu_context *smu)
 871 {
 872         int ret = 0, i = 0;
 873         uint32_t min_freq, max_freq;
 874         enum smu_clk_type clk_type;
 875
 876         enum smu_clk_type clks[] = {
 877                 SMU_GFXCLK,
 878                 SMU_MCLK,
 879                 SMU_SOCCLK,
 880         };
 881
 882         for (i = 0; i < ARRAY_SIZE(clks); i++) {
 883                 clk_type = clks[i];
 884                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
 885                 if (ret)
 886                         return ret;
 887
 888                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
 889                 if (ret)
 890                         return ret;
 891         }
 892
 893         return ret;
 894 }
 895
 896 static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
 897 {
 898         int ret = 0;
 899         SmuMetrics_t metrics;
 900
 901         if (!value)
 902                 return -EINVAL;
 903
 904         ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics,
 905                                false);
 906         if (ret)
 907                 return ret;
 908
 909         *value = metrics.AverageSocketPower << 8;
 910
 911         return 0;
 912 }
 913
 914 static int navi10_get_current_activity_percent(struct smu_context *smu,
 915                                                enum amd_pp_sensors sensor,
 916                                                uint32_t *value)
 917 {
 918         int ret = 0;
 919         SmuMetrics_t metrics;
 920
 921         if (!value)
 922                 return -EINVAL;
 923
 924         msleep(1);
 925
 926         ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 927                                (void *)&metrics, false);
 928         if (ret)
 929                 return ret;
 930
 931         switch (sensor) {
 932         case AMDGPU_PP_SENSOR_GPU_LOAD:
 933                 *value = metrics.AverageGfxActivity;
 934                 break;
 935         case AMDGPU_PP_SENSOR_MEM_LOAD:
 936                 *value = metrics.AverageUclkActivity;
 937                 break;
 938         default:
 939                 pr_err("Invalid sensor for retrieving clock activity\n");
 940                 return -EINVAL;
 941         }
 942
 943         return 0;
 944 }
 945
 946 static bool navi10_is_dpm_running(struct smu_context *smu)
 947 {
 948         int ret = 0;
 949         uint32_t feature_mask[2];
 950         unsigned long feature_enabled;
 951         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 952         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
 953                            ((uint64_t)feature_mask[1] << 32));
 954         return !!(feature_enabled & SMC_DPM_FEATURE);
 955 }
 956
 957 static int navi10_get_fan_speed(struct smu_context *smu, uint16_t *value)
 958 {
 959         SmuMetrics_t metrics;
 960         int ret = 0;
 961
 962         if (!value)
 963                 return -EINVAL;
 964
 965         memset(&metrics, 0, sizeof(metrics));
 966
 967         ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 968                                (void *)&metrics, false);
 969         if (ret)
 970                 return ret;
 971
 972         *value = metrics.CurrFanSpeed;
 973
 974         return ret;
 975 }
 976
 977 static int navi10_get_fan_speed_percent(struct smu_context *smu,
 978                                         uint32_t *speed)
 979 {
 980         int ret = 0;
 981         uint32_t percent = 0;
 982         uint16_t current_rpm;
 983         PPTable_t *pptable = smu->smu_table.driver_pptable;
 984
 985         ret = navi10_get_fan_speed(smu, &current_rpm);
 986         if (ret)
 987                 return ret;
 988
 989         percent = current_rpm * 100 / pptable->FanMaximumRpm;
 990         *speed = percent > 100 ? 100 : percent;
 991
 992         return ret;
 993 }
 994
 995 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
 996 {
 997         DpmActivityMonitorCoeffInt_t activity_monitor;
 998         uint32_t i, size = 0;
 999         uint16_t workload_type = 0;
1000         static const char *profile_name[] = {
1001                                         "BOOTUP_DEFAULT",
1002                                         "3D_FULL_SCREEN",
1003                                         "POWER_SAVING",
1004                                         "VIDEO",
1005                                         "VR",
1006                                         "COMPUTE",
1007                                         "CUSTOM"};
1008         static const char *title[] = {
1009                         "PROFILE_INDEX(NAME)",
1010                         "CLOCK_TYPE(NAME)",
1011                         "FPS",
1012                         "MinFreqType",
1013                         "MinActiveFreqType",
1014                         "MinActiveFreq",
1015                         "BoosterFreqType",
1016                         "BoosterFreq",
1017                         "PD_Data_limit_c",
1018                         "PD_Data_error_coeff",
1019                         "PD_Data_error_rate_coeff"};
1020         int result = 0;
1021
1022         if (!buf)
1023                 return -EINVAL;
1024
1025         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1026                         title[0], title[1], title[2], title[3], title[4], title[5],
1027                         title[6], title[7], title[8], title[9], title[10]);
1028
1029         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1030                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1031                 workload_type = smu_workload_get_type(smu, i);
1032                 result = smu_update_table(smu,
1033                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1034                                           (void *)(&activity_monitor), false);
1035                 if (result) {
1036                         pr_err("[%s] Failed to get activity monitor!", __func__);
1037                         return result;
1038                 }
1039
1040                 size += sprintf(buf + size, "%2d %14s%s:\n",
1041                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1042
1043                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1044                         " ",
1045                         0,
1046                         "GFXCLK",
1047                         activity_monitor.Gfx_FPS,
1048                         activity_monitor.Gfx_MinFreqStep,
1049                         activity_monitor.Gfx_MinActiveFreqType,
1050                         activity_monitor.Gfx_MinActiveFreq,
1051                         activity_monitor.Gfx_BoosterFreqType,
1052                         activity_monitor.Gfx_BoosterFreq,
1053                         activity_monitor.Gfx_PD_Data_limit_c,
1054                         activity_monitor.Gfx_PD_Data_error_coeff,
1055                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1056
1057                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1058                         " ",
1059                         1,
1060                         "SOCCLK",
1061                         activity_monitor.Soc_FPS,
1062                         activity_monitor.Soc_MinFreqStep,
1063                         activity_monitor.Soc_MinActiveFreqType,
1064                         activity_monitor.Soc_MinActiveFreq,
1065                         activity_monitor.Soc_BoosterFreqType,
1066                         activity_monitor.Soc_BoosterFreq,
1067                         activity_monitor.Soc_PD_Data_limit_c,
1068                         activity_monitor.Soc_PD_Data_error_coeff,
1069                         activity_monitor.Soc_PD_Data_error_rate_coeff);
1070
1071                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1072                         " ",
1073                         2,
1074                         "MEMLK",
1075                         activity_monitor.Mem_FPS,
1076                         activity_monitor.Mem_MinFreqStep,
1077                         activity_monitor.Mem_MinActiveFreqType,
1078                         activity_monitor.Mem_MinActiveFreq,
1079                         activity_monitor.Mem_BoosterFreqType,
1080                         activity_monitor.Mem_BoosterFreq,
1081                         activity_monitor.Mem_PD_Data_limit_c,
1082                         activity_monitor.Mem_PD_Data_error_coeff,
1083                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1084         }
1085
1086         return size;
1087 }
1088
1089 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1090 {
1091         DpmActivityMonitorCoeffInt_t activity_monitor;
1092         int workload_type, ret = 0;
1093
1094         smu->power_profile_mode = input[size];
1095
1096         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1097                 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1098                 return -EINVAL;
1099         }
1100
1101         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1102                 if (size < 0)
1103                         return -EINVAL;
1104
1105                 ret = smu_update_table(smu,
1106                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1107                                        (void *)(&activity_monitor), false);
1108                 if (ret) {
1109                         pr_err("[%s] Failed to get activity monitor!", __func__);
1110                         return ret;
1111                 }
1112
1113                 switch (input[0]) {
1114                 case 0: /* Gfxclk */
1115                         activity_monitor.Gfx_FPS = input[1];
1116                         activity_monitor.Gfx_MinFreqStep = input[2];
1117                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1118                         activity_monitor.Gfx_MinActiveFreq = input[4];
1119                         activity_monitor.Gfx_BoosterFreqType = input[5];
1120                         activity_monitor.Gfx_BoosterFreq = input[6];
1121                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1122                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1123                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1124                         break;
1125                 case 1: /* Socclk */
1126                         activity_monitor.Soc_FPS = input[1];
1127                         activity_monitor.Soc_MinFreqStep = input[2];
1128                         activity_monitor.Soc_MinActiveFreqType = input[3];
1129                         activity_monitor.Soc_MinActiveFreq = input[4];
1130                         activity_monitor.Soc_BoosterFreqType = input[5];
1131                         activity_monitor.Soc_BoosterFreq = input[6];
1132                         activity_monitor.Soc_PD_Data_limit_c = input[7];
1133                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
1134                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1135                         break;
1136                 case 2: /* Memlk */
1137                         activity_monitor.Mem_FPS = input[1];
1138                         activity_monitor.Mem_MinFreqStep = input[2];
1139                         activity_monitor.Mem_MinActiveFreqType = input[3];
1140                         activity_monitor.Mem_MinActiveFreq = input[4];
1141                         activity_monitor.Mem_BoosterFreqType = input[5];
1142                         activity_monitor.Mem_BoosterFreq = input[6];
1143                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1144                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1145                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1146                         break;
1147                 }
1148
1149                 ret = smu_update_table(smu,
1150                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1151                                        (void *)(&activity_monitor), true);
1152                 if (ret) {
1153                         pr_err("[%s] Failed to set activity monitor!", __func__);
1154                         return ret;
1155                 }
1156         }
1157
1158         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1159         workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1160         smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1161                                     1 << workload_type);
1162
1163         return ret;
1164 }
1165
1166 static int navi10_get_profiling_clk_mask(struct smu_context *smu,
1167                                          enum amd_dpm_forced_level level,
1168                                          uint32_t *sclk_mask,
1169                                          uint32_t *mclk_mask,
1170                                          uint32_t *soc_mask)
1171 {
1172         int ret = 0;
1173         uint32_t level_count = 0;
1174
1175         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1176                 if (sclk_mask)
1177                         *sclk_mask = 0;
1178         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1179                 if (mclk_mask)
1180                         *mclk_mask = 0;
1181         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1182                 if(sclk_mask) {
1183                         ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1184                         if (ret)
1185                                 return ret;
1186                         *sclk_mask = level_count - 1;
1187                 }
1188
1189                 if(mclk_mask) {
1190                         ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1191                         if (ret)
1192                                 return ret;
1193                         *mclk_mask = level_count - 1;
1194                 }
1195
1196                 if(soc_mask) {
1197                         ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1198                         if (ret)
1199                                 return ret;
1200                         *soc_mask = level_count - 1;
1201                 }
1202         }
1203
1204         return ret;
1205 }
1206
1207 static int navi10_notify_smc_dispaly_config(struct smu_context *smu)
1208 {
1209         struct smu_clocks min_clocks = {0};
1210         struct pp_display_clock_request clock_req;
1211         int ret = 0;
1212
1213         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1214         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1215         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1216
1217         if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1218                 clock_req.clock_type = amd_pp_dcef_clock;
1219                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1220                 if (!smu_display_clock_voltage_request(smu, &clock_req)) {
1221                         if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1222                                 ret = smu_send_smc_msg_with_param(smu,
1223                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1224                                                                   min_clocks.dcef_clock_in_sr/100);
1225                                 if (ret) {
1226                                         pr_err("Attempt to set divider for DCEFCLK Failed!");
1227                                         return ret;
1228                                 }
1229                         }
1230                 } else {
1231                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1232                 }
1233         }
1234
1235         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1236                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1237                 if (ret) {
1238                         pr_err("[%s] Set hard min uclk failed!", __func__);
1239                         return ret;
1240                 }
1241         }
1242
1243         return 0;
1244 }
1245
1246 static int navi10_set_watermarks_table(struct smu_context *smu,
1247                                        void *watermarks, struct
1248                                        dm_pp_wm_sets_with_clock_ranges_soc15
1249                                        *clock_ranges)
1250 {
1251         int i;
1252         Watermarks_t *table = watermarks;
1253
1254         if (!table || !clock_ranges)
1255                 return -EINVAL;
1256
1257         if (clock_ranges->num_wm_dmif_sets > 4 ||
1258             clock_ranges->num_wm_mcif_sets > 4)
1259                 return -EINVAL;
1260
1261         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1262                 table->WatermarkRow[1][i].MinClock =
1263                         cpu_to_le16((uint16_t)
1264                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1265                         1000));
1266                 table->WatermarkRow[1][i].MaxClock =
1267                         cpu_to_le16((uint16_t)
1268                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1269                         1000));
1270                 table->WatermarkRow[1][i].MinUclk =
1271                         cpu_to_le16((uint16_t)
1272                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1273                         1000));
1274                 table->WatermarkRow[1][i].MaxUclk =
1275                         cpu_to_le16((uint16_t)
1276                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1277                         1000));
1278                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1279                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1280         }
1281
1282         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1283                 table->WatermarkRow[0][i].MinClock =
1284                         cpu_to_le16((uint16_t)
1285                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1286                         1000));
1287                 table->WatermarkRow[0][i].MaxClock =
1288                         cpu_to_le16((uint16_t)
1289                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1290                         1000));
1291                 table->WatermarkRow[0][i].MinUclk =
1292                         cpu_to_le16((uint16_t)
1293                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1294                         1000));
1295                 table->WatermarkRow[0][i].MaxUclk =
1296                         cpu_to_le16((uint16_t)
1297                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1298                         1000));
1299                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1300                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1301         }
1302
1303         return 0;
1304 }
1305
1306 static int navi10_thermal_get_temperature(struct smu_context *smu,
1307                                              enum amd_pp_sensors sensor,
1308                                              uint32_t *value)
1309 {
1310         SmuMetrics_t metrics;
1311         int ret = 0;
1312
1313         if (!value)
1314                 return -EINVAL;
1315
1316         ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false);
1317         if (ret)
1318                 return ret;
1319
1320         switch (sensor) {
1321         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1322                 *value = metrics.TemperatureHotspot *
1323                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1324                 break;
1325         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1326                 *value = metrics.TemperatureEdge *
1327                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1328                 break;
1329         case AMDGPU_PP_SENSOR_MEM_TEMP:
1330                 *value = metrics.TemperatureMem *
1331                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1332                 break;
1333         default:
1334                 pr_err("Invalid sensor for retrieving temp\n");
1335                 return -EINVAL;
1336         }
1337
1338         return 0;
1339 }
1340
1341 static int navi10_read_sensor(struct smu_context *smu,
1342                                  enum amd_pp_sensors sensor,
1343                                  void *data, uint32_t *size)
1344 {
1345         int ret = 0;
1346         struct smu_table_context *table_context = &smu->smu_table;
1347         PPTable_t *pptable = table_context->driver_pptable;
1348
1349         switch (sensor) {
1350         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1351                 *(uint32_t *)data = pptable->FanMaximumRpm;
1352                 *size = 4;
1353                 break;
1354         case AMDGPU_PP_SENSOR_MEM_LOAD:
1355         case AMDGPU_PP_SENSOR_GPU_LOAD:
1356                 ret = navi10_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1357                 *size = 4;
1358                 break;
1359         case AMDGPU_PP_SENSOR_GPU_POWER:
1360                 ret = navi10_get_gpu_power(smu, (uint32_t *)data);
1361                 *size = 4;
1362                 break;
1363         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1364         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1365         case AMDGPU_PP_SENSOR_MEM_TEMP:
1366                 ret = navi10_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1367                 *size = 4;
1368                 break;
1369         default:
1370                 return -EINVAL;
1371         }
1372
1373         return ret;
1374 }
1375
1376 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1377 {
1378         uint32_t num_discrete_levels = 0;
1379         uint16_t *dpm_levels = NULL;
1380         uint16_t i = 0;
1381         struct smu_table_context *table_context = &smu->smu_table;
1382         PPTable_t *driver_ppt = NULL;
1383
1384         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1385                 return -EINVAL;
1386
1387         driver_ppt = table_context->driver_pptable;
1388         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1389         dpm_levels = driver_ppt->FreqTableUclk;
1390
1391         if (num_discrete_levels == 0 || dpm_levels == NULL)
1392                 return -EINVAL;
1393
1394         *num_states = num_discrete_levels;
1395         for (i = 0; i < num_discrete_levels; i++) {
1396                 /* convert to khz */
1397                 *clocks_in_khz = (*dpm_levels) * 1000;
1398                 clocks_in_khz++;
1399                 dpm_levels++;
1400         }
1401
1402         return 0;
1403 }
1404
1405 static int navi10_get_ppfeature_status(struct smu_context *smu,
1406                                        char *buf)
1407 {
1408         static const char *ppfeature_name[] = {
1409                                 "DPM_PREFETCHER",
1410                                 "DPM_GFXCLK",
1411                                 "DPM_GFX_PACE",
1412                                 "DPM_UCLK",
1413                                 "DPM_SOCCLK",
1414                                 "DPM_MP0CLK",
1415                                 "DPM_LINK",
1416                                 "DPM_DCEFCLK",
1417                                 "MEM_VDDCI_SCALING",
1418                                 "MEM_MVDD_SCALING",
1419                                 "DS_GFXCLK",
1420                                 "DS_SOCCLK",
1421                                 "DS_LCLK",
1422                                 "DS_DCEFCLK",
1423                                 "DS_UCLK",
1424                                 "GFX_ULV",
1425                                 "FW_DSTATE",
1426                                 "GFXOFF",
1427                                 "BACO",
1428                                 "VCN_PG",
1429                                 "JPEG_PG",
1430                                 "USB_PG",
1431                                 "RSMU_SMN_CG",
1432                                 "PPT",
1433                                 "TDC",
1434                                 "GFX_EDC",
1435                                 "APCC_PLUS",
1436                                 "GTHR",
1437                                 "ACDC",
1438                                 "VR0HOT",
1439                                 "VR1HOT",
1440                                 "FW_CTF",
1441                                 "FAN_CONTROL",
1442                                 "THERMAL",
1443                                 "GFX_DCS",
1444                                 "RM",
1445                                 "LED_DISPLAY",
1446                                 "GFX_SS",
1447                                 "OUT_OF_BAND_MONITOR",
1448                                 "TEMP_DEPENDENT_VMIN",
1449                                 "MMHUB_PG",
1450                                 "ATHUB_PG"};
1451         static const char *output_title[] = {
1452                                 "FEATURES",
1453                                 "BITMASK",
1454                                 "ENABLEMENT"};
1455         uint64_t features_enabled;
1456         uint32_t feature_mask[2];
1457         int i;
1458         int ret = 0;
1459         int size = 0;
1460
1461         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1462         PP_ASSERT_WITH_CODE(!ret,
1463                         "[GetPPfeatureStatus] Failed to get enabled smc features!",
1464                         return ret);
1465         features_enabled = (uint64_t)feature_mask[0] |
1466                            (uint64_t)feature_mask[1] << 32;
1467
1468         size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
1469         size += sprintf(buf + size, "%-19s %-22s %s\n",
1470                                 output_title[0],
1471                                 output_title[1],
1472                                 output_title[2]);
1473         for (i = 0; i < (sizeof(ppfeature_name) / sizeof(ppfeature_name[0])); i++) {
1474                 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
1475                                         ppfeature_name[i],
1476                                         1ULL << i,
1477                                         (features_enabled & (1ULL << i)) ? "Y" : "N");
1478         }
1479
1480         return size;
1481 }
1482
1483 static int navi10_enable_smc_features(struct smu_context *smu,
1484                                       bool enabled,
1485                                       uint64_t feature_masks)
1486 {
1487         struct smu_feature *feature = &smu->smu_feature;
1488         uint32_t feature_low, feature_high;
1489         uint32_t feature_mask[2];
1490         int ret = 0;
1491
1492         feature_low = (uint32_t)(feature_masks & 0xFFFFFFFF);
1493         feature_high = (uint32_t)((feature_masks & 0xFFFFFFFF00000000ULL) >> 32);
1494
1495         if (enabled) {
1496                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
1497                                                   feature_low);
1498                 if (ret)
1499                         return ret;
1500                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
1501                                                   feature_high);
1502                 if (ret)
1503                         return ret;
1504         } else {
1505                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
1506                                                   feature_low);
1507                 if (ret)
1508                         return ret;
1509                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
1510                                                   feature_high);
1511                 if (ret)
1512                         return ret;
1513         }
1514
1515         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1516         if (ret)
1517                 return ret;
1518
1519         mutex_lock(&feature->mutex);
1520         bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
1521                     feature->feature_num);
1522         mutex_unlock(&feature->mutex);
1523
1524         return 0;
1525 }
1526
1527 static int navi10_set_ppfeature_status(struct smu_context *smu,
1528                                        uint64_t new_ppfeature_masks)
1529 {
1530         uint64_t features_enabled;
1531         uint32_t feature_mask[2];
1532         uint64_t features_to_enable;
1533         uint64_t features_to_disable;
1534         int ret = 0;
1535
1536         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1537         PP_ASSERT_WITH_CODE(!ret,
1538                         "[SetPPfeatureStatus] Failed to get enabled smc features!",
1539                         return ret);
1540         features_enabled = (uint64_t)feature_mask[0] |
1541                            (uint64_t)feature_mask[1] << 32;
1542
1543         features_to_disable =
1544                 features_enabled & ~new_ppfeature_masks;
1545         features_to_enable =
1546                 ~features_enabled & new_ppfeature_masks;
1547
1548         pr_debug("features_to_disable 0x%llx\n", features_to_disable);
1549         pr_debug("features_to_enable 0x%llx\n", features_to_enable);
1550
1551         if (features_to_disable) {
1552                 ret = navi10_enable_smc_features(smu, false, features_to_disable);
1553                 PP_ASSERT_WITH_CODE(!ret,
1554                                 "[SetPPfeatureStatus] Failed to disable smc features!",
1555                                 return ret);
1556         }
1557
1558         if (features_to_enable) {
1559                 ret = navi10_enable_smc_features(smu, true, features_to_enable);
1560                 PP_ASSERT_WITH_CODE(!ret,
1561                                 "[SetPPfeatureStatus] Failed to enable smc features!",
1562                                 return ret);
1563         }
1564
1565         return 0;
1566 }
1567
1568 static int navi10_set_peak_clock_by_device(struct smu_context *smu)
1569 {
1570         struct amdgpu_device *adev = smu->adev;
1571         int ret = 0;
1572         uint32_t sclk_freq = 0, uclk_freq = 0;
1573         uint32_t uclk_level = 0;
1574
1575         switch (adev->rev_id) {
1576         case 0xf0: /* XTX */
1577         case 0xc0:
1578                 sclk_freq = NAVI10_PEAK_SCLK_XTX;
1579                 break;
1580         case 0xf1: /* XT */
1581         case 0xc1:
1582                 sclk_freq = NAVI10_PEAK_SCLK_XT;
1583                 break;
1584         default: /* XL */
1585                 sclk_freq = NAVI10_PEAK_SCLK_XL;
1586                 break;
1587         }
1588
1589         ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_level);
1590         if (ret)
1591                 return ret;
1592         ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, uclk_level - 1, &uclk_freq);
1593         if (ret)
1594                 return ret;
1595
1596         ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
1597         if (ret)
1598                 return ret;
1599         ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
1600         if (ret)
1601                 return ret;
1602
1603         return ret;
1604 }
1605
1606 static int navi10_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1607 {
1608         int ret = 0;
1609
1610         switch (level) {
1611         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1612                 ret = navi10_set_peak_clock_by_device(smu);
1613                 break;
1614         default:
1615                 ret = -EINVAL;
1616                 break;
1617         }
1618
1619         return ret;
1620 }
1621
1622 static const struct pptable_funcs navi10_ppt_funcs = {
1623         .tables_init = navi10_tables_init,
1624         .alloc_dpm_context = navi10_allocate_dpm_context,
1625         .store_powerplay_table = navi10_store_powerplay_table,
1626         .check_powerplay_table = navi10_check_powerplay_table,
1627         .append_powerplay_table = navi10_append_powerplay_table,
1628         .get_smu_msg_index = navi10_get_smu_msg_index,
1629         .get_smu_clk_index = navi10_get_smu_clk_index,
1630         .get_smu_feature_index = navi10_get_smu_feature_index,
1631         .get_smu_table_index = navi10_get_smu_table_index,
1632         .get_smu_power_index = navi10_get_pwr_src_index,
1633         .get_workload_type = navi10_get_workload_type,
1634         .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
1635         .set_default_dpm_table = navi10_set_default_dpm_table,
1636         .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
1637         .get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
1638         .print_clk_levels = navi10_print_clk_levels,
1639         .force_clk_levels = navi10_force_clk_levels,
1640         .populate_umd_state_clk = navi10_populate_umd_state_clk,
1641         .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
1642         .pre_display_config_changed = navi10_pre_display_config_changed,
1643         .display_config_changed = navi10_display_config_changed,
1644         .notify_smc_dispaly_config = navi10_notify_smc_dispaly_config,
1645         .force_dpm_limit_value = navi10_force_dpm_limit_value,
1646         .unforce_dpm_levels = navi10_unforce_dpm_levels,
1647         .is_dpm_running = navi10_is_dpm_running,
1648         .get_fan_speed_percent = navi10_get_fan_speed_percent,
1649         .get_power_profile_mode = navi10_get_power_profile_mode,
1650         .set_power_profile_mode = navi10_set_power_profile_mode,
1651         .get_profiling_clk_mask = navi10_get_profiling_clk_mask,
1652         .set_watermarks_table = navi10_set_watermarks_table,
1653         .read_sensor = navi10_read_sensor,
1654         .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
1655         .get_ppfeature_status = navi10_get_ppfeature_status,
1656         .set_ppfeature_status = navi10_set_ppfeature_status,
1657         .set_performance_level = navi10_set_performance_level,
1658 };
1659
1660 void navi10_set_ppt_funcs(struct smu_context *smu)
1661 {
1662         struct smu_table_context *smu_table = &smu->smu_table;
1663
1664         smu->ppt_funcs = &navi10_ppt_funcs;
1665         smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
1666         smu_table->table_count = TABLE_COUNT;
1667 }