drivers/gpu/drm/amd/powerplay/navi10_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "atomfirmware.h"
  29 #include "amdgpu_atomfirmware.h"
  30 #include "smu_v11_0.h"
  31 #include "smu11_driver_if_navi10.h"
  32 #include "soc15_common.h"
  33 #include "atom.h"
  34 #include "navi10_ppt.h"
  35 #include "smu_v11_0_pptable.h"
  36 #include "smu_v11_0_ppsmc.h"
  37
  38 #define MSG_MAP(msg, index) \
  39         [SMU_MSG_##msg] = index
  40
  41 static int navi10_message_map[SMU_MSG_MAX_COUNT] = {
  42         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
  43         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
  44         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion),
  45         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow),
  46         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  47         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures),
  48         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures),
  49         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow),
  50         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh),
  51         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow),
  52         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh),
  53         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetEnabledSmuFeaturesLow),
  54         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetEnabledSmuFeaturesHigh),
  55         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask),
  56         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit),
  57         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh),
  58         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow),
  59         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh),
  60         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow),
  61         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram),
  62         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu),
  63         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable),
  64         MSG_MAP(UseBackupPPTable,               PPSMC_MSG_UseBackupPPTable),
  65         MSG_MAP(RunBtc,                         PPSMC_MSG_RunBtc),
  66         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco),
  67         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq),
  68         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq),
  69         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq),
  70         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq),
  71         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq),
  72         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq),
  73         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex),
  74         MSG_MAP(SetMemoryChannelConfig,         PPSMC_MSG_SetMemoryChannelConfig),
  75         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode),
  76         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh),
  77         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow),
  78         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters),
  79         MSG_MAP(SetMinDeepSleepDcefclk,         PPSMC_MSG_SetMinDeepSleepDcefclk),
  80         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt),
  81         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource),
  82         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch),
  83         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps),
  84         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload),
  85         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh),
  86         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow),
  87         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize),
  88         MSG_MAP(ConfigureGfxDidt,               PPSMC_MSG_ConfigureGfxDidt),
  89         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_NumOfDisplays),
  90         MSG_MAP(SetSystemVirtualDramAddrHigh,   PPSMC_MSG_SetSystemVirtualDramAddrHigh),
  91         MSG_MAP(SetSystemVirtualDramAddrLow,    PPSMC_MSG_SetSystemVirtualDramAddrLow),
  92         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff),
  93         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff),
  94         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit),
  95         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq),
  96         MSG_MAP(GetDebugData,                   PPSMC_MSG_GetDebugData),
  97         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco),
  98         MSG_MAP(PrepareMp1ForReset,             PPSMC_MSG_PrepareMp1ForReset),
  99         MSG_MAP(PrepareMp1ForShutdown,          PPSMC_MSG_PrepareMp1ForShutdown),
 100         MSG_MAP(PowerUpVcn,             PPSMC_MSG_PowerUpVcn),
 101         MSG_MAP(PowerDownVcn,           PPSMC_MSG_PowerDownVcn),
 102         MSG_MAP(PowerUpJpeg,            PPSMC_MSG_PowerUpJpeg),
 103         MSG_MAP(PowerDownJpeg,          PPSMC_MSG_PowerDownJpeg),
 104 };
 105
 106 static int navi10_clk_map[SMU_CLK_COUNT] = {
 107         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 108         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 109         CLK_MAP(UCLK, PPCLK_UCLK),
 110         CLK_MAP(DCLK, PPCLK_DCLK),
 111         CLK_MAP(VCLK, PPCLK_VCLK),
 112         CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
 113         CLK_MAP(DISPCLK, PPCLK_DISPCLK),
 114         CLK_MAP(PIXCLK, PPCLK_PIXCLK),
 115         CLK_MAP(PHYCLK, PPCLK_PHYCLK),
 116 };
 117
 118 static int navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
 119         FEA_MAP(DPM_PREFETCHER),
 120         FEA_MAP(DPM_GFXCLK),
 121         FEA_MAP(DPM_GFX_PACE),
 122         FEA_MAP(DPM_UCLK),
 123         FEA_MAP(DPM_SOCCLK),
 124         FEA_MAP(DPM_MP0CLK),
 125         FEA_MAP(DPM_LINK),
 126         FEA_MAP(DPM_DCEFCLK),
 127         FEA_MAP(MEM_VDDCI_SCALING),
 128         FEA_MAP(MEM_MVDD_SCALING),
 129         FEA_MAP(DS_GFXCLK),
 130         FEA_MAP(DS_SOCCLK),
 131         FEA_MAP(DS_LCLK),
 132         FEA_MAP(DS_DCEFCLK),
 133         FEA_MAP(DS_UCLK),
 134         FEA_MAP(GFX_ULV),
 135         FEA_MAP(FW_DSTATE),
 136         FEA_MAP(GFXOFF),
 137         FEA_MAP(BACO),
 138         FEA_MAP(VCN_PG),
 139         FEA_MAP(JPEG_PG),
 140         FEA_MAP(USB_PG),
 141         FEA_MAP(RSMU_SMN_CG),
 142         FEA_MAP(PPT),
 143         FEA_MAP(TDC),
 144         FEA_MAP(GFX_EDC),
 145         FEA_MAP(APCC_PLUS),
 146         FEA_MAP(GTHR),
 147         FEA_MAP(ACDC),
 148         FEA_MAP(VR0HOT),
 149         FEA_MAP(VR1HOT),
 150         FEA_MAP(FW_CTF),
 151         FEA_MAP(FAN_CONTROL),
 152         FEA_MAP(THERMAL),
 153         FEA_MAP(GFX_DCS),
 154         FEA_MAP(RM),
 155         FEA_MAP(LED_DISPLAY),
 156         FEA_MAP(GFX_SS),
 157         FEA_MAP(OUT_OF_BAND_MONITOR),
 158         FEA_MAP(TEMP_DEPENDENT_VMIN),
 159         FEA_MAP(MMHUB_PG),
 160         FEA_MAP(ATHUB_PG),
 161 };
 162
 163 static int navi10_table_map[SMU_TABLE_COUNT] = {
 164         TAB_MAP(PPTABLE),
 165         TAB_MAP(WATERMARKS),
 166         TAB_MAP(AVFS),
 167         TAB_MAP(AVFS_PSM_DEBUG),
 168         TAB_MAP(AVFS_FUSE_OVERRIDE),
 169         TAB_MAP(PMSTATUSLOG),
 170         TAB_MAP(SMU_METRICS),
 171         TAB_MAP(DRIVER_SMU_CONFIG),
 172         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 173         TAB_MAP(OVERDRIVE),
 174         TAB_MAP(I2C_COMMANDS),
 175         TAB_MAP(PACE),
 176 };
 177
 178 static int navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 179         PWR_MAP(AC),
 180         PWR_MAP(DC),
 181 };
 182
 183 static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 184 {
 185         int val;
 186         if (index > SMU_MSG_MAX_COUNT)
 187                 return -EINVAL;
 188
 189         val = navi10_message_map[index];
 190         if (val > PPSMC_Message_Count)
 191                 return -EINVAL;
 192
 193         return val;
 194 }
 195
 196 static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 197 {
 198         int val;
 199         if (index >= SMU_CLK_COUNT)
 200                 return -EINVAL;
 201
 202         val = navi10_clk_map[index];
 203         if (val >= PPCLK_COUNT)
 204                 return -EINVAL;
 205
 206         return val;
 207 }
 208
 209 static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 210 {
 211         int val;
 212         if (index >= SMU_FEATURE_COUNT)
 213                 return -EINVAL;
 214
 215         val = navi10_feature_mask_map[index];
 216         if (val > 64)
 217                 return -EINVAL;
 218
 219         return val;
 220 }
 221
 222 static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
 223 {
 224         int val;
 225         if (index >= SMU_TABLE_COUNT)
 226                 return -EINVAL;
 227
 228         val = navi10_table_map[index];
 229         if (val >= TABLE_COUNT)
 230                 return -EINVAL;
 231
 232         return val;
 233 }
 234
 235 static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 236 {
 237         int val;
 238         if (index >= SMU_POWER_SOURCE_COUNT)
 239                 return -EINVAL;
 240
 241         val = navi10_pwr_src_map[index];
 242         if (val >= POWER_SOURCE_COUNT)
 243                 return -EINVAL;
 244
 245         return val;
 246 }
 247
 248 #define FEATURE_MASK(feature) (1UL << feature)
 249 static int
 250 navi10_get_allowed_feature_mask(struct smu_context *smu,
 251                                   uint32_t *feature_mask, uint32_t num)
 252 {
 253         struct amdgpu_device *adev = smu->adev;
 254
 255         if (num > 2)
 256                 return -EINVAL;
 257
 258         memset(feature_mask, 0, sizeof(uint32_t) * num);
 259
 260         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 261                                 | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)
 262                                 | FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
 263                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 264                                 | FEATURE_MASK(FEATURE_DPM_LINK_BIT)
 265                                 | FEATURE_MASK(FEATURE_GFX_ULV_BIT)
 266                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 267                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 268                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 269                                 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
 270                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 271                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 272                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 273                                 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
 274                                 | FEATURE_MASK(FEATURE_MMHUB_PG_BIT)
 275                                 | FEATURE_MASK(FEATURE_ATHUB_PG_BIT)
 276                                 | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 277
 278         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 279                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 280                                 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 281                                 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 282
 283         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 284                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
 285                                 | FEATURE_MASK(FEATURE_GFXOFF_BIT);
 286
 287         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
 288                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
 289
 290         return 0;
 291 }
 292
 293 static int navi10_check_powerplay_table(struct smu_context *smu)
 294 {
 295         return 0;
 296 }
 297
 298 static int navi10_append_powerplay_table(struct smu_context *smu)
 299 {
 300         struct amdgpu_device *adev = smu->adev;
 301         struct smu_table_context *table_context = &smu->smu_table;
 302         PPTable_t *smc_pptable = table_context->driver_pptable;
 303         struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
 304         int index, ret;
 305
 306         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 307                                            smc_dpm_info);
 308
 309         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 310                                       (uint8_t **)&smc_dpm_table);
 311         if (ret)
 312                 return ret;
 313
 314         memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 315                sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS);
 316
 317         /* SVI2 Board Parameters */
 318         smc_pptable->MaxVoltageStepGfx = smc_dpm_table->MaxVoltageStepGfx;
 319         smc_pptable->MaxVoltageStepSoc = smc_dpm_table->MaxVoltageStepSoc;
 320         smc_pptable->VddGfxVrMapping = smc_dpm_table->VddGfxVrMapping;
 321         smc_pptable->VddSocVrMapping = smc_dpm_table->VddSocVrMapping;
 322         smc_pptable->VddMem0VrMapping = smc_dpm_table->VddMem0VrMapping;
 323         smc_pptable->VddMem1VrMapping = smc_dpm_table->VddMem1VrMapping;
 324         smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->GfxUlvPhaseSheddingMask;
 325         smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->SocUlvPhaseSheddingMask;
 326         smc_pptable->ExternalSensorPresent = smc_dpm_table->ExternalSensorPresent;
 327         smc_pptable->Padding8_V = smc_dpm_table->Padding8_V;
 328
 329         /* Telemetry Settings */
 330         smc_pptable->GfxMaxCurrent = smc_dpm_table->GfxMaxCurrent;
 331         smc_pptable->GfxOffset = smc_dpm_table->GfxOffset;
 332         smc_pptable->Padding_TelemetryGfx = smc_dpm_table->Padding_TelemetryGfx;
 333         smc_pptable->SocMaxCurrent = smc_dpm_table->SocMaxCurrent;
 334         smc_pptable->SocOffset = smc_dpm_table->SocOffset;
 335         smc_pptable->Padding_TelemetrySoc = smc_dpm_table->Padding_TelemetrySoc;
 336         smc_pptable->Mem0MaxCurrent = smc_dpm_table->Mem0MaxCurrent;
 337         smc_pptable->Mem0Offset = smc_dpm_table->Mem0Offset;
 338         smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->Padding_TelemetryMem0;
 339         smc_pptable->Mem1MaxCurrent = smc_dpm_table->Mem1MaxCurrent;
 340         smc_pptable->Mem1Offset = smc_dpm_table->Mem1Offset;
 341         smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->Padding_TelemetryMem1;
 342
 343         /* GPIO Settings */
 344         smc_pptable->AcDcGpio = smc_dpm_table->AcDcGpio;
 345         smc_pptable->AcDcPolarity = smc_dpm_table->AcDcPolarity;
 346         smc_pptable->VR0HotGpio = smc_dpm_table->VR0HotGpio;
 347         smc_pptable->VR0HotPolarity = smc_dpm_table->VR0HotPolarity;
 348         smc_pptable->VR1HotGpio = smc_dpm_table->VR1HotGpio;
 349         smc_pptable->VR1HotPolarity = smc_dpm_table->VR1HotPolarity;
 350         smc_pptable->GthrGpio = smc_dpm_table->GthrGpio;
 351         smc_pptable->GthrPolarity = smc_dpm_table->GthrPolarity;
 352
 353         /* LED Display Settings */
 354         smc_pptable->LedPin0 = smc_dpm_table->LedPin0;
 355         smc_pptable->LedPin1 = smc_dpm_table->LedPin1;
 356         smc_pptable->LedPin2 = smc_dpm_table->LedPin2;
 357         smc_pptable->padding8_4 = smc_dpm_table->padding8_4;
 358
 359         /* GFXCLK PLL Spread Spectrum */
 360         smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->PllGfxclkSpreadEnabled;
 361         smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->PllGfxclkSpreadPercent;
 362         smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->PllGfxclkSpreadFreq;
 363
 364         /* GFXCLK DFLL Spread Spectrum */
 365         smc_pptable->DfllGfxclkSpreadEnabled = smc_dpm_table->DfllGfxclkSpreadEnabled;
 366         smc_pptable->DfllGfxclkSpreadPercent = smc_dpm_table->DfllGfxclkSpreadPercent;
 367         smc_pptable->DfllGfxclkSpreadFreq = smc_dpm_table->DfllGfxclkSpreadFreq;
 368
 369         /* UCLK Spread Spectrum */
 370         smc_pptable->UclkSpreadEnabled = smc_dpm_table->UclkSpreadEnabled;
 371         smc_pptable->UclkSpreadPercent = smc_dpm_table->UclkSpreadPercent;
 372         smc_pptable->UclkSpreadFreq = smc_dpm_table->UclkSpreadFreq;
 373
 374         /* SOCCLK Spread Spectrum */
 375         smc_pptable->SoclkSpreadEnabled = smc_dpm_table->SoclkSpreadEnabled;
 376         smc_pptable->SocclkSpreadPercent = smc_dpm_table->SocclkSpreadPercent;
 377         smc_pptable->SocclkSpreadFreq = smc_dpm_table->SocclkSpreadFreq;
 378
 379         /* Total board power */
 380         smc_pptable->TotalBoardPower = smc_dpm_table->TotalBoardPower;
 381         smc_pptable->BoardPadding = smc_dpm_table->BoardPadding;
 382
 383         /* Mvdd Svi2 Div Ratio Setting */
 384         smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
 385
 386         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 387                 *(uint64_t *)smc_pptable->FeaturesToRun |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
 388                                         | FEATURE_MASK(FEATURE_GFXOFF_BIT);
 389
 390                 /* TODO: remove it once SMU fw fix it */
 391                 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
 392         }
 393
 394         return 0;
 395 }
 396
 397 static int navi10_store_powerplay_table(struct smu_context *smu)
 398 {
 399         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 400         struct smu_table_context *table_context = &smu->smu_table;
 401
 402         if (!table_context->power_play_table)
 403                 return -EINVAL;
 404
 405         powerplay_table = table_context->power_play_table;
 406
 407         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 408                sizeof(PPTable_t));
 409
 410         return 0;
 411 }
 412
 413 static void navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
 414 {
 415         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 416                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 417         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 418                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 419         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 420                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 421         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 422                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 423         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 424                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 425         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 426                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 427                        AMDGPU_GEM_DOMAIN_VRAM);
 428 }
 429
 430 static int navi10_allocate_dpm_context(struct smu_context *smu)
 431 {
 432         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 433
 434         if (smu_dpm->dpm_context)
 435                 return -EINVAL;
 436
 437         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 438                                        GFP_KERNEL);
 439         if (!smu_dpm->dpm_context)
 440                 return -ENOMEM;
 441
 442         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 443
 444         return 0;
 445 }
 446
 447 static int navi10_set_default_dpm_table(struct smu_context *smu)
 448 {
 449         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 450         struct smu_table_context *table_context = &smu->smu_table;
 451         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 452         PPTable_t *driver_ppt = NULL;
 453
 454         driver_ppt = table_context->driver_pptable;
 455
 456         dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
 457         dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
 458
 459         dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
 460         dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
 461
 462         dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
 463         dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
 464
 465         dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
 466         dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
 467
 468         dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
 469         dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
 470
 471         dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
 472         dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
 473
 474         dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
 475         dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
 476
 477         dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
 478         dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
 479
 480         dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
 481         dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
 482
 483         return 0;
 484 }
 485
 486 static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
 487 {
 488         int ret = 0;
 489
 490         if (enable) {
 491                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
 492                 if (ret)
 493                         return ret;
 494         } else {
 495                 ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
 496                 if (ret)
 497                         return ret;
 498         }
 499
 500         return 0;
 501 }
 502
 503 static const struct pptable_funcs navi10_ppt_funcs = {
 504         .tables_init = navi10_tables_init,
 505         .alloc_dpm_context = navi10_allocate_dpm_context,
 506         .store_powerplay_table = navi10_store_powerplay_table,
 507         .check_powerplay_table = navi10_check_powerplay_table,
 508         .append_powerplay_table = navi10_append_powerplay_table,
 509         .get_smu_msg_index = navi10_get_smu_msg_index,
 510         .get_smu_clk_index = navi10_get_smu_clk_index,
 511         .get_smu_feature_index = navi10_get_smu_feature_index,
 512         .get_smu_table_index = navi10_get_smu_table_index,
 513         .get_smu_power_index = navi10_get_pwr_src_index,
 514         .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
 515         .set_default_dpm_table = navi10_set_default_dpm_table,
 516         .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
 517 };
 518
 519 void navi10_set_ppt_funcs(struct smu_context *smu)
 520 {
 521         struct smu_table_context *smu_table = &smu->smu_table;
 522
 523         smu->ppt_funcs = &navi10_ppt_funcs;
 524         smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
 525         smu_table->table_count = TABLE_COUNT;
 526 }