drivers/gpu/drm/amd/powerplay/navi10_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include <linux/pci.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "smu_internal.h"
  30 #include "atomfirmware.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "smu_v11_0.h"
  33 #include "smu11_driver_if_navi10.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "navi10_ppt.h"
  37 #include "smu_v11_0_pptable.h"
  38 #include "smu_v11_0_ppsmc.h"
  39 #include "nbio/nbio_7_4_sh_mask.h"
  40
  41 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  42
  43 #define FEATURE_MASK(feature) (1ULL << feature)
  44 #define SMC_DPM_FEATURE ( \
  45         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  46         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  47         FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT)   | \
  48         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  49         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  50         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)     | \
  51         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  52         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
  53
  54 #define MSG_MAP(msg, index) \
  55         [SMU_MSG_##msg] = {1, (index)}
  56
  57 static struct smu_11_0_cmn2aisc_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
  58         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
  59         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
  60         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion),
  61         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow),
  62         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  63         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures),
  64         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures),
  65         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow),
  66         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh),
  67         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow),
  68         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh),
  69         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetEnabledSmuFeaturesLow),
  70         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetEnabledSmuFeaturesHigh),
  71         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask),
  72         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit),
  73         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh),
  74         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow),
  75         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh),
  76         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow),
  77         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram),
  78         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu),
  79         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable),
  80         MSG_MAP(UseBackupPPTable,               PPSMC_MSG_UseBackupPPTable),
  81         MSG_MAP(RunBtc,                         PPSMC_MSG_RunBtc),
  82         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco),
  83         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq),
  84         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq),
  85         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq),
  86         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq),
  87         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq),
  88         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq),
  89         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex),
  90         MSG_MAP(SetMemoryChannelConfig,         PPSMC_MSG_SetMemoryChannelConfig),
  91         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode),
  92         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh),
  93         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow),
  94         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters),
  95         MSG_MAP(SetMinDeepSleepDcefclk,         PPSMC_MSG_SetMinDeepSleepDcefclk),
  96         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt),
  97         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource),
  98         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch),
  99         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps),
 100         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload),
 101         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh),
 102         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow),
 103         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize),
 104         MSG_MAP(ConfigureGfxDidt,               PPSMC_MSG_ConfigureGfxDidt),
 105         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_NumOfDisplays),
 106         MSG_MAP(SetSystemVirtualDramAddrHigh,   PPSMC_MSG_SetSystemVirtualDramAddrHigh),
 107         MSG_MAP(SetSystemVirtualDramAddrLow,    PPSMC_MSG_SetSystemVirtualDramAddrLow),
 108         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff),
 109         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff),
 110         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit),
 111         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq),
 112         MSG_MAP(GetDebugData,                   PPSMC_MSG_GetDebugData),
 113         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco),
 114         MSG_MAP(PrepareMp1ForReset,             PPSMC_MSG_PrepareMp1ForReset),
 115         MSG_MAP(PrepareMp1ForShutdown,          PPSMC_MSG_PrepareMp1ForShutdown),
 116         MSG_MAP(PowerUpVcn,             PPSMC_MSG_PowerUpVcn),
 117         MSG_MAP(PowerDownVcn,           PPSMC_MSG_PowerDownVcn),
 118         MSG_MAP(PowerUpJpeg,            PPSMC_MSG_PowerUpJpeg),
 119         MSG_MAP(PowerDownJpeg,          PPSMC_MSG_PowerDownJpeg),
 120         MSG_MAP(BacoAudioD3PME,         PPSMC_MSG_BacoAudioD3PME),
 121         MSG_MAP(ArmD3,                  PPSMC_MSG_ArmD3),
 122         MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE,PPSMC_MSG_DALDisableDummyPstateChange),
 123         MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange),
 124         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm),
 125         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive),
 126 };
 127
 128 static struct smu_11_0_cmn2aisc_mapping navi10_clk_map[SMU_CLK_COUNT] = {
 129         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 130         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 131         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 132         CLK_MAP(FCLK, PPCLK_SOCCLK),
 133         CLK_MAP(UCLK, PPCLK_UCLK),
 134         CLK_MAP(MCLK, PPCLK_UCLK),
 135         CLK_MAP(DCLK, PPCLK_DCLK),
 136         CLK_MAP(VCLK, PPCLK_VCLK),
 137         CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
 138         CLK_MAP(DISPCLK, PPCLK_DISPCLK),
 139         CLK_MAP(PIXCLK, PPCLK_PIXCLK),
 140         CLK_MAP(PHYCLK, PPCLK_PHYCLK),
 141 };
 142
 143 static struct smu_11_0_cmn2aisc_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
 144         FEA_MAP(DPM_PREFETCHER),
 145         FEA_MAP(DPM_GFXCLK),
 146         FEA_MAP(DPM_GFX_PACE),
 147         FEA_MAP(DPM_UCLK),
 148         FEA_MAP(DPM_SOCCLK),
 149         FEA_MAP(DPM_MP0CLK),
 150         FEA_MAP(DPM_LINK),
 151         FEA_MAP(DPM_DCEFCLK),
 152         FEA_MAP(MEM_VDDCI_SCALING),
 153         FEA_MAP(MEM_MVDD_SCALING),
 154         FEA_MAP(DS_GFXCLK),
 155         FEA_MAP(DS_SOCCLK),
 156         FEA_MAP(DS_LCLK),
 157         FEA_MAP(DS_DCEFCLK),
 158         FEA_MAP(DS_UCLK),
 159         FEA_MAP(GFX_ULV),
 160         FEA_MAP(FW_DSTATE),
 161         FEA_MAP(GFXOFF),
 162         FEA_MAP(BACO),
 163         FEA_MAP(VCN_PG),
 164         FEA_MAP(JPEG_PG),
 165         FEA_MAP(USB_PG),
 166         FEA_MAP(RSMU_SMN_CG),
 167         FEA_MAP(PPT),
 168         FEA_MAP(TDC),
 169         FEA_MAP(GFX_EDC),
 170         FEA_MAP(APCC_PLUS),
 171         FEA_MAP(GTHR),
 172         FEA_MAP(ACDC),
 173         FEA_MAP(VR0HOT),
 174         FEA_MAP(VR1HOT),
 175         FEA_MAP(FW_CTF),
 176         FEA_MAP(FAN_CONTROL),
 177         FEA_MAP(THERMAL),
 178         FEA_MAP(GFX_DCS),
 179         FEA_MAP(RM),
 180         FEA_MAP(LED_DISPLAY),
 181         FEA_MAP(GFX_SS),
 182         FEA_MAP(OUT_OF_BAND_MONITOR),
 183         FEA_MAP(TEMP_DEPENDENT_VMIN),
 184         FEA_MAP(MMHUB_PG),
 185         FEA_MAP(ATHUB_PG),
 186         FEA_MAP(APCC_DFLL),
 187 };
 188
 189 static struct smu_11_0_cmn2aisc_mapping navi10_table_map[SMU_TABLE_COUNT] = {
 190         TAB_MAP(PPTABLE),
 191         TAB_MAP(WATERMARKS),
 192         TAB_MAP(AVFS),
 193         TAB_MAP(AVFS_PSM_DEBUG),
 194         TAB_MAP(AVFS_FUSE_OVERRIDE),
 195         TAB_MAP(PMSTATUSLOG),
 196         TAB_MAP(SMU_METRICS),
 197         TAB_MAP(DRIVER_SMU_CONFIG),
 198         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 199         TAB_MAP(OVERDRIVE),
 200         TAB_MAP(I2C_COMMANDS),
 201         TAB_MAP(PACE),
 202 };
 203
 204 static struct smu_11_0_cmn2aisc_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 205         PWR_MAP(AC),
 206         PWR_MAP(DC),
 207 };
 208
 209 static struct smu_11_0_cmn2aisc_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 210         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 211         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 212         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 213         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 214         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 215         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 216         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 217 };
 218
 219 static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 220 {
 221         struct smu_11_0_cmn2aisc_mapping mapping;
 222
 223         if (index >= SMU_MSG_MAX_COUNT)
 224                 return -EINVAL;
 225
 226         mapping = navi10_message_map[index];
 227         if (!(mapping.valid_mapping)) {
 228                 return -EINVAL;
 229         }
 230
 231         return mapping.map_to;
 232 }
 233
 234 static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 235 {
 236         struct smu_11_0_cmn2aisc_mapping mapping;
 237
 238         if (index >= SMU_CLK_COUNT)
 239                 return -EINVAL;
 240
 241         mapping = navi10_clk_map[index];
 242         if (!(mapping.valid_mapping)) {
 243                 return -EINVAL;
 244         }
 245
 246         return mapping.map_to;
 247 }
 248
 249 static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 250 {
 251         struct smu_11_0_cmn2aisc_mapping mapping;
 252
 253         if (index >= SMU_FEATURE_COUNT)
 254                 return -EINVAL;
 255
 256         mapping = navi10_feature_mask_map[index];
 257         if (!(mapping.valid_mapping)) {
 258                 return -EINVAL;
 259         }
 260
 261         return mapping.map_to;
 262 }
 263
 264 static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
 265 {
 266         struct smu_11_0_cmn2aisc_mapping mapping;
 267
 268         if (index >= SMU_TABLE_COUNT)
 269                 return -EINVAL;
 270
 271         mapping = navi10_table_map[index];
 272         if (!(mapping.valid_mapping)) {
 273                 return -EINVAL;
 274         }
 275
 276         return mapping.map_to;
 277 }
 278
 279 static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 280 {
 281         struct smu_11_0_cmn2aisc_mapping mapping;
 282
 283         if (index >= SMU_POWER_SOURCE_COUNT)
 284                 return -EINVAL;
 285
 286         mapping = navi10_pwr_src_map[index];
 287         if (!(mapping.valid_mapping)) {
 288                 return -EINVAL;
 289         }
 290
 291         return mapping.map_to;
 292 }
 293
 294
 295 static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 296 {
 297         struct smu_11_0_cmn2aisc_mapping mapping;
 298
 299         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 300                 return -EINVAL;
 301
 302         mapping = navi10_workload_map[profile];
 303         if (!(mapping.valid_mapping)) {
 304                 return -EINVAL;
 305         }
 306
 307         return mapping.map_to;
 308 }
 309
 310 static bool is_asic_secure(struct smu_context *smu)
 311 {
 312         struct amdgpu_device *adev = smu->adev;
 313         bool is_secure = true;
 314         uint32_t mp0_fw_intf;
 315
 316         mp0_fw_intf = RREG32_PCIE(MP0_Public |
 317                                    (smnMP0_FW_INTF & 0xffffffff));
 318
 319         if (!(mp0_fw_intf & (1 << 19)))
 320                 is_secure = false;
 321
 322         return is_secure;
 323 }
 324
 325 static int
 326 navi10_get_allowed_feature_mask(struct smu_context *smu,
 327                                   uint32_t *feature_mask, uint32_t num)
 328 {
 329         struct amdgpu_device *adev = smu->adev;
 330
 331         if (num > 2)
 332                 return -EINVAL;
 333
 334         memset(feature_mask, 0, sizeof(uint32_t) * num);
 335
 336         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 337                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 338                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 339                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 340                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 341                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 342                                 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
 343                                 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
 344                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 345                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 346                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 347                                 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
 348                                 | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
 349                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 350                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 351                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 352                                 | FEATURE_MASK(FEATURE_ACDC_BIT)
 353                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 354                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 355                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 356                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 357
 358         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 359                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 360
 361         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
 362                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 363
 364         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 365                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 366
 367         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 368                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 369
 370         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 371                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 372                                 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 373                                 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 374
 375         if (adev->pm.pp_feature & PP_ULV_MASK)
 376                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 377
 378         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 379                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 380
 381         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 382                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 383
 384         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 385                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 386
 387         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 388                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 389
 390         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
 391                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
 392
 393         if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 394                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
 395
 396         /* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
 397         if (is_asic_secure(smu)) {
 398                 /* only for navi10 A0 */
 399                 if ((adev->asic_type == CHIP_NAVI10) &&
 400                         (adev->rev_id == 0)) {
 401                         *(uint64_t *)feature_mask &=
 402                                         ~(FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 403                                           | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 404                                           | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT));
 405                         *(uint64_t *)feature_mask &=
 406                                         ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
 407                 }
 408         }
 409
 410         return 0;
 411 }
 412
 413 static int navi10_check_powerplay_table(struct smu_context *smu)
 414 {
 415         return 0;
 416 }
 417
 418 static int navi10_append_powerplay_table(struct smu_context *smu)
 419 {
 420         struct amdgpu_device *adev = smu->adev;
 421         struct smu_table_context *table_context = &smu->smu_table;
 422         PPTable_t *smc_pptable = table_context->driver_pptable;
 423         struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
 424         int index, ret;
 425
 426         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 427                                            smc_dpm_info);
 428
 429         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 430                                       (uint8_t **)&smc_dpm_table);
 431         if (ret)
 432                 return ret;
 433
 434         memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 435                sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS);
 436
 437         /* SVI2 Board Parameters */
 438         smc_pptable->MaxVoltageStepGfx = smc_dpm_table->MaxVoltageStepGfx;
 439         smc_pptable->MaxVoltageStepSoc = smc_dpm_table->MaxVoltageStepSoc;
 440         smc_pptable->VddGfxVrMapping = smc_dpm_table->VddGfxVrMapping;
 441         smc_pptable->VddSocVrMapping = smc_dpm_table->VddSocVrMapping;
 442         smc_pptable->VddMem0VrMapping = smc_dpm_table->VddMem0VrMapping;
 443         smc_pptable->VddMem1VrMapping = smc_dpm_table->VddMem1VrMapping;
 444         smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->GfxUlvPhaseSheddingMask;
 445         smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->SocUlvPhaseSheddingMask;
 446         smc_pptable->ExternalSensorPresent = smc_dpm_table->ExternalSensorPresent;
 447         smc_pptable->Padding8_V = smc_dpm_table->Padding8_V;
 448
 449         /* Telemetry Settings */
 450         smc_pptable->GfxMaxCurrent = smc_dpm_table->GfxMaxCurrent;
 451         smc_pptable->GfxOffset = smc_dpm_table->GfxOffset;
 452         smc_pptable->Padding_TelemetryGfx = smc_dpm_table->Padding_TelemetryGfx;
 453         smc_pptable->SocMaxCurrent = smc_dpm_table->SocMaxCurrent;
 454         smc_pptable->SocOffset = smc_dpm_table->SocOffset;
 455         smc_pptable->Padding_TelemetrySoc = smc_dpm_table->Padding_TelemetrySoc;
 456         smc_pptable->Mem0MaxCurrent = smc_dpm_table->Mem0MaxCurrent;
 457         smc_pptable->Mem0Offset = smc_dpm_table->Mem0Offset;
 458         smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->Padding_TelemetryMem0;
 459         smc_pptable->Mem1MaxCurrent = smc_dpm_table->Mem1MaxCurrent;
 460         smc_pptable->Mem1Offset = smc_dpm_table->Mem1Offset;
 461         smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->Padding_TelemetryMem1;
 462
 463         /* GPIO Settings */
 464         smc_pptable->AcDcGpio = smc_dpm_table->AcDcGpio;
 465         smc_pptable->AcDcPolarity = smc_dpm_table->AcDcPolarity;
 466         smc_pptable->VR0HotGpio = smc_dpm_table->VR0HotGpio;
 467         smc_pptable->VR0HotPolarity = smc_dpm_table->VR0HotPolarity;
 468         smc_pptable->VR1HotGpio = smc_dpm_table->VR1HotGpio;
 469         smc_pptable->VR1HotPolarity = smc_dpm_table->VR1HotPolarity;
 470         smc_pptable->GthrGpio = smc_dpm_table->GthrGpio;
 471         smc_pptable->GthrPolarity = smc_dpm_table->GthrPolarity;
 472
 473         /* LED Display Settings */
 474         smc_pptable->LedPin0 = smc_dpm_table->LedPin0;
 475         smc_pptable->LedPin1 = smc_dpm_table->LedPin1;
 476         smc_pptable->LedPin2 = smc_dpm_table->LedPin2;
 477         smc_pptable->padding8_4 = smc_dpm_table->padding8_4;
 478
 479         /* GFXCLK PLL Spread Spectrum */
 480         smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->PllGfxclkSpreadEnabled;
 481         smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->PllGfxclkSpreadPercent;
 482         smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->PllGfxclkSpreadFreq;
 483
 484         /* GFXCLK DFLL Spread Spectrum */
 485         smc_pptable->DfllGfxclkSpreadEnabled = smc_dpm_table->DfllGfxclkSpreadEnabled;
 486         smc_pptable->DfllGfxclkSpreadPercent = smc_dpm_table->DfllGfxclkSpreadPercent;
 487         smc_pptable->DfllGfxclkSpreadFreq = smc_dpm_table->DfllGfxclkSpreadFreq;
 488
 489         /* UCLK Spread Spectrum */
 490         smc_pptable->UclkSpreadEnabled = smc_dpm_table->UclkSpreadEnabled;
 491         smc_pptable->UclkSpreadPercent = smc_dpm_table->UclkSpreadPercent;
 492         smc_pptable->UclkSpreadFreq = smc_dpm_table->UclkSpreadFreq;
 493
 494         /* SOCCLK Spread Spectrum */
 495         smc_pptable->SoclkSpreadEnabled = smc_dpm_table->SoclkSpreadEnabled;
 496         smc_pptable->SocclkSpreadPercent = smc_dpm_table->SocclkSpreadPercent;
 497         smc_pptable->SocclkSpreadFreq = smc_dpm_table->SocclkSpreadFreq;
 498
 499         /* Total board power */
 500         smc_pptable->TotalBoardPower = smc_dpm_table->TotalBoardPower;
 501         smc_pptable->BoardPadding = smc_dpm_table->BoardPadding;
 502
 503         /* Mvdd Svi2 Div Ratio Setting */
 504         smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
 505
 506         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 507                 /* TODO: remove it once SMU fw fix it */
 508                 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
 509         }
 510
 511         return 0;
 512 }
 513
 514 static int navi10_store_powerplay_table(struct smu_context *smu)
 515 {
 516         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 517         struct smu_table_context *table_context = &smu->smu_table;
 518         struct smu_baco_context *smu_baco = &smu->smu_baco;
 519
 520         if (!table_context->power_play_table)
 521                 return -EINVAL;
 522
 523         powerplay_table = table_context->power_play_table;
 524
 525         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 526                sizeof(PPTable_t));
 527
 528         table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
 529
 530         mutex_lock(&smu_baco->mutex);
 531         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 532             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 533                 smu_baco->platform_support = true;
 534         mutex_unlock(&smu_baco->mutex);
 535
 536         return 0;
 537 }
 538
 539 static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
 540 {
 541         struct smu_table_context *smu_table = &smu->smu_table;
 542
 543         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 544                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 545         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 546                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 547         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 548                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 549         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 550                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 551         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 552                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 553         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 554                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 555                        AMDGPU_GEM_DOMAIN_VRAM);
 556
 557         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 558         if (!smu_table->metrics_table)
 559                 return -ENOMEM;
 560         smu_table->metrics_time = 0;
 561
 562         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 563         if (!smu_table->watermarks_table)
 564                 return -ENOMEM;
 565
 566         return 0;
 567 }
 568
 569 static int navi10_get_metrics_table(struct smu_context *smu,
 570                                     SmuMetrics_t *metrics_table)
 571 {
 572         struct smu_table_context *smu_table= &smu->smu_table;
 573         int ret = 0;
 574
 575         mutex_lock(&smu->metrics_lock);
 576         if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
 577                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 578                                 (void *)smu_table->metrics_table, false);
 579                 if (ret) {
 580                         pr_info("Failed to export SMU metrics table!\n");
 581                         mutex_unlock(&smu->metrics_lock);
 582                         return ret;
 583                 }
 584                 smu_table->metrics_time = jiffies;
 585         }
 586
 587         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
 588         mutex_unlock(&smu->metrics_lock);
 589
 590         return ret;
 591 }
 592
 593 static int navi10_allocate_dpm_context(struct smu_context *smu)
 594 {
 595         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 596
 597         if (smu_dpm->dpm_context)
 598                 return -EINVAL;
 599
 600         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 601                                        GFP_KERNEL);
 602         if (!smu_dpm->dpm_context)
 603                 return -ENOMEM;
 604
 605         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 606
 607         return 0;
 608 }
 609
 610 static int navi10_set_default_dpm_table(struct smu_context *smu)
 611 {
 612         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 613         struct smu_table_context *table_context = &smu->smu_table;
 614         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 615         PPTable_t *driver_ppt = NULL;
 616         int i;
 617
 618         driver_ppt = table_context->driver_pptable;
 619
 620         dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
 621         dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
 622
 623         dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
 624         dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
 625
 626         dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
 627         dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
 628
 629         dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
 630         dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
 631
 632         dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
 633         dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
 634
 635         dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
 636         dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
 637
 638         dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
 639         dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
 640
 641         dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
 642         dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
 643
 644         dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
 645         dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
 646
 647         for (i = 0; i < MAX_PCIE_CONF; i++) {
 648                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
 649                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
 650         }
 651
 652         return 0;
 653 }
 654
 655 static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
 656 {
 657         struct smu_power_context *smu_power = &smu->smu_power;
 658         struct smu_power_gate *power_gate = &smu_power->power_gate;
 659         int ret = 0;
 660
 661         if (enable) {
 662                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 663                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 664                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
 665                         if (ret)
 666                                 return ret;
 667                 }
 668                 power_gate->vcn_gated = false;
 669         } else {
 670                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 671                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
 672                         if (ret)
 673                                 return ret;
 674                 }
 675                 power_gate->vcn_gated = true;
 676         }
 677
 678         return ret;
 679 }
 680
 681 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 682 {
 683         struct smu_power_context *smu_power = &smu->smu_power;
 684         struct smu_power_gate *power_gate = &smu_power->power_gate;
 685         int ret = 0;
 686
 687         if (enable) {
 688                 if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 689                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerUpJpeg);
 690                         if (ret)
 691                                 return ret;
 692                 }
 693                 power_gate->jpeg_gated = false;
 694         } else {
 695                 if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 696                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownJpeg);
 697                         if (ret)
 698                                 return ret;
 699                 }
 700                 power_gate->jpeg_gated = true;
 701         }
 702
 703         return ret;
 704 }
 705
 706 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
 707                                        enum smu_clk_type clk_type,
 708                                        uint32_t *value)
 709 {
 710         int ret = 0, clk_id = 0;
 711         SmuMetrics_t metrics;
 712
 713         ret = navi10_get_metrics_table(smu, &metrics);
 714         if (ret)
 715                 return ret;
 716
 717         clk_id = smu_clk_get_index(smu, clk_type);
 718         if (clk_id < 0)
 719                 return clk_id;
 720
 721         *value = metrics.CurrClock[clk_id];
 722
 723         return ret;
 724 }
 725
 726 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 727 {
 728         PPTable_t *pptable = smu->smu_table.driver_pptable;
 729         DpmDescriptor_t *dpm_desc = NULL;
 730         uint32_t clk_index = 0;
 731
 732         clk_index = smu_clk_get_index(smu, clk_type);
 733         dpm_desc = &pptable->DpmDescriptor[clk_index];
 734
 735         /* 0 - Fine grained DPM, 1 - Discrete DPM */
 736         return dpm_desc->SnapToDiscrete == 0 ? true : false;
 737 }
 738
 739 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_ID feature)
 740 {
 741         return od_table->cap[feature];
 742 }
 743
 744 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table,
 745                                         enum SMU_11_0_ODSETTING_ID setting,
 746                                         uint32_t *min, uint32_t *max)
 747 {
 748         if (min)
 749                 *min = od_table->min[setting];
 750         if (max)
 751                 *max = od_table->max[setting];
 752 }
 753
 754 static int navi10_print_clk_levels(struct smu_context *smu,
 755                         enum smu_clk_type clk_type, char *buf)
 756 {
 757         uint16_t *curve_settings;
 758         int i, size = 0, ret = 0;
 759         uint32_t cur_value = 0, value = 0, count = 0;
 760         uint32_t freq_values[3] = {0};
 761         uint32_t mark_index = 0;
 762         struct smu_table_context *table_context = &smu->smu_table;
 763         uint32_t gen_speed, lane_width;
 764         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 765         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 766         struct amdgpu_device *adev = smu->adev;
 767         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 768         OverDriveTable_t *od_table =
 769                 (OverDriveTable_t *)table_context->overdrive_table;
 770         struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
 771         uint32_t min_value, max_value;
 772
 773         switch (clk_type) {
 774         case SMU_GFXCLK:
 775         case SMU_SCLK:
 776         case SMU_SOCCLK:
 777         case SMU_MCLK:
 778         case SMU_UCLK:
 779         case SMU_FCLK:
 780         case SMU_DCEFCLK:
 781                 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
 782                 if (ret)
 783                         return size;
 784
 785                 /* 10KHz -> MHz */
 786                 cur_value = cur_value / 100;
 787
 788                 ret = smu_get_dpm_level_count(smu, clk_type, &count);
 789                 if (ret)
 790                         return size;
 791
 792                 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
 793                         for (i = 0; i < count; i++) {
 794                                 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
 795                                 if (ret)
 796                                         return size;
 797
 798                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 799                                                 cur_value == value ? "*" : "");
 800                         }
 801                 } else {
 802                         ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
 803                         if (ret)
 804                                 return size;
 805                         ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
 806                         if (ret)
 807                                 return size;
 808
 809                         freq_values[1] = cur_value;
 810                         mark_index = cur_value == freq_values[0] ? 0 :
 811                                      cur_value == freq_values[2] ? 2 : 1;
 812                         if (mark_index != 1)
 813                                 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
 814
 815                         for (i = 0; i < 3; i++) {
 816                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
 817                                                 i == mark_index ? "*" : "");
 818                         }
 819
 820                 }
 821                 break;
 822         case SMU_PCIE:
 823                 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
 824                              PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
 825                         >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
 826                 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
 827                               PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
 828                         >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
 829                 for (i = 0; i < NUM_LINK_LEVELS; i++)
 830                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
 831                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
 832                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
 833                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
 834                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
 835                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
 836                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
 837                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
 838                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
 839                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
 840                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
 841                                         pptable->LclkFreq[i],
 842                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
 843                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
 844                                         "*" : "");
 845                 break;
 846         case SMU_OD_SCLK:
 847                 if (!smu->od_enabled || !od_table || !od_settings)
 848                         break;
 849                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS))
 850                         break;
 851                 size += sprintf(buf + size, "OD_SCLK:\n");
 852                 size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
 853                 break;
 854         case SMU_OD_MCLK:
 855                 if (!smu->od_enabled || !od_table || !od_settings)
 856                         break;
 857                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX))
 858                         break;
 859                 size += sprintf(buf + size, "OD_MCLK:\n");
 860                 size += sprintf(buf + size, "1: %uMHz\n", od_table->UclkFmax);
 861                 break;
 862         case SMU_OD_VDDC_CURVE:
 863                 if (!smu->od_enabled || !od_table || !od_settings)
 864                         break;
 865                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE))
 866                         break;
 867                 size += sprintf(buf + size, "OD_VDDC_CURVE:\n");
 868                 for (i = 0; i < 3; i++) {
 869                         switch (i) {
 870                         case 0:
 871                                 curve_settings = &od_table->GfxclkFreq1;
 872                                 break;
 873                         case 1:
 874                                 curve_settings = &od_table->GfxclkFreq2;
 875                                 break;
 876                         case 2:
 877                                 curve_settings = &od_table->GfxclkFreq3;
 878                                 break;
 879                         default:
 880                                 break;
 881                         }
 882                         size += sprintf(buf + size, "%d: %uMHz @ %umV\n", i, curve_settings[0], curve_settings[1] / NAVI10_VOLTAGE_SCALE);
 883                 }
 884                 break;
 885         case SMU_OD_RANGE:
 886                 if (!smu->od_enabled || !od_table || !od_settings)
 887                         break;
 888                 size = sprintf(buf, "%s:\n", "OD_RANGE");
 889
 890                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS)) {
 891                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
 892                                                     &min_value, NULL);
 893                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
 894                                                     NULL, &max_value);
 895                         size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
 896                                         min_value, max_value);
 897                 }
 898
 899                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX)) {
 900                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
 901                                                     &min_value, &max_value);
 902                         size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
 903                                         min_value, max_value);
 904                 }
 905
 906                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE)) {
 907                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
 908                                                     &min_value, &max_value);
 909                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
 910                                         min_value, max_value);
 911                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
 912                                                     &min_value, &max_value);
 913                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
 914                                         min_value, max_value);
 915                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
 916                                                     &min_value, &max_value);
 917                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
 918                                         min_value, max_value);
 919                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
 920                                                     &min_value, &max_value);
 921                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
 922                                         min_value, max_value);
 923                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
 924                                                     &min_value, &max_value);
 925                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
 926                                         min_value, max_value);
 927                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
 928                                                     &min_value, &max_value);
 929                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
 930                                         min_value, max_value);
 931                 }
 932
 933                 break;
 934         default:
 935                 break;
 936         }
 937
 938         return size;
 939 }
 940
 941 static int navi10_force_clk_levels(struct smu_context *smu,
 942                                    enum smu_clk_type clk_type, uint32_t mask)
 943 {
 944
 945         int ret = 0, size = 0;
 946         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
 947
 948         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 949         soft_max_level = mask ? (fls(mask) - 1) : 0;
 950
 951         switch (clk_type) {
 952         case SMU_GFXCLK:
 953         case SMU_SCLK:
 954         case SMU_SOCCLK:
 955         case SMU_MCLK:
 956         case SMU_UCLK:
 957         case SMU_DCEFCLK:
 958         case SMU_FCLK:
 959                 /* There is only 2 levels for fine grained DPM */
 960                 if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
 961                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
 962                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
 963                 }
 964
 965                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
 966                 if (ret)
 967                         return size;
 968
 969                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
 970                 if (ret)
 971                         return size;
 972
 973                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
 974                 if (ret)
 975                         return size;
 976                 break;
 977         default:
 978                 break;
 979         }
 980
 981         return size;
 982 }
 983
 984 static int navi10_populate_umd_state_clk(struct smu_context *smu)
 985 {
 986         int ret = 0;
 987         uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
 988
 989         ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
 990         if (ret)
 991                 return ret;
 992
 993         smu->pstate_sclk = min_sclk_freq * 100;
 994
 995         ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
 996         if (ret)
 997                 return ret;
 998
 999         smu->pstate_mclk = min_mclk_freq * 100;
1000
1001         return ret;
1002 }
1003
1004 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
1005                                                  enum smu_clk_type clk_type,
1006                                                  struct pp_clock_levels_with_latency *clocks)
1007 {
1008         int ret = 0, i = 0;
1009         uint32_t level_count = 0, freq = 0;
1010
1011         switch (clk_type) {
1012         case SMU_GFXCLK:
1013         case SMU_DCEFCLK:
1014         case SMU_SOCCLK:
1015         case SMU_MCLK:
1016         case SMU_UCLK:
1017                 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
1018                 if (ret)
1019                         return ret;
1020
1021                 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
1022                 clocks->num_levels = level_count;
1023
1024                 for (i = 0; i < level_count; i++) {
1025                         ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
1026                         if (ret)
1027                                 return ret;
1028
1029                         clocks->data[i].clocks_in_khz = freq * 1000;
1030                         clocks->data[i].latency_in_us = 0;
1031                 }
1032                 break;
1033         default:
1034                 break;
1035         }
1036
1037         return ret;
1038 }
1039
1040 static int navi10_pre_display_config_changed(struct smu_context *smu)
1041 {
1042         int ret = 0;
1043         uint32_t max_freq = 0;
1044
1045         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
1046         if (ret)
1047                 return ret;
1048
1049         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1050                 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
1051                 if (ret)
1052                         return ret;
1053                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
1054                 if (ret)
1055                         return ret;
1056         }
1057
1058         return ret;
1059 }
1060
1061 static int navi10_display_config_changed(struct smu_context *smu)
1062 {
1063         int ret = 0;
1064
1065         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1066             !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1067                 ret = smu_write_watermarks_table(smu);
1068                 if (ret)
1069                         return ret;
1070
1071                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1072         }
1073
1074         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1075             smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1076             smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1077                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1078                                                   smu->display_config->num_display);
1079                 if (ret)
1080                         return ret;
1081         }
1082
1083         return ret;
1084 }
1085
1086 static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
1087 {
1088         int ret = 0, i = 0;
1089         uint32_t min_freq, max_freq, force_freq;
1090         enum smu_clk_type clk_type;
1091
1092         enum smu_clk_type clks[] = {
1093                 SMU_GFXCLK,
1094                 SMU_MCLK,
1095                 SMU_SOCCLK,
1096         };
1097
1098         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1099                 clk_type = clks[i];
1100                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
1101                 if (ret)
1102                         return ret;
1103
1104                 force_freq = highest ? max_freq : min_freq;
1105                 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq);
1106                 if (ret)
1107                         return ret;
1108         }
1109
1110         return ret;
1111 }
1112
1113 static int navi10_unforce_dpm_levels(struct smu_context *smu)
1114 {
1115         int ret = 0, i = 0;
1116         uint32_t min_freq, max_freq;
1117         enum smu_clk_type clk_type;
1118
1119         enum smu_clk_type clks[] = {
1120                 SMU_GFXCLK,
1121                 SMU_MCLK,
1122                 SMU_SOCCLK,
1123         };
1124
1125         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1126                 clk_type = clks[i];
1127                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
1128                 if (ret)
1129                         return ret;
1130
1131                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
1132                 if (ret)
1133                         return ret;
1134         }
1135
1136         return ret;
1137 }
1138
1139 static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
1140 {
1141         int ret = 0;
1142         SmuMetrics_t metrics;
1143
1144         if (!value)
1145                 return -EINVAL;
1146
1147         ret = navi10_get_metrics_table(smu, &metrics);
1148         if (ret)
1149                 return ret;
1150
1151         *value = metrics.AverageSocketPower << 8;
1152
1153         return 0;
1154 }
1155
1156 static int navi10_get_current_activity_percent(struct smu_context *smu,
1157                                                enum amd_pp_sensors sensor,
1158                                                uint32_t *value)
1159 {
1160         int ret = 0;
1161         SmuMetrics_t metrics;
1162
1163         if (!value)
1164                 return -EINVAL;
1165
1166         ret = navi10_get_metrics_table(smu, &metrics);
1167         if (ret)
1168                 return ret;
1169
1170         switch (sensor) {
1171         case AMDGPU_PP_SENSOR_GPU_LOAD:
1172                 *value = metrics.AverageGfxActivity;
1173                 break;
1174         case AMDGPU_PP_SENSOR_MEM_LOAD:
1175                 *value = metrics.AverageUclkActivity;
1176                 break;
1177         default:
1178                 pr_err("Invalid sensor for retrieving clock activity\n");
1179                 return -EINVAL;
1180         }
1181
1182         return 0;
1183 }
1184
1185 static bool navi10_is_dpm_running(struct smu_context *smu)
1186 {
1187         int ret = 0;
1188         uint32_t feature_mask[2];
1189         unsigned long feature_enabled;
1190         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1191         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1192                            ((uint64_t)feature_mask[1] << 32));
1193         return !!(feature_enabled & SMC_DPM_FEATURE);
1194 }
1195
1196 static int navi10_get_fan_speed_rpm(struct smu_context *smu,
1197                                     uint32_t *speed)
1198 {
1199         SmuMetrics_t metrics;
1200         int ret = 0;
1201
1202         if (!speed)
1203                 return -EINVAL;
1204
1205         ret = navi10_get_metrics_table(smu, &metrics);
1206         if (ret)
1207                 return ret;
1208
1209         *speed = metrics.CurrFanSpeed;
1210
1211         return ret;
1212 }
1213
1214 static int navi10_get_fan_speed_percent(struct smu_context *smu,
1215                                         uint32_t *speed)
1216 {
1217         int ret = 0;
1218         uint32_t percent = 0;
1219         uint32_t current_rpm;
1220         PPTable_t *pptable = smu->smu_table.driver_pptable;
1221
1222         ret = navi10_get_fan_speed_rpm(smu, &current_rpm);
1223         if (ret)
1224                 return ret;
1225
1226         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1227         *speed = percent > 100 ? 100 : percent;
1228
1229         return ret;
1230 }
1231
1232 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1233 {
1234         DpmActivityMonitorCoeffInt_t activity_monitor;
1235         uint32_t i, size = 0;
1236         int16_t workload_type = 0;
1237         static const char *profile_name[] = {
1238                                         "BOOTUP_DEFAULT",
1239                                         "3D_FULL_SCREEN",
1240                                         "POWER_SAVING",
1241                                         "VIDEO",
1242                                         "VR",
1243                                         "COMPUTE",
1244                                         "CUSTOM"};
1245         static const char *title[] = {
1246                         "PROFILE_INDEX(NAME)",
1247                         "CLOCK_TYPE(NAME)",
1248                         "FPS",
1249                         "MinFreqType",
1250                         "MinActiveFreqType",
1251                         "MinActiveFreq",
1252                         "BoosterFreqType",
1253                         "BoosterFreq",
1254                         "PD_Data_limit_c",
1255                         "PD_Data_error_coeff",
1256                         "PD_Data_error_rate_coeff"};
1257         int result = 0;
1258
1259         if (!buf)
1260                 return -EINVAL;
1261
1262         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1263                         title[0], title[1], title[2], title[3], title[4], title[5],
1264                         title[6], title[7], title[8], title[9], title[10]);
1265
1266         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1267                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1268                 workload_type = smu_workload_get_type(smu, i);
1269                 if (workload_type < 0)
1270                         return -EINVAL;
1271
1272                 result = smu_update_table(smu,
1273                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1274                                           (void *)(&activity_monitor), false);
1275                 if (result) {
1276                         pr_err("[%s] Failed to get activity monitor!", __func__);
1277                         return result;
1278                 }
1279
1280                 size += sprintf(buf + size, "%2d %14s%s:\n",
1281                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1282
1283                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1284                         " ",
1285                         0,
1286                         "GFXCLK",
1287                         activity_monitor.Gfx_FPS,
1288                         activity_monitor.Gfx_MinFreqStep,
1289                         activity_monitor.Gfx_MinActiveFreqType,
1290                         activity_monitor.Gfx_MinActiveFreq,
1291                         activity_monitor.Gfx_BoosterFreqType,
1292                         activity_monitor.Gfx_BoosterFreq,
1293                         activity_monitor.Gfx_PD_Data_limit_c,
1294                         activity_monitor.Gfx_PD_Data_error_coeff,
1295                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1296
1297                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1298                         " ",
1299                         1,
1300                         "SOCCLK",
1301                         activity_monitor.Soc_FPS,
1302                         activity_monitor.Soc_MinFreqStep,
1303                         activity_monitor.Soc_MinActiveFreqType,
1304                         activity_monitor.Soc_MinActiveFreq,
1305                         activity_monitor.Soc_BoosterFreqType,
1306                         activity_monitor.Soc_BoosterFreq,
1307                         activity_monitor.Soc_PD_Data_limit_c,
1308                         activity_monitor.Soc_PD_Data_error_coeff,
1309                         activity_monitor.Soc_PD_Data_error_rate_coeff);
1310
1311                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1312                         " ",
1313                         2,
1314                         "MEMLK",
1315                         activity_monitor.Mem_FPS,
1316                         activity_monitor.Mem_MinFreqStep,
1317                         activity_monitor.Mem_MinActiveFreqType,
1318                         activity_monitor.Mem_MinActiveFreq,
1319                         activity_monitor.Mem_BoosterFreqType,
1320                         activity_monitor.Mem_BoosterFreq,
1321                         activity_monitor.Mem_PD_Data_limit_c,
1322                         activity_monitor.Mem_PD_Data_error_coeff,
1323                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1324         }
1325
1326         return size;
1327 }
1328
1329 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1330 {
1331         DpmActivityMonitorCoeffInt_t activity_monitor;
1332         int workload_type, ret = 0;
1333
1334         smu->power_profile_mode = input[size];
1335
1336         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1337                 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1338                 return -EINVAL;
1339         }
1340
1341         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1342                 if (size < 0)
1343                         return -EINVAL;
1344
1345                 ret = smu_update_table(smu,
1346                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1347                                        (void *)(&activity_monitor), false);
1348                 if (ret) {
1349                         pr_err("[%s] Failed to get activity monitor!", __func__);
1350                         return ret;
1351                 }
1352
1353                 switch (input[0]) {
1354                 case 0: /* Gfxclk */
1355                         activity_monitor.Gfx_FPS = input[1];
1356                         activity_monitor.Gfx_MinFreqStep = input[2];
1357                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1358                         activity_monitor.Gfx_MinActiveFreq = input[4];
1359                         activity_monitor.Gfx_BoosterFreqType = input[5];
1360                         activity_monitor.Gfx_BoosterFreq = input[6];
1361                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1362                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1363                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1364                         break;
1365                 case 1: /* Socclk */
1366                         activity_monitor.Soc_FPS = input[1];
1367                         activity_monitor.Soc_MinFreqStep = input[2];
1368                         activity_monitor.Soc_MinActiveFreqType = input[3];
1369                         activity_monitor.Soc_MinActiveFreq = input[4];
1370                         activity_monitor.Soc_BoosterFreqType = input[5];
1371                         activity_monitor.Soc_BoosterFreq = input[6];
1372                         activity_monitor.Soc_PD_Data_limit_c = input[7];
1373                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
1374                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1375                         break;
1376                 case 2: /* Memlk */
1377                         activity_monitor.Mem_FPS = input[1];
1378                         activity_monitor.Mem_MinFreqStep = input[2];
1379                         activity_monitor.Mem_MinActiveFreqType = input[3];
1380                         activity_monitor.Mem_MinActiveFreq = input[4];
1381                         activity_monitor.Mem_BoosterFreqType = input[5];
1382                         activity_monitor.Mem_BoosterFreq = input[6];
1383                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1384                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1385                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1386                         break;
1387                 }
1388
1389                 ret = smu_update_table(smu,
1390                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1391                                        (void *)(&activity_monitor), true);
1392                 if (ret) {
1393                         pr_err("[%s] Failed to set activity monitor!", __func__);
1394                         return ret;
1395                 }
1396         }
1397
1398         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1399         workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1400         if (workload_type < 0)
1401                 return -EINVAL;
1402         smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1403                                     1 << workload_type);
1404
1405         return ret;
1406 }
1407
1408 static int navi10_get_profiling_clk_mask(struct smu_context *smu,
1409                                          enum amd_dpm_forced_level level,
1410                                          uint32_t *sclk_mask,
1411                                          uint32_t *mclk_mask,
1412                                          uint32_t *soc_mask)
1413 {
1414         int ret = 0;
1415         uint32_t level_count = 0;
1416
1417         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1418                 if (sclk_mask)
1419                         *sclk_mask = 0;
1420         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1421                 if (mclk_mask)
1422                         *mclk_mask = 0;
1423         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1424                 if(sclk_mask) {
1425                         ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1426                         if (ret)
1427                                 return ret;
1428                         *sclk_mask = level_count - 1;
1429                 }
1430
1431                 if(mclk_mask) {
1432                         ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1433                         if (ret)
1434                                 return ret;
1435                         *mclk_mask = level_count - 1;
1436                 }
1437
1438                 if(soc_mask) {
1439                         ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1440                         if (ret)
1441                                 return ret;
1442                         *soc_mask = level_count - 1;
1443                 }
1444         }
1445
1446         return ret;
1447 }
1448
1449 static int navi10_notify_smc_display_config(struct smu_context *smu)
1450 {
1451         struct smu_clocks min_clocks = {0};
1452         struct pp_display_clock_request clock_req;
1453         int ret = 0;
1454
1455         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1456         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1457         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1458
1459         if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1460                 clock_req.clock_type = amd_pp_dcef_clock;
1461                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1462
1463                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1464                 if (!ret) {
1465                         if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1466                                 ret = smu_send_smc_msg_with_param(smu,
1467                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1468                                                                   min_clocks.dcef_clock_in_sr/100);
1469                                 if (ret) {
1470                                         pr_err("Attempt to set divider for DCEFCLK Failed!");
1471                                         return ret;
1472                                 }
1473                         }
1474                 } else {
1475                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1476                 }
1477         }
1478
1479         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1480                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1481                 if (ret) {
1482                         pr_err("[%s] Set hard min uclk failed!", __func__);
1483                         return ret;
1484                 }
1485         }
1486
1487         return 0;
1488 }
1489
1490 static int navi10_set_watermarks_table(struct smu_context *smu,
1491                                        void *watermarks, struct
1492                                        dm_pp_wm_sets_with_clock_ranges_soc15
1493                                        *clock_ranges)
1494 {
1495         int i;
1496         Watermarks_t *table = watermarks;
1497
1498         if (!table || !clock_ranges)
1499                 return -EINVAL;
1500
1501         if (clock_ranges->num_wm_dmif_sets > 4 ||
1502             clock_ranges->num_wm_mcif_sets > 4)
1503                 return -EINVAL;
1504
1505         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1506                 table->WatermarkRow[1][i].MinClock =
1507                         cpu_to_le16((uint16_t)
1508                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1509                         1000));
1510                 table->WatermarkRow[1][i].MaxClock =
1511                         cpu_to_le16((uint16_t)
1512                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1513                         1000));
1514                 table->WatermarkRow[1][i].MinUclk =
1515                         cpu_to_le16((uint16_t)
1516                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1517                         1000));
1518                 table->WatermarkRow[1][i].MaxUclk =
1519                         cpu_to_le16((uint16_t)
1520                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1521                         1000));
1522                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1523                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1524         }
1525
1526         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1527                 table->WatermarkRow[0][i].MinClock =
1528                         cpu_to_le16((uint16_t)
1529                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1530                         1000));
1531                 table->WatermarkRow[0][i].MaxClock =
1532                         cpu_to_le16((uint16_t)
1533                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1534                         1000));
1535                 table->WatermarkRow[0][i].MinUclk =
1536                         cpu_to_le16((uint16_t)
1537                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1538                         1000));
1539                 table->WatermarkRow[0][i].MaxUclk =
1540                         cpu_to_le16((uint16_t)
1541                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1542                         1000));
1543                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1544                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1545         }
1546
1547         return 0;
1548 }
1549
1550 static int navi10_thermal_get_temperature(struct smu_context *smu,
1551                                              enum amd_pp_sensors sensor,
1552                                              uint32_t *value)
1553 {
1554         SmuMetrics_t metrics;
1555         int ret = 0;
1556
1557         if (!value)
1558                 return -EINVAL;
1559
1560         ret = navi10_get_metrics_table(smu, &metrics);
1561         if (ret)
1562                 return ret;
1563
1564         switch (sensor) {
1565         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1566                 *value = metrics.TemperatureHotspot *
1567                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1568                 break;
1569         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1570                 *value = metrics.TemperatureEdge *
1571                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1572                 break;
1573         case AMDGPU_PP_SENSOR_MEM_TEMP:
1574                 *value = metrics.TemperatureMem *
1575                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1576                 break;
1577         default:
1578                 pr_err("Invalid sensor for retrieving temp\n");
1579                 return -EINVAL;
1580         }
1581
1582         return 0;
1583 }
1584
1585 static int navi10_read_sensor(struct smu_context *smu,
1586                                  enum amd_pp_sensors sensor,
1587                                  void *data, uint32_t *size)
1588 {
1589         int ret = 0;
1590         struct smu_table_context *table_context = &smu->smu_table;
1591         PPTable_t *pptable = table_context->driver_pptable;
1592
1593         if(!data || !size)
1594                 return -EINVAL;
1595
1596         mutex_lock(&smu->sensor_lock);
1597         switch (sensor) {
1598         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1599                 *(uint32_t *)data = pptable->FanMaximumRpm;
1600                 *size = 4;
1601                 break;
1602         case AMDGPU_PP_SENSOR_MEM_LOAD:
1603         case AMDGPU_PP_SENSOR_GPU_LOAD:
1604                 ret = navi10_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1605                 *size = 4;
1606                 break;
1607         case AMDGPU_PP_SENSOR_GPU_POWER:
1608                 ret = navi10_get_gpu_power(smu, (uint32_t *)data);
1609                 *size = 4;
1610                 break;
1611         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1612         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1613         case AMDGPU_PP_SENSOR_MEM_TEMP:
1614                 ret = navi10_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1615                 *size = 4;
1616                 break;
1617         default:
1618                 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1619         }
1620         mutex_unlock(&smu->sensor_lock);
1621
1622         return ret;
1623 }
1624
1625 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1626 {
1627         uint32_t num_discrete_levels = 0;
1628         uint16_t *dpm_levels = NULL;
1629         uint16_t i = 0;
1630         struct smu_table_context *table_context = &smu->smu_table;
1631         PPTable_t *driver_ppt = NULL;
1632
1633         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1634                 return -EINVAL;
1635
1636         driver_ppt = table_context->driver_pptable;
1637         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1638         dpm_levels = driver_ppt->FreqTableUclk;
1639
1640         if (num_discrete_levels == 0 || dpm_levels == NULL)
1641                 return -EINVAL;
1642
1643         *num_states = num_discrete_levels;
1644         for (i = 0; i < num_discrete_levels; i++) {
1645                 /* convert to khz */
1646                 *clocks_in_khz = (*dpm_levels) * 1000;
1647                 clocks_in_khz++;
1648                 dpm_levels++;
1649         }
1650
1651         return 0;
1652 }
1653
1654 static int navi10_set_performance_level(struct smu_context *smu,
1655                                         enum amd_dpm_forced_level level);
1656
1657 static int navi10_set_standard_performance_level(struct smu_context *smu)
1658 {
1659         struct amdgpu_device *adev = smu->adev;
1660         int ret = 0;
1661         uint32_t sclk_freq = 0, uclk_freq = 0;
1662
1663         switch (adev->asic_type) {
1664         case CHIP_NAVI10:
1665                 sclk_freq = NAVI10_UMD_PSTATE_PROFILING_GFXCLK;
1666                 uclk_freq = NAVI10_UMD_PSTATE_PROFILING_MEMCLK;
1667                 break;
1668         case CHIP_NAVI14:
1669                 sclk_freq = NAVI14_UMD_PSTATE_PROFILING_GFXCLK;
1670                 uclk_freq = NAVI14_UMD_PSTATE_PROFILING_MEMCLK;
1671                 break;
1672         default:
1673                 /* by default, this is same as auto performance level */
1674                 return navi10_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
1675         }
1676
1677         ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
1678         if (ret)
1679                 return ret;
1680         ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
1681         if (ret)
1682                 return ret;
1683
1684         return ret;
1685 }
1686
1687 static int navi10_set_peak_performance_level(struct smu_context *smu)
1688 {
1689         struct amdgpu_device *adev = smu->adev;
1690         int ret = 0;
1691         uint32_t sclk_freq = 0, uclk_freq = 0;
1692
1693         switch (adev->asic_type) {
1694         case CHIP_NAVI10:
1695                 switch (adev->pdev->revision) {
1696                 case 0xf0: /* XTX */
1697                 case 0xc0:
1698                         sclk_freq = NAVI10_PEAK_SCLK_XTX;
1699                         break;
1700                 case 0xf1: /* XT */
1701                 case 0xc1:
1702                         sclk_freq = NAVI10_PEAK_SCLK_XT;
1703                         break;
1704                 default: /* XL */
1705                         sclk_freq = NAVI10_PEAK_SCLK_XL;
1706                         break;
1707                 }
1708                 break;
1709         case CHIP_NAVI14:
1710                 switch (adev->pdev->revision) {
1711                 case 0xc7: /* XT */
1712                 case 0xf4:
1713                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
1714                         break;
1715                 case 0xc1: /* XTM */
1716                 case 0xf2:
1717                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
1718                         break;
1719                 case 0xc3: /* XLM */
1720                 case 0xf3:
1721                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1722                         break;
1723                 case 0xc5: /* XTX */
1724                 case 0xf6:
1725                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1726                         break;
1727                 default: /* XL */
1728                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
1729                         break;
1730                 }
1731                 break;
1732         case CHIP_NAVI12:
1733                 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
1734                 break;
1735         default:
1736                 ret = smu_get_dpm_level_range(smu, SMU_SCLK, NULL, &sclk_freq);
1737                 if (ret)
1738                         return ret;
1739         }
1740
1741         ret = smu_get_dpm_level_range(smu, SMU_UCLK, NULL, &uclk_freq);
1742         if (ret)
1743                 return ret;
1744
1745         ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
1746         if (ret)
1747                 return ret;
1748         ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
1749         if (ret)
1750                 return ret;
1751
1752         return ret;
1753 }
1754
1755 static int navi10_set_performance_level(struct smu_context *smu,
1756                                         enum amd_dpm_forced_level level)
1757 {
1758         int ret = 0;
1759         uint32_t sclk_mask, mclk_mask, soc_mask;
1760
1761         switch (level) {
1762         case AMD_DPM_FORCED_LEVEL_HIGH:
1763                 ret = smu_force_dpm_limit_value(smu, true);
1764                 break;
1765         case AMD_DPM_FORCED_LEVEL_LOW:
1766                 ret = smu_force_dpm_limit_value(smu, false);
1767                 break;
1768         case AMD_DPM_FORCED_LEVEL_AUTO:
1769                 ret = smu_unforce_dpm_levels(smu);
1770                 break;
1771         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1772                 ret = navi10_set_standard_performance_level(smu);
1773                 break;
1774         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1775         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1776                 ret = smu_get_profiling_clk_mask(smu, level,
1777                                                  &sclk_mask,
1778                                                  &mclk_mask,
1779                                                  &soc_mask);
1780                 if (ret)
1781                         return ret;
1782                 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1783                 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1784                 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1785                 break;
1786         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1787                 ret = navi10_set_peak_performance_level(smu);
1788                 break;
1789         case AMD_DPM_FORCED_LEVEL_MANUAL:
1790         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1791         default:
1792                 break;
1793         }
1794         return ret;
1795 }
1796
1797 static int navi10_get_thermal_temperature_range(struct smu_context *smu,
1798                                                 struct smu_temperature_range *range)
1799 {
1800         struct smu_table_context *table_context = &smu->smu_table;
1801         struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1802
1803         if (!range || !powerplay_table)
1804                 return -EINVAL;
1805
1806         range->max = powerplay_table->software_shutdown_temp *
1807                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1808
1809         return 0;
1810 }
1811
1812 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
1813                                                 bool disable_memory_clock_switch)
1814 {
1815         int ret = 0;
1816         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1817                 (struct smu_11_0_max_sustainable_clocks *)
1818                         smu->smu_table.max_sustainable_clocks;
1819         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1820         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1821
1822         if(smu->disable_uclk_switch == disable_memory_clock_switch)
1823                 return 0;
1824
1825         if(disable_memory_clock_switch)
1826                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
1827         else
1828                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
1829
1830         if(!ret)
1831                 smu->disable_uclk_switch = disable_memory_clock_switch;
1832
1833         return ret;
1834 }
1835
1836 static uint32_t navi10_get_pptable_power_limit(struct smu_context *smu)
1837 {
1838         PPTable_t *pptable = smu->smu_table.driver_pptable;
1839         return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1840 }
1841
1842 static int navi10_get_power_limit(struct smu_context *smu,
1843                                      uint32_t *limit,
1844                                      bool cap)
1845 {
1846         PPTable_t *pptable = smu->smu_table.driver_pptable;
1847         uint32_t asic_default_power_limit = 0;
1848         int ret = 0;
1849         int power_src;
1850
1851         if (!smu->power_limit) {
1852                 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1853                         power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1854                         if (power_src < 0)
1855                                 return -EINVAL;
1856
1857                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1858                                 power_src << 16);
1859                         if (ret) {
1860                                 pr_err("[%s] get PPT limit failed!", __func__);
1861                                 return ret;
1862                         }
1863                         smu_read_smc_arg(smu, &asic_default_power_limit);
1864                 } else {
1865                         /* the last hope to figure out the ppt limit */
1866                         if (!pptable) {
1867                                 pr_err("Cannot get PPT limit due to pptable missing!");
1868                                 return -EINVAL;
1869                         }
1870                         asic_default_power_limit =
1871                                 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1872                 }
1873
1874                 smu->power_limit = asic_default_power_limit;
1875         }
1876
1877         if (cap)
1878                 *limit = smu_v11_0_get_max_power_limit(smu);
1879         else
1880                 *limit = smu->power_limit;
1881
1882         return 0;
1883 }
1884
1885 static int navi10_update_pcie_parameters(struct smu_context *smu,
1886                                      uint32_t pcie_gen_cap,
1887                                      uint32_t pcie_width_cap)
1888 {
1889         PPTable_t *pptable = smu->smu_table.driver_pptable;
1890         int ret, i;
1891         uint32_t smu_pcie_arg;
1892
1893         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1894         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1895
1896         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1897                 smu_pcie_arg = (i << 16) |
1898                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
1899                                 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1900                                         pptable->PcieLaneCount[i] : pcie_width_cap);
1901                 ret = smu_send_smc_msg_with_param(smu,
1902                                           SMU_MSG_OverridePcieParameters,
1903                                           smu_pcie_arg);
1904
1905                 if (ret)
1906                         return ret;
1907
1908                 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1909                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1910                 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1911                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1912         }
1913
1914         return 0;
1915 }
1916
1917 static inline void navi10_dump_od_table(OverDriveTable_t *od_table) {
1918         pr_debug("OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1919         pr_debug("OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
1920         pr_debug("OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
1921         pr_debug("OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
1922         pr_debug("OD: UclkFmax: %d\n", od_table->UclkFmax);
1923         pr_debug("OD: OverDrivePct: %d\n", od_table->OverDrivePct);
1924 }
1925
1926 static int navi10_od_setting_check_range(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODSETTING_ID setting, uint32_t value)
1927 {
1928         if (value < od_table->min[setting]) {
1929                 pr_warn("OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
1930                 return -EINVAL;
1931         }
1932         if (value > od_table->max[setting]) {
1933                 pr_warn("OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
1934                 return -EINVAL;
1935         }
1936         return 0;
1937 }
1938
1939 static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
1940                                                      uint16_t *voltage,
1941                                                      uint32_t freq)
1942 {
1943         uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16);
1944         uint32_t value = 0;
1945         int ret;
1946
1947         ret = smu_send_smc_msg_with_param(smu,
1948                                           SMU_MSG_GetVoltageByDpm,
1949                                           param);
1950         if (ret) {
1951                 pr_err("[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
1952                 return ret;
1953         }
1954
1955         smu_read_smc_arg(smu, &value);
1956         *voltage = (uint16_t)value;
1957
1958         return 0;
1959 }
1960
1961 static int navi10_setup_od_limits(struct smu_context *smu) {
1962         struct smu_11_0_overdrive_table *overdrive_table = NULL;
1963         struct smu_11_0_powerplay_table *powerplay_table = NULL;
1964
1965         if (!smu->smu_table.power_play_table) {
1966                 pr_err("powerplay table uninitialized!\n");
1967                 return -ENOENT;
1968         }
1969         powerplay_table = (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1970         overdrive_table = &powerplay_table->overdrive_table;
1971         if (!smu->od_settings) {
1972                 smu->od_settings = kmemdup(overdrive_table, sizeof(struct smu_11_0_overdrive_table), GFP_KERNEL);
1973         } else {
1974                 memcpy(smu->od_settings, overdrive_table, sizeof(struct smu_11_0_overdrive_table));
1975         }
1976         return 0;
1977 }
1978
1979 static int navi10_set_default_od_settings(struct smu_context *smu, bool initialize) {
1980         OverDriveTable_t *od_table, *boot_od_table;
1981         int ret = 0;
1982
1983         ret = smu_v11_0_set_default_od_settings(smu, initialize, sizeof(OverDriveTable_t));
1984         if (ret)
1985                 return ret;
1986
1987         od_table = (OverDriveTable_t *)smu->smu_table.overdrive_table;
1988         boot_od_table = (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
1989         if (initialize) {
1990                 ret = navi10_setup_od_limits(smu);
1991                 if (ret) {
1992                         pr_err("Failed to retrieve board OD limits\n");
1993                         return ret;
1994                 }
1995                 if (od_table) {
1996                         if (!od_table->GfxclkVolt1) {
1997                                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
1998                                                                                 &od_table->GfxclkVolt1,
1999                                                                                 od_table->GfxclkFreq1);
2000                                 if (ret)
2001                                         od_table->GfxclkVolt1 = 0;
2002                                 if (boot_od_table)
2003                                         boot_od_table->GfxclkVolt1 = od_table->GfxclkVolt1;
2004                         }
2005
2006                         if (!od_table->GfxclkVolt2) {
2007                                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2008                                                                                 &od_table->GfxclkVolt2,
2009                                                                                 od_table->GfxclkFreq2);
2010                                 if (ret)
2011                                         od_table->GfxclkVolt2 = 0;
2012                                 if (boot_od_table)
2013                                         boot_od_table->GfxclkVolt2 = od_table->GfxclkVolt2;
2014                         }
2015
2016                         if (!od_table->GfxclkVolt3) {
2017                                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2018                                                                                 &od_table->GfxclkVolt3,
2019                                                                                 od_table->GfxclkFreq3);
2020                                 if (ret)
2021                                         od_table->GfxclkVolt3 = 0;
2022                                 if (boot_od_table)
2023                                         boot_od_table->GfxclkVolt3 = od_table->GfxclkVolt3;
2024                         }
2025                 }
2026         }
2027
2028         if (od_table) {
2029                 navi10_dump_od_table(od_table);
2030         }
2031
2032         return ret;
2033 }
2034
2035 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) {
2036         int i;
2037         int ret = 0;
2038         struct smu_table_context *table_context = &smu->smu_table;
2039         OverDriveTable_t *od_table;
2040         struct smu_11_0_overdrive_table *od_settings;
2041         enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting;
2042         uint16_t *freq_ptr, *voltage_ptr;
2043         od_table = (OverDriveTable_t *)table_context->overdrive_table;
2044
2045         if (!smu->od_enabled) {
2046                 pr_warn("OverDrive is not enabled!\n");
2047                 return -EINVAL;
2048         }
2049
2050         if (!smu->od_settings) {
2051                 pr_err("OD board limits are not set!\n");
2052                 return -ENOENT;
2053         }
2054
2055         od_settings = smu->od_settings;
2056
2057         switch (type) {
2058         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2059                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS)) {
2060                         pr_warn("GFXCLK_LIMITS not supported!\n");
2061                         return -ENOTSUPP;
2062                 }
2063                 if (!table_context->overdrive_table) {
2064                         pr_err("Overdrive is not initialized\n");
2065                         return -EINVAL;
2066                 }
2067                 for (i = 0; i < size; i += 2) {
2068                         if (i + 2 > size) {
2069                                 pr_info("invalid number of input parameters %d\n", size);
2070                                 return -EINVAL;
2071                         }
2072                         switch (input[i]) {
2073                         case 0:
2074                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
2075                                 freq_ptr = &od_table->GfxclkFmin;
2076                                 if (input[i + 1] > od_table->GfxclkFmax) {
2077                                         pr_info("GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2078                                                 input[i + 1],
2079                                                 od_table->GfxclkFmin);
2080                                         return -EINVAL;
2081                                 }
2082                                 break;
2083                         case 1:
2084                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
2085                                 freq_ptr = &od_table->GfxclkFmax;
2086                                 if (input[i + 1] < od_table->GfxclkFmin) {
2087                                         pr_info("GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2088                                                 input[i + 1],
2089                                                 od_table->GfxclkFmax);
2090                                         return -EINVAL;
2091                                 }
2092                                 break;
2093                         default:
2094                                 pr_info("Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2095                                 pr_info("Supported indices: [0:min,1:max]\n");
2096                                 return -EINVAL;
2097                         }
2098                         ret = navi10_od_setting_check_range(od_settings, freq_setting, input[i + 1]);
2099                         if (ret)
2100                                 return ret;
2101                         *freq_ptr = input[i + 1];
2102                 }
2103                 break;
2104         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2105                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX)) {
2106                         pr_warn("UCLK_MAX not supported!\n");
2107                         return -ENOTSUPP;
2108                 }
2109                 if (size < 2) {
2110                         pr_info("invalid number of parameters: %d\n", size);
2111                         return -EINVAL;
2112                 }
2113                 if (input[0] != 1) {
2114                         pr_info("Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
2115                         pr_info("Supported indices: [1:max]\n");
2116                         return -EINVAL;
2117                 }
2118                 ret = navi10_od_setting_check_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
2119                 if (ret)
2120                         return ret;
2121                 od_table->UclkFmax = input[1];
2122                 break;
2123         case PP_OD_RESTORE_DEFAULT_TABLE:
2124                 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2125                         pr_err("Overdrive table was not initialized!\n");
2126                         return -EINVAL;
2127                 }
2128                 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t));
2129                 break;
2130         case PP_OD_COMMIT_DPM_TABLE:
2131                 navi10_dump_od_table(od_table);
2132                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2133                 if (ret) {
2134                         pr_err("Failed to import overdrive table!\n");
2135                         return ret;
2136                 }
2137                 // no lock needed because smu_od_edit_dpm_table has it
2138                 ret = smu_handle_task(smu, smu->smu_dpm.dpm_level,
2139                         AMD_PP_TASK_READJUST_POWER_STATE,
2140                         false);
2141                 if (ret) {
2142                         return ret;
2143                 }
2144                 break;
2145         case PP_OD_EDIT_VDDC_CURVE:
2146                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE)) {
2147                         pr_warn("GFXCLK_CURVE not supported!\n");
2148                         return -ENOTSUPP;
2149                 }
2150                 if (size < 3) {
2151                         pr_info("invalid number of parameters: %d\n", size);
2152                         return -EINVAL;
2153                 }
2154                 if (!od_table) {
2155                         pr_info("Overdrive is not initialized\n");
2156                         return -EINVAL;
2157                 }
2158
2159                 switch (input[0]) {
2160                 case 0:
2161                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1;
2162                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1;
2163                         freq_ptr = &od_table->GfxclkFreq1;
2164                         voltage_ptr = &od_table->GfxclkVolt1;
2165                         break;
2166                 case 1:
2167                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2;
2168                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2;
2169                         freq_ptr = &od_table->GfxclkFreq2;
2170                         voltage_ptr = &od_table->GfxclkVolt2;
2171                         break;
2172                 case 2:
2173                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3;
2174                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3;
2175                         freq_ptr = &od_table->GfxclkFreq3;
2176                         voltage_ptr = &od_table->GfxclkVolt3;
2177                         break;
2178                 default:
2179                         pr_info("Invalid VDDC_CURVE index: %ld\n", input[0]);
2180                         pr_info("Supported indices: [0, 1, 2]\n");
2181                         return -EINVAL;
2182                 }
2183                 ret = navi10_od_setting_check_range(od_settings, freq_setting, input[1]);
2184                 if (ret)
2185                         return ret;
2186                 // Allow setting zero to disable the OverDrive VDDC curve
2187                 if (input[2] != 0) {
2188                         ret = navi10_od_setting_check_range(od_settings, voltage_setting, input[2]);
2189                         if (ret)
2190                                 return ret;
2191                         *freq_ptr = input[1];
2192                         *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
2193                         pr_debug("OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
2194                 } else {
2195                         // If setting 0, disable all voltage curve settings
2196                         od_table->GfxclkVolt1 = 0;
2197                         od_table->GfxclkVolt2 = 0;
2198                         od_table->GfxclkVolt3 = 0;
2199                 }
2200                 navi10_dump_od_table(od_table);
2201                 break;
2202         default:
2203                 return -ENOSYS;
2204         }
2205         return ret;
2206 }
2207
2208 static int navi10_run_btc(struct smu_context *smu)
2209 {
2210         int ret = 0;
2211
2212         ret = smu_send_smc_msg(smu, SMU_MSG_RunBtc);
2213         if (ret)
2214                 pr_err("RunBtc failed!\n");
2215
2216         return ret;
2217 }
2218
2219 static int navi10_dummy_pstate_control(struct smu_context *smu, bool enable)
2220 {
2221         int result = 0;
2222
2223         if (!enable)
2224                 result = smu_send_smc_msg(smu, SMU_MSG_DAL_DISABLE_DUMMY_PSTATE_CHANGE);
2225         else
2226                 result = smu_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE);
2227
2228         return result;
2229 }
2230
2231 static int navi10_disable_umc_cdr_12gbps_workaround(struct smu_context *smu)
2232 {
2233         uint32_t uclk_count, uclk_min, uclk_max;
2234         uint32_t smu_version;
2235         int ret = 0;
2236
2237         ret = smu_get_smc_version(smu, NULL, &smu_version);
2238         if (ret)
2239                 return ret;
2240
2241         /* This workaround is available only for 42.50 or later SMC firmwares */
2242         if (smu_version < 0x2A3200)
2243                 return 0;
2244
2245         ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_count);
2246         if (ret)
2247                 return ret;
2248
2249         ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min);
2250         if (ret)
2251                 return ret;
2252
2253         ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max);
2254         if (ret)
2255                 return ret;
2256
2257         /* Force UCLK out of the highest DPM */
2258         ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, uclk_min);
2259         if (ret)
2260                 return ret;
2261
2262         /* Revert the UCLK Hardmax */
2263         ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, uclk_max);
2264         if (ret)
2265                 return ret;
2266
2267         /*
2268          * In this case, SMU already disabled dummy pstate during enablement
2269          * of UCLK DPM, we have to re-enabled it.
2270          * */
2271         return navi10_dummy_pstate_control(smu, true);
2272 }
2273
2274 static const struct pptable_funcs navi10_ppt_funcs = {
2275         .tables_init = navi10_tables_init,
2276         .alloc_dpm_context = navi10_allocate_dpm_context,
2277         .store_powerplay_table = navi10_store_powerplay_table,
2278         .check_powerplay_table = navi10_check_powerplay_table,
2279         .append_powerplay_table = navi10_append_powerplay_table,
2280         .get_smu_msg_index = navi10_get_smu_msg_index,
2281         .get_smu_clk_index = navi10_get_smu_clk_index,
2282         .get_smu_feature_index = navi10_get_smu_feature_index,
2283         .get_smu_table_index = navi10_get_smu_table_index,
2284         .get_smu_power_index = navi10_get_pwr_src_index,
2285         .get_workload_type = navi10_get_workload_type,
2286         .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
2287         .set_default_dpm_table = navi10_set_default_dpm_table,
2288         .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
2289         .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
2290         .get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
2291         .print_clk_levels = navi10_print_clk_levels,
2292         .force_clk_levels = navi10_force_clk_levels,
2293         .populate_umd_state_clk = navi10_populate_umd_state_clk,
2294         .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
2295         .pre_display_config_changed = navi10_pre_display_config_changed,
2296         .display_config_changed = navi10_display_config_changed,
2297         .notify_smc_display_config = navi10_notify_smc_display_config,
2298         .force_dpm_limit_value = navi10_force_dpm_limit_value,
2299         .unforce_dpm_levels = navi10_unforce_dpm_levels,
2300         .is_dpm_running = navi10_is_dpm_running,
2301         .get_fan_speed_percent = navi10_get_fan_speed_percent,
2302         .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
2303         .get_power_profile_mode = navi10_get_power_profile_mode,
2304         .set_power_profile_mode = navi10_set_power_profile_mode,
2305         .get_profiling_clk_mask = navi10_get_profiling_clk_mask,
2306         .set_watermarks_table = navi10_set_watermarks_table,
2307         .read_sensor = navi10_read_sensor,
2308         .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
2309         .set_performance_level = navi10_set_performance_level,
2310         .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
2311         .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
2312         .get_power_limit = navi10_get_power_limit,
2313         .update_pcie_parameters = navi10_update_pcie_parameters,
2314         .init_microcode = smu_v11_0_init_microcode,
2315         .load_microcode = smu_v11_0_load_microcode,
2316         .init_smc_tables = smu_v11_0_init_smc_tables,
2317         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2318         .init_power = smu_v11_0_init_power,
2319         .fini_power = smu_v11_0_fini_power,
2320         .check_fw_status = smu_v11_0_check_fw_status,
2321         .setup_pptable = smu_v11_0_setup_pptable,
2322         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2323         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2324         .check_pptable = smu_v11_0_check_pptable,
2325         .parse_pptable = smu_v11_0_parse_pptable,
2326         .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2327         .check_fw_version = smu_v11_0_check_fw_version,
2328         .write_pptable = smu_v11_0_write_pptable,
2329         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2330         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2331         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2332         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2333         .system_features_control = smu_v11_0_system_features_control,
2334         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2335         .read_smc_arg = smu_v11_0_read_arg,
2336         .init_display_count = smu_v11_0_init_display_count,
2337         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2338         .get_enabled_mask = smu_v11_0_get_enabled_mask,
2339         .notify_display_change = smu_v11_0_notify_display_change,
2340         .set_power_limit = smu_v11_0_set_power_limit,
2341         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2342         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2343         .start_thermal_control = smu_v11_0_start_thermal_control,
2344         .stop_thermal_control = smu_v11_0_stop_thermal_control,
2345         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2346         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2347         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2348         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2349         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2350         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2351         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2352         .gfx_off_control = smu_v11_0_gfx_off_control,
2353         .register_irq_handler = smu_v11_0_register_irq_handler,
2354         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2355         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2356         .baco_is_support= smu_v11_0_baco_is_support,
2357         .baco_get_state = smu_v11_0_baco_get_state,
2358         .baco_set_state = smu_v11_0_baco_set_state,
2359         .baco_enter = smu_v11_0_baco_enter,
2360         .baco_exit = smu_v11_0_baco_exit,
2361         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2362         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2363         .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2364         .set_default_od_settings = navi10_set_default_od_settings,
2365         .od_edit_dpm_table = navi10_od_edit_dpm_table,
2366         .get_pptable_power_limit = navi10_get_pptable_power_limit,
2367         .run_btc = navi10_run_btc,
2368         .disable_umc_cdr_12gbps_workaround = navi10_disable_umc_cdr_12gbps_workaround,
2369 };
2370
2371 void navi10_set_ppt_funcs(struct smu_context *smu)
2372 {
2373         smu->ppt_funcs = &navi10_ppt_funcs;
2374 }