drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 #ifndef SMU_11_0_PPTABLE_H
  23 #define SMU_11_0_PPTABLE_H
  24
  25
  26 #define SMU_11_0_TABLE_FORMAT_REVISION                  12
  27
  28 //// POWERPLAYTABLE::ulPlatformCaps
  29 #define SMU_11_0_PP_PLATFORM_CAP_POWERPLAY              0x1
  30 #define SMU_11_0_PP_PLATFORM_CAP_SBIOSPOWERSOURCE       0x2
  31 #define SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC             0x4
  32 #define SMU_11_0_PP_PLATFORM_CAP_BACO                   0x8
  33 #define SMU_11_0_PP_PLATFORM_CAP_MACO                   0x10
  34 #define SMU_11_0_PP_PLATFORM_CAP_SHADOWPSTATE           0x20
  35
  36 // SMU_11_0_PP_THERMALCONTROLLER - Thermal Controller Type
  37 #define SMU_11_0_PP_THERMALCONTROLLER_NONE              0
  38
  39 #define SMU_11_0_PP_OVERDRIVE_VERSION                   0x0800
  40 #define SMU_11_0_PP_POWERSAVINGCLOCK_VERSION            0x0100
  41
  42 enum SMU_11_0_ODFEATURE_CAP {
  43     SMU_11_0_ODCAP_GFXCLK_LIMITS = 0,
  44     SMU_11_0_ODCAP_GFXCLK_CURVE,
  45     SMU_11_0_ODCAP_UCLK_MAX,
  46     SMU_11_0_ODCAP_POWER_LIMIT,
  47     SMU_11_0_ODCAP_FAN_ACOUSTIC_LIMIT,
  48     SMU_11_0_ODCAP_FAN_SPEED_MIN,
  49     SMU_11_0_ODCAP_TEMPERATURE_FAN,
  50     SMU_11_0_ODCAP_TEMPERATURE_SYSTEM,
  51     SMU_11_0_ODCAP_MEMORY_TIMING_TUNE,
  52     SMU_11_0_ODCAP_FAN_ZERO_RPM_CONTROL,
  53     SMU_11_0_ODCAP_AUTO_UV_ENGINE,
  54     SMU_11_0_ODCAP_AUTO_OC_ENGINE,
  55     SMU_11_0_ODCAP_AUTO_OC_MEMORY,
  56     SMU_11_0_ODCAP_FAN_CURVE,
  57     SMU_11_0_ODCAP_COUNT,
  58 };
  59
  60 enum SMU_11_0_ODFEATURE_ID {
  61     SMU_11_0_ODFEATURE_GFXCLK_LIMITS        = 1 << SMU_11_0_ODCAP_GFXCLK_LIMITS,            //GFXCLK Limit feature
  62     SMU_11_0_ODFEATURE_GFXCLK_CURVE         = 1 << SMU_11_0_ODCAP_GFXCLK_CURVE,             //GFXCLK Curve feature
  63     SMU_11_0_ODFEATURE_UCLK_MAX             = 1 << SMU_11_0_ODCAP_UCLK_MAX,                 //UCLK Limit feature
  64     SMU_11_0_ODFEATURE_POWER_LIMIT          = 1 << SMU_11_0_ODCAP_POWER_LIMIT,              //Power Limit feature
  65     SMU_11_0_ODFEATURE_FAN_ACOUSTIC_LIMIT   = 1 << SMU_11_0_ODCAP_FAN_ACOUSTIC_LIMIT,       //Fan Acoustic RPM feature
  66     SMU_11_0_ODFEATURE_FAN_SPEED_MIN        = 1 << SMU_11_0_ODCAP_FAN_SPEED_MIN,            //Minimum Fan Speed feature
  67     SMU_11_0_ODFEATURE_TEMPERATURE_FAN      = 1 << SMU_11_0_ODCAP_TEMPERATURE_FAN,          //Fan Target Temperature Limit feature
  68     SMU_11_0_ODFEATURE_TEMPERATURE_SYSTEM   = 1 << SMU_11_0_ODCAP_TEMPERATURE_SYSTEM,       //Operating Temperature Limit feature
  69     SMU_11_0_ODFEATURE_MEMORY_TIMING_TUNE   = 1 << SMU_11_0_ODCAP_MEMORY_TIMING_TUNE,       //AC Timing Tuning feature
  70     SMU_11_0_ODFEATURE_FAN_ZERO_RPM_CONTROL = 1 << SMU_11_0_ODCAP_FAN_ZERO_RPM_CONTROL,     //Zero RPM feature
  71     SMU_11_0_ODFEATURE_AUTO_UV_ENGINE       = 1 << SMU_11_0_ODCAP_AUTO_UV_ENGINE,           //Auto Under Volt GFXCLK feature
  72     SMU_11_0_ODFEATURE_AUTO_OC_ENGINE       = 1 << SMU_11_0_ODCAP_AUTO_OC_ENGINE,           //Auto Over Clock GFXCLK feature
  73     SMU_11_0_ODFEATURE_AUTO_OC_MEMORY       = 1 << SMU_11_0_ODCAP_AUTO_OC_MEMORY,           //Auto Over Clock MCLK feature
  74     SMU_11_0_ODFEATURE_FAN_CURVE            = 1 << SMU_11_0_ODCAP_FAN_CURVE,                //Fan Curve feature
  75     SMU_11_0_ODFEATURE_COUNT                = 14,
  76 };
  77 #define SMU_11_0_MAX_ODFEATURE    32          //Maximum Number of OD Features
  78
  79 enum SMU_11_0_ODSETTING_ID {
  80     SMU_11_0_ODSETTING_GFXCLKFMAX = 0,
  81     SMU_11_0_ODSETTING_GFXCLKFMIN,
  82     SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
  83     SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
  84     SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
  85     SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
  86     SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
  87     SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
  88     SMU_11_0_ODSETTING_UCLKFMAX,
  89     SMU_11_0_ODSETTING_POWERPERCENTAGE,
  90     SMU_11_0_ODSETTING_FANRPMMIN,
  91     SMU_11_0_ODSETTING_FANRPMACOUSTICLIMIT,
  92     SMU_11_0_ODSETTING_FANTARGETTEMPERATURE,
  93     SMU_11_0_ODSETTING_OPERATINGTEMPMAX,
  94     SMU_11_0_ODSETTING_ACTIMING,
  95     SMU_11_0_ODSETTING_FAN_ZERO_RPM_CONTROL,
  96     SMU_11_0_ODSETTING_AUTOUVENGINE,
  97     SMU_11_0_ODSETTING_AUTOOCENGINE,
  98     SMU_11_0_ODSETTING_AUTOOCMEMORY,
  99     SMU_11_0_ODSETTING_COUNT,
 100 };
 101 #define SMU_11_0_MAX_ODSETTING    32          //Maximum Number of ODSettings
 102
 103 struct smu_11_0_overdrive_table
 104 {
 105     uint8_t  revision;                                        //Revision = SMU_11_0_PP_OVERDRIVE_VERSION
 106     uint8_t  reserve[3];                                      //Zero filled field reserved for future use
 107     uint32_t feature_count;                                   //Total number of supported features
 108     uint32_t setting_count;                                   //Total number of supported settings
 109     uint8_t  cap[SMU_11_0_MAX_ODFEATURE];                     //OD feature support flags
 110     uint32_t max[SMU_11_0_MAX_ODSETTING];                     //default maximum settings
 111     uint32_t min[SMU_11_0_MAX_ODSETTING];                     //default minimum settings
 112 } __attribute__((packed));
 113
 114 enum SMU_11_0_PPCLOCK_ID {
 115     SMU_11_0_PPCLOCK_GFXCLK = 0,
 116     SMU_11_0_PPCLOCK_VCLK,
 117     SMU_11_0_PPCLOCK_DCLK,
 118     SMU_11_0_PPCLOCK_ECLK,
 119     SMU_11_0_PPCLOCK_SOCCLK,
 120     SMU_11_0_PPCLOCK_UCLK,
 121     SMU_11_0_PPCLOCK_DCEFCLK,
 122     SMU_11_0_PPCLOCK_DISPCLK,
 123     SMU_11_0_PPCLOCK_PIXCLK,
 124     SMU_11_0_PPCLOCK_PHYCLK,
 125     SMU_11_0_PPCLOCK_COUNT,
 126 };
 127 #define SMU_11_0_MAX_PPCLOCK      16          //Maximum Number of PP Clocks
 128
 129 struct smu_11_0_power_saving_clock_table
 130 {
 131     uint8_t  revision;                                        //Revision = SMU_11_0_PP_POWERSAVINGCLOCK_VERSION
 132     uint8_t  reserve[3];                                      //Zero filled field reserved for future use
 133     uint32_t count;                                           //power_saving_clock_count = SMU_11_0_PPCLOCK_COUNT
 134     uint32_t max[SMU_11_0_MAX_PPCLOCK];                       //PowerSavingClock Mode Clock Maximum array In MHz
 135     uint32_t min[SMU_11_0_MAX_PPCLOCK];                       //PowerSavingClock Mode Clock Minimum array In MHz
 136 } __attribute__((packed));
 137
 138 struct smu_11_0_powerplay_table
 139 {
 140       struct atom_common_table_header header;
 141       uint8_t  table_revision;
 142       uint16_t table_size;                          //Driver portion table size. The offset to smc_pptable including header size
 143       uint32_t golden_pp_id;
 144       uint32_t golden_revision;
 145       uint16_t format_id;
 146       uint32_t platform_caps;                       //POWERPLAYABLE::ulPlatformCaps
 147
 148       uint8_t  thermal_controller_type;             //one of SMU_11_0_PP_THERMALCONTROLLER
 149
 150       uint16_t small_power_limit1;
 151       uint16_t small_power_limit2;
 152       uint16_t boost_power_limit;
 153       uint16_t od_turbo_power_limit;                //Power limit setting for Turbo mode in Performance UI Tuning.
 154       uint16_t od_power_save_power_limit;           //Power limit setting for PowerSave/Optimal mode in Performance UI Tuning.
 155       uint16_t software_shutdown_temp;
 156
 157       uint16_t reserve[6];                          //Zero filled field reserved for future use
 158
 159       struct smu_11_0_power_saving_clock_table      power_saving_clock;
 160       struct smu_11_0_overdrive_table               overdrive_table;
 161
 162 #ifndef SMU_11_0_PARTIAL_PPTABLE
 163       PPTable_t smc_pptable;                        //PPTable_t in smu11_driver_if.h
 164 #endif
 165 } __attribute__((packed));
 166
 167 #endif