2 * Copyright 2016 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef SMU71_DISCRETE_H
24 #define SMU71_DISCRETE_H
28 #if !defined(SMC_MICROCODE)
32 #define VDDC_ON_SVI2 0x1
33 #define VDDCI_ON_SVI2 0x2
34 #define MVDD_ON_SVI2 0x4
36 struct SMU71_Discrete_VoltageLevel
39 uint16_t StdVoltageHiSidd;
40 uint16_t StdVoltageLoSidd;
45 typedef struct SMU71_Discrete_VoltageLevel SMU71_Discrete_VoltageLevel;
47 struct SMU71_Discrete_GraphicsLevel
50 uint32_t MinVddcPhases;
52 uint32_t SclkFrequency;
55 uint8_t DeepSleepDivId;
56 uint16_t ActivityLevel;
58 uint32_t CgSpllFuncCntl3;
59 uint32_t CgSpllFuncCntl4;
60 uint32_t SpllSpreadSpectrum;
61 uint32_t SpllSpreadSpectrum2;
65 uint8_t DisplayWatermark;
66 uint8_t EnabledForActivity;
67 uint8_t EnabledForThrottle;
70 uint8_t VoltageDownHyst;
71 uint8_t PowerThrottle;
74 typedef struct SMU71_Discrete_GraphicsLevel SMU71_Discrete_GraphicsLevel;
76 struct SMU71_Discrete_ACPILevel
80 uint32_t MinVddcPhases;
81 uint32_t SclkFrequency;
83 uint8_t DisplayWatermark;
84 uint8_t DeepSleepDivId;
86 uint32_t CgSpllFuncCntl;
87 uint32_t CgSpllFuncCntl2;
88 uint32_t CgSpllFuncCntl3;
89 uint32_t CgSpllFuncCntl4;
90 uint32_t SpllSpreadSpectrum;
91 uint32_t SpllSpreadSpectrum2;
96 typedef struct SMU71_Discrete_ACPILevel SMU71_Discrete_ACPILevel;
98 struct SMU71_Discrete_Ulv
101 uint32_t CcPwrDynRm1;
103 uint8_t VddcOffsetVid;
108 typedef struct SMU71_Discrete_Ulv SMU71_Discrete_Ulv;
110 struct SMU71_Discrete_MemoryLevel
113 uint32_t MinVddcPhases;
117 uint32_t MclkFrequency;
119 uint8_t EdcReadEnable;
120 uint8_t EdcWriteEnable;
122 uint8_t StutterEnable;
124 uint8_t StrobeEnable;
126 uint8_t EnabledForThrottle;
127 uint8_t EnabledForActivity;
131 uint8_t VoltageDownHyst;
134 uint16_t ActivityLevel;
135 uint8_t DisplayWatermark;
138 uint32_t MpllFuncCntl;
139 uint32_t MpllFuncCntl_1;
140 uint32_t MpllFuncCntl_2;
141 uint32_t MpllAdFuncCntl;
142 uint32_t MpllDqFuncCntl;
143 uint32_t MclkPwrmgtCntl;
149 typedef struct SMU71_Discrete_MemoryLevel SMU71_Discrete_MemoryLevel;
151 struct SMU71_Discrete_LinkLevel
153 uint8_t PcieGenSpeed; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3
154 uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
155 uint8_t EnabledForActivity;
157 uint32_t DownThreshold;
158 uint32_t UpThreshold;
162 typedef struct SMU71_Discrete_LinkLevel SMU71_Discrete_LinkLevel;
165 #ifdef SMU__DYNAMIC_MCARB_SETTINGS
166 // MC ARB DRAM Timing registers.
167 struct SMU71_Discrete_MCArbDramTimingTableEntry
169 uint32_t McArbDramTiming;
170 uint32_t McArbDramTiming2;
171 uint8_t McArbBurstTime;
175 typedef struct SMU71_Discrete_MCArbDramTimingTableEntry SMU71_Discrete_MCArbDramTimingTableEntry;
177 struct SMU71_Discrete_MCArbDramTimingTable
179 SMU71_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
182 typedef struct SMU71_Discrete_MCArbDramTimingTable SMU71_Discrete_MCArbDramTimingTable;
185 // UVD VCLK/DCLK state (level) definition.
186 struct SMU71_Discrete_UvdLevel
188 uint32_t VclkFrequency;
189 uint32_t DclkFrequency;
191 uint8_t MinVddcPhases;
197 typedef struct SMU71_Discrete_UvdLevel SMU71_Discrete_UvdLevel;
199 // Clocks for other external blocks (VCE, ACP, SAMU).
200 struct SMU71_Discrete_ExtClkLevel
208 typedef struct SMU71_Discrete_ExtClkLevel SMU71_Discrete_ExtClkLevel;
210 // Everything that we need to keep track of about the current state.
211 // Use this instead of copies of the GraphicsLevel and MemoryLevel structures to keep track of state parameters
212 // that need to be checked later.
213 // We don't need to cache everything about a state, just a few parameters.
214 struct SMU71_Discrete_StateInfo
216 uint32_t SclkFrequency;
217 uint32_t MclkFrequency;
218 uint32_t VclkFrequency;
219 uint32_t DclkFrequency;
220 uint32_t SamclkFrequency;
221 uint32_t AclkFrequency;
222 uint32_t EclkFrequency;
223 uint16_t MvddVoltage;
225 uint8_t DisplayWatermark;
236 typedef struct SMU71_Discrete_StateInfo SMU71_Discrete_StateInfo;
239 struct SMU71_Discrete_DpmTable
241 // Multi-DPM controller settings
242 SMU71_PIDController GraphicsPIDController;
243 SMU71_PIDController MemoryPIDController;
244 SMU71_PIDController LinkPIDController;
246 uint32_t SystemFlags;
248 // SMIO masks for voltage and phase controls
249 uint32_t SmioMaskVddcVid;
250 uint32_t SmioMaskVddcPhase;
251 uint32_t SmioMaskVddciVid;
252 uint32_t SmioMaskMvddVid;
254 uint32_t VddcLevelCount;
255 uint32_t VddciLevelCount;
256 uint32_t MvddLevelCount;
258 SMU71_Discrete_VoltageLevel VddcLevel [SMU71_MAX_LEVELS_VDDC];
259 SMU71_Discrete_VoltageLevel VddciLevel [SMU71_MAX_LEVELS_VDDCI];
260 SMU71_Discrete_VoltageLevel MvddLevel [SMU71_MAX_LEVELS_MVDD];
262 uint8_t GraphicsDpmLevelCount;
263 uint8_t MemoryDpmLevelCount;
264 uint8_t LinkLevelCount;
265 uint8_t MasterDeepSleepControl;
267 uint32_t Reserved[5];
269 // State table entries for each DPM state
270 SMU71_Discrete_GraphicsLevel GraphicsLevel [SMU71_MAX_LEVELS_GRAPHICS];
271 SMU71_Discrete_MemoryLevel MemoryACPILevel;
272 SMU71_Discrete_MemoryLevel MemoryLevel [SMU71_MAX_LEVELS_MEMORY];
273 SMU71_Discrete_LinkLevel LinkLevel [SMU71_MAX_LEVELS_LINK];
274 SMU71_Discrete_ACPILevel ACPILevel;
276 uint32_t SclkStepSize;
277 uint32_t Smio [SMU71_MAX_ENTRIES_SMIO];
279 uint8_t GraphicsBootLevel;
280 uint8_t GraphicsVoltageChangeEnable;
281 uint8_t GraphicsThermThrottleEnable;
282 uint8_t GraphicsInterval;
284 uint8_t VoltageInterval;
285 uint8_t ThermalInterval;
286 uint16_t TemperatureLimitHigh;
288 uint16_t TemperatureLimitLow;
289 uint8_t MemoryBootLevel;
290 uint8_t MemoryVoltageChangeEnable;
292 uint8_t MemoryInterval;
293 uint8_t MemoryThermThrottleEnable;
297 uint16_t VoltageResponseTime;
298 uint16_t PhaseResponseTime;
300 uint8_t PCIeBootLinkLevel;
301 uint8_t PCIeGenInterval;
315 uint16_t FpsHighThreshold;
316 uint16_t FpsLowThreshold;
318 uint16_t BAPMTI_R [SMU71_DTE_ITERATIONS][SMU71_DTE_SOURCES][SMU71_DTE_SINKS];
319 uint16_t BAPMTI_RC [SMU71_DTE_ITERATIONS][SMU71_DTE_SOURCES][SMU71_DTE_SINKS];
321 uint8_t DTEAmbientTempBase;
332 uint32_t BAPM_TEMP_GRADIENT;
334 uint32_t LowSclkInterruptThreshold;
335 uint32_t VddGfxReChkWait;
337 uint16_t PPM_PkgPwrLimit;
338 uint16_t PPM_TemperatureLimit;
344 typedef struct SMU71_Discrete_DpmTable SMU71_Discrete_DpmTable;
346 // --------------------------------------------------- AC Timing Parameters ------------------------------------------------
347 #define SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
348 #define SMU71_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU71_MAX_LEVELS_MEMORY
350 struct SMU71_Discrete_MCRegisterAddress
356 typedef struct SMU71_Discrete_MCRegisterAddress SMU71_Discrete_MCRegisterAddress;
358 struct SMU71_Discrete_MCRegisterSet
360 uint32_t value[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];
363 typedef struct SMU71_Discrete_MCRegisterSet SMU71_Discrete_MCRegisterSet;
365 struct SMU71_Discrete_MCRegisters
369 SMU71_Discrete_MCRegisterAddress address[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];
370 SMU71_Discrete_MCRegisterSet data[SMU71_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
373 typedef struct SMU71_Discrete_MCRegisters SMU71_Discrete_MCRegisters;
376 // --------------------------------------------------- Fan Table -----------------------------------------------------------
377 struct SMU71_Discrete_FanTable
393 uint32_t RefreshPeriod;
399 typedef struct SMU71_Discrete_FanTable SMU71_Discrete_FanTable;
401 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4
402 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
404 struct SMU71_MclkDpmScoreboard
407 uint32_t PercentageBusy;
413 uint32_t SigmaDeltaAccum;
414 uint32_t SigmaDeltaOutput;
415 uint32_t SigmaDeltaLevel;
417 uint32_t UtilizationSetpoint;
419 uint8_t TdpClampMode;
420 uint8_t TdcClampMode;
421 uint8_t ThermClampMode;
426 uint8_t LevelChangeInProgress;
430 uint8_t VoltageDownHyst;
435 uint8_t DpmForceLevel;
436 uint8_t DisplayWatermark;
439 uint32_t MinimumPerfMclk;
443 uint8_t MclkSwitchInProgress;
444 uint8_t MclkSwitchCritical;
446 uint8_t TargetMclkIndex;
447 uint8_t TargetMvddIndex;
448 uint8_t MclkSwitchResult;
450 uint8_t EnabledLevelsChange;
452 uint16_t LevelResidencyCounters [SMU71_MAX_LEVELS_MEMORY];
453 uint16_t LevelSwitchCounters [SMU71_MAX_LEVELS_MEMORY];
455 void (*TargetStateCalculator)(uint8_t);
456 void (*SavedTargetStateCalculator)(uint8_t);
458 uint16_t AutoDpmInterval;
459 uint16_t AutoDpmRange;
461 uint16_t MclkSwitchingTime;
465 typedef struct SMU71_MclkDpmScoreboard SMU71_MclkDpmScoreboard;
467 struct SMU71_UlvScoreboard
472 uint8_t WaitingForUlv;
475 uint8_t UlvMasterEnable;
477 uint32_t UlvAbortedCount;
478 uint32_t UlvTimeStamp;
481 typedef struct SMU71_UlvScoreboard SMU71_UlvScoreboard;
483 struct SMU71_VddGfxScoreboard
485 uint8_t VddGfxEnable;
486 uint8_t VddGfxActive;
489 uint32_t VddGfxEnteredCount;
490 uint32_t VddGfxAbortedCount;
493 typedef struct SMU71_VddGfxScoreboard SMU71_VddGfxScoreboard;
495 struct SMU71_AcpiScoreboard {
496 uint32_t SavedInterruptMask[2];
497 uint8_t LastACPIRequest;
501 SMU71_Discrete_ACPILevel D0Level;
504 typedef struct SMU71_AcpiScoreboard SMU71_AcpiScoreboard;
507 struct SMU71_Discrete_PmFuses {
509 uint8_t BapmVddCVidHiSidd[8];
512 uint8_t BapmVddCVidLoSidd[8];
518 uint8_t SviLoadLineEn;
519 uint8_t SviLoadLineVddC;
520 uint8_t SviLoadLineTrimVddC;
521 uint8_t SviLoadLineOffsetVddC;
524 uint16_t TDC_VDDC_PkgLimit;
525 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
529 uint8_t TdcWaterfallCtl;
530 uint8_t LPMLTemperatureMin;
531 uint8_t LPMLTemperatureMax;
535 uint8_t LPMLTemperatureScaler[16];
538 int16_t FuzzyFan_ErrorSetDelta;
539 int16_t FuzzyFan_ErrorRateSetDelta;
540 int16_t FuzzyFan_PwmSetDelta;
547 uint8_t GnbLPMLMaxVid;
548 uint8_t GnbLPMLMinVid;
549 uint8_t Reserved1[2];
552 uint16_t BapmVddCBaseLeakageHiSidd;
553 uint16_t BapmVddCBaseLeakageLoSidd;
556 typedef struct SMU71_Discrete_PmFuses SMU71_Discrete_PmFuses;
558 struct SMU71_Discrete_Log_Header_Table {
564 uint32_t num_of_entries;
568 uint32_t filler_1[2];
571 typedef struct SMU71_Discrete_Log_Header_Table SMU71_Discrete_Log_Header_Table;
573 struct SMU71_Discrete_Log_Cntl {
578 uint32_t SamplesLogged;
584 typedef struct SMU71_Discrete_Log_Cntl SMU71_Discrete_Log_Cntl;
586 #if defined SMU__DGPU_ONLY
587 #define CAC_ACC_NW_NUM_OF_SIGNALS 83
591 struct SMU71_Discrete_Cac_Collection_Table {
592 uint32_t temperature;
593 uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
597 typedef struct SMU71_Discrete_Cac_Collection_Table SMU71_Discrete_Cac_Collection_Table;
599 struct SMU71_Discrete_Cac_Verification_Table {
600 uint32_t VddcTotalPower;
601 uint32_t VddcLeakagePower;
602 uint32_t VddcConstantPower;
603 uint32_t VddcGfxDynamicPower;
604 uint32_t VddcUvdDynamicPower;
605 uint32_t VddcVceDynamicPower;
606 uint32_t VddcAcpDynamicPower;
607 uint32_t VddcPcieDynamicPower;
608 uint32_t VddcDceDynamicPower;
609 uint32_t VddcCurrent;
610 uint32_t VddcVoltage;
611 uint32_t VddciTotalPower;
612 uint32_t VddciLeakagePower;
613 uint32_t VddciConstantPower;
614 uint32_t VddciDynamicPower;
615 uint32_t Vddr1TotalPower;
616 uint32_t Vddr1LeakagePower;
617 uint32_t Vddr1ConstantPower;
618 uint32_t Vddr1DynamicPower;
620 uint32_t temperature;
623 typedef struct SMU71_Discrete_Cac_Verification_Table SMU71_Discrete_Cac_Verification_Table;
625 #if !defined(SMC_MICROCODE)