2 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef SMU10_DRIVER_IF_H
25 #define SMU10_DRIVER_IF_H
27 #define SMU10_DRIVER_IF_VERSION 0x6
29 #define NUM_DSPCLK_LEVELS 8
33 uint32_t numFractionalBits;
47 } DisplayClockTable_t;
51 uint16_t MinClock; /* This is either DCFCLK or SOCCLK (in MHz) */
52 uint16_t MaxClock; /* This is either DCFCLK or SOCCLK (in MHz) */
58 } WatermarkRowGeneric_t;
60 #define NUM_WM_RANGES 4
69 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
70 uint32_t MmHubPadding[7];
74 CUSTOM_DPM_SETTING_GFXCLK,
75 CUSTOM_DPM_SETTING_CCLK,
76 CUSTOM_DPM_SETTING_FCLK_CCX,
77 CUSTOM_DPM_SETTING_FCLK_GFX,
78 CUSTOM_DPM_SETTING_FCLK_STALLS,
79 CUSTOM_DPM_SETTING_LCLK,
80 CUSTOM_DPM_SETTING_COUNT,
81 } CUSTOM_DPM_SETTING_e;
84 uint8_t ActiveHystLimit;
85 uint8_t IdleHystLimit;
87 uint8_t MinActiveFreqType;
88 FloatInIntFormat_t MinActiveFreq;
89 FloatInIntFormat_t PD_Data_limit;
90 FloatInIntFormat_t PD_Data_time_constant;
91 FloatInIntFormat_t PD_Data_error_coeff;
92 FloatInIntFormat_t PD_Data_error_rate_coeff;
93 } DpmActivityMonitorCoeffExt_t;
96 DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
97 } CustomDpmSettings_t;
99 #define NUM_SOCCLK_DPM_LEVELS 8
100 #define NUM_DCEFCLK_DPM_LEVELS 4
101 #define NUM_FCLK_DPM_LEVELS 4
102 #define NUM_MEMCLK_DPM_LEVELS 4
105 uint32_t Freq; /* In MHz */
106 uint32_t Vol; /* Millivolts with 2 fractional bits */
110 DpmClock_t DcefClocks[NUM_DCEFCLK_DPM_LEVELS];
111 DpmClock_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
112 DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS];
113 DpmClock_t MemClocks[NUM_MEMCLK_DPM_LEVELS];