drivers/gpu/drm/amd/powerplay/inc/hwmgr.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef _HWMGR_H_
  24 #define _HWMGR_H_
  25
  26 #include <linux/seq_file.h>
  27 #include "amd_powerplay.h"
  28 #include "pp_instance.h"
  29 #include "hardwaremanager.h"
  30 #include "pp_power_source.h"
  31 #include "hwmgr_ppt.h"
  32 #include "ppatomctrl.h"
  33 #include "hwmgr_ppt.h"
  34 #include "power_state.h"
  35
  36 struct pp_instance;
  37 struct pp_hwmgr;
  38 struct phm_fan_speed_info;
  39 struct pp_atomctrl_voltage_table;
  40
  41 #define VOLTAGE_SCALE 4
  42
  43 uint8_t convert_to_vid(uint16_t vddc);
  44
  45 enum DISPLAY_GAP {
  46         DISPLAY_GAP_VBLANK_OR_WM = 0,   /* Wait for vblank or MCHG watermark. */
  47         DISPLAY_GAP_VBLANK       = 1,   /* Wait for vblank. */
  48         DISPLAY_GAP_WATERMARK    = 2,   /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
  49         DISPLAY_GAP_IGNORE       = 3    /* Do not wait. */
  50 };
  51 typedef enum DISPLAY_GAP DISPLAY_GAP;
  52
  53 struct vi_dpm_level {
  54         bool enabled;
  55         uint32_t value;
  56         uint32_t param1;
  57 };
  58
  59 struct vi_dpm_table {
  60         uint32_t count;
  61         struct vi_dpm_level dpm_level[1];
  62 };
  63
  64 enum PP_Result {
  65         PP_Result_TableImmediateExit = 0x13,
  66 };
  67
  68 #define PCIE_PERF_REQ_REMOVE_REGISTRY   0
  69 #define PCIE_PERF_REQ_FORCE_LOWPOWER    1
  70 #define PCIE_PERF_REQ_GEN1         2
  71 #define PCIE_PERF_REQ_GEN2         3
  72 #define PCIE_PERF_REQ_GEN3         4
  73
  74 enum PP_FEATURE_MASK {
  75         PP_SCLK_DPM_MASK = 0x1,
  76         PP_MCLK_DPM_MASK = 0x2,
  77         PP_PCIE_DPM_MASK = 0x4,
  78         PP_SCLK_DEEP_SLEEP_MASK = 0x8,
  79         PP_POWER_CONTAINMENT_MASK = 0x10,
  80         PP_UVD_HANDSHAKE_MASK = 0x20,
  81         PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
  82         PP_VBI_TIME_SUPPORT_MASK = 0x80,
  83         PP_ULV_MASK = 0x100,
  84         PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
  85         PP_CLOCK_STRETCH_MASK = 0x400,
  86         PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
  87         PP_SOCCLK_DPM_MASK = 0x1000,
  88         PP_DCEFCLK_DPM_MASK = 0x2000,
  89 };
  90
  91 enum PHM_BackEnd_Magic {
  92         PHM_Dummy_Magic       = 0xAA5555AA,
  93         PHM_RV770_Magic       = 0xDCBAABCD,
  94         PHM_Kong_Magic        = 0x239478DF,
  95         PHM_NIslands_Magic    = 0x736C494E,
  96         PHM_Sumo_Magic        = 0x8339FA11,
  97         PHM_SIslands_Magic    = 0x369431AC,
  98         PHM_Trinity_Magic     = 0x96751873,
  99         PHM_CIslands_Magic    = 0x38AC78B0,
 100         PHM_Kv_Magic          = 0xDCBBABC0,
 101         PHM_VIslands_Magic    = 0x20130307,
 102         PHM_Cz_Magic          = 0x67DCBA25,
 103         PHM_Rv_Magic          = 0x20161121
 104 };
 105
 106
 107 #define PHM_PCIE_POWERGATING_TARGET_GFX            0
 108 #define PHM_PCIE_POWERGATING_TARGET_DDI            1
 109 #define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE     2
 110 #define PHM_PCIE_POWERGATING_TARGET_PHY            3
 111
 112
 113 struct phm_set_power_state_input {
 114         const struct pp_hw_power_state *pcurrent_state;
 115         const struct pp_hw_power_state *pnew_state;
 116 };
 117
 118 struct phm_acp_arbiter {
 119         uint32_t acpclk;
 120 };
 121
 122 struct phm_uvd_arbiter {
 123         uint32_t vclk;
 124         uint32_t dclk;
 125         uint32_t vclk_ceiling;
 126         uint32_t dclk_ceiling;
 127         uint32_t vclk_soft_min;
 128         uint32_t dclk_soft_min;
 129 };
 130
 131 struct phm_vce_arbiter {
 132         uint32_t   evclk;
 133         uint32_t   ecclk;
 134 };
 135
 136 struct phm_gfx_arbiter {
 137         uint32_t sclk;
 138         uint32_t sclk_hard_min;
 139         uint32_t mclk;
 140         uint32_t sclk_over_drive;
 141         uint32_t mclk_over_drive;
 142         uint32_t sclk_threshold;
 143         uint32_t num_cus;
 144         uint32_t gfxclk;
 145         uint32_t fclk;
 146 };
 147
 148 struct phm_clock_array {
 149         uint32_t count;
 150         uint32_t values[1];
 151 };
 152
 153 struct phm_clock_voltage_dependency_record {
 154         uint32_t clk;
 155         uint32_t v;
 156 };
 157
 158 struct phm_vceclock_voltage_dependency_record {
 159         uint32_t ecclk;
 160         uint32_t evclk;
 161         uint32_t v;
 162 };
 163
 164 struct phm_uvdclock_voltage_dependency_record {
 165         uint32_t vclk;
 166         uint32_t dclk;
 167         uint32_t v;
 168 };
 169
 170 struct phm_samuclock_voltage_dependency_record {
 171         uint32_t samclk;
 172         uint32_t v;
 173 };
 174
 175 struct phm_acpclock_voltage_dependency_record {
 176         uint32_t acpclk;
 177         uint32_t v;
 178 };
 179
 180 struct phm_clock_voltage_dependency_table {
 181         uint32_t count;                                                                         /* Number of entries. */
 182         struct phm_clock_voltage_dependency_record entries[1];          /* Dynamically allocate count entries. */
 183 };
 184
 185 struct phm_phase_shedding_limits_record {
 186         uint32_t  Voltage;
 187         uint32_t    Sclk;
 188         uint32_t    Mclk;
 189 };
 190
 191 struct phm_uvd_clock_voltage_dependency_record {
 192         uint32_t vclk;
 193         uint32_t dclk;
 194         uint32_t v;
 195 };
 196
 197 struct phm_uvd_clock_voltage_dependency_table {
 198         uint8_t count;
 199         struct phm_uvd_clock_voltage_dependency_record entries[1];
 200 };
 201
 202 struct phm_acp_clock_voltage_dependency_record {
 203         uint32_t acpclk;
 204         uint32_t v;
 205 };
 206
 207 struct phm_acp_clock_voltage_dependency_table {
 208         uint32_t count;
 209         struct phm_acp_clock_voltage_dependency_record entries[1];
 210 };
 211
 212 struct phm_vce_clock_voltage_dependency_record {
 213         uint32_t ecclk;
 214         uint32_t evclk;
 215         uint32_t v;
 216 };
 217
 218 struct phm_phase_shedding_limits_table {
 219         uint32_t                           count;
 220         struct phm_phase_shedding_limits_record  entries[1];
 221 };
 222
 223 struct phm_vceclock_voltage_dependency_table {
 224         uint8_t count;                                    /* Number of entries. */
 225         struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 226 };
 227
 228 struct phm_uvdclock_voltage_dependency_table {
 229         uint8_t count;                                    /* Number of entries. */
 230         struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 231 };
 232
 233 struct phm_samuclock_voltage_dependency_table {
 234         uint8_t count;                                    /* Number of entries. */
 235         struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 236 };
 237
 238 struct phm_acpclock_voltage_dependency_table {
 239         uint32_t count;                                    /* Number of entries. */
 240         struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 241 };
 242
 243 struct phm_vce_clock_voltage_dependency_table {
 244         uint8_t count;
 245         struct phm_vce_clock_voltage_dependency_record entries[1];
 246 };
 247
 248 struct pp_hwmgr_func {
 249         int (*backend_init)(struct pp_hwmgr *hw_mgr);
 250         int (*backend_fini)(struct pp_hwmgr *hw_mgr);
 251         int (*asic_setup)(struct pp_hwmgr *hw_mgr);
 252         int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
 253
 254         int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
 255                                 struct pp_power_state  *prequest_ps,
 256                         const struct pp_power_state *pcurrent_ps);
 257
 258         int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
 259                                         enum amd_dpm_forced_level level);
 260
 261         int (*dynamic_state_management_enable)(
 262                                                 struct pp_hwmgr *hw_mgr);
 263         int (*dynamic_state_management_disable)(
 264                                                 struct pp_hwmgr *hw_mgr);
 265
 266         int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
 267                                      struct pp_hw_power_state *hw_ps);
 268
 269         int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
 270                             unsigned long, struct pp_power_state *);
 271         int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
 272         int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
 273         int (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
 274         int (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
 275         int (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
 276         int (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
 277         int (*power_state_set)(struct pp_hwmgr *hwmgr,
 278                                                 const void *state);
 279         int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
 280         int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
 281         int (*display_config_changed)(struct pp_hwmgr *hwmgr);
 282         int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
 283         int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
 284                                                 const uint32_t *msg_id);
 285         int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
 286         int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
 287         int (*get_temperature)(struct pp_hwmgr *hwmgr);
 288         int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
 289         int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
 290         int (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
 291         int (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
 292         int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent);
 293         int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed);
 294         int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent);
 295         int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
 296         int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
 297         int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
 298         int (*register_internal_thermal_interrupt)(struct pp_hwmgr *hwmgr,
 299                                         const void *thermal_interrupt_info);
 300         bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
 301         int (*check_states_equal)(struct pp_hwmgr *hwmgr,
 302                                         const struct pp_hw_power_state *pstate1,
 303                                         const struct pp_hw_power_state *pstate2,
 304                                         bool *equal);
 305         int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
 306         int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
 307                                 bool cc6_disable, bool pstate_disable,
 308                                 bool pstate_switch_disable);
 309         int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
 310                         struct amd_pp_simple_clock_info *info);
 311         int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
 312                         PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
 313         int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
 314                                 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
 315         int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
 316         int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr,
 317                         enum amd_pp_clock_type type,
 318                         struct pp_clock_levels_with_latency *clocks);
 319         int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
 320                         enum amd_pp_clock_type type,
 321                         struct pp_clock_levels_with_voltage *clocks);
 322         int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr,
 323                         struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
 324         int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
 325                         struct pp_display_clock_request *clock);
 326         int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
 327         int (*power_off_asic)(struct pp_hwmgr *hwmgr);
 328         int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
 329         int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
 330         int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable);
 331         int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
 332         int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
 333         int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
 334         int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
 335         int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size);
 336         int (*set_power_profile_state)(struct pp_hwmgr *hwmgr,
 337                         struct amd_pp_profile *request);
 338         int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
 339         int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
 340         int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
 341         int (*set_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
 342         int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
 343 };
 344
 345 struct pp_table_func {
 346         int (*pptable_init)(struct pp_hwmgr *hw_mgr);
 347         int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
 348         int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
 349         int (*pptable_get_vce_state_table_entry)(
 350                                                 struct pp_hwmgr *hwmgr,
 351                                                 unsigned long i,
 352                                                 struct amd_vce_state *vce_state,
 353                                                 void **clock_info,
 354                                                 unsigned long *flag);
 355 };
 356
 357 union phm_cac_leakage_record {
 358         struct {
 359                 uint16_t Vddc;          /* in CI, we use it for StdVoltageHiSidd */
 360                 uint32_t Leakage;       /* in CI, we use it for StdVoltageLoSidd */
 361         };
 362         struct {
 363                 uint16_t Vddc1;
 364                 uint16_t Vddc2;
 365                 uint16_t Vddc3;
 366         };
 367 };
 368
 369 struct phm_cac_leakage_table {
 370         uint32_t count;
 371         union phm_cac_leakage_record entries[1];
 372 };
 373
 374 struct phm_samu_clock_voltage_dependency_record {
 375         uint32_t samclk;
 376         uint32_t v;
 377 };
 378
 379
 380 struct phm_samu_clock_voltage_dependency_table {
 381         uint8_t count;
 382         struct phm_samu_clock_voltage_dependency_record entries[1];
 383 };
 384
 385 struct phm_cac_tdp_table {
 386         uint16_t usTDP;
 387         uint16_t usConfigurableTDP;
 388         uint16_t usTDC;
 389         uint16_t usBatteryPowerLimit;
 390         uint16_t usSmallPowerLimit;
 391         uint16_t usLowCACLeakage;
 392         uint16_t usHighCACLeakage;
 393         uint16_t usMaximumPowerDeliveryLimit;
 394         uint16_t usEDCLimit;
 395         uint16_t usOperatingTempMinLimit;
 396         uint16_t usOperatingTempMaxLimit;
 397         uint16_t usOperatingTempStep;
 398         uint16_t usOperatingTempHyst;
 399         uint16_t usDefaultTargetOperatingTemp;
 400         uint16_t usTargetOperatingTemp;
 401         uint16_t usPowerTuneDataSetID;
 402         uint16_t usSoftwareShutdownTemp;
 403         uint16_t usClockStretchAmount;
 404         uint16_t usTemperatureLimitHotspot;
 405         uint16_t usTemperatureLimitLiquid1;
 406         uint16_t usTemperatureLimitLiquid2;
 407         uint16_t usTemperatureLimitVrVddc;
 408         uint16_t usTemperatureLimitVrMvdd;
 409         uint16_t usTemperatureLimitPlx;
 410         uint8_t  ucLiquid1_I2C_address;
 411         uint8_t  ucLiquid2_I2C_address;
 412         uint8_t  ucLiquid_I2C_Line;
 413         uint8_t  ucVr_I2C_address;
 414         uint8_t  ucVr_I2C_Line;
 415         uint8_t  ucPlx_I2C_address;
 416         uint8_t  ucPlx_I2C_Line;
 417         uint32_t usBoostPowerLimit;
 418         uint8_t  ucCKS_LDO_REFSEL;
 419 };
 420
 421 struct phm_tdp_table {
 422         uint16_t usTDP;
 423         uint16_t usConfigurableTDP;
 424         uint16_t usTDC;
 425         uint16_t usBatteryPowerLimit;
 426         uint16_t usSmallPowerLimit;
 427         uint16_t usLowCACLeakage;
 428         uint16_t usHighCACLeakage;
 429         uint16_t usMaximumPowerDeliveryLimit;
 430         uint16_t usEDCLimit;
 431         uint16_t usOperatingTempMinLimit;
 432         uint16_t usOperatingTempMaxLimit;
 433         uint16_t usOperatingTempStep;
 434         uint16_t usOperatingTempHyst;
 435         uint16_t usDefaultTargetOperatingTemp;
 436         uint16_t usTargetOperatingTemp;
 437         uint16_t usPowerTuneDataSetID;
 438         uint16_t usSoftwareShutdownTemp;
 439         uint16_t usClockStretchAmount;
 440         uint16_t usTemperatureLimitTedge;
 441         uint16_t usTemperatureLimitHotspot;
 442         uint16_t usTemperatureLimitLiquid1;
 443         uint16_t usTemperatureLimitLiquid2;
 444         uint16_t usTemperatureLimitHBM;
 445         uint16_t usTemperatureLimitVrVddc;
 446         uint16_t usTemperatureLimitVrMvdd;
 447         uint16_t usTemperatureLimitPlx;
 448         uint8_t  ucLiquid1_I2C_address;
 449         uint8_t  ucLiquid2_I2C_address;
 450         uint8_t  ucLiquid_I2C_Line;
 451         uint8_t  ucVr_I2C_address;
 452         uint8_t  ucVr_I2C_Line;
 453         uint8_t  ucPlx_I2C_address;
 454         uint8_t  ucPlx_I2C_Line;
 455         uint8_t  ucLiquid_I2C_LineSDA;
 456         uint8_t  ucVr_I2C_LineSDA;
 457         uint8_t  ucPlx_I2C_LineSDA;
 458         uint32_t usBoostPowerLimit;
 459         uint16_t usBoostStartTemperature;
 460         uint16_t usBoostStopTemperature;
 461         uint32_t  ulBoostClock;
 462 };
 463
 464 struct phm_ppm_table {
 465         uint8_t   ppm_design;
 466         uint16_t  cpu_core_number;
 467         uint32_t  platform_tdp;
 468         uint32_t  small_ac_platform_tdp;
 469         uint32_t  platform_tdc;
 470         uint32_t  small_ac_platform_tdc;
 471         uint32_t  apu_tdp;
 472         uint32_t  dgpu_tdp;
 473         uint32_t  dgpu_ulv_power;
 474         uint32_t  tj_max;
 475 };
 476
 477 struct phm_vq_budgeting_record {
 478         uint32_t ulCUs;
 479         uint32_t ulSustainableSOCPowerLimitLow;
 480         uint32_t ulSustainableSOCPowerLimitHigh;
 481         uint32_t ulMinSclkLow;
 482         uint32_t ulMinSclkHigh;
 483         uint8_t  ucDispConfig;
 484         uint32_t ulDClk;
 485         uint32_t ulEClk;
 486         uint32_t ulSustainableSclk;
 487         uint32_t ulSustainableCUs;
 488 };
 489
 490 struct phm_vq_budgeting_table {
 491         uint8_t numEntries;
 492         struct phm_vq_budgeting_record entries[1];
 493 };
 494
 495 struct phm_clock_and_voltage_limits {
 496         uint32_t sclk;
 497         uint32_t mclk;
 498         uint32_t gfxclk;
 499         uint16_t vddc;
 500         uint16_t vddci;
 501         uint16_t vddgfx;
 502         uint16_t vddmem;
 503 };
 504
 505 /* Structure to hold PPTable information */
 506
 507 struct phm_ppt_v1_information {
 508         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
 509         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
 510         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
 511         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
 512         struct phm_clock_array *valid_sclk_values;
 513         struct phm_clock_array *valid_mclk_values;
 514         struct phm_clock_array *valid_socclk_values;
 515         struct phm_clock_array *valid_dcefclk_values;
 516         struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
 517         struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
 518         struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
 519         struct phm_ppm_table *ppm_parameter_table;
 520         struct phm_cac_tdp_table *cac_dtp_table;
 521         struct phm_tdp_table *tdp_table;
 522         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
 523         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
 524         struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
 525         struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
 526         struct phm_ppt_v1_pcie_table *pcie_table;
 527         struct phm_ppt_v1_gpio_table *gpio_table;
 528         uint16_t us_ulv_voltage_offset;
 529         uint16_t us_ulv_smnclk_did;
 530         uint16_t us_ulv_mp1clk_did;
 531         uint16_t us_ulv_gfxclk_bypass;
 532         uint16_t us_gfxclk_slew_rate;
 533         uint16_t us_min_gfxclk_freq_limit;
 534 };
 535
 536 struct phm_ppt_v2_information {
 537         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
 538         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
 539         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
 540         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
 541         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk;
 542         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk;
 543         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk;
 544         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
 545
 546         struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl;
 547
 548         struct phm_clock_array *valid_sclk_values;
 549         struct phm_clock_array *valid_mclk_values;
 550         struct phm_clock_array *valid_socclk_values;
 551         struct phm_clock_array *valid_dcefclk_values;
 552
 553         struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
 554         struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
 555
 556         struct phm_ppm_table *ppm_parameter_table;
 557         struct phm_cac_tdp_table *cac_dtp_table;
 558         struct phm_tdp_table *tdp_table;
 559
 560         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
 561         struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
 562         struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
 563         struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table;
 564
 565         struct phm_ppt_v1_pcie_table *pcie_table;
 566
 567         uint16_t us_ulv_voltage_offset;
 568         uint16_t us_ulv_smnclk_did;
 569         uint16_t us_ulv_mp1clk_did;
 570         uint16_t us_ulv_gfxclk_bypass;
 571         uint16_t us_gfxclk_slew_rate;
 572         uint16_t us_min_gfxclk_freq_limit;
 573
 574         uint8_t  uc_gfx_dpm_voltage_mode;
 575         uint8_t  uc_soc_dpm_voltage_mode;
 576         uint8_t  uc_uclk_dpm_voltage_mode;
 577         uint8_t  uc_uvd_dpm_voltage_mode;
 578         uint8_t  uc_vce_dpm_voltage_mode;
 579         uint8_t  uc_mp0_dpm_voltage_mode;
 580         uint8_t  uc_dcef_dpm_voltage_mode;
 581 };
 582
 583 struct phm_dynamic_state_info {
 584         struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
 585         struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
 586         struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
 587         struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
 588         struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
 589         struct phm_clock_array                    *valid_sclk_values;
 590         struct phm_clock_array                    *valid_mclk_values;
 591         struct phm_clock_and_voltage_limits       max_clock_voltage_on_dc;
 592         struct phm_clock_and_voltage_limits       max_clock_voltage_on_ac;
 593         uint32_t                                  mclk_sclk_ratio;
 594         uint32_t                                  sclk_mclk_delta;
 595         uint32_t                                  vddc_vddci_delta;
 596         uint32_t                                  min_vddc_for_pcie_gen2;
 597         struct phm_cac_leakage_table              *cac_leakage_table;
 598         struct phm_phase_shedding_limits_table  *vddc_phase_shed_limits_table;
 599
 600         struct phm_vce_clock_voltage_dependency_table
 601                                             *vce_clock_voltage_dependency_table;
 602         struct phm_uvd_clock_voltage_dependency_table
 603                                             *uvd_clock_voltage_dependency_table;
 604         struct phm_acp_clock_voltage_dependency_table
 605                                             *acp_clock_voltage_dependency_table;
 606         struct phm_samu_clock_voltage_dependency_table
 607                                            *samu_clock_voltage_dependency_table;
 608
 609         struct phm_ppm_table                          *ppm_parameter_table;
 610         struct phm_cac_tdp_table                      *cac_dtp_table;
 611         struct phm_clock_voltage_dependency_table       *vdd_gfx_dependency_on_sclk;
 612         struct phm_vq_budgeting_table                           *vq_budgeting_table;
 613 };
 614
 615 struct pp_fan_info {
 616         bool bNoFan;
 617         uint8_t   ucTachometerPulsesPerRevolution;
 618         uint32_t   ulMinRPM;
 619         uint32_t   ulMaxRPM;
 620 };
 621
 622 struct pp_advance_fan_control_parameters {
 623         uint16_t  usTMin;                          /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
 624         uint16_t  usTMed;                          /* The middle temperature where we change slopes. */
 625         uint16_t  usTHigh;                         /* The high temperature for setting the second slope. */
 626         uint16_t  usPWMMin;                        /* The minimum PWM value in percent (0.01% increments). */
 627         uint16_t  usPWMMed;                        /* The PWM value (in percent) at TMed. */
 628         uint16_t  usPWMHigh;                       /* The PWM value at THigh. */
 629         uint8_t   ucTHyst;                         /* Temperature hysteresis. Integer. */
 630         uint32_t   ulCycleDelay;                   /* The time between two invocations of the fan control routine in microseconds. */
 631         uint16_t  usTMax;                          /* The max temperature */
 632         uint8_t   ucFanControlMode;
 633         uint16_t  usFanPWMMinLimit;
 634         uint16_t  usFanPWMMaxLimit;
 635         uint16_t  usFanPWMStep;
 636         uint16_t  usDefaultMaxFanPWM;
 637         uint16_t  usFanOutputSensitivity;
 638         uint16_t  usDefaultFanOutputSensitivity;
 639         uint16_t  usMaxFanPWM;                     /* The max Fan PWM value for Fuzzy Fan Control feature */
 640         uint16_t  usFanRPMMinLimit;                /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
 641         uint16_t  usFanRPMMaxLimit;                /* Maximum limit range in percentage, usually set to 100% by default */
 642         uint16_t  usFanRPMStep;                    /* Step increments/decerements, in percent */
 643         uint16_t  usDefaultMaxFanRPM;              /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
 644         uint16_t  usMaxFanRPM;                     /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
 645         uint16_t  usFanCurrentLow;                 /* Low current */
 646         uint16_t  usFanCurrentHigh;                /* High current */
 647         uint16_t  usFanRPMLow;                     /* Low RPM */
 648         uint16_t  usFanRPMHigh;                    /* High RPM */
 649         uint32_t   ulMinFanSCLKAcousticLimit;      /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
 650         uint8_t   ucTargetTemperature;             /* Advanced fan controller target temperature. */
 651         uint8_t   ucMinimumPWMLimit;               /* The minimum PWM that the advanced fan controller can set.  This should be set to the highest PWM that will run the fan at its lowest RPM. */
 652         uint16_t  usFanGainEdge;                   /* The following is added for Fiji */
 653         uint16_t  usFanGainHotspot;
 654         uint16_t  usFanGainLiquid;
 655         uint16_t  usFanGainVrVddc;
 656         uint16_t  usFanGainVrMvdd;
 657         uint16_t  usFanGainPlx;
 658         uint16_t  usFanGainHbm;
 659         uint8_t   ucEnableZeroRPM;
 660         uint8_t   ucFanStopTemperature;
 661         uint8_t   ucFanStartTemperature;
 662         uint32_t  ulMaxFanSCLKAcousticLimit;       /* Maximum Fan Controller SCLK Frequency Acoustic Limit. */
 663         uint32_t  ulTargetGfxClk;
 664         uint16_t  usZeroRPMStartTemperature;
 665         uint16_t  usZeroRPMStopTemperature;
 666 };
 667
 668 struct pp_thermal_controller_info {
 669         uint8_t ucType;
 670         uint8_t ucI2cLine;
 671         uint8_t ucI2cAddress;
 672         struct pp_fan_info fanInfo;
 673         struct pp_advance_fan_control_parameters advanceFanControlParameters;
 674 };
 675
 676 struct phm_microcode_version_info {
 677         uint32_t SMC;
 678         uint32_t DMCU;
 679         uint32_t MC;
 680         uint32_t NB;
 681 };
 682
 683 enum PP_TABLE_VERSION {
 684         PP_TABLE_V0 = 0,
 685         PP_TABLE_V1,
 686         PP_TABLE_V2,
 687         PP_TABLE_MAX
 688 };
 689
 690 /**
 691  * The main hardware manager structure.
 692  */
 693 struct pp_hwmgr {
 694         uint32_t chip_family;
 695         uint32_t chip_id;
 696
 697         uint32_t pp_table_version;
 698         void *device;
 699         struct pp_smumgr *smumgr;
 700         const void *soft_pp_table;
 701         uint32_t soft_pp_table_size;
 702         void *hardcode_pp_table;
 703         bool need_pp_table_upload;
 704
 705         struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
 706         uint32_t num_vce_state_tables;
 707
 708         enum amd_dpm_forced_level dpm_level;
 709         enum amd_dpm_forced_level saved_dpm_level;
 710         enum amd_dpm_forced_level request_dpm_level;
 711         struct phm_gfx_arbiter gfx_arbiter;
 712         struct phm_acp_arbiter acp_arbiter;
 713         struct phm_uvd_arbiter uvd_arbiter;
 714         struct phm_vce_arbiter vce_arbiter;
 715         uint32_t usec_timeout;
 716         void *pptable;
 717         struct phm_platform_descriptor platform_descriptor;
 718         void *backend;
 719         enum PP_DAL_POWERLEVEL dal_power_level;
 720         struct phm_dynamic_state_info dyn_state;
 721         const struct pp_hwmgr_func *hwmgr_func;
 722         const struct pp_table_func *pptable_func;
 723         struct pp_power_state    *ps;
 724         enum pp_power_source  power_source;
 725         uint32_t num_ps;
 726         struct pp_thermal_controller_info thermal_controller;
 727         bool fan_ctrl_is_in_default_mode;
 728         uint32_t fan_ctrl_default_mode;
 729         bool fan_ctrl_enabled;
 730         uint32_t tmin;
 731         struct phm_microcode_version_info microcode_version_info;
 732         uint32_t ps_size;
 733         struct pp_power_state    *current_ps;
 734         struct pp_power_state    *request_ps;
 735         struct pp_power_state    *boot_ps;
 736         struct pp_power_state    *uvd_ps;
 737         struct amd_pp_display_configuration display_config;
 738         uint32_t feature_mask;
 739
 740         /* UMD Pstate */
 741         struct amd_pp_profile gfx_power_profile;
 742         struct amd_pp_profile compute_power_profile;
 743         struct amd_pp_profile default_gfx_power_profile;
 744         struct amd_pp_profile default_compute_power_profile;
 745         enum amd_pp_profile_type current_power_profile;
 746         bool en_umd_pstate;
 747 };
 748
 749 extern int hwmgr_early_init(struct pp_instance *handle);
 750 extern int hwmgr_hw_init(struct pp_instance *handle);
 751 extern int hwmgr_hw_fini(struct pp_instance *handle);
 752 extern int hwmgr_hw_suspend(struct pp_instance *handle);
 753 extern int hwmgr_hw_resume(struct pp_instance *handle);
 754 extern int hwmgr_handle_task(struct pp_instance *handle,
 755                                 enum amd_pp_task task_id,
 756                                 void *input, void *output);
 757 extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
 758                                 uint32_t value, uint32_t mask);
 759
 760 extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
 761                                 uint32_t indirect_port,
 762                                 uint32_t index,
 763                                 uint32_t value,
 764                                 uint32_t mask);
 765
 766
 767
 768 extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
 769 extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
 770 extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
 771
 772 extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table);
 773 extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
 774 extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
 775 extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table);
 776 extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table);
 777 extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);
 778 extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);
 779 extern int32_t phm_get_dpm_level_enable_mask_value(void *table);
 780 extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table *voltage_table,
 781                 uint32_t voltage);
 782 extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage);
 783 extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci);
 784 extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);
 785 extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table,
 786                                                                 uint16_t virtual_voltage_id, int32_t *sclk);
 787 extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
 788 extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
 789 extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
 790
 791 extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
 792 extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
 793 extern int rv_init_function_pointers(struct pp_hwmgr *hwmgr);
 794
 795 extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
 796                                 uint32_t sclk, uint16_t id, uint16_t *voltage);
 797
 798 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
 799
 800 #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
 801 #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
 802
 803 #define PHM_SET_FIELD(origval, reg, field, fieldval)    \
 804         (((origval) & ~PHM_FIELD_MASK(reg, field)) |    \
 805          (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
 806
 807 #define PHM_GET_FIELD(value, reg, field)        \
 808         (((value) & PHM_FIELD_MASK(reg, field)) >>      \
 809          PHM_FIELD_SHIFT(reg, field))
 810
 811
 812 /* Operations on named fields. */
 813
 814 #define PHM_READ_FIELD(device, reg, field)      \
 815         PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
 816
 817 #define PHM_READ_INDIRECT_FIELD(device, port, reg, field)       \
 818         PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 819                         reg, field)
 820
 821 #define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field)  \
 822         PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 823                         reg, field)
 824
 825 #define PHM_WRITE_FIELD(device, reg, field, fieldval)   \
 826         cgs_write_register(device, mm##reg, PHM_SET_FIELD(      \
 827                                 cgs_read_register(device, mm##reg), reg, field, fieldval))
 828
 829 #define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval)    \
 830         cgs_write_ind_register(device, port, ix##reg,   \
 831                         PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 832                                 reg, field, fieldval))
 833
 834 #define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval)       \
 835         cgs_write_ind_register(device, port, ix##reg,   \
 836                         PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 837                                 reg, field, fieldval))
 838
 839 #define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask)        \
 840        phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
 841
 842
 843 #define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask)      \
 844        PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 845
 846 #define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval)      \
 847         PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
 848                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 849
 850
 851 #endif /* _HWMGR_H_ */