2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 #ifndef __AMDGPU_SMU_H__
23 #define __AMDGPU_SMU_H__
26 #include "kgd_pp_interface.h"
27 #include "dm_pp_interface.h"
29 struct smu_hw_power_state {
33 struct smu_power_state;
35 enum smu_state_ui_label {
36 SMU_STATE_UI_LABEL_NONE,
37 SMU_STATE_UI_LABEL_BATTERY,
38 SMU_STATE_UI_TABEL_MIDDLE_LOW,
39 SMU_STATE_UI_LABEL_BALLANCED,
40 SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
41 SMU_STATE_UI_LABEL_PERFORMANCE,
42 SMU_STATE_UI_LABEL_BACO,
45 enum smu_state_classification_flag {
46 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001,
47 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002,
48 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004,
49 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008,
50 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010,
51 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020,
52 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040,
53 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080,
54 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100,
55 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200,
56 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400,
57 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800,
58 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000,
59 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000,
60 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000,
61 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000,
62 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000,
63 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000,
64 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000,
65 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000,
66 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000,
69 struct smu_state_classification_block {
70 enum smu_state_ui_label ui_label;
71 enum smu_state_classification_flag flags;
77 struct smu_state_pcie_block {
81 enum smu_refreshrate_source {
82 SMU_REFRESHRATE_SOURCE_EDID,
83 SMU_REFRESHRATE_SOURCE_EXPLICIT
86 struct smu_state_display_block {
87 bool disable_frame_modulation;
88 bool limit_refreshrate;
89 enum smu_refreshrate_source refreshrate_source;
90 int explicit_refreshrate;
91 int edid_refreshrate_index;
92 bool enable_vari_bright;
95 struct smu_state_memroy_block {
101 struct smu_state_software_algorithm_block {
102 bool disable_load_balancing;
103 bool enable_sleep_for_timestamps;
106 struct smu_temperature_range {
111 struct smu_state_validation_block {
112 bool single_display_only;
114 uint8_t supported_power_levels;
117 struct smu_uvd_clocks {
123 * Structure to hold a SMU Power State.
125 struct smu_power_state {
127 struct list_head ordered_list;
128 struct list_head all_states_list;
130 struct smu_state_classification_block classification;
131 struct smu_state_validation_block validation;
132 struct smu_state_pcie_block pcie;
133 struct smu_state_display_block display;
134 struct smu_state_memroy_block memory;
135 struct smu_temperature_range temperatures;
136 struct smu_state_software_algorithm_block software;
137 struct smu_uvd_clocks uvd_clocks;
138 struct smu_hw_power_state hardware;
141 enum smu_message_type
143 SMU_MSG_TestMessage = 0,
144 SMU_MSG_GetSmuVersion,
145 SMU_MSG_GetDriverIfVersion,
146 SMU_MSG_SetAllowedFeaturesMaskLow,
147 SMU_MSG_SetAllowedFeaturesMaskHigh,
148 SMU_MSG_EnableAllSmuFeatures,
149 SMU_MSG_DisableAllSmuFeatures,
150 SMU_MSG_EnableSmuFeaturesLow,
151 SMU_MSG_EnableSmuFeaturesHigh,
152 SMU_MSG_DisableSmuFeaturesLow,
153 SMU_MSG_DisableSmuFeaturesHigh,
154 SMU_MSG_GetEnabledSmuFeaturesLow,
155 SMU_MSG_GetEnabledSmuFeaturesHigh,
156 SMU_MSG_SetWorkloadMask,
158 SMU_MSG_SetDriverDramAddrHigh,
159 SMU_MSG_SetDriverDramAddrLow,
160 SMU_MSG_SetToolsDramAddrHigh,
161 SMU_MSG_SetToolsDramAddrLow,
162 SMU_MSG_TransferTableSmu2Dram,
163 SMU_MSG_TransferTableDram2Smu,
164 SMU_MSG_UseDefaultPPTable,
165 SMU_MSG_UseBackupPPTable,
167 SMU_MSG_RequestI2CBus,
168 SMU_MSG_ReleaseI2CBus,
169 SMU_MSG_SetFloorSocVoltage,
171 SMU_MSG_StartBacoMonitor,
172 SMU_MSG_CancelBacoMonitor,
174 SMU_MSG_SetSoftMinByFreq,
175 SMU_MSG_SetSoftMaxByFreq,
176 SMU_MSG_SetHardMinByFreq,
177 SMU_MSG_SetHardMaxByFreq,
178 SMU_MSG_GetMinDpmFreq,
179 SMU_MSG_GetMaxDpmFreq,
180 SMU_MSG_GetDpmFreqByIndex,
181 SMU_MSG_GetDpmClockFreq,
182 SMU_MSG_GetSsVoltageByDpm,
183 SMU_MSG_SetMemoryChannelConfig,
184 SMU_MSG_SetGeminiMode,
185 SMU_MSG_SetGeminiApertureHigh,
186 SMU_MSG_SetGeminiApertureLow,
187 SMU_MSG_SetMinLinkDpmByIndex,
188 SMU_MSG_OverridePcieParameters,
189 SMU_MSG_OverDriveSetPercentage,
190 SMU_MSG_SetMinDeepSleepDcefclk,
191 SMU_MSG_ReenableAcDcInterrupt,
192 SMU_MSG_NotifyPowerSource,
193 SMU_MSG_SetUclkFastSwitch,
194 SMU_MSG_SetUclkDownHyst,
195 SMU_MSG_GfxDeviceDriverReset,
196 SMU_MSG_GetCurrentRpm,
199 SMU_MSG_SetFanTemperatureTarget,
200 SMU_MSG_PrepareMp1ForUnload,
201 SMU_MSG_DramLogSetDramAddrHigh,
202 SMU_MSG_DramLogSetDramAddrLow,
203 SMU_MSG_DramLogSetDramSize,
204 SMU_MSG_SetFanMaxRpm,
205 SMU_MSG_SetFanMinPwm,
206 SMU_MSG_ConfigureGfxDidt,
207 SMU_MSG_NumOfDisplays,
208 SMU_MSG_RemoveMargins,
209 SMU_MSG_ReadSerialNumTop32,
210 SMU_MSG_ReadSerialNumBottom32,
211 SMU_MSG_SetSystemVirtualDramAddrHigh,
212 SMU_MSG_SetSystemVirtualDramAddrLow,
214 SMU_MSG_SetFclkGfxClkRatio,
216 SMU_MSG_DisallowGfxOff,
218 SMU_MSG_GetDcModeMaxDpmFreq,
219 SMU_MSG_GetDebugData,
223 SMU_MSG_PrepareMp1ForReset,
224 SMU_MSG_PrepareMp1ForShutdown,
225 SMU_MSG_SetMGpuFanBoostLimitRpm,
226 SMU_MSG_GetAVFSVoltageByDpm,
230 enum smu_memory_pool_size
232 SMU_MEMORY_POOL_SIZE_ZERO = 0,
233 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
234 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
235 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000,
236 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
239 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \
241 tables[table_id].size = s; \
242 tables[table_id].align = a; \
243 tables[table_id].domain = d; \
252 struct amdgpu_bo *bo;
255 enum smu_perf_level_designation {
257 PERF_LEVEL_POWER_CONTAINMENT,
260 struct smu_performance_level {
262 uint32_t memory_clock;
265 uint32_t non_local_mem_freq;
266 uint32_t non_local_mem_width;
269 struct smu_clock_info {
270 uint32_t min_mem_clk;
271 uint32_t max_mem_clk;
272 uint32_t min_eng_clk;
273 uint32_t max_eng_clk;
274 uint32_t min_bus_bandwidth;
275 uint32_t max_bus_bandwidth;
278 struct smu_bios_boot_up_values
293 uint32_t pp_table_id;
296 struct smu_table_context
298 void *power_play_table;
299 uint32_t power_play_table_size;
300 void *hardcode_pptable;
302 void *max_sustainable_clocks;
303 struct smu_bios_boot_up_values boot_values;
304 void *driver_pptable;
305 struct smu_table *tables;
306 uint32_t table_count;
307 struct smu_table memory_pool;
308 uint16_t software_shutdown_temp;
309 uint8_t thermal_controller_type;
311 uint8_t *od_feature_capabilities;
312 uint32_t *od_settings_max;
313 uint32_t *od_settings_min;
314 void *overdrive_table;
316 bool od_gfxclk_update;
317 bool od_memclk_update;
320 struct smu_dpm_context {
321 uint32_t dpm_context_size;
323 void *golden_dpm_context;
324 bool enable_umd_pstate;
325 enum amd_dpm_forced_level dpm_level;
326 enum amd_dpm_forced_level saved_dpm_level;
327 enum amd_dpm_forced_level requested_dpm_level;
328 struct smu_power_state *dpm_request_power_state;
329 struct smu_power_state *dpm_current_power_state;
330 struct mclock_latency_table *mclk_latency_table;
333 struct smu_power_context {
335 uint32_t power_context_size;
339 #define SMU_FEATURE_MAX (64)
342 uint32_t feature_num;
343 DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
344 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
345 DECLARE_BITMAP(enabled, SMU_FEATURE_MAX);
350 uint32_t engine_clock;
351 uint32_t memory_clock;
352 uint32_t bus_bandwidth;
353 uint32_t engine_clock_in_sr;
355 uint32_t dcef_clock_in_sr;
358 #define MAX_REGULAR_DPM_NUM 16
359 struct mclk_latency_entries {
363 struct mclock_latency_table {
365 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM];
368 #define WORKLOAD_POLICY_MAX 7
371 struct amdgpu_device *adev;
373 const struct smu_funcs *funcs;
374 const struct pptable_funcs *ppt_funcs;
378 struct smu_table_context smu_table;
379 struct smu_dpm_context smu_dpm;
380 struct smu_power_context smu_power;
381 struct smu_feature smu_feature;
382 struct amd_pp_display_configuration *display_config;
384 uint32_t pstate_sclk;
385 uint32_t pstate_mclk;
387 uint32_t power_limit;
388 uint32_t default_power_limit;
390 bool support_power_containment;
391 bool disable_watermark;
393 #define WATERMARKS_EXIST (1 << 0)
394 #define WATERMARKS_LOADED (1 << 1)
395 uint32_t watermarks_bitmap;
397 uint32_t workload_mask;
398 uint32_t workload_prority[WORKLOAD_POLICY_MAX];
399 uint32_t workload_setting[WORKLOAD_POLICY_MAX];
400 uint32_t power_profile_mode;
401 uint32_t default_power_profile_mode;
404 struct pptable_funcs {
405 int (*alloc_dpm_context)(struct smu_context *smu);
406 int (*store_powerplay_table)(struct smu_context *smu);
407 int (*check_powerplay_table)(struct smu_context *smu);
408 int (*append_powerplay_table)(struct smu_context *smu);
409 int (*get_smu_msg_index)(struct smu_context *smu, uint32_t index);
410 int (*run_afll_btc)(struct smu_context *smu);
411 int (*get_unallowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
412 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
413 int (*set_default_dpm_table)(struct smu_context *smu);
414 int (*set_power_state)(struct smu_context *smu);
415 int (*populate_umd_state_clk)(struct smu_context *smu);
416 int (*print_clk_levels)(struct smu_context *smu, enum pp_clock_type type, char *buf);
417 int (*force_clk_levels)(struct smu_context *smu, enum pp_clock_type type, uint32_t mask);
418 int (*set_default_od8_settings)(struct smu_context *smu);
419 int (*update_specified_od8_value)(struct smu_context *smu,
422 int (*get_od_percentage)(struct smu_context *smu, enum pp_clock_type type);
423 int (*set_od_percentage)(struct smu_context *smu,
424 enum pp_clock_type type,
426 int (*od_edit_dpm_table)(struct smu_context *smu,
427 enum PP_OD_DPM_TABLE_COMMAND type,
428 long *input, uint32_t size);
429 int (*get_clock_by_type_with_latency)(struct smu_context *smu,
430 enum amd_pp_clock_type type,
432 pp_clock_levels_with_latency
434 int (*get_clock_by_type_with_voltage)(struct smu_context *smu,
435 enum amd_pp_clock_type type,
437 pp_clock_levels_with_voltage
439 int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
440 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
441 enum amd_dpm_forced_level (*get_performance_level)(struct smu_context *smu);
442 int (*force_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
443 int (*pre_display_config_changed)(struct smu_context *smu);
444 int (*display_config_changed)(struct smu_context *smu);
445 int (*apply_clocks_adjust_rules)(struct smu_context *smu);
446 int (*notify_smc_dispaly_config)(struct smu_context *smu);
447 int (*force_dpm_limit_value)(struct smu_context *smu, bool highest);
448 int (*upload_dpm_level)(struct smu_context *smu, bool max);
449 int (*get_profiling_clk_mask)(struct smu_context *smu,
450 enum amd_dpm_forced_level level,
454 int (*set_cpu_power_state)(struct smu_context *smu);
459 int (*init_microcode)(struct smu_context *smu);
460 int (*init_smc_tables)(struct smu_context *smu);
461 int (*fini_smc_tables)(struct smu_context *smu);
462 int (*init_power)(struct smu_context *smu);
463 int (*fini_power)(struct smu_context *smu);
464 int (*load_microcode)(struct smu_context *smu);
465 int (*check_fw_status)(struct smu_context *smu);
466 int (*read_pptable_from_vbios)(struct smu_context *smu);
467 int (*get_vbios_bootup_values)(struct smu_context *smu);
468 int (*get_clk_info_from_vbios)(struct smu_context *smu);
469 int (*check_pptable)(struct smu_context *smu);
470 int (*parse_pptable)(struct smu_context *smu);
471 int (*populate_smc_pptable)(struct smu_context *smu);
472 int (*check_fw_version)(struct smu_context *smu);
473 int (*write_pptable)(struct smu_context *smu);
474 int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
475 int (*set_tool_table_location)(struct smu_context *smu);
476 int (*notify_memory_pool_location)(struct smu_context *smu);
477 int (*write_watermarks_table)(struct smu_context *smu);
478 int (*set_last_dcef_min_deep_sleep_clk)(struct smu_context *smu);
479 int (*system_features_control)(struct smu_context *smu, bool en);
480 int (*send_smc_msg)(struct smu_context *smu, uint16_t msg);
481 int (*send_smc_msg_with_param)(struct smu_context *smu, uint16_t msg, uint32_t param);
482 int (*read_smc_arg)(struct smu_context *smu, uint32_t *arg);
483 int (*init_display)(struct smu_context *smu);
484 int (*set_allowed_mask)(struct smu_context *smu);
485 int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
486 bool (*is_dpm_running)(struct smu_context *smu);
487 int (*enable_all_mask)(struct smu_context *smu);
488 int (*disable_all_mask)(struct smu_context *smu);
489 int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled);
490 int (*notify_display_change)(struct smu_context *smu);
491 int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool def);
492 int (*set_power_limit)(struct smu_context *smu, uint32_t n);
493 int (*get_current_clk_freq)(struct smu_context *smu, uint32_t clk_id, uint32_t *value);
494 int (*init_max_sustainable_clocks)(struct smu_context *smu);
495 int (*start_thermal_control)(struct smu_context *smu);
496 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
497 void *data, uint32_t *size);
498 int (*set_deep_sleep_dcefclk)(struct smu_context *smu, uint32_t clk);
499 int (*set_active_display_count)(struct smu_context *smu, uint32_t count);
500 int (*store_cc6_data)(struct smu_context *smu, uint32_t separation_time,
501 bool cc6_disable, bool pstate_disable,
502 bool pstate_switch_disable);
503 int (*get_clock_by_type)(struct smu_context *smu,
504 enum amd_pp_clock_type type,
505 struct amd_pp_clocks *clocks);
506 int (*get_max_high_clocks)(struct smu_context *smu,
507 struct amd_pp_simple_clock_info *clocks);
508 int (*display_clock_voltage_request)(struct smu_context *smu, struct
509 pp_display_clock_request
511 int (*get_dal_power_level)(struct smu_context *smu,
512 struct amd_pp_simple_clock_info *clocks);
513 int (*get_perf_level)(struct smu_context *smu,
514 enum smu_perf_level_designation designation,
515 struct smu_performance_level *level);
516 int (*get_current_shallow_sleep_clocks)(struct smu_context *smu,
517 struct smu_clock_info *clocks);
518 int (*notify_smu_enable_pwe)(struct smu_context *smu);
519 int (*set_watermarks_for_clock_ranges)(struct smu_context *smu,
520 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges);
521 int (*set_od8_default_settings)(struct smu_context *smu,
523 int (*get_activity_monitor_coeff)(struct smu_context *smu,
525 uint16_t workload_type);
526 int (*set_activity_monitor_coeff)(struct smu_context *smu,
528 uint16_t workload_type);
529 int (*conv_power_profile_to_pplib_workload)(int power_profile);
530 int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
531 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
532 int (*update_od8_settings)(struct smu_context *smu,
535 int (*dpm_set_uvd_enable)(struct smu_context *smu, bool enable);
536 int (*dpm_set_vce_enable)(struct smu_context *smu, bool enable);
537 uint32_t (*get_sclk)(struct smu_context *smu, bool low);
538 uint32_t (*get_mclk)(struct smu_context *smu, bool low);
539 int (*get_current_rpm)(struct smu_context *smu, uint32_t *speed);
540 uint32_t (*get_fan_control_mode)(struct smu_context *smu);
541 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
542 int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
543 int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed);
544 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
547 #define smu_init_microcode(smu) \
548 ((smu)->funcs->init_microcode ? (smu)->funcs->init_microcode((smu)) : 0)
549 #define smu_init_smc_tables(smu) \
550 ((smu)->funcs->init_smc_tables ? (smu)->funcs->init_smc_tables((smu)) : 0)
551 #define smu_fini_smc_tables(smu) \
552 ((smu)->funcs->fini_smc_tables ? (smu)->funcs->fini_smc_tables((smu)) : 0)
553 #define smu_init_power(smu) \
554 ((smu)->funcs->init_power ? (smu)->funcs->init_power((smu)) : 0)
555 #define smu_fini_power(smu) \
556 ((smu)->funcs->fini_power ? (smu)->funcs->fini_power((smu)) : 0)
557 #define smu_load_microcode(smu) \
558 ((smu)->funcs->load_microcode ? (smu)->funcs->load_microcode((smu)) : 0)
559 #define smu_check_fw_status(smu) \
560 ((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
561 #define smu_read_pptable_from_vbios(smu) \
562 ((smu)->funcs->read_pptable_from_vbios ? (smu)->funcs->read_pptable_from_vbios((smu)) : 0)
563 #define smu_get_vbios_bootup_values(smu) \
564 ((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
565 #define smu_get_clk_info_from_vbios(smu) \
566 ((smu)->funcs->get_clk_info_from_vbios ? (smu)->funcs->get_clk_info_from_vbios((smu)) : 0)
567 #define smu_check_pptable(smu) \
568 ((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
569 #define smu_parse_pptable(smu) \
570 ((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
571 #define smu_populate_smc_pptable(smu) \
572 ((smu)->funcs->populate_smc_pptable ? (smu)->funcs->populate_smc_pptable((smu)) : 0)
573 #define smu_check_fw_version(smu) \
574 ((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
575 #define smu_write_pptable(smu) \
576 ((smu)->funcs->write_pptable ? (smu)->funcs->write_pptable((smu)) : 0)
577 #define smu_set_min_dcef_deep_sleep(smu) \
578 ((smu)->funcs->set_min_dcef_deep_sleep ? (smu)->funcs->set_min_dcef_deep_sleep((smu)) : 0)
579 #define smu_set_tool_table_location(smu) \
580 ((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0)
581 #define smu_notify_memory_pool_location(smu) \
582 ((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0)
583 #define smu_write_watermarks_table(smu) \
584 ((smu)->funcs->write_watermarks_table ? (smu)->funcs->write_watermarks_table((smu)) : 0)
585 #define smu_set_last_dcef_min_deep_sleep_clk(smu) \
586 ((smu)->funcs->set_last_dcef_min_deep_sleep_clk ? (smu)->funcs->set_last_dcef_min_deep_sleep_clk((smu)) : 0)
587 #define smu_system_features_control(smu, en) \
588 ((smu)->funcs->system_features_control ? (smu)->funcs->system_features_control((smu), (en)) : 0)
589 #define smu_init_max_sustainable_clocks(smu) \
590 ((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0)
591 #define smu_set_od8_default_settings(smu, initialize) \
592 ((smu)->funcs->set_od8_default_settings ? (smu)->funcs->set_od8_default_settings((smu), (initialize)) : 0)
593 #define smu_update_od8_settings(smu, index, value) \
594 ((smu)->funcs->update_od8_settings ? (smu)->funcs->update_od8_settings((smu), (index), (value)) : 0)
595 #define smu_get_current_rpm(smu, speed) \
596 ((smu)->funcs->get_current_rpm ? (smu)->funcs->get_current_rpm((smu), (speed)) : 0)
597 #define smu_set_fan_speed_rpm(smu, speed) \
598 ((smu)->funcs->set_fan_speed_rpm ? (smu)->funcs->set_fan_speed_rpm((smu), (speed)) : 0)
599 #define smu_send_smc_msg(smu, msg) \
600 ((smu)->funcs->send_smc_msg? (smu)->funcs->send_smc_msg((smu), (msg)) : 0)
601 #define smu_send_smc_msg_with_param(smu, msg, param) \
602 ((smu)->funcs->send_smc_msg_with_param? (smu)->funcs->send_smc_msg_with_param((smu), (msg), (param)) : 0)
603 #define smu_read_smc_arg(smu, arg) \
604 ((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
605 #define smu_alloc_dpm_context(smu) \
606 ((smu)->ppt_funcs->alloc_dpm_context ? (smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
607 #define smu_init_display(smu) \
608 ((smu)->funcs->init_display ? (smu)->funcs->init_display((smu)) : 0)
609 #define smu_feature_set_allowed_mask(smu) \
610 ((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu)) : 0)
611 #define smu_feature_get_enabled_mask(smu, mask, num) \
612 ((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
613 #define smu_is_dpm_running(smu) \
614 ((smu)->funcs->is_dpm_running ? (smu)->funcs->is_dpm_running((smu)) : 0)
615 #define smu_feature_enable_all(smu) \
616 ((smu)->funcs->enable_all_mask? (smu)->funcs->enable_all_mask((smu)) : 0)
617 #define smu_feature_disable_all(smu) \
618 ((smu)->funcs->disable_all_mask? (smu)->funcs->disable_all_mask((smu)) : 0)
619 #define smu_feature_update_enable_state(smu, feature_id, enabled) \
620 ((smu)->funcs->update_feature_enable_state? (smu)->funcs->update_feature_enable_state((smu), (feature_id), (enabled)) : 0)
621 #define smu_notify_display_change(smu) \
622 ((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
623 #define smu_store_powerplay_table(smu) \
624 ((smu)->ppt_funcs->store_powerplay_table ? (smu)->ppt_funcs->store_powerplay_table((smu)) : 0)
625 #define smu_check_powerplay_table(smu) \
626 ((smu)->ppt_funcs->check_powerplay_table ? (smu)->ppt_funcs->check_powerplay_table((smu)) : 0)
627 #define smu_append_powerplay_table(smu) \
628 ((smu)->ppt_funcs->append_powerplay_table ? (smu)->ppt_funcs->append_powerplay_table((smu)) : 0)
629 #define smu_set_default_dpm_table(smu) \
630 ((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
631 #define smu_populate_umd_state_clk(smu) \
632 ((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
633 #define smu_set_default_od8_settings(smu) \
634 ((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
635 #define smu_update_specified_od8_value(smu, index, value) \
636 ((smu)->ppt_funcs->update_specified_od8_value ? (smu)->ppt_funcs->update_specified_od8_value((smu), (index), (value)) : 0)
637 #define smu_get_power_limit(smu, limit, def) \
638 ((smu)->funcs->get_power_limit ? (smu)->funcs->get_power_limit((smu), (limit), (def)) : 0)
639 #define smu_set_power_limit(smu, limit) \
640 ((smu)->funcs->set_power_limit ? (smu)->funcs->set_power_limit((smu), (limit)) : 0)
641 #define smu_get_current_clk_freq(smu, clk_id, value) \
642 ((smu)->funcs->get_current_clk_freq? (smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
643 #define smu_print_clk_levels(smu, type, buf) \
644 ((smu)->ppt_funcs->print_clk_levels ? (smu)->ppt_funcs->print_clk_levels((smu), (type), (buf)) : 0)
645 #define smu_force_clk_levels(smu, type, level) \
646 ((smu)->ppt_funcs->force_clk_levels ? (smu)->ppt_funcs->force_clk_levels((smu), (type), (level)) : 0)
647 #define smu_get_od_percentage(smu, type) \
648 ((smu)->ppt_funcs->get_od_percentage ? (smu)->ppt_funcs->get_od_percentage((smu), (type)) : 0)
649 #define smu_set_od_percentage(smu, type, value) \
650 ((smu)->ppt_funcs->set_od_percentage ? (smu)->ppt_funcs->set_od_percentage((smu), (type), (value)) : 0)
651 #define smu_od_edit_dpm_table(smu, type, input, size) \
652 ((smu)->ppt_funcs->od_edit_dpm_table ? (smu)->ppt_funcs->od_edit_dpm_table((smu), (type), (input), (size)) : 0)
653 #define smu_start_thermal_control(smu) \
654 ((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
655 #define smu_read_sensor(smu, sensor, data, size) \
656 ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
657 #define smu_get_power_profile_mode(smu, buf) \
658 ((smu)->funcs->get_power_profile_mode ? (smu)->funcs->get_power_profile_mode((smu), buf) : 0)
659 #define smu_set_power_profile_mode(smu, param, param_size) \
660 ((smu)->funcs->set_power_profile_mode ? (smu)->funcs->set_power_profile_mode((smu), (param), (param_size)) : 0)
661 #define smu_get_performance_level(smu) \
662 ((smu)->ppt_funcs->get_performance_level ? (smu)->ppt_funcs->get_performance_level((smu)) : 0)
663 #define smu_force_performance_level(smu, level) \
664 ((smu)->ppt_funcs->force_performance_level ? (smu)->ppt_funcs->force_performance_level((smu), (level)) : 0)
665 #define smu_pre_display_config_changed(smu) \
666 ((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed((smu)) : 0)
667 #define smu_display_config_changed(smu) \
668 ((smu)->ppt_funcs->display_config_changed ? (smu)->ppt_funcs->display_config_changed((smu)) : 0)
669 #define smu_apply_clocks_adjust_rules(smu) \
670 ((smu)->ppt_funcs->apply_clocks_adjust_rules ? (smu)->ppt_funcs->apply_clocks_adjust_rules((smu)) : 0)
671 #define smu_notify_smc_dispaly_config(smu) \
672 ((smu)->ppt_funcs->notify_smc_dispaly_config ? (smu)->ppt_funcs->notify_smc_dispaly_config((smu)) : 0)
673 #define smu_force_dpm_limit_value(smu, highest) \
674 ((smu)->ppt_funcs->force_dpm_limit_value ? (smu)->ppt_funcs->force_dpm_limit_value((smu), (highest)) : 0)
675 #define smu_upload_dpm_level(smu, max) \
676 ((smu)->ppt_funcs->upload_dpm_level ? (smu)->ppt_funcs->upload_dpm_level((smu), (max)) : 0)
677 #define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
678 ((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
679 #define smu_set_cpu_power_state(smu) \
680 ((smu)->ppt_funcs->set_cpu_power_state ? (smu)->ppt_funcs->set_cpu_power_state((smu)) : 0)
681 #define smu_get_fan_control_mode(smu) \
682 ((smu)->funcs->get_fan_control_mode ? (smu)->funcs->get_fan_control_mode((smu)) : 0)
683 #define smu_set_fan_control_mode(smu, value) \
684 ((smu)->funcs->set_fan_control_mode ? (smu)->funcs->set_fan_control_mode((smu), (value)) : 0)
685 #define smu_get_fan_speed_percent(smu, speed) \
686 ((smu)->funcs->get_fan_speed_percent ? (smu)->funcs->get_fan_speed_percent((smu), (speed)) : 0)
687 #define smu_set_fan_speed_percent(smu, speed) \
688 ((smu)->funcs->set_fan_speed_percent ? (smu)->funcs->set_fan_speed_percent((smu), (speed)) : 0)
690 #define smu_msg_get_index(smu, msg) \
691 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
692 #define smu_run_afll_btc(smu) \
693 ((smu)->ppt_funcs? ((smu)->ppt_funcs->run_afll_btc? (smu)->ppt_funcs->run_afll_btc((smu)) : 0) : 0)
694 #define smu_get_unallowed_feature_mask(smu, feature_mask, num) \
695 ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_unallowed_feature_mask? (smu)->ppt_funcs->get_unallowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
696 #define smu_set_deep_sleep_dcefclk(smu, clk) \
697 ((smu)->funcs->set_deep_sleep_dcefclk ? (smu)->funcs->set_deep_sleep_dcefclk((smu), (clk)) : 0)
698 #define smu_set_active_display_count(smu, count) \
699 ((smu)->funcs->set_active_display_count ? (smu)->funcs->set_active_display_count((smu), (count)) : 0)
700 #define smu_store_cc6_data(smu, st, cc6_dis, pst_dis, pst_sw_dis) \
701 ((smu)->funcs->store_cc6_data ? (smu)->funcs->store_cc6_data((smu), (st), (cc6_dis), (pst_dis), (pst_sw_dis)) : 0)
702 #define smu_get_clock_by_type(smu, type, clocks) \
703 ((smu)->funcs->get_clock_by_type ? (smu)->funcs->get_clock_by_type((smu), (type), (clocks)) : 0)
704 #define smu_get_max_high_clocks(smu, clocks) \
705 ((smu)->funcs->get_max_high_clocks ? (smu)->funcs->get_max_high_clocks((smu), (clocks)) : 0)
706 #define smu_get_clock_by_type_with_latency(smu, type, clocks) \
707 ((smu)->ppt_funcs->get_clock_by_type_with_latency ? (smu)->ppt_funcs->get_clock_by_type_with_latency((smu), (type), (clocks)) : 0)
708 #define smu_get_clock_by_type_with_voltage(smu, type, clocks) \
709 ((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
710 #define smu_display_clock_voltage_request(smu, clock_req) \
711 ((smu)->funcs->display_clock_voltage_request ? (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
712 #define smu_get_dal_power_level(smu, clocks) \
713 ((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
714 #define smu_get_perf_level(smu, designation, level) \
715 ((smu)->funcs->get_perf_level ? (smu)->funcs->get_perf_level((smu), (designation), (level)) : 0)
716 #define smu_get_current_shallow_sleep_clocks(smu, clocks) \
717 ((smu)->funcs->get_current_shallow_sleep_clocks ? (smu)->funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
718 #define smu_notify_smu_enable_pwe(smu) \
719 ((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
720 #define smu_set_watermarks_for_clock_ranges(smu, clock_ranges) \
721 ((smu)->funcs->set_watermarks_for_clock_ranges ? (smu)->funcs->set_watermarks_for_clock_ranges((smu), (clock_ranges)) : 0)
722 #define smu_dpm_set_uvd_enable(smu, enable) \
723 ((smu)->funcs->dpm_set_uvd_enable ? (smu)->funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
724 #define smu_dpm_set_vce_enable(smu, enable) \
725 ((smu)->funcs->dpm_set_vce_enable ? (smu)->funcs->dpm_set_vce_enable((smu), (enable)) : 0)
726 #define smu_get_sclk(smu, low) \
727 ((smu)->funcs->get_sclk ? (smu)->funcs->get_sclk((smu), (low)) : 0)
728 #define smu_get_mclk(smu, low) \
729 ((smu)->funcs->get_mclk ? (smu)->funcs->get_mclk((smu), (low)) : 0)
732 extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
733 uint16_t *size, uint8_t *frev, uint8_t *crev,
736 extern const struct amd_ip_funcs smu_ip_funcs;
738 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
739 extern int smu_feature_init_dpm(struct smu_context *smu);
741 extern int smu_feature_is_enabled(struct smu_context *smu, int feature_id);
742 extern int smu_feature_set_enabled(struct smu_context *smu, int feature_id, bool enable);
743 extern int smu_feature_is_supported(struct smu_context *smu, int feature_id);
744 extern int smu_feature_set_supported(struct smu_context *smu, int feature_id, bool enable);
746 int smu_update_table(struct smu_context *smu, uint32_t table_id,
747 void *table_data, bool drv2smu);
748 bool is_support_sw_smu(struct amdgpu_device *adev);
749 int smu_reset(struct smu_context *smu);
750 int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
751 void *data, uint32_t *size);
752 int smu_sys_get_pp_table(struct smu_context *smu, void **table);
753 int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size);
754 int smu_get_power_num_states(struct smu_context *smu, struct pp_states_info *state_info);
755 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu);
757 /* smu to display interface */
758 extern int smu_display_configuration_change(struct smu_context *smu, const
759 struct amd_pp_display_configuration
761 extern int smu_get_current_clocks(struct smu_context *smu,
762 struct amd_pp_clock_info *clocks);
763 extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
764 extern int smu_handle_task(struct smu_context *smu,
765 enum amd_dpm_forced_level level,
766 enum amd_pp_task task_id);