drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/fb.h>
  26 #include <linux/module.h>
  27 #include <linux/slab.h>
  28
  29 #include "hwmgr.h"
  30 #include "amd_powerplay.h"
  31 #include "vega20_smumgr.h"
  32 #include "hardwaremanager.h"
  33 #include "ppatomfwctrl.h"
  34 #include "atomfirmware.h"
  35 #include "cgs_common.h"
  36 #include "vega20_powertune.h"
  37 #include "vega20_inc.h"
  38 #include "pppcielanes.h"
  39 #include "vega20_hwmgr.h"
  40 #include "vega20_processpptables.h"
  41 #include "vega20_pptable.h"
  42 #include "vega20_thermal.h"
  43 #include "vega20_ppsmc.h"
  44 #include "pp_debug.h"
  45 #include "amd_pcie_helpers.h"
  46 #include "ppinterrupt.h"
  47 #include "pp_overdriver.h"
  48 #include "pp_thermal.h"
  49 #include "soc15_common.h"
  50 #include "vega20_baco.h"
  51 #include "smuio/smuio_9_0_offset.h"
  52 #include "smuio/smuio_9_0_sh_mask.h"
  53 #include "nbio/nbio_7_4_sh_mask.h"
  54
  55 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  56 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  57
  58 static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
  59 {
  60         struct vega20_hwmgr *data =
  61                         (struct vega20_hwmgr *)(hwmgr->backend);
  62
  63         data->gfxclk_average_alpha = PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT;
  64         data->socclk_average_alpha = PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT;
  65         data->uclk_average_alpha = PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT;
  66         data->gfx_activity_average_alpha = PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT;
  67         data->lowest_uclk_reserved_for_ulv = PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT;
  68
  69         data->display_voltage_mode = PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT;
  70         data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  71         data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  72         data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  73         data->disp_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  74         data->disp_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  75         data->disp_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  76         data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  77         data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  78         data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  79         data->phy_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  80         data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  81         data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
  82
  83         /*
  84          * Disable the following features for now:
  85          *   GFXCLK DS
  86          *   SOCLK DS
  87          *   LCLK DS
  88          *   DCEFCLK DS
  89          *   FCLK DS
  90          *   MP1CLK DS
  91          *   MP0CLK DS
  92          */
  93         data->registry_data.disallowed_features = 0xE0041C00;
  94         /* ECC feature should be disabled on old SMUs */
  95         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion, &hwmgr->smu_version);
  96         if (hwmgr->smu_version < 0x282100)
  97                 data->registry_data.disallowed_features |= FEATURE_ECC_MASK;
  98
  99         if (!(hwmgr->feature_mask & PP_PCIE_DPM_MASK))
 100                 data->registry_data.disallowed_features |= FEATURE_DPM_LINK_MASK;
 101
 102         if (!(hwmgr->feature_mask & PP_SCLK_DPM_MASK))
 103                 data->registry_data.disallowed_features |= FEATURE_DPM_GFXCLK_MASK;
 104
 105         if (!(hwmgr->feature_mask & PP_SOCCLK_DPM_MASK))
 106                 data->registry_data.disallowed_features |= FEATURE_DPM_SOCCLK_MASK;
 107
 108         if (!(hwmgr->feature_mask & PP_MCLK_DPM_MASK))
 109                 data->registry_data.disallowed_features |= FEATURE_DPM_UCLK_MASK;
 110
 111         if (!(hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK))
 112                 data->registry_data.disallowed_features |= FEATURE_DPM_DCEFCLK_MASK;
 113
 114         if (!(hwmgr->feature_mask & PP_ULV_MASK))
 115                 data->registry_data.disallowed_features |= FEATURE_ULV_MASK;
 116
 117         if (!(hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK))
 118                 data->registry_data.disallowed_features |= FEATURE_DS_GFXCLK_MASK;
 119
 120         data->registry_data.od_state_in_dc_support = 0;
 121         data->registry_data.thermal_support = 1;
 122         data->registry_data.skip_baco_hardware = 0;
 123
 124         data->registry_data.log_avfs_param = 0;
 125         data->registry_data.sclk_throttle_low_notification = 1;
 126         data->registry_data.force_dpm_high = 0;
 127         data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
 128
 129         data->registry_data.didt_support = 0;
 130         if (data->registry_data.didt_support) {
 131                 data->registry_data.didt_mode = 6;
 132                 data->registry_data.sq_ramping_support = 1;
 133                 data->registry_data.db_ramping_support = 0;
 134                 data->registry_data.td_ramping_support = 0;
 135                 data->registry_data.tcp_ramping_support = 0;
 136                 data->registry_data.dbr_ramping_support = 0;
 137                 data->registry_data.edc_didt_support = 1;
 138                 data->registry_data.gc_didt_support = 0;
 139                 data->registry_data.psm_didt_support = 0;
 140         }
 141
 142         data->registry_data.pcie_lane_override = 0xff;
 143         data->registry_data.pcie_speed_override = 0xff;
 144         data->registry_data.pcie_clock_override = 0xffffffff;
 145         data->registry_data.regulator_hot_gpio_support = 1;
 146         data->registry_data.ac_dc_switch_gpio_support = 0;
 147         data->registry_data.quick_transition_support = 0;
 148         data->registry_data.zrpm_start_temp = 0xffff;
 149         data->registry_data.zrpm_stop_temp = 0xffff;
 150         data->registry_data.od8_feature_enable = 1;
 151         data->registry_data.disable_water_mark = 0;
 152         data->registry_data.disable_pp_tuning = 0;
 153         data->registry_data.disable_xlpp_tuning = 0;
 154         data->registry_data.disable_workload_policy = 0;
 155         data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
 156         data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
 157         data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
 158         data->registry_data.force_workload_policy_mask = 0;
 159         data->registry_data.disable_3d_fs_detection = 0;
 160         data->registry_data.fps_support = 1;
 161         data->registry_data.disable_auto_wattman = 1;
 162         data->registry_data.auto_wattman_debug = 0;
 163         data->registry_data.auto_wattman_sample_period = 100;
 164         data->registry_data.fclk_gfxclk_ratio = 0;
 165         data->registry_data.auto_wattman_threshold = 50;
 166         data->registry_data.gfxoff_controlled_by_driver = 1;
 167         data->gfxoff_allowed = false;
 168         data->counter_gfxoff = 0;
 169 }
 170
 171 static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr)
 172 {
 173         struct vega20_hwmgr *data =
 174                         (struct vega20_hwmgr *)(hwmgr->backend);
 175         struct amdgpu_device *adev = hwmgr->adev;
 176
 177         if (data->vddci_control == VEGA20_VOLTAGE_CONTROL_NONE)
 178                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 179                                 PHM_PlatformCaps_ControlVDDCI);
 180
 181         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 182                         PHM_PlatformCaps_TablelessHardwareInterface);
 183
 184         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 185                         PHM_PlatformCaps_BACO);
 186
 187         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 188                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
 189
 190         if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
 191                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 192                                 PHM_PlatformCaps_UVDPowerGating);
 193
 194         if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
 195                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 196                                 PHM_PlatformCaps_VCEPowerGating);
 197
 198         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 199                         PHM_PlatformCaps_UnTabledHardwareInterface);
 200
 201         if (data->registry_data.od8_feature_enable)
 202                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 203                                 PHM_PlatformCaps_OD8inACSupport);
 204
 205         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 206                         PHM_PlatformCaps_ActivityReporting);
 207         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 208                         PHM_PlatformCaps_FanSpeedInTableIsRPM);
 209
 210         if (data->registry_data.od_state_in_dc_support) {
 211                 if (data->registry_data.od8_feature_enable)
 212                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 213                                         PHM_PlatformCaps_OD8inDCSupport);
 214         }
 215
 216         if (data->registry_data.thermal_support &&
 217             data->registry_data.fuzzy_fan_control_support &&
 218             hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
 219                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 220                                 PHM_PlatformCaps_ODFuzzyFanControlSupport);
 221
 222         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 223                         PHM_PlatformCaps_DynamicPowerManagement);
 224         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 225                         PHM_PlatformCaps_SMC);
 226         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 227                         PHM_PlatformCaps_ThermalPolicyDelay);
 228
 229         if (data->registry_data.force_dpm_high)
 230                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 231                                 PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
 232
 233         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 234                         PHM_PlatformCaps_DynamicUVDState);
 235
 236         if (data->registry_data.sclk_throttle_low_notification)
 237                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 238                                 PHM_PlatformCaps_SclkThrottleLowNotification);
 239
 240         /* power tune caps */
 241         /* assume disabled */
 242         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 243                         PHM_PlatformCaps_PowerContainment);
 244         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 245                         PHM_PlatformCaps_DiDtSupport);
 246         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 247                         PHM_PlatformCaps_SQRamping);
 248         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 249                         PHM_PlatformCaps_DBRamping);
 250         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 251                         PHM_PlatformCaps_TDRamping);
 252         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 253                         PHM_PlatformCaps_TCPRamping);
 254         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 255                         PHM_PlatformCaps_DBRRamping);
 256         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 257                         PHM_PlatformCaps_DiDtEDCEnable);
 258         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 259                         PHM_PlatformCaps_GCEDC);
 260         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 261                         PHM_PlatformCaps_PSM);
 262
 263         if (data->registry_data.didt_support) {
 264                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 265                                 PHM_PlatformCaps_DiDtSupport);
 266                 if (data->registry_data.sq_ramping_support)
 267                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 268                                         PHM_PlatformCaps_SQRamping);
 269                 if (data->registry_data.db_ramping_support)
 270                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 271                                         PHM_PlatformCaps_DBRamping);
 272                 if (data->registry_data.td_ramping_support)
 273                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 274                                         PHM_PlatformCaps_TDRamping);
 275                 if (data->registry_data.tcp_ramping_support)
 276                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 277                                         PHM_PlatformCaps_TCPRamping);
 278                 if (data->registry_data.dbr_ramping_support)
 279                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 280                                         PHM_PlatformCaps_DBRRamping);
 281                 if (data->registry_data.edc_didt_support)
 282                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 283                                         PHM_PlatformCaps_DiDtEDCEnable);
 284                 if (data->registry_data.gc_didt_support)
 285                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 286                                         PHM_PlatformCaps_GCEDC);
 287                 if (data->registry_data.psm_didt_support)
 288                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 289                                         PHM_PlatformCaps_PSM);
 290         }
 291
 292         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 293                         PHM_PlatformCaps_RegulatorHot);
 294
 295         if (data->registry_data.ac_dc_switch_gpio_support) {
 296                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 297                                 PHM_PlatformCaps_AutomaticDCTransition);
 298                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 299                                 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
 300         }
 301
 302         if (data->registry_data.quick_transition_support) {
 303                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 304                                 PHM_PlatformCaps_AutomaticDCTransition);
 305                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 306                                 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
 307                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 308                                 PHM_PlatformCaps_Falcon_QuickTransition);
 309         }
 310
 311         if (data->lowest_uclk_reserved_for_ulv != PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT) {
 312                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 313                                 PHM_PlatformCaps_LowestUclkReservedForUlv);
 314                 if (data->lowest_uclk_reserved_for_ulv == 1)
 315                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 316                                         PHM_PlatformCaps_LowestUclkReservedForUlv);
 317         }
 318
 319         if (data->registry_data.custom_fan_support)
 320                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 321                                 PHM_PlatformCaps_CustomFanControlSupport);
 322
 323         return 0;
 324 }
 325
 326 static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 327 {
 328         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 329         struct amdgpu_device *adev = hwmgr->adev;
 330         uint32_t top32, bottom32;
 331         int i;
 332
 333         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
 334                         FEATURE_DPM_PREFETCHER_BIT;
 335         data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
 336                         FEATURE_DPM_GFXCLK_BIT;
 337         data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
 338                         FEATURE_DPM_UCLK_BIT;
 339         data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
 340                         FEATURE_DPM_SOCCLK_BIT;
 341         data->smu_features[GNLD_DPM_UVD].smu_feature_id =
 342                         FEATURE_DPM_UVD_BIT;
 343         data->smu_features[GNLD_DPM_VCE].smu_feature_id =
 344                         FEATURE_DPM_VCE_BIT;
 345         data->smu_features[GNLD_ULV].smu_feature_id =
 346                         FEATURE_ULV_BIT;
 347         data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
 348                         FEATURE_DPM_MP0CLK_BIT;
 349         data->smu_features[GNLD_DPM_LINK].smu_feature_id =
 350                         FEATURE_DPM_LINK_BIT;
 351         data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
 352                         FEATURE_DPM_DCEFCLK_BIT;
 353         data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
 354                         FEATURE_DS_GFXCLK_BIT;
 355         data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
 356                         FEATURE_DS_SOCCLK_BIT;
 357         data->smu_features[GNLD_DS_LCLK].smu_feature_id =
 358                         FEATURE_DS_LCLK_BIT;
 359         data->smu_features[GNLD_PPT].smu_feature_id =
 360                         FEATURE_PPT_BIT;
 361         data->smu_features[GNLD_TDC].smu_feature_id =
 362                         FEATURE_TDC_BIT;
 363         data->smu_features[GNLD_THERMAL].smu_feature_id =
 364                         FEATURE_THERMAL_BIT;
 365         data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
 366                         FEATURE_GFX_PER_CU_CG_BIT;
 367         data->smu_features[GNLD_RM].smu_feature_id =
 368                         FEATURE_RM_BIT;
 369         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
 370                         FEATURE_DS_DCEFCLK_BIT;
 371         data->smu_features[GNLD_ACDC].smu_feature_id =
 372                         FEATURE_ACDC_BIT;
 373         data->smu_features[GNLD_VR0HOT].smu_feature_id =
 374                         FEATURE_VR0HOT_BIT;
 375         data->smu_features[GNLD_VR1HOT].smu_feature_id =
 376                         FEATURE_VR1HOT_BIT;
 377         data->smu_features[GNLD_FW_CTF].smu_feature_id =
 378                         FEATURE_FW_CTF_BIT;
 379         data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
 380                         FEATURE_LED_DISPLAY_BIT;
 381         data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
 382                         FEATURE_FAN_CONTROL_BIT;
 383         data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
 384         data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
 385         data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
 386         data->smu_features[GNLD_DPM_FCLK].smu_feature_id = FEATURE_DPM_FCLK_BIT;
 387         data->smu_features[GNLD_DS_FCLK].smu_feature_id = FEATURE_DS_FCLK_BIT;
 388         data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT;
 389         data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT;
 390         data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT;
 391         data->smu_features[GNLD_ECC].smu_feature_id = FEATURE_ECC_BIT;
 392
 393         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 394                 data->smu_features[i].smu_feature_bitmap =
 395                         (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
 396                 data->smu_features[i].allowed =
 397                         ((data->registry_data.disallowed_features >> i) & 1) ?
 398                         false : true;
 399         }
 400
 401         /* Get the SN to turn into a Unique ID */
 402         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
 403         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
 404
 405         adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
 406 }
 407
 408 static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
 409 {
 410         return 0;
 411 }
 412
 413 static int vega20_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 414 {
 415         kfree(hwmgr->backend);
 416         hwmgr->backend = NULL;
 417
 418         return 0;
 419 }
 420
 421 static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 422 {
 423         struct vega20_hwmgr *data;
 424         struct amdgpu_device *adev = hwmgr->adev;
 425
 426         data = kzalloc(sizeof(struct vega20_hwmgr), GFP_KERNEL);
 427         if (data == NULL)
 428                 return -ENOMEM;
 429
 430         hwmgr->backend = data;
 431
 432         hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 433         hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 434         hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 435
 436         vega20_set_default_registry_data(hwmgr);
 437
 438         data->disable_dpm_mask = 0xff;
 439
 440         /* need to set voltage control types before EVV patching */
 441         data->vddc_control = VEGA20_VOLTAGE_CONTROL_NONE;
 442         data->mvdd_control = VEGA20_VOLTAGE_CONTROL_NONE;
 443         data->vddci_control = VEGA20_VOLTAGE_CONTROL_NONE;
 444
 445         data->water_marks_bitmap = 0;
 446         data->avfs_exist = false;
 447
 448         vega20_set_features_platform_caps(hwmgr);
 449
 450         vega20_init_dpm_defaults(hwmgr);
 451
 452         /* Parse pptable data read from VBIOS */
 453         vega20_set_private_data_based_on_pptable(hwmgr);
 454
 455         data->is_tlu_enabled = false;
 456
 457         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 458                         VEGA20_MAX_HARDWARE_POWERLEVELS;
 459         hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
 460         hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 461
 462         hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
 463         /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
 464         hwmgr->platform_descriptor.clockStep.engineClock = 500;
 465         hwmgr->platform_descriptor.clockStep.memoryClock = 500;
 466
 467         data->total_active_cus = adev->gfx.cu_info.number;
 468         data->is_custom_profile_set = false;
 469
 470         return 0;
 471 }
 472
 473 static int vega20_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 474 {
 475         struct vega20_hwmgr *data =
 476                         (struct vega20_hwmgr *)(hwmgr->backend);
 477
 478         data->low_sclk_interrupt_threshold = 0;
 479
 480         return 0;
 481 }
 482
 483 static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
 484 {
 485         struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
 486         int ret = 0;
 487         bool use_baco = (adev->in_gpu_reset &&
 488                          (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
 489                 (adev->in_runpm && amdgpu_asic_supports_baco(adev));
 490
 491         ret = vega20_init_sclk_threshold(hwmgr);
 492         PP_ASSERT_WITH_CODE(!ret,
 493                         "Failed to init sclk threshold!",
 494                         return ret);
 495
 496         if (use_baco) {
 497                 ret = vega20_baco_apply_vdci_flush_workaround(hwmgr);
 498                 if (ret)
 499                         pr_err("Failed to apply vega20 baco workaround!\n");
 500         }
 501
 502         return ret;
 503 }
 504
 505 /*
 506  * @fn vega20_init_dpm_state
 507  * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
 508  *
 509  * @param    dpm_state - the address of the DPM Table to initiailize.
 510  * @return   None.
 511  */
 512 static void vega20_init_dpm_state(struct vega20_dpm_state *dpm_state)
 513 {
 514         dpm_state->soft_min_level = 0x0;
 515         dpm_state->soft_max_level = VG20_CLOCK_MAX_DEFAULT;
 516         dpm_state->hard_min_level = 0x0;
 517         dpm_state->hard_max_level = VG20_CLOCK_MAX_DEFAULT;
 518 }
 519
 520 static int vega20_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
 521                 PPCLK_e clk_id, uint32_t *num_of_levels)
 522 {
 523         int ret = 0;
 524
 525         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 526                         PPSMC_MSG_GetDpmFreqByIndex,
 527                         (clk_id << 16 | 0xFF),
 528                         num_of_levels);
 529         PP_ASSERT_WITH_CODE(!ret,
 530                         "[GetNumOfDpmLevel] failed to get dpm levels!",
 531                         return ret);
 532
 533         return ret;
 534 }
 535
 536 static int vega20_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
 537                 PPCLK_e clk_id, uint32_t index, uint32_t *clk)
 538 {
 539         int ret = 0;
 540
 541         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 542                         PPSMC_MSG_GetDpmFreqByIndex,
 543                         (clk_id << 16 | index),
 544                         clk);
 545         PP_ASSERT_WITH_CODE(!ret,
 546                         "[GetDpmFreqByIndex] failed to get dpm freq by index!",
 547                         return ret);
 548
 549         return ret;
 550 }
 551
 552 static int vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
 553                 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id)
 554 {
 555         int ret = 0;
 556         uint32_t i, num_of_levels, clk;
 557
 558         ret = vega20_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
 559         PP_ASSERT_WITH_CODE(!ret,
 560                         "[SetupSingleDpmTable] failed to get clk levels!",
 561                         return ret);
 562
 563         dpm_table->count = num_of_levels;
 564
 565         for (i = 0; i < num_of_levels; i++) {
 566                 ret = vega20_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
 567                 PP_ASSERT_WITH_CODE(!ret,
 568                         "[SetupSingleDpmTable] failed to get clk of specific level!",
 569                         return ret);
 570                 dpm_table->dpm_levels[i].value = clk;
 571                 dpm_table->dpm_levels[i].enabled = true;
 572         }
 573
 574         return ret;
 575 }
 576
 577 static int vega20_setup_gfxclk_dpm_table(struct pp_hwmgr *hwmgr)
 578 {
 579         struct vega20_hwmgr *data =
 580                         (struct vega20_hwmgr *)(hwmgr->backend);
 581         struct vega20_single_dpm_table *dpm_table;
 582         int ret = 0;
 583
 584         dpm_table = &(data->dpm_table.gfx_table);
 585         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
 586                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
 587                 PP_ASSERT_WITH_CODE(!ret,
 588                                 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
 589                                 return ret);
 590         } else {
 591                 dpm_table->count = 1;
 592                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
 593         }
 594
 595         return ret;
 596 }
 597
 598 static int vega20_setup_memclk_dpm_table(struct pp_hwmgr *hwmgr)
 599 {
 600         struct vega20_hwmgr *data =
 601                         (struct vega20_hwmgr *)(hwmgr->backend);
 602         struct vega20_single_dpm_table *dpm_table;
 603         int ret = 0;
 604
 605         dpm_table = &(data->dpm_table.mem_table);
 606         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
 607                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
 608                 PP_ASSERT_WITH_CODE(!ret,
 609                                 "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
 610                                 return ret);
 611         } else {
 612                 dpm_table->count = 1;
 613                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
 614         }
 615
 616         return ret;
 617 }
 618
 619 /*
 620  * This function is to initialize all DPM state tables
 621  * for SMU based on the dependency table.
 622  * Dynamic state patching function will then trim these
 623  * state tables to the allowed range based
 624  * on the power policy or external client requests,
 625  * such as UVD request, etc.
 626  */
 627 static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 628 {
 629         struct vega20_hwmgr *data =
 630                         (struct vega20_hwmgr *)(hwmgr->backend);
 631         struct vega20_single_dpm_table *dpm_table;
 632         int ret = 0;
 633
 634         memset(&data->dpm_table, 0, sizeof(data->dpm_table));
 635
 636         /* socclk */
 637         dpm_table = &(data->dpm_table.soc_table);
 638         if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
 639                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
 640                 PP_ASSERT_WITH_CODE(!ret,
 641                                 "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
 642                                 return ret);
 643         } else {
 644                 dpm_table->count = 1;
 645                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
 646         }
 647         vega20_init_dpm_state(&(dpm_table->dpm_state));
 648
 649         /* gfxclk */
 650         dpm_table = &(data->dpm_table.gfx_table);
 651         ret = vega20_setup_gfxclk_dpm_table(hwmgr);
 652         if (ret)
 653                 return ret;
 654         vega20_init_dpm_state(&(dpm_table->dpm_state));
 655
 656         /* memclk */
 657         dpm_table = &(data->dpm_table.mem_table);
 658         ret = vega20_setup_memclk_dpm_table(hwmgr);
 659         if (ret)
 660                 return ret;
 661         vega20_init_dpm_state(&(dpm_table->dpm_state));
 662
 663         /* eclk */
 664         dpm_table = &(data->dpm_table.eclk_table);
 665         if (data->smu_features[GNLD_DPM_VCE].enabled) {
 666                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
 667                 PP_ASSERT_WITH_CODE(!ret,
 668                                 "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
 669                                 return ret);
 670         } else {
 671                 dpm_table->count = 1;
 672                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
 673         }
 674         vega20_init_dpm_state(&(dpm_table->dpm_state));
 675
 676         /* vclk */
 677         dpm_table = &(data->dpm_table.vclk_table);
 678         if (data->smu_features[GNLD_DPM_UVD].enabled) {
 679                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
 680                 PP_ASSERT_WITH_CODE(!ret,
 681                                 "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
 682                                 return ret);
 683         } else {
 684                 dpm_table->count = 1;
 685                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
 686         }
 687         vega20_init_dpm_state(&(dpm_table->dpm_state));
 688
 689         /* dclk */
 690         dpm_table = &(data->dpm_table.dclk_table);
 691         if (data->smu_features[GNLD_DPM_UVD].enabled) {
 692                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
 693                 PP_ASSERT_WITH_CODE(!ret,
 694                                 "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
 695                                 return ret);
 696         } else {
 697                 dpm_table->count = 1;
 698                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
 699         }
 700         vega20_init_dpm_state(&(dpm_table->dpm_state));
 701
 702         /* dcefclk */
 703         dpm_table = &(data->dpm_table.dcef_table);
 704         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 705                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
 706                 PP_ASSERT_WITH_CODE(!ret,
 707                                 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
 708                                 return ret);
 709         } else {
 710                 dpm_table->count = 1;
 711                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
 712         }
 713         vega20_init_dpm_state(&(dpm_table->dpm_state));
 714
 715         /* pixclk */
 716         dpm_table = &(data->dpm_table.pixel_table);
 717         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 718                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
 719                 PP_ASSERT_WITH_CODE(!ret,
 720                                 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
 721                                 return ret);
 722         } else
 723                 dpm_table->count = 0;
 724         vega20_init_dpm_state(&(dpm_table->dpm_state));
 725
 726         /* dispclk */
 727         dpm_table = &(data->dpm_table.display_table);
 728         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 729                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
 730                 PP_ASSERT_WITH_CODE(!ret,
 731                                 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
 732                                 return ret);
 733         } else
 734                 dpm_table->count = 0;
 735         vega20_init_dpm_state(&(dpm_table->dpm_state));
 736
 737         /* phyclk */
 738         dpm_table = &(data->dpm_table.phy_table);
 739         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 740                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
 741                 PP_ASSERT_WITH_CODE(!ret,
 742                                 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
 743                                 return ret);
 744         } else
 745                 dpm_table->count = 0;
 746         vega20_init_dpm_state(&(dpm_table->dpm_state));
 747
 748         /* fclk */
 749         dpm_table = &(data->dpm_table.fclk_table);
 750         if (data->smu_features[GNLD_DPM_FCLK].enabled) {
 751                 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_FCLK);
 752                 PP_ASSERT_WITH_CODE(!ret,
 753                                 "[SetupDefaultDpmTable] failed to get fclk dpm levels!",
 754                                 return ret);
 755         } else {
 756                 dpm_table->count = 1;
 757                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.fclock / 100;
 758         }
 759         vega20_init_dpm_state(&(dpm_table->dpm_state));
 760
 761         /* save a copy of the default DPM table */
 762         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 763                         sizeof(struct vega20_dpm_table));
 764
 765         return 0;
 766 }
 767
 768 /**
 769 * Initializes the SMC table and uploads it
 770 *
 771 * @param    hwmgr  the address of the powerplay hardware manager.
 772 * @param    pInput  the pointer to input data (PowerState)
 773 * @return   always 0
 774 */
 775 static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
 776 {
 777         int result;
 778         struct vega20_hwmgr *data =
 779                         (struct vega20_hwmgr *)(hwmgr->backend);
 780         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
 781         struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
 782         struct phm_ppt_v3_information *pptable_information =
 783                 (struct phm_ppt_v3_information *)hwmgr->pptable;
 784
 785         result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
 786         PP_ASSERT_WITH_CODE(!result,
 787                         "[InitSMCTable] Failed to get vbios bootup values!",
 788                         return result);
 789
 790         data->vbios_boot_state.vddc     = boot_up_values.usVddc;
 791         data->vbios_boot_state.vddci    = boot_up_values.usVddci;
 792         data->vbios_boot_state.mvddc    = boot_up_values.usMvddc;
 793         data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
 794         data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
 795         data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
 796         data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
 797         data->vbios_boot_state.eclock = boot_up_values.ulEClk;
 798         data->vbios_boot_state.vclock = boot_up_values.ulVClk;
 799         data->vbios_boot_state.dclock = boot_up_values.ulDClk;
 800         data->vbios_boot_state.fclock = boot_up_values.ulFClk;
 801         data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
 802
 803         smum_send_msg_to_smc_with_parameter(hwmgr,
 804                         PPSMC_MSG_SetMinDeepSleepDcefclk,
 805                 (uint32_t)(data->vbios_boot_state.dcef_clock / 100),
 806                         NULL);
 807
 808         memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
 809
 810         result = smum_smc_table_manager(hwmgr,
 811                                         (uint8_t *)pp_table, TABLE_PPTABLE, false);
 812         PP_ASSERT_WITH_CODE(!result,
 813                         "[InitSMCTable] Failed to upload PPtable!",
 814                         return result);
 815
 816         return 0;
 817 }
 818
 819 /*
 820  * Override PCIe link speed and link width for DPM Level 1. PPTable entries
 821  * reflect the ASIC capabilities and not the system capabilities. For e.g.
 822  * Vega20 board in a PCI Gen3 system. In this case, when SMU's tries to switch
 823  * to DPM1, it fails as system doesn't support Gen4.
 824  */
 825 static int vega20_override_pcie_parameters(struct pp_hwmgr *hwmgr)
 826 {
 827         struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
 828         struct vega20_hwmgr *data =
 829                         (struct vega20_hwmgr *)(hwmgr->backend);
 830         uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
 831         int ret;
 832
 833         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
 834                 pcie_gen = 3;
 835         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 836                 pcie_gen = 2;
 837         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
 838                 pcie_gen = 1;
 839         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
 840                 pcie_gen = 0;
 841
 842         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
 843                 pcie_width = 6;
 844         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
 845                 pcie_width = 5;
 846         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
 847                 pcie_width = 4;
 848         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
 849                 pcie_width = 3;
 850         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
 851                 pcie_width = 2;
 852         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
 853                 pcie_width = 1;
 854
 855         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
 856          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
 857          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
 858          */
 859         smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
 860         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 861                         PPSMC_MSG_OverridePcieParameters, smu_pcie_arg,
 862                         NULL);
 863         PP_ASSERT_WITH_CODE(!ret,
 864                 "[OverridePcieParameters] Attempt to override pcie params failed!",
 865                 return ret);
 866
 867         data->pcie_parameters_override = true;
 868         data->pcie_gen_level1 = pcie_gen;
 869         data->pcie_width_level1 = pcie_width;
 870
 871         return 0;
 872 }
 873
 874 static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
 875 {
 876         struct vega20_hwmgr *data =
 877                         (struct vega20_hwmgr *)(hwmgr->backend);
 878         uint32_t allowed_features_low = 0, allowed_features_high = 0;
 879         int i;
 880         int ret = 0;
 881
 882         for (i = 0; i < GNLD_FEATURES_MAX; i++)
 883                 if (data->smu_features[i].allowed)
 884                         data->smu_features[i].smu_feature_id > 31 ?
 885                                 (allowed_features_high |=
 886                                  ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT)
 887                                   & 0xFFFFFFFF)) :
 888                                 (allowed_features_low |=
 889                                  ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT)
 890                                   & 0xFFFFFFFF));
 891
 892         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 893                 PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high, NULL);
 894         PP_ASSERT_WITH_CODE(!ret,
 895                 "[SetAllowedFeaturesMask] Attempt to set allowed features mask(high) failed!",
 896                 return ret);
 897
 898         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 899                 PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low, NULL);
 900         PP_ASSERT_WITH_CODE(!ret,
 901                 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
 902                 return ret);
 903
 904         return 0;
 905 }
 906
 907 static int vega20_run_btc(struct pp_hwmgr *hwmgr)
 908 {
 909         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunBtc, NULL);
 910 }
 911
 912 static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr)
 913 {
 914         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAfllBtc, NULL);
 915 }
 916
 917 static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
 918 {
 919         struct vega20_hwmgr *data =
 920                         (struct vega20_hwmgr *)(hwmgr->backend);
 921         uint64_t features_enabled;
 922         int i;
 923         bool enabled;
 924         int ret = 0;
 925
 926         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
 927                         PPSMC_MSG_EnableAllSmuFeatures,
 928                         NULL)) == 0,
 929                         "[EnableAllSMUFeatures] Failed to enable all smu features!",
 930                         return ret);
 931
 932         ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
 933         PP_ASSERT_WITH_CODE(!ret,
 934                         "[EnableAllSmuFeatures] Failed to get enabled smc features!",
 935                         return ret);
 936
 937         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 938                 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
 939                         true : false;
 940                 data->smu_features[i].enabled = enabled;
 941                 data->smu_features[i].supported = enabled;
 942
 943 #if 0
 944                 if (data->smu_features[i].allowed && !enabled)
 945                         pr_info("[EnableAllSMUFeatures] feature %d is expected enabled!", i);
 946                 else if (!data->smu_features[i].allowed && enabled)
 947                         pr_info("[EnableAllSMUFeatures] feature %d is expected disabled!", i);
 948 #endif
 949         }
 950
 951         return 0;
 952 }
 953
 954 static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr)
 955 {
 956         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
 957
 958         if (data->smu_features[GNLD_DPM_UCLK].enabled)
 959                 return smum_send_msg_to_smc_with_parameter(hwmgr,
 960                         PPSMC_MSG_SetUclkFastSwitch,
 961                         1,
 962                         NULL);
 963
 964         return 0;
 965 }
 966
 967 static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
 968 {
 969         struct vega20_hwmgr *data =
 970                         (struct vega20_hwmgr *)(hwmgr->backend);
 971
 972         return smum_send_msg_to_smc_with_parameter(hwmgr,
 973                         PPSMC_MSG_SetFclkGfxClkRatio,
 974                         data->registry_data.fclk_gfxclk_ratio,
 975                         NULL);
 976 }
 977
 978 static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)
 979 {
 980         struct vega20_hwmgr *data =
 981                         (struct vega20_hwmgr *)(hwmgr->backend);
 982         int i, ret = 0;
 983
 984         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
 985                         PPSMC_MSG_DisableAllSmuFeatures,
 986                         NULL)) == 0,
 987                         "[DisableAllSMUFeatures] Failed to disable all smu features!",
 988                         return ret);
 989
 990         for (i = 0; i < GNLD_FEATURES_MAX; i++)
 991                 data->smu_features[i].enabled = 0;
 992
 993         return 0;
 994 }
 995
 996 static int vega20_od8_set_feature_capabilities(
 997                 struct pp_hwmgr *hwmgr)
 998 {
 999         struct phm_ppt_v3_information *pptable_information =
1000                 (struct phm_ppt_v3_information *)hwmgr->pptable;
1001         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1002         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1003         struct vega20_od8_settings *od_settings = &(data->od8_settings);
1004
1005         od_settings->overdrive8_capabilities = 0;
1006
1007         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1008                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
1009                     pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
1010                     pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
1011                     (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
1012                     pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN]))
1013                         od_settings->overdrive8_capabilities |= OD8_GFXCLK_LIMITS;
1014
1015                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
1016                     (pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
1017                      pp_table->MinVoltageGfx / VOLTAGE_SCALE) &&
1018                     (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
1019                      pp_table->MaxVoltageGfx / VOLTAGE_SCALE) &&
1020                     (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] >=
1021                      pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1]))
1022                         od_settings->overdrive8_capabilities |= OD8_GFXCLK_CURVE;
1023         }
1024
1025         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1026                 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] =
1027                         data->dpm_table.mem_table.dpm_levels[data->dpm_table.mem_table.count - 2].value;
1028                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
1029                     pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
1030                     pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
1031                     (pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
1032                     pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX]))
1033                         od_settings->overdrive8_capabilities |= OD8_UCLK_MAX;
1034         }
1035
1036         if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
1037             pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1038             pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
1039             pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
1040             pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100)
1041                 od_settings->overdrive8_capabilities |= OD8_POWER_LIMIT;
1042
1043         if (data->smu_features[GNLD_FAN_CONTROL].enabled) {
1044                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
1045                     pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1046                     pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
1047                     (pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
1048                      pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT]))
1049                         od_settings->overdrive8_capabilities |= OD8_ACOUSTIC_LIMIT_SCLK;
1050
1051                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
1052                     (pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] >=
1053                     (pp_table->FanPwmMin * pp_table->FanMaximumRpm / 100)) &&
1054                     pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
1055                     (pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
1056                      pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED]))
1057                         od_settings->overdrive8_capabilities |= OD8_FAN_SPEED_MIN;
1058         }
1059
1060         if (data->smu_features[GNLD_THERMAL].enabled) {
1061                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
1062                     pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1063                     pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
1064                     (pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
1065                      pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP]))
1066                         od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_FAN;
1067
1068                 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
1069                     pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1070                     pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
1071                     (pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
1072                      pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX]))
1073                         od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_SYSTEM;
1074         }
1075
1076         if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE])
1077                 od_settings->overdrive8_capabilities |= OD8_MEMORY_TIMING_TUNE;
1078
1079         if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL] &&
1080             pp_table->FanZeroRpmEnable)
1081                 od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL;
1082
1083         if (!od_settings->overdrive8_capabilities)
1084                 hwmgr->od_enabled = false;
1085
1086         return 0;
1087 }
1088
1089 static int vega20_od8_set_feature_id(
1090                 struct pp_hwmgr *hwmgr)
1091 {
1092         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1093         struct vega20_od8_settings *od_settings = &(data->od8_settings);
1094
1095         if (od_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1096                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1097                         OD8_GFXCLK_LIMITS;
1098                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1099                         OD8_GFXCLK_LIMITS;
1100         } else {
1101                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
1102                         0;
1103                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1104                         0;
1105         }
1106
1107         if (od_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1108                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1109                         OD8_GFXCLK_CURVE;
1110                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1111                         OD8_GFXCLK_CURVE;
1112                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1113                         OD8_GFXCLK_CURVE;
1114                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1115                         OD8_GFXCLK_CURVE;
1116                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1117                         OD8_GFXCLK_CURVE;
1118                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1119                         OD8_GFXCLK_CURVE;
1120         } else {
1121                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1122                         0;
1123                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1124                         0;
1125                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1126                         0;
1127                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1128                         0;
1129                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1130                         0;
1131                 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1132                         0;
1133         }
1134
1135         if (od_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1136                 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = OD8_UCLK_MAX;
1137         else
1138                 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = 0;
1139
1140         if (od_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1141                 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = OD8_POWER_LIMIT;
1142         else
1143                 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = 0;
1144
1145         if (od_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1146                 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1147                         OD8_ACOUSTIC_LIMIT_SCLK;
1148         else
1149                 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1150                         0;
1151
1152         if (od_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1153                 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1154                         OD8_FAN_SPEED_MIN;
1155         else
1156                 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1157                         0;
1158
1159         if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1160                 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1161                         OD8_TEMPERATURE_FAN;
1162         else
1163                 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1164                         0;
1165
1166         if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1167                 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1168                         OD8_TEMPERATURE_SYSTEM;
1169         else
1170                 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1171                         0;
1172
1173         return 0;
1174 }
1175
1176 static int vega20_od8_get_gfx_clock_base_voltage(
1177                 struct pp_hwmgr *hwmgr,
1178                 uint32_t *voltage,
1179                 uint32_t freq)
1180 {
1181         int ret = 0;
1182
1183         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1184                         PPSMC_MSG_GetAVFSVoltageByDpm,
1185                         ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq),
1186                         voltage);
1187         PP_ASSERT_WITH_CODE(!ret,
1188                         "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!",
1189                         return ret);
1190
1191         *voltage = *voltage / VOLTAGE_SCALE;
1192
1193         return 0;
1194 }
1195
1196 static int vega20_od8_initialize_default_settings(
1197                 struct pp_hwmgr *hwmgr)
1198 {
1199         struct phm_ppt_v3_information *pptable_information =
1200                 (struct phm_ppt_v3_information *)hwmgr->pptable;
1201         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1202         struct vega20_od8_settings *od8_settings = &(data->od8_settings);
1203         OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table);
1204         int i, ret = 0;
1205
1206         /* Set Feature Capabilities */
1207         vega20_od8_set_feature_capabilities(hwmgr);
1208
1209         /* Map FeatureID to individual settings */
1210         vega20_od8_set_feature_id(hwmgr);
1211
1212         /* Set default values */
1213         ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true);
1214         PP_ASSERT_WITH_CODE(!ret,
1215                         "Failed to export over drive table!",
1216                         return ret);
1217
1218         if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1219                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1220                         od_table->GfxclkFmin;
1221                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1222                         od_table->GfxclkFmax;
1223         } else {
1224                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1225                         0;
1226                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1227                         0;
1228         }
1229
1230         if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1231                 od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1232                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1233                         od_table->GfxclkFreq1;
1234
1235                 od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1236                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1237                         od_table->GfxclkFreq3;
1238
1239                 od_table->GfxclkFreq2 = (od_table->GfxclkFreq1 + od_table->GfxclkFreq3) / 2;
1240                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1241                         od_table->GfxclkFreq2;
1242
1243                 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1244                                    &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value),
1245                                      od_table->GfxclkFreq1),
1246                                 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1247                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0);
1248                 od_table->GfxclkVolt1 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1249                         * VOLTAGE_SCALE;
1250
1251                 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1252                                    &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value),
1253                                      od_table->GfxclkFreq2),
1254                                 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1255                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0);
1256                 od_table->GfxclkVolt2 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1257                         * VOLTAGE_SCALE;
1258
1259                 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1260                                    &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value),
1261                                      od_table->GfxclkFreq3),
1262                                 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1263                                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0);
1264                 od_table->GfxclkVolt3 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1265                         * VOLTAGE_SCALE;
1266         } else {
1267                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1268                         0;
1269                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value =
1270                         0;
1271                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1272                         0;
1273                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value =
1274                         0;
1275                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1276                         0;
1277                 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value =
1278                         0;
1279         }
1280
1281         if (od8_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1282                 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1283                         od_table->UclkFmax;
1284         else
1285                 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1286                         0;
1287
1288         if (od8_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1289                 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1290                         od_table->OverDrivePct;
1291         else
1292                 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1293                         0;
1294
1295         if (od8_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1296                 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1297                         od_table->FanMaximumRpm;
1298         else
1299                 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1300                         0;
1301
1302         if (od8_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1303                 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1304                         od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100;
1305         else
1306                 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1307                         0;
1308
1309         if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1310                 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1311                         od_table->FanTargetTemperature;
1312         else
1313                 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1314                         0;
1315
1316         if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1317                 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1318                         od_table->MaxOpTemp;
1319         else
1320                 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1321                         0;
1322
1323         for (i = 0; i < OD8_SETTING_COUNT; i++) {
1324                 if (od8_settings->od8_settings_array[i].feature_id) {
1325                         od8_settings->od8_settings_array[i].min_value =
1326                                 pptable_information->od_settings_min[i];
1327                         od8_settings->od8_settings_array[i].max_value =
1328                                 pptable_information->od_settings_max[i];
1329                         od8_settings->od8_settings_array[i].current_value =
1330                                 od8_settings->od8_settings_array[i].default_value;
1331                 } else {
1332                         od8_settings->od8_settings_array[i].min_value =
1333                                 0;
1334                         od8_settings->od8_settings_array[i].max_value =
1335                                 0;
1336                         od8_settings->od8_settings_array[i].current_value =
1337                                 0;
1338                 }
1339         }
1340
1341         ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false);
1342         PP_ASSERT_WITH_CODE(!ret,
1343                         "Failed to import over drive table!",
1344                         return ret);
1345
1346         return 0;
1347 }
1348
1349 static int vega20_od8_set_settings(
1350                 struct pp_hwmgr *hwmgr,
1351                 uint32_t index,
1352                 uint32_t value)
1353 {
1354         OverDriveTable_t od_table;
1355         int ret = 0;
1356         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1357         struct vega20_od8_single_setting *od8_settings =
1358                         data->od8_settings.od8_settings_array;
1359
1360         ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true);
1361         PP_ASSERT_WITH_CODE(!ret,
1362                         "Failed to export over drive table!",
1363                         return ret);
1364
1365         switch(index) {
1366         case OD8_SETTING_GFXCLK_FMIN:
1367                 od_table.GfxclkFmin = (uint16_t)value;
1368                 break;
1369         case OD8_SETTING_GFXCLK_FMAX:
1370                 if (value < od8_settings[OD8_SETTING_GFXCLK_FMAX].min_value ||
1371                     value > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value)
1372                         return -EINVAL;
1373
1374                 od_table.GfxclkFmax = (uint16_t)value;
1375                 break;
1376         case OD8_SETTING_GFXCLK_FREQ1:
1377                 od_table.GfxclkFreq1 = (uint16_t)value;
1378                 break;
1379         case OD8_SETTING_GFXCLK_VOLTAGE1:
1380                 od_table.GfxclkVolt1 = (uint16_t)value;
1381                 break;
1382         case OD8_SETTING_GFXCLK_FREQ2:
1383                 od_table.GfxclkFreq2 = (uint16_t)value;
1384                 break;
1385         case OD8_SETTING_GFXCLK_VOLTAGE2:
1386                 od_table.GfxclkVolt2 = (uint16_t)value;
1387                 break;
1388         case OD8_SETTING_GFXCLK_FREQ3:
1389                 od_table.GfxclkFreq3 = (uint16_t)value;
1390                 break;
1391         case OD8_SETTING_GFXCLK_VOLTAGE3:
1392                 od_table.GfxclkVolt3 = (uint16_t)value;
1393                 break;
1394         case OD8_SETTING_UCLK_FMAX:
1395                 if (value < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
1396                     value > od8_settings[OD8_SETTING_UCLK_FMAX].max_value)
1397                         return -EINVAL;
1398                 od_table.UclkFmax = (uint16_t)value;
1399                 break;
1400         case OD8_SETTING_POWER_PERCENTAGE:
1401                 od_table.OverDrivePct = (int16_t)value;
1402                 break;
1403         case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
1404                 od_table.FanMaximumRpm = (uint16_t)value;
1405                 break;
1406         case OD8_SETTING_FAN_MIN_SPEED:
1407                 od_table.FanMinimumPwm = (uint16_t)value;
1408                 break;
1409         case OD8_SETTING_FAN_TARGET_TEMP:
1410                 od_table.FanTargetTemperature = (uint16_t)value;
1411                 break;
1412         case OD8_SETTING_OPERATING_TEMP_MAX:
1413                 od_table.MaxOpTemp = (uint16_t)value;
1414                 break;
1415         }
1416
1417         ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false);
1418         PP_ASSERT_WITH_CODE(!ret,
1419                         "Failed to import over drive table!",
1420                         return ret);
1421
1422         return 0;
1423 }
1424
1425 static int vega20_get_sclk_od(
1426                 struct pp_hwmgr *hwmgr)
1427 {
1428         struct vega20_hwmgr *data = hwmgr->backend;
1429         struct vega20_single_dpm_table *sclk_table =
1430                         &(data->dpm_table.gfx_table);
1431         struct vega20_single_dpm_table *golden_sclk_table =
1432                         &(data->golden_dpm_table.gfx_table);
1433         int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
1434         int golden_value = golden_sclk_table->dpm_levels
1435                         [golden_sclk_table->count - 1].value;
1436
1437         /* od percentage */
1438         value -= golden_value;
1439         value = DIV_ROUND_UP(value * 100, golden_value);
1440
1441         return value;
1442 }
1443
1444 static int vega20_set_sclk_od(
1445                 struct pp_hwmgr *hwmgr, uint32_t value)
1446 {
1447         struct vega20_hwmgr *data = hwmgr->backend;
1448         struct vega20_single_dpm_table *golden_sclk_table =
1449                         &(data->golden_dpm_table.gfx_table);
1450         uint32_t od_sclk;
1451         int ret = 0;
1452
1453         od_sclk = golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value;
1454         od_sclk /= 100;
1455         od_sclk += golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
1456
1457         ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk);
1458         PP_ASSERT_WITH_CODE(!ret,
1459                         "[SetSclkOD] failed to set od gfxclk!",
1460                         return ret);
1461
1462         /* retrieve updated gfxclk table */
1463         ret = vega20_setup_gfxclk_dpm_table(hwmgr);
1464         PP_ASSERT_WITH_CODE(!ret,
1465                         "[SetSclkOD] failed to refresh gfxclk table!",
1466                         return ret);
1467
1468         return 0;
1469 }
1470
1471 static int vega20_get_mclk_od(
1472                 struct pp_hwmgr *hwmgr)
1473 {
1474         struct vega20_hwmgr *data = hwmgr->backend;
1475         struct vega20_single_dpm_table *mclk_table =
1476                         &(data->dpm_table.mem_table);
1477         struct vega20_single_dpm_table *golden_mclk_table =
1478                         &(data->golden_dpm_table.mem_table);
1479         int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
1480         int golden_value = golden_mclk_table->dpm_levels
1481                         [golden_mclk_table->count - 1].value;
1482
1483         /* od percentage */
1484         value -= golden_value;
1485         value = DIV_ROUND_UP(value * 100, golden_value);
1486
1487         return value;
1488 }
1489
1490 static int vega20_set_mclk_od(
1491                 struct pp_hwmgr *hwmgr, uint32_t value)
1492 {
1493         struct vega20_hwmgr *data = hwmgr->backend;
1494         struct vega20_single_dpm_table *golden_mclk_table =
1495                         &(data->golden_dpm_table.mem_table);
1496         uint32_t od_mclk;
1497         int ret = 0;
1498
1499         od_mclk = golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * value;
1500         od_mclk /= 100;
1501         od_mclk += golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
1502
1503         ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk);
1504         PP_ASSERT_WITH_CODE(!ret,
1505                         "[SetMclkOD] failed to set od memclk!",
1506                         return ret);
1507
1508         /* retrieve updated memclk table */
1509         ret = vega20_setup_memclk_dpm_table(hwmgr);
1510         PP_ASSERT_WITH_CODE(!ret,
1511                         "[SetMclkOD] failed to refresh memclk table!",
1512                         return ret);
1513
1514         return 0;
1515 }
1516
1517 static int vega20_populate_umdpstate_clocks(
1518                 struct pp_hwmgr *hwmgr)
1519 {
1520         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1521         struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table);
1522         struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table);
1523
1524         hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value;
1525         hwmgr->pstate_mclk = mem_table->dpm_levels[0].value;
1526
1527         if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1528             mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
1529                 hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
1530                 hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
1531         }
1532
1533         hwmgr->pstate_sclk = hwmgr->pstate_sclk * 100;
1534         hwmgr->pstate_mclk = hwmgr->pstate_mclk * 100;
1535
1536         return 0;
1537 }
1538
1539 static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr,
1540                 PP_Clock *clock, PPCLK_e clock_select)
1541 {
1542         int ret = 0;
1543
1544         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1545                         PPSMC_MSG_GetDcModeMaxDpmFreq,
1546                         (clock_select << 16),
1547                         clock)) == 0,
1548                         "[GetMaxSustainableClock] Failed to get max DC clock from SMC!",
1549                         return ret);
1550
1551         /* if DC limit is zero, return AC limit */
1552         if (*clock == 0) {
1553                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1554                         PPSMC_MSG_GetMaxDpmFreq,
1555                         (clock_select << 16),
1556                         clock)) == 0,
1557                         "[GetMaxSustainableClock] failed to get max AC clock from SMC!",
1558                         return ret);
1559         }
1560
1561         return 0;
1562 }
1563
1564 static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr)
1565 {
1566         struct vega20_hwmgr *data =
1567                 (struct vega20_hwmgr *)(hwmgr->backend);
1568         struct vega20_max_sustainable_clocks *max_sustainable_clocks =
1569                 &(data->max_sustainable_clocks);
1570         int ret = 0;
1571
1572         max_sustainable_clocks->uclock = data->vbios_boot_state.mem_clock / 100;
1573         max_sustainable_clocks->soc_clock = data->vbios_boot_state.soc_clock / 100;
1574         max_sustainable_clocks->dcef_clock = data->vbios_boot_state.dcef_clock / 100;
1575         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
1576         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
1577         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
1578
1579         if (data->smu_features[GNLD_DPM_UCLK].enabled)
1580                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1581                                 &(max_sustainable_clocks->uclock),
1582                                 PPCLK_UCLK)) == 0,
1583                                 "[InitMaxSustainableClocks] failed to get max UCLK from SMC!",
1584                                 return ret);
1585
1586         if (data->smu_features[GNLD_DPM_SOCCLK].enabled)
1587                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1588                                 &(max_sustainable_clocks->soc_clock),
1589                                 PPCLK_SOCCLK)) == 0,
1590                                 "[InitMaxSustainableClocks] failed to get max SOCCLK from SMC!",
1591                                 return ret);
1592
1593         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1594                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1595                                 &(max_sustainable_clocks->dcef_clock),
1596                                 PPCLK_DCEFCLK)) == 0,
1597                                 "[InitMaxSustainableClocks] failed to get max DCEFCLK from SMC!",
1598                                 return ret);
1599                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1600                                 &(max_sustainable_clocks->display_clock),
1601                                 PPCLK_DISPCLK)) == 0,
1602                                 "[InitMaxSustainableClocks] failed to get max DISPCLK from SMC!",
1603                                 return ret);
1604                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1605                                 &(max_sustainable_clocks->phy_clock),
1606                                 PPCLK_PHYCLK)) == 0,
1607                                 "[InitMaxSustainableClocks] failed to get max PHYCLK from SMC!",
1608                                 return ret);
1609                 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1610                                 &(max_sustainable_clocks->pixel_clock),
1611                                 PPCLK_PIXCLK)) == 0,
1612                                 "[InitMaxSustainableClocks] failed to get max PIXCLK from SMC!",
1613                                 return ret);
1614         }
1615
1616         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1617                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1618
1619         return 0;
1620 }
1621
1622 static int vega20_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
1623 {
1624         int result;
1625
1626         result = smum_send_msg_to_smc(hwmgr,
1627                 PPSMC_MSG_SetMGpuFanBoostLimitRpm,
1628                 NULL);
1629         PP_ASSERT_WITH_CODE(!result,
1630                         "[EnableMgpuFan] Failed to enable mgpu fan boost!",
1631                         return result);
1632
1633         return 0;
1634 }
1635
1636 static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)
1637 {
1638         struct vega20_hwmgr *data =
1639                 (struct vega20_hwmgr *)(hwmgr->backend);
1640
1641         data->uvd_power_gated = true;
1642         data->vce_power_gated = true;
1643
1644         if (data->smu_features[GNLD_DPM_UVD].enabled)
1645                 data->uvd_power_gated = false;
1646
1647         if (data->smu_features[GNLD_DPM_VCE].enabled)
1648                 data->vce_power_gated = false;
1649 }
1650
1651 static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1652 {
1653         int result = 0;
1654
1655         smum_send_msg_to_smc_with_parameter(hwmgr,
1656                         PPSMC_MSG_NumOfDisplays, 0, NULL);
1657
1658         result = vega20_set_allowed_featuresmask(hwmgr);
1659         PP_ASSERT_WITH_CODE(!result,
1660                         "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
1661                         return result);
1662
1663         result = vega20_init_smc_table(hwmgr);
1664         PP_ASSERT_WITH_CODE(!result,
1665                         "[EnableDPMTasks] Failed to initialize SMC table!",
1666                         return result);
1667
1668         result = vega20_run_btc(hwmgr);
1669         PP_ASSERT_WITH_CODE(!result,
1670                         "[EnableDPMTasks] Failed to run btc!",
1671                         return result);
1672
1673         result = vega20_run_btc_afll(hwmgr);
1674         PP_ASSERT_WITH_CODE(!result,
1675                         "[EnableDPMTasks] Failed to run btc afll!",
1676                         return result);
1677
1678         result = vega20_enable_all_smu_features(hwmgr);
1679         PP_ASSERT_WITH_CODE(!result,
1680                         "[EnableDPMTasks] Failed to enable all smu features!",
1681                         return result);
1682
1683         result = vega20_override_pcie_parameters(hwmgr);
1684         PP_ASSERT_WITH_CODE(!result,
1685                         "[EnableDPMTasks] Failed to override pcie parameters!",
1686                         return result);
1687
1688         result = vega20_notify_smc_display_change(hwmgr);
1689         PP_ASSERT_WITH_CODE(!result,
1690                         "[EnableDPMTasks] Failed to notify smc display change!",
1691                         return result);
1692
1693         result = vega20_send_clock_ratio(hwmgr);
1694         PP_ASSERT_WITH_CODE(!result,
1695                         "[EnableDPMTasks] Failed to send clock ratio!",
1696                         return result);
1697
1698         /* Initialize UVD/VCE powergating state */
1699         vega20_init_powergate_state(hwmgr);
1700
1701         result = vega20_setup_default_dpm_tables(hwmgr);
1702         PP_ASSERT_WITH_CODE(!result,
1703                         "[EnableDPMTasks] Failed to setup default DPM tables!",
1704                         return result);
1705
1706         result = vega20_init_max_sustainable_clocks(hwmgr);
1707         PP_ASSERT_WITH_CODE(!result,
1708                         "[EnableDPMTasks] Failed to get maximum sustainable clocks!",
1709                         return result);
1710
1711         result = vega20_power_control_set_level(hwmgr);
1712         PP_ASSERT_WITH_CODE(!result,
1713                         "[EnableDPMTasks] Failed to power control set level!",
1714                         return result);
1715
1716         result = vega20_od8_initialize_default_settings(hwmgr);
1717         PP_ASSERT_WITH_CODE(!result,
1718                         "[EnableDPMTasks] Failed to initialize odn settings!",
1719                         return result);
1720
1721         result = vega20_populate_umdpstate_clocks(hwmgr);
1722         PP_ASSERT_WITH_CODE(!result,
1723                         "[EnableDPMTasks] Failed to populate umdpstate clocks!",
1724                         return result);
1725
1726         result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit,
1727                         POWER_SOURCE_AC << 16, &hwmgr->default_power_limit);
1728         PP_ASSERT_WITH_CODE(!result,
1729                         "[GetPptLimit] get default PPT limit failed!",
1730                         return result);
1731         hwmgr->power_limit =
1732                 hwmgr->default_power_limit;
1733
1734         return 0;
1735 }
1736
1737 static uint32_t vega20_find_lowest_dpm_level(
1738                 struct vega20_single_dpm_table *table)
1739 {
1740         uint32_t i;
1741
1742         for (i = 0; i < table->count; i++) {
1743                 if (table->dpm_levels[i].enabled)
1744                         break;
1745         }
1746         if (i >= table->count) {
1747                 i = 0;
1748                 table->dpm_levels[i].enabled = true;
1749         }
1750
1751         return i;
1752 }
1753
1754 static uint32_t vega20_find_highest_dpm_level(
1755                 struct vega20_single_dpm_table *table)
1756 {
1757         int i = 0;
1758
1759         PP_ASSERT_WITH_CODE(table != NULL,
1760                         "[FindHighestDPMLevel] DPM Table does not exist!",
1761                         return 0);
1762         PP_ASSERT_WITH_CODE(table->count > 0,
1763                         "[FindHighestDPMLevel] DPM Table has no entry!",
1764                         return 0);
1765         PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1766                         "[FindHighestDPMLevel] DPM Table has too many entries!",
1767                         return MAX_REGULAR_DPM_NUMBER - 1);
1768
1769         for (i = table->count - 1; i >= 0; i--) {
1770                 if (table->dpm_levels[i].enabled)
1771                         break;
1772         }
1773         if (i < 0) {
1774                 i = 0;
1775                 table->dpm_levels[i].enabled = true;
1776         }
1777
1778         return i;
1779 }
1780
1781 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1782 {
1783         struct vega20_hwmgr *data =
1784                         (struct vega20_hwmgr *)(hwmgr->backend);
1785         uint32_t min_freq;
1786         int ret = 0;
1787
1788         if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1789            (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1790                 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1791                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1792                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1793                                         (PPCLK_GFXCLK << 16) | (min_freq & 0xffff),
1794                                         NULL)),
1795                                         "Failed to set soft min gfxclk !",
1796                                         return ret);
1797         }
1798
1799         if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1800            (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1801                 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1802                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1803                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1804                                         (PPCLK_UCLK << 16) | (min_freq & 0xffff),
1805                                         NULL)),
1806                                         "Failed to set soft min memclk !",
1807                                         return ret);
1808         }
1809
1810         if (data->smu_features[GNLD_DPM_UVD].enabled &&
1811            (feature_mask & FEATURE_DPM_UVD_MASK)) {
1812                 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1813
1814                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1815                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1816                                         (PPCLK_VCLK << 16) | (min_freq & 0xffff),
1817                                         NULL)),
1818                                         "Failed to set soft min vclk!",
1819                                         return ret);
1820
1821                 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1822
1823                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1824                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1825                                         (PPCLK_DCLK << 16) | (min_freq & 0xffff),
1826                                         NULL)),
1827                                         "Failed to set soft min dclk!",
1828                                         return ret);
1829         }
1830
1831         if (data->smu_features[GNLD_DPM_VCE].enabled &&
1832            (feature_mask & FEATURE_DPM_VCE_MASK)) {
1833                 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1834
1835                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1836                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1837                                         (PPCLK_ECLK << 16) | (min_freq & 0xffff),
1838                                         NULL)),
1839                                         "Failed to set soft min eclk!",
1840                                         return ret);
1841         }
1842
1843         if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1844            (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1845                 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1846
1847                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1848                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1849                                         (PPCLK_SOCCLK << 16) | (min_freq & 0xffff),
1850                                         NULL)),
1851                                         "Failed to set soft min socclk!",
1852                                         return ret);
1853         }
1854
1855         if (data->smu_features[GNLD_DPM_FCLK].enabled &&
1856            (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1857                 min_freq = data->dpm_table.fclk_table.dpm_state.soft_min_level;
1858
1859                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1860                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1861                                         (PPCLK_FCLK << 16) | (min_freq & 0xffff),
1862                                         NULL)),
1863                                         "Failed to set soft min fclk!",
1864                                         return ret);
1865         }
1866
1867         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled &&
1868            (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
1869                 min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level;
1870
1871                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1872                                         hwmgr, PPSMC_MSG_SetHardMinByFreq,
1873                                         (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff),
1874                                         NULL)),
1875                                         "Failed to set hard min dcefclk!",
1876                                         return ret);
1877         }
1878
1879         return ret;
1880 }
1881
1882 static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1883 {
1884         struct vega20_hwmgr *data =
1885                         (struct vega20_hwmgr *)(hwmgr->backend);
1886         uint32_t max_freq;
1887         int ret = 0;
1888
1889         if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1890            (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1891                 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1892
1893                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1894                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1895                                         (PPCLK_GFXCLK << 16) | (max_freq & 0xffff),
1896                                         NULL)),
1897                                         "Failed to set soft max gfxclk!",
1898                                         return ret);
1899         }
1900
1901         if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1902            (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1903                 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1904
1905                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1906                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1907                                         (PPCLK_UCLK << 16) | (max_freq & 0xffff),
1908                                         NULL)),
1909                                         "Failed to set soft max memclk!",
1910                                         return ret);
1911         }
1912
1913         if (data->smu_features[GNLD_DPM_UVD].enabled &&
1914            (feature_mask & FEATURE_DPM_UVD_MASK)) {
1915                 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1916
1917                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1918                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1919                                         (PPCLK_VCLK << 16) | (max_freq & 0xffff),
1920                                         NULL)),
1921                                         "Failed to set soft max vclk!",
1922                                         return ret);
1923
1924                 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1925                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1926                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1927                                         (PPCLK_DCLK << 16) | (max_freq & 0xffff),
1928                                         NULL)),
1929                                         "Failed to set soft max dclk!",
1930                                         return ret);
1931         }
1932
1933         if (data->smu_features[GNLD_DPM_VCE].enabled &&
1934            (feature_mask & FEATURE_DPM_VCE_MASK)) {
1935                 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1936
1937                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1938                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1939                                         (PPCLK_ECLK << 16) | (max_freq & 0xffff),
1940                                         NULL)),
1941                                         "Failed to set soft max eclk!",
1942                                         return ret);
1943         }
1944
1945         if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1946            (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1947                 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1948
1949                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1950                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1951                                         (PPCLK_SOCCLK << 16) | (max_freq & 0xffff),
1952                                         NULL)),
1953                                         "Failed to set soft max socclk!",
1954                                         return ret);
1955         }
1956
1957         if (data->smu_features[GNLD_DPM_FCLK].enabled &&
1958            (feature_mask & FEATURE_DPM_FCLK_MASK)) {
1959                 max_freq = data->dpm_table.fclk_table.dpm_state.soft_max_level;
1960
1961                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1962                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1963                                         (PPCLK_FCLK << 16) | (max_freq & 0xffff),
1964                                         NULL)),
1965                                         "Failed to set soft max fclk!",
1966                                         return ret);
1967         }
1968
1969         return ret;
1970 }
1971
1972 static int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1973 {
1974         struct vega20_hwmgr *data =
1975                         (struct vega20_hwmgr *)(hwmgr->backend);
1976         int ret = 0;
1977
1978         if (data->smu_features[GNLD_DPM_VCE].supported) {
1979                 if (data->smu_features[GNLD_DPM_VCE].enabled == enable) {
1980                         if (enable)
1981                                 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already enabled!\n");
1982                         else
1983                                 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already disabled!\n");
1984                 }
1985
1986                 ret = vega20_enable_smc_features(hwmgr,
1987                                 enable,
1988                                 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap);
1989                 PP_ASSERT_WITH_CODE(!ret,
1990                                 "Attempt to Enable/Disable DPM VCE Failed!",
1991                                 return ret);
1992                 data->smu_features[GNLD_DPM_VCE].enabled = enable;
1993         }
1994
1995         return 0;
1996 }
1997
1998 static int vega20_get_clock_ranges(struct pp_hwmgr *hwmgr,
1999                 uint32_t *clock,
2000                 PPCLK_e clock_select,
2001                 bool max)
2002 {
2003         int ret;
2004         *clock = 0;
2005
2006         if (max) {
2007                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2008                                 PPSMC_MSG_GetMaxDpmFreq, (clock_select << 16),
2009                                 clock)) == 0,
2010                                 "[GetClockRanges] Failed to get max clock from SMC!",
2011                                 return ret);
2012         } else {
2013                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2014                                 PPSMC_MSG_GetMinDpmFreq,
2015                                 (clock_select << 16),
2016                                 clock)) == 0,
2017                                 "[GetClockRanges] Failed to get min clock from SMC!",
2018                                 return ret);
2019         }
2020
2021         return 0;
2022 }
2023
2024 static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
2025 {
2026         struct vega20_hwmgr *data =
2027                         (struct vega20_hwmgr *)(hwmgr->backend);
2028         uint32_t gfx_clk;
2029         int ret = 0;
2030
2031         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
2032                         "[GetSclks]: gfxclk dpm not enabled!\n",
2033                         return -EPERM);
2034
2035         if (low) {
2036                 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false);
2037                 PP_ASSERT_WITH_CODE(!ret,
2038                         "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
2039                         return ret);
2040         } else {
2041                 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true);
2042                 PP_ASSERT_WITH_CODE(!ret,
2043                         "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
2044                         return ret);
2045         }
2046
2047         return (gfx_clk * 100);
2048 }
2049
2050 static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
2051 {
2052         struct vega20_hwmgr *data =
2053                         (struct vega20_hwmgr *)(hwmgr->backend);
2054         uint32_t mem_clk;
2055         int ret = 0;
2056
2057         PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
2058                         "[MemMclks]: memclk dpm not enabled!\n",
2059                         return -EPERM);
2060
2061         if (low) {
2062                 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false);
2063                 PP_ASSERT_WITH_CODE(!ret,
2064                         "[GetMclks]: fail to get min PPCLK_UCLK\n",
2065                         return ret);
2066         } else {
2067                 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true);
2068                 PP_ASSERT_WITH_CODE(!ret,
2069                         "[GetMclks]: fail to get max PPCLK_UCLK\n",
2070                         return ret);
2071         }
2072
2073         return (mem_clk * 100);
2074 }
2075
2076 static int vega20_get_metrics_table(struct pp_hwmgr *hwmgr, SmuMetrics_t *metrics_table)
2077 {
2078         struct vega20_hwmgr *data =
2079                         (struct vega20_hwmgr *)(hwmgr->backend);
2080         int ret = 0;
2081
2082         if (!data->metrics_time || time_after(jiffies, data->metrics_time + HZ / 2)) {
2083                 ret = smum_smc_table_manager(hwmgr, (uint8_t *)metrics_table,
2084                                 TABLE_SMU_METRICS, true);
2085                 if (ret) {
2086                         pr_info("Failed to export SMU metrics table!\n");
2087                         return ret;
2088                 }
2089                 memcpy(&data->metrics_table, metrics_table, sizeof(SmuMetrics_t));
2090                 data->metrics_time = jiffies;
2091         } else
2092                 memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t));
2093
2094         return ret;
2095 }
2096
2097 static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
2098                 uint32_t *query)
2099 {
2100         int ret = 0;
2101         SmuMetrics_t metrics_table;
2102
2103         ret = vega20_get_metrics_table(hwmgr, &metrics_table);
2104         if (ret)
2105                 return ret;
2106
2107         /* For the 40.46 release, they changed the value name */
2108         if (hwmgr->smu_version == 0x282e00)
2109                 *query = metrics_table.AverageSocketPower << 8;
2110         else
2111                 *query = metrics_table.CurrSocketPower << 8;
2112
2113         return ret;
2114 }
2115
2116 static int vega20_get_current_clk_freq(struct pp_hwmgr *hwmgr,
2117                 PPCLK_e clk_id, uint32_t *clk_freq)
2118 {
2119         int ret = 0;
2120
2121         *clk_freq = 0;
2122
2123         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2124                         PPSMC_MSG_GetDpmClockFreq, (clk_id << 16),
2125                         clk_freq)) == 0,
2126                         "[GetCurrentClkFreq] Attempt to get Current Frequency Failed!",
2127                         return ret);
2128
2129         *clk_freq = *clk_freq * 100;
2130
2131         return 0;
2132 }
2133
2134 static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr,
2135                 int idx,
2136                 uint32_t *activity_percent)
2137 {
2138         int ret = 0;
2139         SmuMetrics_t metrics_table;
2140
2141         ret = vega20_get_metrics_table(hwmgr, &metrics_table);
2142         if (ret)
2143                 return ret;
2144
2145         switch (idx) {
2146         case AMDGPU_PP_SENSOR_GPU_LOAD:
2147                 *activity_percent = metrics_table.AverageGfxActivity;
2148                 break;
2149         case AMDGPU_PP_SENSOR_MEM_LOAD:
2150                 *activity_percent = metrics_table.AverageUclkActivity;
2151                 break;
2152         default:
2153                 pr_err("Invalid index for retrieving clock activity\n");
2154                 return -EINVAL;
2155         }
2156
2157         return ret;
2158 }
2159
2160 static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
2161                               void *value, int *size)
2162 {
2163         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2164         struct amdgpu_device *adev = hwmgr->adev;
2165         SmuMetrics_t metrics_table;
2166         uint32_t val_vid;
2167         int ret = 0;
2168
2169         switch (idx) {
2170         case AMDGPU_PP_SENSOR_GFX_SCLK:
2171                 ret = vega20_get_metrics_table(hwmgr, &metrics_table);
2172                 if (ret)
2173                         return ret;
2174
2175                 *((uint32_t *)value) = metrics_table.AverageGfxclkFrequency * 100;
2176                 *size = 4;
2177                 break;
2178         case AMDGPU_PP_SENSOR_GFX_MCLK:
2179                 ret = vega20_get_current_clk_freq(hwmgr,
2180                                 PPCLK_UCLK,
2181                                 (uint32_t *)value);
2182                 if (!ret)
2183                         *size = 4;
2184                 break;
2185         case AMDGPU_PP_SENSOR_GPU_LOAD:
2186         case AMDGPU_PP_SENSOR_MEM_LOAD:
2187                 ret = vega20_get_current_activity_percent(hwmgr, idx, (uint32_t *)value);
2188                 if (!ret)
2189                         *size = 4;
2190                 break;
2191         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
2192                 *((uint32_t *)value) = vega20_thermal_get_temperature(hwmgr);
2193                 *size = 4;
2194                 break;
2195         case AMDGPU_PP_SENSOR_EDGE_TEMP:
2196                 ret = vega20_get_metrics_table(hwmgr, &metrics_table);
2197                 if (ret)
2198                         return ret;
2199
2200                 *((uint32_t *)value) = metrics_table.TemperatureEdge *
2201                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2202                 *size = 4;
2203                 break;
2204         case AMDGPU_PP_SENSOR_MEM_TEMP:
2205                 ret = vega20_get_metrics_table(hwmgr, &metrics_table);
2206                 if (ret)
2207                         return ret;
2208
2209                 *((uint32_t *)value) = metrics_table.TemperatureHBM *
2210                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2211                 *size = 4;
2212                 break;
2213         case AMDGPU_PP_SENSOR_UVD_POWER:
2214                 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
2215                 *size = 4;
2216                 break;
2217         case AMDGPU_PP_SENSOR_VCE_POWER:
2218                 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
2219                 *size = 4;
2220                 break;
2221         case AMDGPU_PP_SENSOR_GPU_POWER:
2222                 *size = 16;
2223                 ret = vega20_get_gpu_power(hwmgr, (uint32_t *)value);
2224                 break;
2225         case AMDGPU_PP_SENSOR_VDDGFX:
2226                 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
2227                         SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
2228                         SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
2229                 *((uint32_t *)value) =
2230                         (uint32_t)convert_to_vddc((uint8_t)val_vid);
2231                 break;
2232         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2233                 ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value);
2234                 if (!ret)
2235                         *size = 8;
2236                 break;
2237         default:
2238                 ret = -EINVAL;
2239                 break;
2240         }
2241         return ret;
2242 }
2243
2244 static int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
2245                 struct pp_display_clock_request *clock_req)
2246 {
2247         int result = 0;
2248         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2249         enum amd_pp_clock_type clk_type = clock_req->clock_type;
2250         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
2251         PPCLK_e clk_select = 0;
2252         uint32_t clk_request = 0;
2253
2254         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
2255                 switch (clk_type) {
2256                 case amd_pp_dcef_clock:
2257                         clk_select = PPCLK_DCEFCLK;
2258                         break;
2259                 case amd_pp_disp_clock:
2260                         clk_select = PPCLK_DISPCLK;
2261                         break;
2262                 case amd_pp_pixel_clock:
2263                         clk_select = PPCLK_PIXCLK;
2264                         break;
2265                 case amd_pp_phy_clock:
2266                         clk_select = PPCLK_PHYCLK;
2267                         break;
2268                 default:
2269                         pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
2270                         result = -EINVAL;
2271                         break;
2272                 }
2273
2274                 if (!result) {
2275                         clk_request = (clk_select << 16) | clk_freq;
2276                         result = smum_send_msg_to_smc_with_parameter(hwmgr,
2277                                         PPSMC_MSG_SetHardMinByFreq,
2278                                         clk_request,
2279                                         NULL);
2280                 }
2281         }
2282
2283         return result;
2284 }
2285
2286 static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2287                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
2288                                 PHM_PerformanceLevel *level)
2289 {
2290         return 0;
2291 }
2292
2293 static int vega20_notify_smc_display_config_after_ps_adjustment(
2294                 struct pp_hwmgr *hwmgr)
2295 {
2296         struct vega20_hwmgr *data =
2297                         (struct vega20_hwmgr *)(hwmgr->backend);
2298         struct vega20_single_dpm_table *dpm_table =
2299                         &data->dpm_table.mem_table;
2300         struct PP_Clocks min_clocks = {0};
2301         struct pp_display_clock_request clock_req;
2302         int ret = 0;
2303
2304         min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
2305         min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
2306         min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2307
2308         if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
2309                 clock_req.clock_type = amd_pp_dcef_clock;
2310                 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10;
2311                 if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) {
2312                         if (data->smu_features[GNLD_DS_DCEFCLK].supported)
2313                                 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(
2314                                         hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
2315                                         min_clocks.dcefClockInSR / 100,
2316                                         NULL)) == 0,
2317                                         "Attempt to set divider for DCEFCLK Failed!",
2318                                         return ret);
2319                 } else {
2320                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2321                 }
2322         }
2323
2324         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2325                 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
2326                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2327                                 PPSMC_MSG_SetHardMinByFreq,
2328                                 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level,
2329                                 NULL)),
2330                                 "[SetHardMinFreq] Set hard min uclk failed!",
2331                                 return ret);
2332         }
2333
2334         return 0;
2335 }
2336
2337 static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
2338 {
2339         struct vega20_hwmgr *data =
2340                         (struct vega20_hwmgr *)(hwmgr->backend);
2341         uint32_t soft_level;
2342         int ret = 0;
2343
2344         soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
2345
2346         data->dpm_table.gfx_table.dpm_state.soft_min_level =
2347                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2348                 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2349
2350         soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
2351
2352         data->dpm_table.mem_table.dpm_state.soft_min_level =
2353                 data->dpm_table.mem_table.dpm_state.soft_max_level =
2354                 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2355
2356         soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.soc_table));
2357
2358         data->dpm_table.soc_table.dpm_state.soft_min_level =
2359                 data->dpm_table.soc_table.dpm_state.soft_max_level =
2360                 data->dpm_table.soc_table.dpm_levels[soft_level].value;
2361
2362         ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2363                                                  FEATURE_DPM_UCLK_MASK |
2364                                                  FEATURE_DPM_SOCCLK_MASK);
2365         PP_ASSERT_WITH_CODE(!ret,
2366                         "Failed to upload boot level to highest!",
2367                         return ret);
2368
2369         ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2370                                                  FEATURE_DPM_UCLK_MASK |
2371                                                  FEATURE_DPM_SOCCLK_MASK);
2372         PP_ASSERT_WITH_CODE(!ret,
2373                         "Failed to upload dpm max level to highest!",
2374                         return ret);
2375
2376         return 0;
2377 }
2378
2379 static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2380 {
2381         struct vega20_hwmgr *data =
2382                         (struct vega20_hwmgr *)(hwmgr->backend);
2383         uint32_t soft_level;
2384         int ret = 0;
2385
2386         soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
2387
2388         data->dpm_table.gfx_table.dpm_state.soft_min_level =
2389                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2390                 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2391
2392         soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
2393
2394         data->dpm_table.mem_table.dpm_state.soft_min_level =
2395                 data->dpm_table.mem_table.dpm_state.soft_max_level =
2396                 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2397
2398         soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table));
2399
2400         data->dpm_table.soc_table.dpm_state.soft_min_level =
2401                 data->dpm_table.soc_table.dpm_state.soft_max_level =
2402                 data->dpm_table.soc_table.dpm_levels[soft_level].value;
2403
2404         ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2405                                                  FEATURE_DPM_UCLK_MASK |
2406                                                  FEATURE_DPM_SOCCLK_MASK);
2407         PP_ASSERT_WITH_CODE(!ret,
2408                         "Failed to upload boot level to highest!",
2409                         return ret);
2410
2411         ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2412                                                  FEATURE_DPM_UCLK_MASK |
2413                                                  FEATURE_DPM_SOCCLK_MASK);
2414         PP_ASSERT_WITH_CODE(!ret,
2415                         "Failed to upload dpm max level to highest!",
2416                         return ret);
2417
2418         return 0;
2419
2420 }
2421
2422 static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2423 {
2424         struct vega20_hwmgr *data =
2425                         (struct vega20_hwmgr *)(hwmgr->backend);
2426         uint32_t soft_min_level, soft_max_level;
2427         int ret = 0;
2428
2429         /* gfxclk soft min/max settings */
2430         soft_min_level =
2431                 vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
2432         soft_max_level =
2433                 vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
2434
2435         data->dpm_table.gfx_table.dpm_state.soft_min_level =
2436                 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2437         data->dpm_table.gfx_table.dpm_state.soft_max_level =
2438                 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2439
2440         /* uclk soft min/max settings */
2441         soft_min_level =
2442                 vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
2443         soft_max_level =
2444                 vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
2445
2446         data->dpm_table.mem_table.dpm_state.soft_min_level =
2447                 data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2448         data->dpm_table.mem_table.dpm_state.soft_max_level =
2449                 data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2450
2451         /* socclk soft min/max settings */
2452         soft_min_level =
2453                 vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table));
2454         soft_max_level =
2455                 vega20_find_highest_dpm_level(&(data->dpm_table.soc_table));
2456
2457         data->dpm_table.soc_table.dpm_state.soft_min_level =
2458                 data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
2459         data->dpm_table.soc_table.dpm_state.soft_max_level =
2460                 data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
2461
2462         ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2463                                                  FEATURE_DPM_UCLK_MASK |
2464                                                  FEATURE_DPM_SOCCLK_MASK);
2465         PP_ASSERT_WITH_CODE(!ret,
2466                         "Failed to upload DPM Bootup Levels!",
2467                         return ret);
2468
2469         ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
2470                                                  FEATURE_DPM_UCLK_MASK |
2471                                                  FEATURE_DPM_SOCCLK_MASK);
2472         PP_ASSERT_WITH_CODE(!ret,
2473                         "Failed to upload DPM Max Levels!",
2474                         return ret);
2475
2476         return 0;
2477 }
2478
2479 static int vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2480                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
2481 {
2482         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2483         struct vega20_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
2484         struct vega20_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
2485         struct vega20_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
2486
2487         *sclk_mask = 0;
2488         *mclk_mask = 0;
2489         *soc_mask  = 0;
2490
2491         if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
2492             mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
2493             soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
2494                 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
2495                 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
2496                 *soc_mask  = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2497         }
2498
2499         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2500                 *sclk_mask = 0;
2501         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2502                 *mclk_mask = 0;
2503         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2504                 *sclk_mask = gfx_dpm_table->count - 1;
2505                 *mclk_mask = mem_dpm_table->count - 1;
2506                 *soc_mask  = soc_dpm_table->count - 1;
2507         }
2508
2509         return 0;
2510 }
2511
2512 static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
2513                 enum pp_clock_type type, uint32_t mask)
2514 {
2515         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2516         uint32_t soft_min_level, soft_max_level, hard_min_level;
2517         int ret = 0;
2518
2519         switch (type) {
2520         case PP_SCLK:
2521                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2522                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2523
2524                 if (soft_max_level >= data->dpm_table.gfx_table.count) {
2525                         pr_err("Clock level specified %d is over max allowed %d\n",
2526                                         soft_max_level,
2527                                         data->dpm_table.gfx_table.count - 1);
2528                         return -EINVAL;
2529                 }
2530
2531                 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2532                         data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2533                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2534                         data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2535
2536                 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2537                 PP_ASSERT_WITH_CODE(!ret,
2538                         "Failed to upload boot level to lowest!",
2539                         return ret);
2540
2541                 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2542                 PP_ASSERT_WITH_CODE(!ret,
2543                         "Failed to upload dpm max level to highest!",
2544                         return ret);
2545                 break;
2546
2547         case PP_MCLK:
2548                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2549                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2550
2551                 if (soft_max_level >= data->dpm_table.mem_table.count) {
2552                         pr_err("Clock level specified %d is over max allowed %d\n",
2553                                         soft_max_level,
2554                                         data->dpm_table.mem_table.count - 1);
2555                         return -EINVAL;
2556                 }
2557
2558                 data->dpm_table.mem_table.dpm_state.soft_min_level =
2559                         data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2560                 data->dpm_table.mem_table.dpm_state.soft_max_level =
2561                         data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2562
2563                 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2564                 PP_ASSERT_WITH_CODE(!ret,
2565                         "Failed to upload boot level to lowest!",
2566                         return ret);
2567
2568                 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2569                 PP_ASSERT_WITH_CODE(!ret,
2570                         "Failed to upload dpm max level to highest!",
2571                         return ret);
2572
2573                 break;
2574
2575         case PP_SOCCLK:
2576                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2577                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2578
2579                 if (soft_max_level >= data->dpm_table.soc_table.count) {
2580                         pr_err("Clock level specified %d is over max allowed %d\n",
2581                                         soft_max_level,
2582                                         data->dpm_table.soc_table.count - 1);
2583                         return -EINVAL;
2584                 }
2585
2586                 data->dpm_table.soc_table.dpm_state.soft_min_level =
2587                         data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
2588                 data->dpm_table.soc_table.dpm_state.soft_max_level =
2589                         data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
2590
2591                 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_SOCCLK_MASK);
2592                 PP_ASSERT_WITH_CODE(!ret,
2593                         "Failed to upload boot level to lowest!",
2594                         return ret);
2595
2596                 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_SOCCLK_MASK);
2597                 PP_ASSERT_WITH_CODE(!ret,
2598                         "Failed to upload dpm max level to highest!",
2599                         return ret);
2600
2601                 break;
2602
2603         case PP_FCLK:
2604                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2605                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2606
2607                 if (soft_max_level >= data->dpm_table.fclk_table.count) {
2608                         pr_err("Clock level specified %d is over max allowed %d\n",
2609                                         soft_max_level,
2610                                         data->dpm_table.fclk_table.count - 1);
2611                         return -EINVAL;
2612                 }
2613
2614                 data->dpm_table.fclk_table.dpm_state.soft_min_level =
2615                         data->dpm_table.fclk_table.dpm_levels[soft_min_level].value;
2616                 data->dpm_table.fclk_table.dpm_state.soft_max_level =
2617                         data->dpm_table.fclk_table.dpm_levels[soft_max_level].value;
2618
2619                 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_FCLK_MASK);
2620                 PP_ASSERT_WITH_CODE(!ret,
2621                         "Failed to upload boot level to lowest!",
2622                         return ret);
2623
2624                 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_FCLK_MASK);
2625                 PP_ASSERT_WITH_CODE(!ret,
2626                         "Failed to upload dpm max level to highest!",
2627                         return ret);
2628
2629                 break;
2630
2631         case PP_DCEFCLK:
2632                 hard_min_level = mask ? (ffs(mask) - 1) : 0;
2633
2634                 if (hard_min_level >= data->dpm_table.dcef_table.count) {
2635                         pr_err("Clock level specified %d is over max allowed %d\n",
2636                                         hard_min_level,
2637                                         data->dpm_table.dcef_table.count - 1);
2638                         return -EINVAL;
2639                 }
2640
2641                 data->dpm_table.dcef_table.dpm_state.hard_min_level =
2642                         data->dpm_table.dcef_table.dpm_levels[hard_min_level].value;
2643
2644                 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_DCEFCLK_MASK);
2645                 PP_ASSERT_WITH_CODE(!ret,
2646                         "Failed to upload boot level to lowest!",
2647                         return ret);
2648
2649                 //TODO: Setting DCEFCLK max dpm level is not supported
2650
2651                 break;
2652
2653         case PP_PCIE:
2654                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2655                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2656                 if (soft_min_level >= NUM_LINK_LEVELS ||
2657                     soft_max_level >= NUM_LINK_LEVELS)
2658                         return -EINVAL;
2659
2660                 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2661                         PPSMC_MSG_SetMinLinkDpmByIndex, soft_min_level,
2662                         NULL);
2663                 PP_ASSERT_WITH_CODE(!ret,
2664                         "Failed to set min link dpm level!",
2665                         return ret);
2666
2667                 break;
2668
2669         default:
2670                 break;
2671         }
2672
2673         return 0;
2674 }
2675
2676 static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
2677                                 enum amd_dpm_forced_level level)
2678 {
2679         int ret = 0;
2680         uint32_t sclk_mask, mclk_mask, soc_mask;
2681
2682         switch (level) {
2683         case AMD_DPM_FORCED_LEVEL_HIGH:
2684                 ret = vega20_force_dpm_highest(hwmgr);
2685                 break;
2686
2687         case AMD_DPM_FORCED_LEVEL_LOW:
2688                 ret = vega20_force_dpm_lowest(hwmgr);
2689                 break;
2690
2691         case AMD_DPM_FORCED_LEVEL_AUTO:
2692                 ret = vega20_unforce_dpm_levels(hwmgr);
2693                 break;
2694
2695         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
2696         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
2697         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
2698         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
2699                 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
2700                 if (ret)
2701                         return ret;
2702                 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
2703                 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
2704                 vega20_force_clock_level(hwmgr, PP_SOCCLK, 1 << soc_mask);
2705                 break;
2706
2707         case AMD_DPM_FORCED_LEVEL_MANUAL:
2708         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
2709         default:
2710                 break;
2711         }
2712
2713         return ret;
2714 }
2715
2716 static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr)
2717 {
2718         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2719
2720         if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
2721                 return AMD_FAN_CTRL_MANUAL;
2722         else
2723                 return AMD_FAN_CTRL_AUTO;
2724 }
2725
2726 static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
2727 {
2728         switch (mode) {
2729         case AMD_FAN_CTRL_NONE:
2730                 vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
2731                 break;
2732         case AMD_FAN_CTRL_MANUAL:
2733                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2734                         vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
2735                 break;
2736         case AMD_FAN_CTRL_AUTO:
2737                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2738                         vega20_fan_ctrl_start_smc_fan_control(hwmgr);
2739                 break;
2740         default:
2741                 break;
2742         }
2743 }
2744
2745 static int vega20_get_dal_power_level(struct pp_hwmgr *hwmgr,
2746                 struct amd_pp_simple_clock_info *info)
2747 {
2748 #if 0
2749         struct phm_ppt_v2_information *table_info =
2750                         (struct phm_ppt_v2_information *)hwmgr->pptable;
2751         struct phm_clock_and_voltage_limits *max_limits =
2752                         &table_info->max_clock_voltage_on_ac;
2753
2754         info->engine_max_clock = max_limits->sclk;
2755         info->memory_max_clock = max_limits->mclk;
2756 #endif
2757         return 0;
2758 }
2759
2760
2761 static int vega20_get_sclks(struct pp_hwmgr *hwmgr,
2762                 struct pp_clock_levels_with_latency *clocks)
2763 {
2764         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2765         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
2766         int i, count;
2767
2768         if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
2769                 return -1;
2770
2771         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2772         clocks->num_levels = count;
2773
2774         for (i = 0; i < count; i++) {
2775                 clocks->data[i].clocks_in_khz =
2776                         dpm_table->dpm_levels[i].value * 1000;
2777                 clocks->data[i].latency_in_us = 0;
2778         }
2779
2780         return 0;
2781 }
2782
2783 static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr,
2784                 uint32_t clock)
2785 {
2786         return 25;
2787 }
2788
2789 static int vega20_get_memclocks(struct pp_hwmgr *hwmgr,
2790                 struct pp_clock_levels_with_latency *clocks)
2791 {
2792         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2793         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table);
2794         int i, count;
2795
2796         if (!data->smu_features[GNLD_DPM_UCLK].enabled)
2797                 return -1;
2798
2799         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2800         clocks->num_levels = data->mclk_latency_table.count = count;
2801
2802         for (i = 0; i < count; i++) {
2803                 clocks->data[i].clocks_in_khz =
2804                         data->mclk_latency_table.entries[i].frequency =
2805                         dpm_table->dpm_levels[i].value * 1000;
2806                 clocks->data[i].latency_in_us =
2807                         data->mclk_latency_table.entries[i].latency =
2808                         vega20_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
2809         }
2810
2811         return 0;
2812 }
2813
2814 static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr,
2815                 struct pp_clock_levels_with_latency *clocks)
2816 {
2817         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2818         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table);
2819         int i, count;
2820
2821         if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled)
2822                 return -1;
2823
2824         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2825         clocks->num_levels = count;
2826
2827         for (i = 0; i < count; i++) {
2828                 clocks->data[i].clocks_in_khz =
2829                         dpm_table->dpm_levels[i].value * 1000;
2830                 clocks->data[i].latency_in_us = 0;
2831         }
2832
2833         return 0;
2834 }
2835
2836 static int vega20_get_socclocks(struct pp_hwmgr *hwmgr,
2837                 struct pp_clock_levels_with_latency *clocks)
2838 {
2839         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2840         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table);
2841         int i, count;
2842
2843         if (!data->smu_features[GNLD_DPM_SOCCLK].enabled)
2844                 return -1;
2845
2846         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2847         clocks->num_levels = count;
2848
2849         for (i = 0; i < count; i++) {
2850                 clocks->data[i].clocks_in_khz =
2851                         dpm_table->dpm_levels[i].value * 1000;
2852                 clocks->data[i].latency_in_us = 0;
2853         }
2854
2855         return 0;
2856
2857 }
2858
2859 static int vega20_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
2860                 enum amd_pp_clock_type type,
2861                 struct pp_clock_levels_with_latency *clocks)
2862 {
2863         int ret;
2864
2865         switch (type) {
2866         case amd_pp_sys_clock:
2867                 ret = vega20_get_sclks(hwmgr, clocks);
2868                 break;
2869         case amd_pp_mem_clock:
2870                 ret = vega20_get_memclocks(hwmgr, clocks);
2871                 break;
2872         case amd_pp_dcef_clock:
2873                 ret = vega20_get_dcefclocks(hwmgr, clocks);
2874                 break;
2875         case amd_pp_soc_clock:
2876                 ret = vega20_get_socclocks(hwmgr, clocks);
2877                 break;
2878         default:
2879                 return -EINVAL;
2880         }
2881
2882         return ret;
2883 }
2884
2885 static int vega20_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
2886                 enum amd_pp_clock_type type,
2887                 struct pp_clock_levels_with_voltage *clocks)
2888 {
2889         clocks->num_levels = 0;
2890
2891         return 0;
2892 }
2893
2894 static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
2895                                                    void *clock_ranges)
2896 {
2897         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2898         Watermarks_t *table = &(data->smc_state_table.water_marks_table);
2899         struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
2900
2901         if (!data->registry_data.disable_water_mark &&
2902             data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2903             data->smu_features[GNLD_DPM_SOCCLK].supported) {
2904                 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
2905                 data->water_marks_bitmap |= WaterMarksExist;
2906                 data->water_marks_bitmap &= ~WaterMarksLoaded;
2907         }
2908
2909         return 0;
2910 }
2911
2912 static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
2913                                         enum PP_OD_DPM_TABLE_COMMAND type,
2914                                         long *input, uint32_t size)
2915 {
2916         struct vega20_hwmgr *data =
2917                         (struct vega20_hwmgr *)(hwmgr->backend);
2918         struct vega20_od8_single_setting *od8_settings =
2919                         data->od8_settings.od8_settings_array;
2920         OverDriveTable_t *od_table =
2921                         &(data->smc_state_table.overdrive_table);
2922         int32_t input_index, input_clk, input_vol, i;
2923         int od8_id;
2924         int ret;
2925
2926         PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
2927                                 return -EINVAL);
2928
2929         switch (type) {
2930         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2931                 if (!(od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2932                       od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2933                         pr_info("Sclk min/max frequency overdrive not supported\n");
2934                         return -EOPNOTSUPP;
2935                 }
2936
2937                 for (i = 0; i < size; i += 2) {
2938                         if (i + 2 > size) {
2939                                 pr_info("invalid number of input parameters %d\n",
2940                                         size);
2941                                 return -EINVAL;
2942                         }
2943
2944                         input_index = input[i];
2945                         input_clk = input[i + 1];
2946
2947                         if (input_index != 0 && input_index != 1) {
2948                                 pr_info("Invalid index %d\n", input_index);
2949                                 pr_info("Support min/max sclk frequency setting only which index by 0/1\n");
2950                                 return -EINVAL;
2951                         }
2952
2953                         if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value ||
2954                             input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) {
2955                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2956                                         input_clk,
2957                                         od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2958                                         od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2959                                 return -EINVAL;
2960                         }
2961
2962                         if ((input_index == 0 && od_table->GfxclkFmin != input_clk) ||
2963                             (input_index == 1 && od_table->GfxclkFmax != input_clk))
2964                                 data->gfxclk_overdrive = true;
2965
2966                         if (input_index == 0)
2967                                 od_table->GfxclkFmin = input_clk;
2968                         else
2969                                 od_table->GfxclkFmax = input_clk;
2970                 }
2971
2972                 break;
2973
2974         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2975                 if (!od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2976                         pr_info("Mclk max frequency overdrive not supported\n");
2977                         return -EOPNOTSUPP;
2978                 }
2979
2980                 for (i = 0; i < size; i += 2) {
2981                         if (i + 2 > size) {
2982                                 pr_info("invalid number of input parameters %d\n",
2983                                         size);
2984                                 return -EINVAL;
2985                         }
2986
2987                         input_index = input[i];
2988                         input_clk = input[i + 1];
2989
2990                         if (input_index != 1) {
2991                                 pr_info("Invalid index %d\n", input_index);
2992                                 pr_info("Support max Mclk frequency setting only which index by 1\n");
2993                                 return -EINVAL;
2994                         }
2995
2996                         if (input_clk < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
2997                             input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) {
2998                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2999                                         input_clk,
3000                                         od8_settings[OD8_SETTING_UCLK_FMAX].min_value,
3001                                         od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
3002                                 return -EINVAL;
3003                         }
3004
3005                         if (input_index == 1 && od_table->UclkFmax != input_clk)
3006                                 data->memclk_overdrive = true;
3007
3008                         od_table->UclkFmax = input_clk;
3009                 }
3010
3011                 break;
3012
3013         case PP_OD_EDIT_VDDC_CURVE:
3014                 if (!(od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
3015                     od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
3016                     od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
3017                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
3018                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
3019                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
3020                         pr_info("Voltage curve calibrate not supported\n");
3021                         return -EOPNOTSUPP;
3022                 }
3023
3024                 for (i = 0; i < size; i += 3) {
3025                         if (i + 3 > size) {
3026                                 pr_info("invalid number of input parameters %d\n",
3027                                         size);
3028                                 return -EINVAL;
3029                         }
3030
3031                         input_index = input[i];
3032                         input_clk = input[i + 1];
3033                         input_vol = input[i + 2];
3034
3035                         if (input_index > 2) {
3036                                 pr_info("Setting for point %d is not supported\n",
3037                                                 input_index + 1);
3038                                 pr_info("Three supported points index by 0, 1, 2\n");
3039                                 return -EINVAL;
3040                         }
3041
3042                         od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
3043                         if (input_clk < od8_settings[od8_id].min_value ||
3044                             input_clk > od8_settings[od8_id].max_value) {
3045                                 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
3046                                         input_clk,
3047                                         od8_settings[od8_id].min_value,
3048                                         od8_settings[od8_id].max_value);
3049                                 return -EINVAL;
3050                         }
3051
3052                         od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
3053                         if (input_vol < od8_settings[od8_id].min_value ||
3054                             input_vol > od8_settings[od8_id].max_value) {
3055                                 pr_info("clock voltage %d is not within allowed range [%d - %d]\n",
3056                                         input_vol,
3057                                         od8_settings[od8_id].min_value,
3058                                         od8_settings[od8_id].max_value);
3059                                 return -EINVAL;
3060                         }
3061
3062                         switch (input_index) {
3063                         case 0:
3064                                 od_table->GfxclkFreq1 = input_clk;
3065                                 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
3066                                 break;
3067                         case 1:
3068                                 od_table->GfxclkFreq2 = input_clk;
3069                                 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
3070                                 break;
3071                         case 2:
3072                                 od_table->GfxclkFreq3 = input_clk;
3073                                 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
3074                                 break;
3075                         }
3076                 }
3077                 break;
3078
3079         case PP_OD_RESTORE_DEFAULT_TABLE:
3080                 data->gfxclk_overdrive = false;
3081                 data->memclk_overdrive = false;
3082
3083                 ret = smum_smc_table_manager(hwmgr,
3084                                              (uint8_t *)od_table,
3085                                              TABLE_OVERDRIVE, true);
3086                 PP_ASSERT_WITH_CODE(!ret,
3087                                 "Failed to export overdrive table!",
3088                                 return ret);
3089                 break;
3090
3091         case PP_OD_COMMIT_DPM_TABLE:
3092                 ret = smum_smc_table_manager(hwmgr,
3093                                              (uint8_t *)od_table,
3094                                              TABLE_OVERDRIVE, false);
3095                 PP_ASSERT_WITH_CODE(!ret,
3096                                 "Failed to import overdrive table!",
3097                                 return ret);
3098
3099                 /* retrieve updated gfxclk table */
3100                 if (data->gfxclk_overdrive) {
3101                         data->gfxclk_overdrive = false;
3102
3103                         ret = vega20_setup_gfxclk_dpm_table(hwmgr);
3104                         if (ret)
3105                                 return ret;
3106                 }
3107
3108                 /* retrieve updated memclk table */
3109                 if (data->memclk_overdrive) {
3110                         data->memclk_overdrive = false;
3111
3112                         ret = vega20_setup_memclk_dpm_table(hwmgr);
3113                         if (ret)
3114                                 return ret;
3115                 }
3116                 break;
3117
3118         default:
3119                 return -EINVAL;
3120         }
3121
3122         return 0;
3123 }
3124
3125 static int vega20_set_mp1_state(struct pp_hwmgr *hwmgr,
3126                                 enum pp_mp1_state mp1_state)
3127 {
3128         uint16_t msg;
3129         int ret;
3130
3131         switch (mp1_state) {
3132         case PP_MP1_STATE_SHUTDOWN:
3133                 msg = PPSMC_MSG_PrepareMp1ForShutdown;
3134                 break;
3135         case PP_MP1_STATE_UNLOAD:
3136                 msg = PPSMC_MSG_PrepareMp1ForUnload;
3137                 break;
3138         case PP_MP1_STATE_RESET:
3139                 msg = PPSMC_MSG_PrepareMp1ForReset;
3140                 break;
3141         case PP_MP1_STATE_NONE:
3142         default:
3143                 return 0;
3144         }
3145
3146         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0,
3147                             "[PrepareMp1] Failed!",
3148                             return ret);
3149
3150         return 0;
3151 }
3152
3153 static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
3154 {
3155         static const char *ppfeature_name[] = {
3156                                 "DPM_PREFETCHER",
3157                                 "GFXCLK_DPM",
3158                                 "UCLK_DPM",
3159                                 "SOCCLK_DPM",
3160                                 "UVD_DPM",
3161                                 "VCE_DPM",
3162                                 "ULV",
3163                                 "MP0CLK_DPM",
3164                                 "LINK_DPM",
3165                                 "DCEFCLK_DPM",
3166                                 "GFXCLK_DS",
3167                                 "SOCCLK_DS",
3168                                 "LCLK_DS",
3169                                 "PPT",
3170                                 "TDC",
3171                                 "THERMAL",
3172                                 "GFX_PER_CU_CG",
3173                                 "RM",
3174                                 "DCEFCLK_DS",
3175                                 "ACDC",
3176                                 "VR0HOT",
3177                                 "VR1HOT",
3178                                 "FW_CTF",
3179                                 "LED_DISPLAY",
3180                                 "FAN_CONTROL",
3181                                 "GFX_EDC",
3182                                 "GFXOFF",
3183                                 "CG",
3184                                 "FCLK_DPM",
3185                                 "FCLK_DS",
3186                                 "MP1CLK_DS",
3187                                 "MP0CLK_DS",
3188                                 "XGMI",
3189                                 "ECC"};
3190         static const char *output_title[] = {
3191                                 "FEATURES",
3192                                 "BITMASK",
3193                                 "ENABLEMENT"};
3194         uint64_t features_enabled;
3195         int i;
3196         int ret = 0;
3197         int size = 0;
3198
3199         ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
3200         PP_ASSERT_WITH_CODE(!ret,
3201                         "[EnableAllSmuFeatures] Failed to get enabled smc features!",
3202                         return ret);
3203
3204         size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
3205         size += sprintf(buf + size, "%-19s %-22s %s\n",
3206                                 output_title[0],
3207                                 output_title[1],
3208                                 output_title[2]);
3209         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
3210                 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
3211                                         ppfeature_name[i],
3212                                         1ULL << i,
3213                                         (features_enabled & (1ULL << i)) ? "Y" : "N");
3214         }
3215
3216         return size;
3217 }
3218
3219 static int vega20_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
3220 {
3221         struct vega20_hwmgr *data =
3222                         (struct vega20_hwmgr *)(hwmgr->backend);
3223         uint64_t features_enabled, features_to_enable, features_to_disable;
3224         int i, ret = 0;
3225         bool enabled;
3226
3227         if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
3228                 return -EINVAL;
3229
3230         ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
3231         if (ret)
3232                 return ret;
3233
3234         features_to_disable =
3235                 features_enabled & ~new_ppfeature_masks;
3236         features_to_enable =
3237                 ~features_enabled & new_ppfeature_masks;
3238
3239         pr_debug("features_to_disable 0x%llx\n", features_to_disable);
3240         pr_debug("features_to_enable 0x%llx\n", features_to_enable);
3241
3242         if (features_to_disable) {
3243                 ret = vega20_enable_smc_features(hwmgr, false, features_to_disable);
3244                 if (ret)
3245                         return ret;
3246         }
3247
3248         if (features_to_enable) {
3249                 ret = vega20_enable_smc_features(hwmgr, true, features_to_enable);
3250                 if (ret)
3251                         return ret;
3252         }
3253
3254         /* Update the cached feature enablement state */
3255         ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
3256         if (ret)
3257                 return ret;
3258
3259         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
3260                 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
3261                         true : false;
3262                 data->smu_features[i].enabled = enabled;
3263         }
3264
3265         return 0;
3266 }
3267
3268 static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
3269                 enum pp_clock_type type, char *buf)
3270 {
3271         struct vega20_hwmgr *data =
3272                         (struct vega20_hwmgr *)(hwmgr->backend);
3273         struct vega20_od8_single_setting *od8_settings =
3274                         data->od8_settings.od8_settings_array;
3275         OverDriveTable_t *od_table =
3276                         &(data->smc_state_table.overdrive_table);
3277         struct phm_ppt_v3_information *pptable_information =
3278                 (struct phm_ppt_v3_information *)hwmgr->pptable;
3279         PPTable_t *pptable = (PPTable_t *)pptable_information->smc_pptable;
3280         struct amdgpu_device *adev = hwmgr->adev;
3281         struct pp_clock_levels_with_latency clocks;
3282         struct vega20_single_dpm_table *fclk_dpm_table =
3283                         &(data->dpm_table.fclk_table);
3284         int i, now, size = 0;
3285         int ret = 0;
3286         uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;
3287
3288         switch (type) {
3289         case PP_SCLK:
3290                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now);
3291                 PP_ASSERT_WITH_CODE(!ret,
3292                                 "Attempt to get current gfx clk Failed!",
3293                                 return ret);
3294
3295                 if (vega20_get_sclks(hwmgr, &clocks)) {
3296                         size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
3297                                 now / 100);
3298                         break;
3299                 }
3300
3301                 for (i = 0; i < clocks.num_levels; i++)
3302                         size += sprintf(buf + size, "%d: %uMhz %s\n",
3303                                 i, clocks.data[i].clocks_in_khz / 1000,
3304                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3305                 break;
3306
3307         case PP_MCLK:
3308                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now);
3309                 PP_ASSERT_WITH_CODE(!ret,
3310                                 "Attempt to get current mclk freq Failed!",
3311                                 return ret);
3312
3313                 if (vega20_get_memclocks(hwmgr, &clocks)) {
3314                         size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
3315                                 now / 100);
3316                         break;
3317                 }
3318
3319                 for (i = 0; i < clocks.num_levels; i++)
3320                         size += sprintf(buf + size, "%d: %uMhz %s\n",
3321                                 i, clocks.data[i].clocks_in_khz / 1000,
3322                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3323                 break;
3324
3325         case PP_SOCCLK:
3326                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_SOCCLK, &now);
3327                 PP_ASSERT_WITH_CODE(!ret,
3328                                 "Attempt to get current socclk freq Failed!",
3329                                 return ret);
3330
3331                 if (vega20_get_socclocks(hwmgr, &clocks)) {
3332                         size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
3333                                 now / 100);
3334                         break;
3335                 }
3336
3337                 for (i = 0; i < clocks.num_levels; i++)
3338                         size += sprintf(buf + size, "%d: %uMhz %s\n",
3339                                 i, clocks.data[i].clocks_in_khz / 1000,
3340                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3341                 break;
3342
3343         case PP_FCLK:
3344                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_FCLK, &now);
3345                 PP_ASSERT_WITH_CODE(!ret,
3346                                 "Attempt to get current fclk freq Failed!",
3347                                 return ret);
3348
3349                 for (i = 0; i < fclk_dpm_table->count; i++)
3350                         size += sprintf(buf + size, "%d: %uMhz %s\n",
3351                                 i, fclk_dpm_table->dpm_levels[i].value,
3352                                 fclk_dpm_table->dpm_levels[i].value == (now / 100) ? "*" : "");
3353                 break;
3354
3355         case PP_DCEFCLK:
3356                 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_DCEFCLK, &now);
3357                 PP_ASSERT_WITH_CODE(!ret,
3358                                 "Attempt to get current dcefclk freq Failed!",
3359                                 return ret);
3360
3361                 if (vega20_get_dcefclocks(hwmgr, &clocks)) {
3362                         size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n",
3363                                 now / 100);
3364                         break;
3365                 }
3366
3367                 for (i = 0; i < clocks.num_levels; i++)
3368                         size += sprintf(buf + size, "%d: %uMhz %s\n",
3369                                 i, clocks.data[i].clocks_in_khz / 1000,
3370                                 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : "");
3371                 break;
3372
3373         case PP_PCIE:
3374                 current_gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
3375                              PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
3376                             >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
3377                 current_lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
3378                               PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
3379                             >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
3380                 for (i = 0; i < NUM_LINK_LEVELS; i++) {
3381                         if (i == 1 && data->pcie_parameters_override) {
3382                                 gen_speed = data->pcie_gen_level1;
3383                                 lane_width = data->pcie_width_level1;
3384                         } else {
3385                                 gen_speed = pptable->PcieGenSpeed[i];
3386                                 lane_width = pptable->PcieLaneCount[i];
3387                         }
3388                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
3389                                         (gen_speed == 0) ? "2.5GT/s," :
3390                                         (gen_speed == 1) ? "5.0GT/s," :
3391                                         (gen_speed == 2) ? "8.0GT/s," :
3392                                         (gen_speed == 3) ? "16.0GT/s," : "",
3393                                         (lane_width == 1) ? "x1" :
3394                                         (lane_width == 2) ? "x2" :
3395                                         (lane_width == 3) ? "x4" :
3396                                         (lane_width == 4) ? "x8" :
3397                                         (lane_width == 5) ? "x12" :
3398                                         (lane_width == 6) ? "x16" : "",
3399                                         pptable->LclkFreq[i],
3400                                         (current_gen_speed == gen_speed) &&
3401                                         (current_lane_width == lane_width) ?
3402                                         "*" : "");
3403                 }
3404                 break;
3405
3406         case OD_SCLK:
3407                 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
3408                     od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
3409                         size = sprintf(buf, "%s:\n", "OD_SCLK");
3410                         size += sprintf(buf + size, "0: %10uMhz\n",
3411                                 od_table->GfxclkFmin);
3412                         size += sprintf(buf + size, "1: %10uMhz\n",
3413                                 od_table->GfxclkFmax);
3414                 }
3415                 break;
3416
3417         case OD_MCLK:
3418                 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
3419                         size = sprintf(buf, "%s:\n", "OD_MCLK");
3420                         size += sprintf(buf + size, "1: %10uMhz\n",
3421                                 od_table->UclkFmax);
3422                 }
3423
3424                 break;
3425
3426         case OD_VDDC_CURVE:
3427                 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
3428                     od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
3429                     od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
3430                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
3431                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
3432                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
3433                         size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
3434                         size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
3435                                 od_table->GfxclkFreq1,
3436                                 od_table->GfxclkVolt1 / VOLTAGE_SCALE);
3437                         size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
3438                                 od_table->GfxclkFreq2,
3439                                 od_table->GfxclkVolt2 / VOLTAGE_SCALE);
3440                         size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
3441                                 od_table->GfxclkFreq3,
3442                                 od_table->GfxclkVolt3 / VOLTAGE_SCALE);
3443                 }
3444
3445                 break;
3446
3447         case OD_RANGE:
3448                 size = sprintf(buf, "%s:\n", "OD_RANGE");
3449
3450                 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
3451                     od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
3452                         size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
3453                                 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
3454                                 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
3455                 }
3456
3457                 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
3458                         size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
3459                                 od8_settings[OD8_SETTING_UCLK_FMAX].min_value,
3460                                 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
3461                 }
3462
3463                 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
3464                     od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
3465                     od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
3466                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
3467                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
3468                     od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
3469                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
3470                                 od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value,
3471                                 od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value);
3472                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
3473                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
3474                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
3475                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
3476                                 od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value,
3477                                 od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value);
3478                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
3479                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
3480                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
3481                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
3482                                 od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value,
3483                                 od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value);
3484                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
3485                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
3486                                 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
3487                 }
3488
3489                 break;
3490         default:
3491                 break;
3492         }
3493         return size;
3494 }
3495
3496 static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
3497                 struct vega20_single_dpm_table *dpm_table)
3498 {
3499         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3500         int ret = 0;
3501
3502         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
3503                 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
3504                                 "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
3505                                 return -EINVAL);
3506                 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
3507                                 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
3508                                 return -EINVAL);
3509
3510                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3511                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
3512                                 PPSMC_MSG_SetHardMinByFreq,
3513                                 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level,
3514                                 NULL)),
3515                                 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
3516                                 return ret);
3517         }
3518
3519         return ret;
3520 }
3521
3522 static int vega20_set_fclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr)
3523 {
3524         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3525         struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.fclk_table);
3526         int ret = 0;
3527
3528         if (data->smu_features[GNLD_DPM_FCLK].enabled) {
3529                 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
3530                                 "[SetFclkToHightestDpmLevel] Dpm table has no entry!",
3531                                 return -EINVAL);
3532                 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_FCLK_DPM_LEVELS,
3533                                 "[SetFclkToHightestDpmLevel] Dpm table has too many entries!",
3534                                 return -EINVAL);
3535
3536                 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3537                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
3538                                 PPSMC_MSG_SetSoftMinByFreq,
3539                                 (PPCLK_FCLK << 16 ) | dpm_table->dpm_state.soft_min_level,
3540                                 NULL)),
3541                                 "[SetFclkToHightestDpmLevel] Set soft min fclk failed!",
3542                                 return ret);
3543         }
3544
3545         return ret;
3546 }
3547
3548 static int vega20_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
3549 {
3550         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3551         int ret = 0;
3552
3553         smum_send_msg_to_smc_with_parameter(hwmgr,
3554                         PPSMC_MSG_NumOfDisplays, 0, NULL);
3555
3556         ret = vega20_set_uclk_to_highest_dpm_level(hwmgr,
3557                         &data->dpm_table.mem_table);
3558         if (ret)
3559                 return ret;
3560
3561         return vega20_set_fclk_to_highest_dpm_level(hwmgr);
3562 }
3563
3564 static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
3565 {
3566         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3567         int result = 0;
3568         Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
3569
3570         if ((data->water_marks_bitmap & WaterMarksExist) &&
3571             !(data->water_marks_bitmap & WaterMarksLoaded)) {
3572                 result = smum_smc_table_manager(hwmgr,
3573                                                 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
3574                 PP_ASSERT_WITH_CODE(!result,
3575                                 "Failed to update WMTABLE!",
3576                                 return result);
3577                 data->water_marks_bitmap |= WaterMarksLoaded;
3578         }
3579
3580         if ((data->water_marks_bitmap & WaterMarksExist) &&
3581             data->smu_features[GNLD_DPM_DCEFCLK].supported &&
3582             data->smu_features[GNLD_DPM_SOCCLK].supported) {
3583                 result = smum_send_msg_to_smc_with_parameter(hwmgr,
3584                         PPSMC_MSG_NumOfDisplays,
3585                         hwmgr->display_config->num_display,
3586                         NULL);
3587         }
3588
3589         return result;
3590 }
3591
3592 static int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
3593 {
3594         struct vega20_hwmgr *data =
3595                         (struct vega20_hwmgr *)(hwmgr->backend);
3596         int ret = 0;
3597
3598         if (data->smu_features[GNLD_DPM_UVD].supported) {
3599                 if (data->smu_features[GNLD_DPM_UVD].enabled == enable) {
3600                         if (enable)
3601                                 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already enabled!\n");
3602                         else
3603                                 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already disabled!\n");
3604                 }
3605
3606                 ret = vega20_enable_smc_features(hwmgr,
3607                                 enable,
3608                                 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap);
3609                 PP_ASSERT_WITH_CODE(!ret,
3610                                 "[EnableDisableUVDDPM] Attempt to Enable/Disable DPM UVD Failed!",
3611                                 return ret);
3612                 data->smu_features[GNLD_DPM_UVD].enabled = enable;
3613         }
3614
3615         return 0;
3616 }
3617
3618 static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
3619 {
3620         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3621
3622         if (data->vce_power_gated == bgate)
3623                 return ;
3624
3625         data->vce_power_gated = bgate;
3626         if (bgate) {
3627                 vega20_enable_disable_vce_dpm(hwmgr, !bgate);
3628                 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
3629                                                 AMD_IP_BLOCK_TYPE_VCE,
3630                                                 AMD_PG_STATE_GATE);
3631         } else {
3632                 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
3633                                                 AMD_IP_BLOCK_TYPE_VCE,
3634                                                 AMD_PG_STATE_UNGATE);
3635                 vega20_enable_disable_vce_dpm(hwmgr, !bgate);
3636         }
3637
3638 }
3639
3640 static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
3641 {
3642         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3643
3644         if (data->uvd_power_gated == bgate)
3645                 return ;
3646
3647         data->uvd_power_gated = bgate;
3648         vega20_enable_disable_uvd_dpm(hwmgr, !bgate);
3649 }
3650
3651 static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
3652 {
3653         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3654         struct vega20_single_dpm_table *dpm_table;
3655         bool vblank_too_short = false;
3656         bool disable_mclk_switching;
3657         bool disable_fclk_switching;
3658         uint32_t i, latency;
3659
3660         disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3661                            !hwmgr->display_config->multi_monitor_in_sync) ||
3662                             vblank_too_short;
3663         latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3664
3665         /* gfxclk */
3666         dpm_table = &(data->dpm_table.gfx_table);
3667         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3668         dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3669         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3670         dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3671
3672         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3673                 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
3674                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3675                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3676                 }
3677
3678                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
3679                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3680                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3681                 }
3682
3683                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3684                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3685                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3686                 }
3687         }
3688
3689         /* memclk */
3690         dpm_table = &(data->dpm_table.mem_table);
3691         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3692         dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3693         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3694         dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3695
3696         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3697                 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
3698                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3699                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3700                 }
3701
3702                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
3703                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3704                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3705                 }
3706
3707                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3708                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3709                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3710                 }
3711         }
3712
3713         /* honour DAL's UCLK Hardmin */
3714         if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
3715                 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
3716
3717         /* Hardmin is dependent on displayconfig */
3718         if (disable_mclk_switching) {
3719                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3720                 for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
3721                         if (data->mclk_latency_table.entries[i].latency <= latency) {
3722                                 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
3723                                         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
3724                                         break;
3725                                 }
3726                         }
3727                 }
3728         }
3729
3730         if (hwmgr->display_config->nb_pstate_switch_disable)
3731                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3732
3733         if ((disable_mclk_switching &&
3734             (dpm_table->dpm_state.hard_min_level == dpm_table->dpm_levels[dpm_table->count - 1].value)) ||
3735              hwmgr->display_config->min_mem_set_clock / 100 >= dpm_table->dpm_levels[dpm_table->count - 1].value)
3736                 disable_fclk_switching = true;
3737         else
3738                 disable_fclk_switching = false;
3739
3740         /* fclk */
3741         dpm_table = &(data->dpm_table.fclk_table);
3742         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3743         dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3744         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3745         dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3746         if (hwmgr->display_config->nb_pstate_switch_disable || disable_fclk_switching)
3747                 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3748
3749         /* vclk */
3750         dpm_table = &(data->dpm_table.vclk_table);
3751         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3752         dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3753         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3754         dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3755
3756         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3757                 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3758                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3759                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3760                 }
3761
3762                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3763                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3764                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3765                 }
3766         }
3767
3768         /* dclk */
3769         dpm_table = &(data->dpm_table.dclk_table);
3770         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3771         dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3772         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3773         dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3774
3775         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3776                 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3777                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3778                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3779                 }
3780
3781                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3782                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3783                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3784                 }
3785         }
3786
3787         /* socclk */
3788         dpm_table = &(data->dpm_table.soc_table);
3789         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3790         dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3791         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3792         dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3793
3794         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3795                 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
3796                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3797                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3798                 }
3799
3800                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3801                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3802                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3803                 }
3804         }
3805
3806         /* eclk */
3807         dpm_table = &(data->dpm_table.eclk_table);
3808         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3809         dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
3810         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3811         dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
3812
3813         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3814                 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
3815                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3816                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3817                 }
3818
3819                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3820                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3821                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3822                 }
3823         }
3824
3825         return 0;
3826 }
3827
3828 static bool
3829 vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
3830 {
3831         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3832         bool is_update_required = false;
3833
3834         if (data->display_timing.num_existing_displays !=
3835                         hwmgr->display_config->num_display)
3836                 is_update_required = true;
3837
3838         if (data->registry_data.gfx_clk_deep_sleep_support &&
3839            (data->display_timing.min_clock_in_sr !=
3840             hwmgr->display_config->min_core_set_clock_in_sr))
3841                 is_update_required = true;
3842
3843         return is_update_required;
3844 }
3845
3846 static int vega20_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
3847 {
3848         int ret = 0;
3849
3850         ret = vega20_disable_all_smu_features(hwmgr);
3851         PP_ASSERT_WITH_CODE(!ret,
3852                         "[DisableDpmTasks] Failed to disable all smu features!",
3853                         return ret);
3854
3855         return 0;
3856 }
3857
3858 static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
3859 {
3860         struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3861         int result;
3862
3863         result = vega20_disable_dpm_tasks(hwmgr);
3864         PP_ASSERT_WITH_CODE((0 == result),
3865                         "[PowerOffAsic] Failed to disable DPM!",
3866                         );
3867         data->water_marks_bitmap &= ~(WaterMarksLoaded);
3868
3869         return result;
3870 }
3871
3872 static int conv_power_profile_to_pplib_workload(int power_profile)
3873 {
3874         int pplib_workload = 0;
3875
3876         switch (power_profile) {
3877         case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
3878                 pplib_workload = WORKLOAD_DEFAULT_BIT;
3879                 break;
3880         case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
3881                 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
3882                 break;
3883         case PP_SMC_POWER_PROFILE_POWERSAVING:
3884                 pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
3885                 break;
3886         case PP_SMC_POWER_PROFILE_VIDEO:
3887                 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
3888                 break;
3889         case PP_SMC_POWER_PROFILE_VR:
3890                 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
3891                 break;
3892         case PP_SMC_POWER_PROFILE_COMPUTE:
3893                 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
3894                 break;
3895         case PP_SMC_POWER_PROFILE_CUSTOM:
3896                 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
3897                 break;
3898         }
3899
3900         return pplib_workload;
3901 }
3902
3903 static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
3904 {
3905         DpmActivityMonitorCoeffInt_t activity_monitor;
3906         uint32_t i, size = 0;
3907         uint16_t workload_type = 0;
3908         static const char *profile_name[] = {
3909                                         "BOOTUP_DEFAULT",
3910                                         "3D_FULL_SCREEN",
3911                                         "POWER_SAVING",
3912                                         "VIDEO",
3913                                         "VR",
3914                                         "COMPUTE",
3915                                         "CUSTOM"};
3916         static const char *title[] = {
3917                         "PROFILE_INDEX(NAME)",
3918                         "CLOCK_TYPE(NAME)",
3919                         "FPS",
3920                         "UseRlcBusy",
3921                         "MinActiveFreqType",
3922                         "MinActiveFreq",
3923                         "BoosterFreqType",
3924                         "BoosterFreq",
3925                         "PD_Data_limit_c",
3926                         "PD_Data_error_coeff",
3927                         "PD_Data_error_rate_coeff"};
3928         int result = 0;
3929
3930         if (!buf)
3931                 return -EINVAL;
3932
3933         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
3934                         title[0], title[1], title[2], title[3], title[4], title[5],
3935                         title[6], title[7], title[8], title[9], title[10]);
3936
3937         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
3938                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3939                 workload_type = conv_power_profile_to_pplib_workload(i);
3940                 result = vega20_get_activity_monitor_coeff(hwmgr,
3941                                 (uint8_t *)(&activity_monitor), workload_type);
3942                 PP_ASSERT_WITH_CODE(!result,
3943                                 "[GetPowerProfile] Failed to get activity monitor!",
3944                                 return result);
3945
3946                 size += sprintf(buf + size, "%2d %14s%s:\n",
3947                         i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ");
3948
3949                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3950                         " ",
3951                         0,
3952                         "GFXCLK",
3953                         activity_monitor.Gfx_FPS,
3954                         activity_monitor.Gfx_UseRlcBusy,
3955                         activity_monitor.Gfx_MinActiveFreqType,
3956                         activity_monitor.Gfx_MinActiveFreq,
3957                         activity_monitor.Gfx_BoosterFreqType,
3958                         activity_monitor.Gfx_BoosterFreq,
3959                         activity_monitor.Gfx_PD_Data_limit_c,
3960                         activity_monitor.Gfx_PD_Data_error_coeff,
3961                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
3962
3963                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3964                         " ",
3965                         1,
3966                         "SOCCLK",
3967                         activity_monitor.Soc_FPS,
3968                         activity_monitor.Soc_UseRlcBusy,
3969                         activity_monitor.Soc_MinActiveFreqType,
3970                         activity_monitor.Soc_MinActiveFreq,
3971                         activity_monitor.Soc_BoosterFreqType,
3972                         activity_monitor.Soc_BoosterFreq,
3973                         activity_monitor.Soc_PD_Data_limit_c,
3974                         activity_monitor.Soc_PD_Data_error_coeff,
3975                         activity_monitor.Soc_PD_Data_error_rate_coeff);
3976
3977                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3978                         " ",
3979                         2,
3980                         "UCLK",
3981                         activity_monitor.Mem_FPS,
3982                         activity_monitor.Mem_UseRlcBusy,
3983                         activity_monitor.Mem_MinActiveFreqType,
3984                         activity_monitor.Mem_MinActiveFreq,
3985                         activity_monitor.Mem_BoosterFreqType,
3986                         activity_monitor.Mem_BoosterFreq,
3987                         activity_monitor.Mem_PD_Data_limit_c,
3988                         activity_monitor.Mem_PD_Data_error_coeff,
3989                         activity_monitor.Mem_PD_Data_error_rate_coeff);
3990
3991                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3992                         " ",
3993                         3,
3994                         "FCLK",
3995                         activity_monitor.Fclk_FPS,
3996                         activity_monitor.Fclk_UseRlcBusy,
3997                         activity_monitor.Fclk_MinActiveFreqType,
3998                         activity_monitor.Fclk_MinActiveFreq,
3999                         activity_monitor.Fclk_BoosterFreqType,
4000                         activity_monitor.Fclk_BoosterFreq,
4001                         activity_monitor.Fclk_PD_Data_limit_c,
4002                         activity_monitor.Fclk_PD_Data_error_coeff,
4003                         activity_monitor.Fclk_PD_Data_error_rate_coeff);
4004         }
4005
4006         return size;
4007 }
4008
4009 static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
4010 {
4011         DpmActivityMonitorCoeffInt_t activity_monitor;
4012         int workload_type, result = 0;
4013         uint32_t power_profile_mode = input[size];
4014
4015         if (power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
4016                 pr_err("Invalid power profile mode %d\n", power_profile_mode);
4017                 return -EINVAL;
4018         }
4019
4020         if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
4021                 struct vega20_hwmgr *data =
4022                         (struct vega20_hwmgr *)(hwmgr->backend);
4023                 if (size == 0 && !data->is_custom_profile_set)
4024                         return -EINVAL;
4025                 if (size < 10 && size != 0)
4026                         return -EINVAL;
4027
4028                 result = vega20_get_activity_monitor_coeff(hwmgr,
4029                                 (uint8_t *)(&activity_monitor),
4030                                 WORKLOAD_PPLIB_CUSTOM_BIT);
4031                 PP_ASSERT_WITH_CODE(!result,
4032                                 "[SetPowerProfile] Failed to get activity monitor!",
4033                                 return result);
4034
4035                 /* If size==0, then we want to apply the already-configured
4036                  * CUSTOM profile again. Just apply it, since we checked its
4037                  * validity above
4038                  */
4039                 if (size == 0)
4040                         goto out;
4041
4042                 switch (input[0]) {
4043                 case 0: /* Gfxclk */
4044                         activity_monitor.Gfx_FPS = input[1];
4045                         activity_monitor.Gfx_UseRlcBusy = input[2];
4046                         activity_monitor.Gfx_MinActiveFreqType = input[3];
4047                         activity_monitor.Gfx_MinActiveFreq = input[4];
4048                         activity_monitor.Gfx_BoosterFreqType = input[5];
4049                         activity_monitor.Gfx_BoosterFreq = input[6];
4050                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
4051                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
4052                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
4053                         break;
4054                 case 1: /* Socclk */
4055                         activity_monitor.Soc_FPS = input[1];
4056                         activity_monitor.Soc_UseRlcBusy = input[2];
4057                         activity_monitor.Soc_MinActiveFreqType = input[3];
4058                         activity_monitor.Soc_MinActiveFreq = input[4];
4059                         activity_monitor.Soc_BoosterFreqType = input[5];
4060                         activity_monitor.Soc_BoosterFreq = input[6];
4061                         activity_monitor.Soc_PD_Data_limit_c = input[7];
4062                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
4063                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
4064                         break;
4065                 case 2: /* Uclk */
4066                         activity_monitor.Mem_FPS = input[1];
4067                         activity_monitor.Mem_UseRlcBusy = input[2];
4068                         activity_monitor.Mem_MinActiveFreqType = input[3];
4069                         activity_monitor.Mem_MinActiveFreq = input[4];
4070                         activity_monitor.Mem_BoosterFreqType = input[5];
4071                         activity_monitor.Mem_BoosterFreq = input[6];
4072                         activity_monitor.Mem_PD_Data_limit_c = input[7];
4073                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
4074                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
4075                         break;
4076                 case 3: /* Fclk */
4077                         activity_monitor.Fclk_FPS = input[1];
4078                         activity_monitor.Fclk_UseRlcBusy = input[2];
4079                         activity_monitor.Fclk_MinActiveFreqType = input[3];
4080                         activity_monitor.Fclk_MinActiveFreq = input[4];
4081                         activity_monitor.Fclk_BoosterFreqType = input[5];
4082                         activity_monitor.Fclk_BoosterFreq = input[6];
4083                         activity_monitor.Fclk_PD_Data_limit_c = input[7];
4084                         activity_monitor.Fclk_PD_Data_error_coeff = input[8];
4085                         activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
4086                         break;
4087                 }
4088
4089                 result = vega20_set_activity_monitor_coeff(hwmgr,
4090                                 (uint8_t *)(&activity_monitor),
4091                                 WORKLOAD_PPLIB_CUSTOM_BIT);
4092                 data->is_custom_profile_set = true;
4093                 PP_ASSERT_WITH_CODE(!result,
4094                                 "[SetPowerProfile] Failed to set activity monitor!",
4095                                 return result);
4096         }
4097
4098 out:
4099         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
4100         workload_type =
4101                 conv_power_profile_to_pplib_workload(power_profile_mode);
4102         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
4103                                                 1 << workload_type,
4104                                                 NULL);
4105
4106         hwmgr->power_profile_mode = power_profile_mode;
4107
4108         return 0;
4109 }
4110
4111 static int vega20_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
4112                                         uint32_t virtual_addr_low,
4113                                         uint32_t virtual_addr_hi,
4114                                         uint32_t mc_addr_low,
4115                                         uint32_t mc_addr_hi,
4116                                         uint32_t size)
4117 {
4118         smum_send_msg_to_smc_with_parameter(hwmgr,
4119                                         PPSMC_MSG_SetSystemVirtualDramAddrHigh,
4120                                         virtual_addr_hi,
4121                                         NULL);
4122         smum_send_msg_to_smc_with_parameter(hwmgr,
4123                                         PPSMC_MSG_SetSystemVirtualDramAddrLow,
4124                                         virtual_addr_low,
4125                                         NULL);
4126         smum_send_msg_to_smc_with_parameter(hwmgr,
4127                                         PPSMC_MSG_DramLogSetDramAddrHigh,
4128                                         mc_addr_hi,
4129                                         NULL);
4130
4131         smum_send_msg_to_smc_with_parameter(hwmgr,
4132                                         PPSMC_MSG_DramLogSetDramAddrLow,
4133                                         mc_addr_low,
4134                                         NULL);
4135
4136         smum_send_msg_to_smc_with_parameter(hwmgr,
4137                                         PPSMC_MSG_DramLogSetDramSize,
4138                                         size,
4139                                         NULL);
4140         return 0;
4141 }
4142
4143 static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
4144                 struct PP_TemperatureRange *thermal_data)
4145 {
4146         struct vega20_hwmgr *data =
4147                         (struct vega20_hwmgr *)(hwmgr->backend);
4148         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
4149
4150         memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
4151
4152         thermal_data->max = pp_table->TedgeLimit *
4153                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4154         thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) *
4155                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4156         thermal_data->hotspot_crit_max = pp_table->ThotspotLimit *
4157                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4158         thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
4159                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4160         thermal_data->mem_crit_max = pp_table->ThbmLimit *
4161                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4162         thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)*
4163                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4164
4165         return 0;
4166 }
4167
4168 static int vega20_smu_i2c_bus_access(struct pp_hwmgr *hwmgr, bool acquire)
4169 {
4170         int res;
4171
4172         /* I2C bus access can happen very early, when SMU not loaded yet */
4173         if (!vega20_is_smc_ram_running(hwmgr))
4174                 return 0;
4175
4176         res = smum_send_msg_to_smc_with_parameter(hwmgr,
4177                                                   (acquire ?
4178                                                   PPSMC_MSG_RequestI2CBus :
4179                                                   PPSMC_MSG_ReleaseI2CBus),
4180                                                   0,
4181                                                   NULL);
4182
4183         PP_ASSERT_WITH_CODE(!res, "[SmuI2CAccessBus] Failed to access bus!", return res);
4184         return res;
4185 }
4186
4187 static int vega20_set_df_cstate(struct pp_hwmgr *hwmgr,
4188                                 enum pp_df_cstate state)
4189 {
4190         int ret;
4191
4192         /* PPSMC_MSG_DFCstateControl is supported with 40.50 and later fws */
4193         if (hwmgr->smu_version < 0x283200) {
4194                 pr_err("Df cstate control is supported with 40.50 and later SMC fw!\n");
4195                 return -EINVAL;
4196         }
4197
4198         ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DFCstateControl, state,
4199                                 NULL);
4200         if (ret)
4201                 pr_err("SetDfCstate failed!\n");
4202
4203         return ret;
4204 }
4205
4206 static int vega20_set_xgmi_pstate(struct pp_hwmgr *hwmgr,
4207                                   uint32_t pstate)
4208 {
4209         int ret;
4210
4211         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
4212                                                   PPSMC_MSG_SetXgmiMode,
4213                                                   pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
4214                                                   NULL);
4215         if (ret)
4216                 pr_err("SetXgmiPstate failed!\n");
4217
4218         return ret;
4219 }
4220
4221 static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
4222         /* init/fini related */
4223         .backend_init = vega20_hwmgr_backend_init,
4224         .backend_fini = vega20_hwmgr_backend_fini,
4225         .asic_setup = vega20_setup_asic_task,
4226         .power_off_asic = vega20_power_off_asic,
4227         .dynamic_state_management_enable = vega20_enable_dpm_tasks,
4228         .dynamic_state_management_disable = vega20_disable_dpm_tasks,
4229         /* power state related */
4230         .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
4231         .pre_display_config_changed = vega20_pre_display_configuration_changed_task,
4232         .display_config_changed = vega20_display_configuration_changed_task,
4233         .check_smc_update_required_for_display_configuration =
4234                 vega20_check_smc_update_required_for_display_configuration,
4235         .notify_smc_display_config_after_ps_adjustment =
4236                 vega20_notify_smc_display_config_after_ps_adjustment,
4237         /* export to DAL */
4238         .get_sclk = vega20_dpm_get_sclk,
4239         .get_mclk = vega20_dpm_get_mclk,
4240         .get_dal_power_level = vega20_get_dal_power_level,
4241         .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
4242         .get_clock_by_type_with_voltage = vega20_get_clock_by_type_with_voltage,
4243         .set_watermarks_for_clocks_ranges = vega20_set_watermarks_for_clocks_ranges,
4244         .display_clock_voltage_request = vega20_display_clock_voltage_request,
4245         .get_performance_level = vega20_get_performance_level,
4246         /* UMD pstate, profile related */
4247         .force_dpm_level = vega20_dpm_force_dpm_level,
4248         .get_power_profile_mode = vega20_get_power_profile_mode,
4249         .set_power_profile_mode = vega20_set_power_profile_mode,
4250         /* od related */
4251         .set_power_limit = vega20_set_power_limit,
4252         .get_sclk_od = vega20_get_sclk_od,
4253         .set_sclk_od = vega20_set_sclk_od,
4254         .get_mclk_od = vega20_get_mclk_od,
4255         .set_mclk_od = vega20_set_mclk_od,
4256         .odn_edit_dpm_table = vega20_odn_edit_dpm_table,
4257         /* for sysfs to retrive/set gfxclk/memclk */
4258         .force_clock_level = vega20_force_clock_level,
4259         .print_clock_levels = vega20_print_clock_levels,
4260         .read_sensor = vega20_read_sensor,
4261         .get_ppfeature_status = vega20_get_ppfeature_status,
4262         .set_ppfeature_status = vega20_set_ppfeature_status,
4263         /* powergate related */
4264         .powergate_uvd = vega20_power_gate_uvd,
4265         .powergate_vce = vega20_power_gate_vce,
4266         /* thermal related */
4267         .start_thermal_controller = vega20_start_thermal_controller,
4268         .stop_thermal_controller = vega20_thermal_stop_thermal_controller,
4269         .get_thermal_temperature_range = vega20_get_thermal_temperature_range,
4270         .register_irq_handlers = smu9_register_irq_handlers,
4271         .disable_smc_firmware_ctf = vega20_thermal_disable_alert,
4272         /* fan control related */
4273         .get_fan_speed_percent = vega20_fan_ctrl_get_fan_speed_percent,
4274         .set_fan_speed_percent = vega20_fan_ctrl_set_fan_speed_percent,
4275         .get_fan_speed_info = vega20_fan_ctrl_get_fan_speed_info,
4276         .get_fan_speed_rpm = vega20_fan_ctrl_get_fan_speed_rpm,
4277         .set_fan_speed_rpm = vega20_fan_ctrl_set_fan_speed_rpm,
4278         .get_fan_control_mode = vega20_get_fan_control_mode,
4279         .set_fan_control_mode = vega20_set_fan_control_mode,
4280         /* smu memory related */
4281         .notify_cac_buffer_info = vega20_notify_cac_buffer_info,
4282         .enable_mgpu_fan_boost = vega20_enable_mgpu_fan_boost,
4283         /* BACO related */
4284         .get_asic_baco_capability = vega20_baco_get_capability,
4285         .get_asic_baco_state = vega20_baco_get_state,
4286         .set_asic_baco_state = vega20_baco_set_state,
4287         .set_mp1_state = vega20_set_mp1_state,
4288         .smu_i2c_bus_access = vega20_smu_i2c_bus_access,
4289         .set_df_cstate = vega20_set_df_cstate,
4290         .set_xgmi_pstate = vega20_set_xgmi_pstate,
4291 };
4292
4293 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
4294 {
4295         hwmgr->hwmgr_func = &vega20_hwmgr_funcs;
4296         hwmgr->pptable_func = &vega20_pptable_funcs;
4297
4298         return 0;
4299 }